1 /**************************************************************************//** 2 * @file M2354.h 3 * @version V3.0 4 * @brief Peripheral Access Layer Header File 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 ******************************************************************************/ 9 10 /** 11 \mainpage Introduction 12 * 13 * 14 * This user manual describes the usage of M2354 device driver 15 * 16 * <b>Disclaimer</b> 17 * 18 * The Software is furnished "AS IS", without warranty as to performance or results, and 19 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all 20 * warranties, express, implied or otherwise, with regard to the Software, its use, or 21 * operation, including without limitation any and all warranties of merchantability, fitness 22 * for a particular purpose, and non-infringement of intellectual property rights. 23 * 24 */ 25 26 27 #ifndef __M2354_H__ 28 #define __M2354_H__ 29 30 /*=============================================================================*/ 31 typedef volatile unsigned char vu8; 32 typedef volatile unsigned int vu32; 33 typedef volatile unsigned short vu16; 34 #define M8(adr) (*((vu8 *) (adr))) 35 #define M16(adr) (*((vu16 *) (adr))) 36 #define M32(adr) (*((vu32 *) (adr))) 37 38 #define outpw(port,value) (*((volatile unsigned int *)(port))=(value)) 39 #define inpw(port) ((*((volatile unsigned int *)(port)))) 40 #define outpb(port,value) (*((volatile unsigned char *)(port))=(value)) 41 #define inpb(port) ((*((volatile unsigned char *)(port)))) 42 #define outps(port,value) (*((volatile unsigned short *)(port))=(value)) 43 #define inps(port) ((*((volatile unsigned short *)(port)))) 44 45 #define outp32(port,value) (*((volatile unsigned int *)(port))=(value)) 46 #define inp32(port) ((*((volatile unsigned int *)(port)))) 47 #define outp8(port,value) (*((volatile unsigned char *)(port))=(value)) 48 #define inp8(port) ((*((volatile unsigned char *)(port)))) 49 #define outp16(port,value) (*((volatile unsigned short *)(port))=(value)) 50 #define inp16(port) ((*((volatile unsigned short *)(port)))) 51 52 53 #define E_SUCCESS 0 54 55 #define TRUE (1L) 56 #define FALSE (0L) 57 58 #define ENABLE 1 59 #define DISABLE 0 60 61 /* Bit Mask Definitions */ 62 #define BIT0 0x00000001UL 63 #define BIT1 0x00000002UL 64 #define BIT2 0x00000004UL 65 #define BIT3 0x00000008UL 66 #define BIT4 0x00000010UL 67 #define BIT5 0x00000020UL 68 #define BIT6 0x00000040UL 69 #define BIT7 0x00000080UL 70 #define BIT8 0x00000100UL 71 #define BIT9 0x00000200UL 72 #define BIT10 0x00000400UL 73 #define BIT11 0x00000800UL 74 #define BIT12 0x00001000UL 75 #define BIT13 0x00002000UL 76 #define BIT14 0x00004000UL 77 #define BIT15 0x00008000UL 78 #define BIT16 0x00010000UL 79 #define BIT17 0x00020000UL 80 #define BIT18 0x00040000UL 81 #define BIT19 0x00080000UL 82 #define BIT20 0x00100000UL 83 #define BIT21 0x00200000UL 84 #define BIT22 0x00400000UL 85 #define BIT23 0x00800000UL 86 #define BIT24 0x01000000UL 87 #define BIT25 0x02000000UL 88 #define BIT26 0x04000000UL 89 #define BIT27 0x08000000UL 90 #define BIT28 0x10000000UL 91 #define BIT29 0x20000000UL 92 #define BIT30 0x40000000UL 93 #define BIT31 0x80000000UL 94 95 96 /* Byte Mask Definitions */ 97 #define BYTE0_Msk (0x000000FFUL) 98 #define BYTE1_Msk (0x0000FF00UL) 99 #define BYTE2_Msk (0x00FF0000UL) 100 #define BYTE3_Msk (0xFF000000UL) 101 102 #define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */ 103 #define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */ 104 #define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */ 105 #define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */ 106 107 108 109 #ifdef __cplusplus 110 extern "C" { 111 #endif 112 113 /******************************************************************************/ 114 /* Processor and Core Peripherals */ 115 /******************************************************************************/ 116 /** @addtogroup CMSIS_Device CMSIS Definitions 117 Configuration of the Cortex-M23 Processor and Core Peripherals 118 @{ 119 */ 120 121 122 /* 123 * ========================================================================== 124 * ---------- Interrupt Number Definition ----------------------------------- 125 * ========================================================================== 126 */ 127 128 /** 129 * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible. 130 */ 131 typedef enum IRQn 132 { 133 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ 134 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 135 HardFault_IRQn = -13, /*!< 3 Cortex-M23 Hard Fault Interrupt */ 136 SVCall_IRQn = -5, /*!< 11 Cortex-M23 SV Call Interrupt */ 137 PendSV_IRQn = -2, /*!< 14 Cortex-M23 Pend SV Interrupt */ 138 SysTick_IRQn = -1, /*!< 15 Cortex-M23 System Tick Interrupt */ 139 140 /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/ 141 142 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */ 143 IRC_IRQn = 1, /*!< Internal RC Interrupt */ 144 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */ 145 RAMPE_IRQn = 3, /*!< SRAM parity check failed Interrupt */ 146 CKFAIL_IRQn = 4, /*!< Clock failed Interrupt */ 147 ISP_IRQn = 5, /*!< FMC ISP Interrupt */ 148 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */ 149 RTC_TAMPER_IRQn = 7, /*!< RTC Tamper detection Interrupt */ 150 WDT_IRQn = 8, /*!< Watchdog Timer Interrupt */ 151 WWDT_IRQn = 9, /*!< Window Watchdog Timer Interrupt */ 152 EINT0_IRQn = 10, /*!< External Input 0 Interrupt */ 153 EINT1_IRQn = 11, /*!< External Input 1 Interrupt */ 154 EINT2_IRQn = 12, /*!< External Input 2 Interrupt */ 155 EINT3_IRQn = 13, /*!< External Input 3 Interrupt */ 156 EINT4_IRQn = 14, /*!< External Input 4 Interrupt */ 157 EINT5_IRQn = 15, /*!< External Input 5 Interrupt */ 158 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */ 159 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */ 160 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */ 161 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */ 162 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */ 163 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */ 164 QSPI0_IRQn = 22, /*!< QSPI0 Interrupt */ 165 SPI0_IRQn = 23, /*!< SPI0 Interrupt */ 166 BRAKE0_IRQn = 24, /*!< BRAKE0 Interrupt */ 167 EPWM0_P0_IRQn = 25, /*!< EPWM0P0 Interrupt */ 168 EPWM0_P1_IRQn = 26, /*!< EPWM0P1 Interrupt */ 169 EPWM0_P2_IRQn = 27, /*!< EPWM0P2 Interrupt */ 170 BRAKE1_IRQn = 28, /*!< BRAKE1 Interrupt */ 171 EPWM1_P0_IRQn = 29, /*!< EPWM1P0 Interrupt */ 172 EPWM1_P1_IRQn = 30, /*!< EPWM1P1 Interrupt */ 173 EPWM1_P2_IRQn = 31, /*!< EPWM1P2 Interrupt */ 174 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */ 175 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */ 176 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */ 177 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */ 178 UART0_IRQn = 36, /*!< UART 0 Interrupt */ 179 UART1_IRQn = 37, /*!< UART 1 Interrupt */ 180 I2C0_IRQn = 38, /*!< I2C 0 Interrupt */ 181 I2C1_IRQn = 39, /*!< I2C 1 Interrupt */ 182 PDMA0_IRQn = 40, /*!< Peripheral DMA 0 Interrupt */ 183 DAC_IRQn = 41, /*!< DAC Interrupt */ 184 EADC0_IRQn = 42, /*!< EADC Source 0 Interrupt */ 185 EADC1_IRQn = 43, /*!< EADC Source 1 Interrupt */ 186 ACMP01_IRQn = 44, /*!< Analog Comparator 0 and 1 Interrupt */ 187 EADC2_IRQn = 46, /*!< EADC Source 2 Interrupt */ 188 EADC3_IRQn = 47, /*!< EADC Source 3 Interrupt */ 189 UART2_IRQn = 48, /*!< UART2 Interrupt */ 190 UART3_IRQn = 49, /*!< UART3 Interrupt */ 191 SPI1_IRQn = 51, /*!< SPI1 Interrupt */ 192 SPI2_IRQn = 52, /*!< SPI2 Interrupt */ 193 USBD_IRQn = 53, /*!< USB device Interrupt */ 194 USBH_IRQn = 54, /*!< USB host Interrupt */ 195 USBOTG_IRQn = 55, /*!< USB OTG Interrupt */ 196 CAN0_IRQn = 56, /*!< CAN0 Interrupt */ 197 SC0_IRQn = 58, /*!< Smart Card 0 Interrupt */ 198 SC1_IRQn = 59, /*!< Smart Card 1 Interrupt */ 199 SC2_IRQn = 60, /*!< Smart Card 2 Interrupt */ 200 SPI3_IRQn = 62, /*!< SPI3 Interrupt */ 201 SDH0_IRQn = 64, /*!< SDH0 Interrupt */ 202 I2S0_IRQn = 68, /*!< I2S0 Interrupt */ 203 CRPT_IRQn = 71, /*!< CRPT Interrupt */ 204 GPG_IRQn = 72, /*!< GPIO Port G Interrupt */ 205 EINT6_IRQn = 73, /*!< External Input 6 Interrupt */ 206 UART4_IRQn = 74, /*!< UART4 Interrupt */ 207 UART5_IRQn = 75, /*!< UART5 Interrupt */ 208 USCI0_IRQn = 76, /*!< USCI0 Interrupt */ 209 USCI1_IRQn = 77, /*!< USCI1 Interrupt */ 210 BPWM0_IRQn = 78, /*!< BPWM0 Interrupt */ 211 BPWM1_IRQn = 79, /*!< BPWM1 Interrupt */ 212 I2C2_IRQn = 82, /*!< I2C2 Interrupt */ 213 QEI0_IRQn = 84, /*!< QEI0 Interrupt */ 214 QEI1_IRQn = 85, /*!< QEI1 Interrupt */ 215 ECAP0_IRQn = 86, /*!< ECAP0 Interrupt */ 216 ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ 217 GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ 218 EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ 219 PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */ 220 SCU_IRQn = 99, /*!< SCU Interrupt */ 221 LCD_IRQn = 100, /*!< LCD interrupt */ 222 TRNG_IRQn = 101, /*!< TRNG interrupt */ 223 KS_IRQn = 109, /*!< Key Store interrupt */ 224 TAMPER_IRQn = 110, /*!< TAMPER interrupt */ 225 EWDT_IRQn = 111, /*!< Extra Watchdog Timer interrupt */ 226 EWWDT_IRQn = 112, /*!< Extra Window Watchdog Timer interrupt */ 227 NS_ISP_IRQn = 113, /*!< Non-secure FMC ISP interrupt */ 228 TMR4_IRQn = 114, /*!< Timer 4 Interrupt */ 229 TMR5_IRQn = 115, /*!< Timer 5 Interrupt */ 230 231 232 } IRQn_Type; 233 234 235 /* ================================================================================ */ 236 /* ================ Processor and Core Peripheral Section ================ */ 237 /* ================================================================================ */ 238 239 /* ------- Start of section using anonymous unions and disabling warnings ------- */ 240 #if defined (__CC_ARM) 241 #pragma push 242 #pragma anon_unions 243 #elif defined (__ICCARM__) 244 #pragma language=extended 245 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 246 #pragma clang diagnostic push 247 #pragma clang diagnostic ignored "-Wc11-extensions" 248 #pragma clang diagnostic ignored "-Wreserved-id-macro" 249 #elif defined (__GNUC__) 250 /* anonymous unions are enabled by default */ 251 #elif defined (__TMS470__) 252 /* anonymous unions are enabled by default */ 253 #elif defined (__TASKING__) 254 #pragma warning 586 255 #elif defined (__CSMC__) 256 /* anonymous unions are enabled by default */ 257 #else 258 #warning Not supported compiler type 259 #endif 260 261 262 /* -------- Configuration of the Cortex-ARMv8MBL Processor and Core Peripherals ------- */ 263 #define __ARMv8MBL_REV 0x0000U /* Core revision r0p0 */ 264 #define __SAU_PRESENT 1U /* SAU present */ 265 #define __SAUREGION_PRESENT 1U /* SAU present */ 266 #define __MPU_PRESENT 1U /* MPU present */ 267 #define __VTOR_PRESENT 1U /* VTOR present */ 268 #define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ 269 #define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ 270 #define USE_ASSERT 0U /* Define to use Assert function or not */ 271 272 /**@}*/ /* end of group CMSIS */ 273 274 #include "core_cm23.h" /* Processor and core peripherals */ 275 #include "system_M2354.h" /* System Header */ 276 #include "partition_M2354.h" 277 278 /** 279 * Initialize the system clock 280 * 281 * @brief Setup the micro controller system 282 * Initialize the PLL and update the SystemFrequency variable 283 */ 284 extern void SystemInit(void); 285 286 287 /******************************************************************************/ 288 /* Device Specific Peripheral registers structures */ 289 /******************************************************************************/ 290 291 292 #include "acmp_reg.h" 293 #include "bpwm_reg.h" 294 #include "can_reg.h" 295 #include "clk_reg.h" 296 #include "crc_reg.h" 297 #include "dac_reg.h" 298 #include "eadc_reg.h" 299 #include "ebi_reg.h" 300 #include "ecap_reg.h" 301 #include "fmc_reg.h" 302 #include "gpio_reg.h" 303 #include "hdiv_reg.h" 304 #include "i2c_reg.h" 305 #include "i2s_reg.h" 306 #include "pdma_reg.h" 307 #include "epwm_reg.h" 308 #include "qei_reg.h" 309 #include "rtc_reg.h" 310 #include "sc_reg.h" 311 #include "scu_reg.h" 312 #include "sdh_reg.h" 313 #include "qspi_reg.h" 314 #include "spi_reg.h" 315 #include "sys_reg.h" 316 #include "timer_reg.h" 317 #include "trng_reg.h" 318 #include "uart_reg.h" 319 #include "ui2c_reg.h" 320 #include "usbh_reg.h" 321 #include "usbd_reg.h" 322 #include "otg_reg.h" 323 #include "crpt_reg.h" 324 #include "uspi_reg.h" 325 #include "uuart_reg.h" 326 #include "wdt_reg.h" 327 #include "wwdt_reg.h" 328 #include "keystore_reg.h" 329 #include "tamper_reg.h" 330 #include "lcd_reg.h" 331 #include "ewdt_reg.h" 332 #include "ewwdt_reg.h" 333 334 335 336 /******************************************************************************/ 337 /* Peripheral memory map */ 338 /******************************************************************************/ 339 /** @addtogroup PERIPHERAL_BASE Peripheral Memory Base 340 Memory Mapped Structure for Series Peripheral 341 @{ 342 */ 343 344 345 /* Peripheral and SRAM base address */ 346 #define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ 347 #define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ 348 #define NS_OFFSET (0x10000000UL) 349 350 /* Peripheral memory map */ 351 #define AHBPERIPH_BASE PERIPH_BASE 352 #define APBPERIPH_BASE (PERIPH_BASE + 0x00040000UL) 353 354 /*!< AHB peripherals */ 355 #define SYS_BASE (AHBPERIPH_BASE + 0x00000UL) 356 #define CLK_BASE (AHBPERIPH_BASE + 0x00200UL) 357 #define INT_BASE (AHBPERIPH_BASE + 0x00300UL) 358 #define GPIO_BASE (AHBPERIPH_BASE + 0x04000UL) 359 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000UL) 360 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040UL) 361 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080UL) 362 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0UL) 363 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100UL) 364 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140UL) 365 #define GPIOG_BASE (AHBPERIPH_BASE + 0x04180UL) 366 #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) 367 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) 368 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) 369 #define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL) 370 #define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL) 371 #define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) 372 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000UL) 373 #define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) 374 #define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) 375 #define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) 376 #define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) 377 #define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL) 378 #define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL) 379 #define FVC_BASE (AHBPERIPH_BASE + 0x2F500UL) 380 #define DPM_BASE (AHBPERIPH_BASE + 0x2F600UL) 381 #define PLM_BASE (AHBPERIPH_BASE + 0x2F700UL) 382 383 #define BTF_BASE (AHBPERIPH_BASE + 0x2F800UL) 384 385 /*!< APB peripherals */ 386 #define WDT_BASE (APBPERIPH_BASE + 0x00000UL) 387 #define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) 388 #define RTC_BASE (APBPERIPH_BASE + 0x01000UL) 389 #define EADC_BASE (APBPERIPH_BASE + 0x03000UL) 390 #define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) 391 #define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) 392 #define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) 393 #define I2S0_BASE (APBPERIPH_BASE + 0x08000UL) 394 #define OTG_BASE (APBPERIPH_BASE + 0x0D000UL) 395 #define TMR01_BASE (APBPERIPH_BASE + 0x10000UL) 396 #define TMR23_BASE (APBPERIPH_BASE + 0x11000UL) 397 #define TMR45_BASE (APBPERIPH_BASE + 0x12000UL) 398 #define EPWM0_BASE (APBPERIPH_BASE + 0x18000UL) 399 #define EPWM1_BASE (APBPERIPH_BASE + 0x19000UL) 400 #define BPWM0_BASE (APBPERIPH_BASE + 0x1A000UL) 401 #define BPWM1_BASE (APBPERIPH_BASE + 0x1B000UL) 402 #define QSPI0_BASE (APBPERIPH_BASE + 0x20000UL) 403 #define SPI0_BASE (APBPERIPH_BASE + 0x21000UL) 404 #define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) 405 #define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) 406 #define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) 407 #define UART0_BASE (APBPERIPH_BASE + 0x30000UL) 408 #define UART0_BASE (APBPERIPH_BASE + 0x30000UL) 409 #define UART1_BASE (APBPERIPH_BASE + 0x31000UL) 410 #define UART2_BASE (APBPERIPH_BASE + 0x32000UL) 411 #define UART3_BASE (APBPERIPH_BASE + 0x33000UL) 412 #define UART4_BASE (APBPERIPH_BASE + 0x34000UL) 413 #define UART5_BASE (APBPERIPH_BASE + 0x35000UL) 414 #define I2C0_BASE (APBPERIPH_BASE + 0x40000UL) 415 #define I2C1_BASE (APBPERIPH_BASE + 0x41000UL) 416 #define I2C2_BASE (APBPERIPH_BASE + 0x42000UL) 417 #define SC0_BASE (APBPERIPH_BASE + 0x50000UL) 418 #define SC1_BASE (APBPERIPH_BASE + 0x51000UL) 419 #define SC2_BASE (APBPERIPH_BASE + 0x52000UL) 420 #define CAN0_BASE (APBPERIPH_BASE + 0x60000UL) 421 #define QEI0_BASE (APBPERIPH_BASE + 0x70000UL) 422 #define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) 423 #define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) 424 #define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) 425 #define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) 426 #define USBD_BASE (APBPERIPH_BASE + 0x80000UL) 427 #define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) 428 #define USCI1_BASE (APBPERIPH_BASE + 0x91000UL) 429 430 #define EWDT_BASE (APBPERIPH_BASE + 0x02000UL) 431 #define EWWDT_BASE (APBPERIPH_BASE + 0x02100UL) 432 433 434 #define KS_BASE (AHBPERIPH_BASE + 0x35000UL) 435 #define TAMPER_BASE (AHBPERIPH_BASE + 0xBD000UL) 436 #define LCD_BASE (AHBPERIPH_BASE + 0xBB000UL) 437 438 439 440 /**@}*/ /* PERIPHERAL */ 441 442 /******************************************************************************/ 443 /* Peripheral declaration */ 444 /******************************************************************************/ 445 446 /** @addtogroup PMODULE Peripheral Pointer 447 The Declaration of Peripheral Pointer 448 @{ 449 */ 450 451 /** @addtogroup PMODULE_S Secure Peripheral Pointer 452 The Declaration of Secure Peripheral Pointer 453 @{ 454 */ 455 456 #define PA_S ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */ 457 #define PB_S ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */ 458 #define PC_S ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */ 459 #define PD_S ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */ 460 #define PE_S ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */ 461 #define PF_S ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */ 462 #define PG_S ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */ 463 #define PH_S ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */ 464 465 #define UART0_S ((UART_T *) UART0_BASE) /*!< UART0 Pointer */ 466 #define UART1_S ((UART_T *) UART1_BASE) /*!< UART1 Pointer */ 467 #define UART2_S ((UART_T *) UART2_BASE) /*!< UART2 Pointer */ 468 #define UART3_S ((UART_T *) UART3_BASE) /*!< UART3 Pointer */ 469 #define UART4_S ((UART_T *) UART4_BASE) /*!< UART4 Pointer */ 470 #define UART5_S ((UART_T *) UART5_BASE) /*!< UART5 Pointer */ 471 472 473 #define TIMER0_S ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */ 474 #define TIMER1_S ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */ 475 #define TIMER2_S ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */ 476 #define TIMER3_S ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */ 477 #define TIMER4_S ((TIMER_T *) TMR45_BASE) /*!< TIMER4 Pointer */ 478 #define TIMER5_S ((TIMER_T *) (TMR45_BASE + 0x100UL)) /*!< TIMER5 Pointer */ 479 480 #define WDT_S ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */ 481 482 #define WWDT_S ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */ 483 484 #define QSPI0_S ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */ 485 #define SPI0_S ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */ 486 #define SPI1_S ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */ 487 #define SPI2_S ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */ 488 #define SPI3_S ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */ 489 490 #define I2S0_S ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */ 491 492 #define I2C0_S ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */ 493 #define I2C1_S ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */ 494 #define I2C2_S ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */ 495 496 #define QEI0_S ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */ 497 #define QEI1_S ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */ 498 499 #define RTC_S ((RTC_T *) RTC_BASE) /*!< RTC Pointer */ 500 501 #define ACMP01_S ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */ 502 503 #define CLK_S ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */ 504 505 #define DAC0_S ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */ 506 #define DAC1_S ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */ 507 508 #define EADC_S ((EADC_T *) EADC_BASE) /*!< EADC Pointer */ 509 510 #define SYS_S ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */ 511 512 #define SYSINT_S ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */ 513 514 #define FMC_S ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */ 515 516 #define SDH0_S ((SDH_T *) SDH0_BASE) 517 518 #define CRPT_S ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */ 519 #define TRNG_S ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */ 520 521 #define BPWM0_S ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */ 522 #define BPWM1_S ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */ 523 524 #define EPWM0_S ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */ 525 #define EPWM1_S ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */ 526 527 #define SC0_S ((SC_T *) SC0_BASE) /*!< SC0 Pointer */ 528 #define SC1_S ((SC_T *) SC1_BASE) /*!< SC1 Pointer */ 529 #define SC2_S ((SC_T *) SC2_BASE) /*!< SC2 Pointer */ 530 531 #define EBI_S ((EBI_T *) EBI_BASE) /*!< EBI Pointer */ 532 533 #define CRC_S ((CRC_T *) CRC_BASE) /*!< CRC Pointer */ 534 535 #define USBD_S ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */ 536 #define USBH_S ((USBH_T *) USBH_BASE) /*!< USBH Pointer */ 537 #define OTG_S ((OTG_T *) OTG_BASE) /*!< OTG Pointer */ 538 539 #define PDMA0_S ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */ 540 #define PDMA1_S ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */ 541 542 #define UI2C0_S ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */ 543 #define UI2C1_S ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */ 544 545 #define USPI0_S ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */ 546 #define USPI1_S ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */ 547 548 #define UUART0_S ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */ 549 #define UUART1_S ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */ 550 551 #define SCU_S ((SCU_T *) SCU_BASE) /*!< SCU Pointer */ 552 #define ECAP0_S ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */ 553 #define ECAP1_S ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */ 554 555 #define CAN0_S ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */ 556 557 #define KS_S ((KS_T *)KS_BASE) /*!< Key Store Pointer */ 558 #define TAMPER_S ((TAMPER_T *)TAMPER_BASE) /*!< TAMPER Pointer */ 559 #define LCD_S ((LCD_T *)LCD_BASE) /*!< LCD Pointer */ 560 561 #define EWDT_S ((EWDT_T *) EWDT_BASE) /*!< Extra Watch Dog Timer Pointer */ 562 563 #define EWWDT_S ((EWWDT_T *) EWWDT_BASE) /*!< Extra Window Watch Dog Timer Pointer*/ 564 565 #define FVC_S ((FVC_T *) FVC_BASE) 566 #define DPM_S ((DPM_T *) DPM_BASE) 567 #define PLM_S ((PLM_T *) PLM_BASE) 568 569 570 571 /**@}*/ /* end of group PMODULE_S */ 572 573 /** @addtogroup PMODULE_NS Non-secure Peripheral Pointer 574 The Declaration of Non-secure Peripheral Pointer 575 @{ 576 */ 577 578 579 #define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */ 580 #define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */ 581 #define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */ 582 #define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */ 583 #define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */ 584 #define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */ 585 #define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */ 586 #define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */ 587 #define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */ 588 #define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */ 589 #define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */ 590 #define UART3_NS ((UART_T *) (UART3_BASE+NS_OFFSET)) /*!< UART3 Pointer */ 591 #define UART4_NS ((UART_T *) (UART4_BASE+NS_OFFSET)) /*!< UART4 Pointer */ 592 #define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */ 593 #define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */ 594 #define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */ 595 #define TIMER4_NS ((TIMER_T *) (TMR45_BASE+NS_OFFSET)) /*!< TIMER4 Pointer */ 596 #define TIMER5_NS ((TIMER_T *) (TMR45_BASE+NS_OFFSET+0x100UL)) /*!< TIMER5 Pointer */ 597 #define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */ 598 #define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */ 599 #define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */ 600 #define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */ 601 #define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */ 602 #define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */ 603 #define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */ 604 #define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ 605 #define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ 606 #define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */ 607 #define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */ 608 #define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */ 609 #define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */ 610 #define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */ 611 #define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */ 612 #define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET)) 613 #define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET)) 614 #define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */ 615 #define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */ 616 #define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */ 617 #define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */ 618 #define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */ 619 #define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */ 620 #define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */ 621 #define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */ 622 #define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */ 623 #define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */ 624 #define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */ 625 #define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */ 626 #define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */ 627 #define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */ 628 #define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */ 629 #define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */ 630 #define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */ 631 #define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */ 632 #define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */ 633 #define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */ 634 #define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */ 635 #define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */ 636 #define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */ 637 #define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */ 638 639 #define EWDT_NS ((EWDT_T *) (EWDT_BASE+NS_OFFSET)) /*!< Extra Watch Dog Timer Pointer */ 640 641 #define EWWDT_NS ((EWWDT_T *) (EWWDT_BASE+NS_OFFSET)) /*!< Extra Window Watch Dog Timer Pointer*/ 642 643 644 #define LCD_NS ((LCD_T *)(LCD_BASE+NS_OFFSET)) /*!< LCD Pointer */ 645 #define DPM_NS ((DPM_T *)(DPM_BASE+NS_OFFSET)) 646 #define FMC_NS ((FMC_T *)(FMC_BASE+NS_OFFSET)) /*!< Flash Memory Controller */ 647 #define SYS_NS ((SYS_T *)(SYS_BASE+NS_OFFSET)) 648 #define CLK_NS ((CLK_T *)(CLK_BASE+NS_OFFSET)) 649 650 651 /**@}*/ /* end of group PMODULE_NS */ 652 653 /** @addtogroup PMODULE_SNS Peripheral Pointer 654 The Declaration of Peripheral Pointer 655 @{ 656 */ 657 658 /* Always Secure Modules */ 659 #define SYS SYS_S 660 #define SYSINT SYSINT_S 661 #define CLK CLK_S 662 #define FMC FMC_S 663 #define SCU SCU_S 664 #define FVC FVC_S 665 #define PLM PLM_S 666 #define DPM DPM_S 667 #define PDMA0 PDMA0_S 668 #define WDT WDT_S 669 #define WWDT WWDT_S 670 #define TIMER0 TIMER0_S 671 #define TIMER1 TIMER1_S 672 #define RTC RTC_S 673 #define KS KS_S 674 #define TAMPER TAMPER_S 675 676 #if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT9 ) 677 # define USBH USBH_NS 678 #else 679 # define USBH USBH_S 680 #endif 681 682 #if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT13) 683 # define SDH0 SDH0_NS 684 #else 685 # define SDH0 SDH0_S 686 #endif 687 688 #if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT16) 689 # define EBI EBI_NS 690 #else 691 # define EBI EBI_S 692 #endif 693 694 695 #if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT24) 696 # define PDMA1 PDMA1_NS 697 #else 698 # define PDMA1 PDMA1_S 699 #endif 700 701 #if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT17) 702 # define CRC CRC_NS 703 #else 704 # define CRC CRC_S 705 #endif 706 707 #if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT18) 708 # define CRPT CRPT_NS 709 #else 710 # define CRPT CRPT_S 711 #endif 712 713 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT2 ) 714 # define EWDT EWDT_NS 715 # define EWWDT EWWDT_NS 716 #else 717 # define EWDT EWDT_S 718 # define EWWDT EWWDT_S 719 #endif 720 721 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) 722 # define EADC EADC_NS 723 #else 724 # define EADC EADC_S 725 #endif 726 727 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) 728 # define EADC EADC_NS 729 #else 730 # define EADC EADC_S 731 #endif 732 733 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) 734 # define EADC EADC_NS 735 #else 736 # define EADC EADC_S 737 #endif 738 739 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 ) 740 # define EADC EADC_NS 741 #else 742 # define EADC EADC_S 743 #endif 744 745 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT5 ) 746 # define ACMP01 ACMP01_NS 747 #else 748 # define ACMP01 ACMP01_S 749 #endif 750 751 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT7 ) 752 # define DAC0 DAC0_NS 753 # define DAC1 DAC1_NS 754 #else 755 # define DAC0 DAC0_S 756 # define DAC1 DAC1_S 757 #endif 758 759 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT8 ) 760 # define I2S0 I2S0_NS 761 #else 762 # define I2S0 I2S0_S 763 #endif 764 765 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT13) 766 # define OTG OTG_NS 767 #else 768 # define OTG OTG_S 769 #endif 770 771 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT17) 772 # define TIMER2 TIMER2_NS 773 # define TIMER3 TIMER3_NS 774 #else 775 # define TIMER2 TIMER2_S 776 # define TIMER3 TIMER3_S 777 #endif 778 779 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT18) 780 # define TIMER4 TIMER4_NS 781 # define TIMER5 TIMER5_NS 782 #else 783 # define TIMER4 TIMER4_S 784 # define TIMER5 TIMER5_S 785 #endif 786 787 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) 788 # define EPWM0 EPWM0_NS 789 #else 790 # define EPWM0 EPWM0_S 791 #endif 792 793 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) 794 # define EPWM0 EPWM0_NS 795 #else 796 # define EPWM0 EPWM0_S 797 #endif 798 799 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24) 800 # define EPWM0 EPWM0_NS 801 #else 802 # define EPWM0 EPWM0_S 803 #endif 804 805 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) 806 # define EPWM1 EPWM1_NS 807 #else 808 # define EPWM1 EPWM1_S 809 #endif 810 811 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) 812 # define EPWM1 EPWM1_NS 813 #else 814 # define EPWM1 EPWM1_S 815 #endif 816 817 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25) 818 # define EPWM1 EPWM1_NS 819 #else 820 # define EPWM1 EPWM1_S 821 #endif 822 823 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT26) 824 # define BPWM0 BPWM0_NS 825 #else 826 # define BPWM0 BPWM0_S 827 #endif 828 829 #if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT27) 830 # define BPWM1 BPWM1_NS 831 #else 832 # define BPWM1 BPWM1_S 833 #endif 834 835 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT0 ) 836 # define QSPI0 QSPI0_NS 837 #else 838 # define QSPI0 QSPI0_S 839 #endif 840 841 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT1 ) 842 # define SPI0 SPI0_NS 843 #else 844 # define SPI0 SPI0_S 845 #endif 846 847 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT2 ) 848 # define SPI1 SPI1_NS 849 #else 850 # define SPI1 SPI1_S 851 #endif 852 853 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT3 ) 854 # define SPI2 SPI2_NS 855 #else 856 # define SPI2 SPI2_S 857 #endif 858 859 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT4 ) 860 # define SPI3 SPI3_NS 861 #else 862 # define SPI3 SPI3_S 863 #endif 864 865 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT16) 866 # define UART0 UART0_NS 867 #else 868 # define UART0 UART0_S 869 #endif 870 871 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT17) 872 # define UART1 UART1_NS 873 #else 874 # define UART1 UART1_S 875 #endif 876 877 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT18) 878 # define UART2 UART2_NS 879 #else 880 # define UART2 UART2_S 881 #endif 882 883 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT19) 884 # define UART3 UART3_NS 885 #else 886 # define UART3 UART3_S 887 #endif 888 889 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT20) 890 # define UART4 UART4_NS 891 #else 892 # define UART4 UART4_S 893 #endif 894 895 #if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT21) 896 # define UART5 UART5_NS 897 #else 898 # define UART5 UART5_S 899 #endif 900 901 #if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT0 ) 902 # define I2C0 I2C0_NS 903 #else 904 # define I2C0 I2C0_S 905 #endif 906 907 #if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT1 ) 908 # define I2C1 I2C1_NS 909 #else 910 # define I2C1 I2C1_S 911 #endif 912 913 #if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT2 ) 914 # define I2C2 I2C2_NS 915 #else 916 # define I2C2 I2C2_S 917 #endif 918 919 #if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT16) 920 # define SC0 SC0_NS 921 #else 922 # define SC0 SC0_S 923 #endif 924 925 #if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT17) 926 # define SC1 SC1_NS 927 #else 928 # define SC1 SC1_S 929 #endif 930 931 #if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT18) 932 # define SC2 SC2_NS 933 #else 934 # define SC2 SC2_S 935 #endif 936 937 #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT0 ) 938 # define CAN0 CAN0_NS 939 #else 940 # define CAN0 CAN0_S 941 #endif 942 943 #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT16) 944 # define QEI0 QEI0_NS 945 #else 946 # define QEI0 QEI0_S 947 #endif 948 949 #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT17) 950 # define QEI1 QEI1_NS 951 #else 952 # define QEI1 QEI1_S 953 #endif 954 955 #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT20) 956 # define ECAP0 ECAP0_NS 957 #else 958 # define ECAP0 ECAP0_S 959 #endif 960 961 #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT21) 962 # define ECAP1 ECAP1_NS 963 #else 964 # define ECAP1 ECAP1_S 965 #endif 966 967 #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT25) 968 # define TRNG TRNG_NS 969 #else 970 # define TRNG TRNG_S 971 #endif 972 973 #if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT27) 974 # define LCD LCD_NS 975 #else 976 # define LCD LCD_S 977 #endif 978 979 #if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT0 ) 980 # define USBD USBD_NS 981 #else 982 # define USBD USBD_S 983 #endif 984 985 #if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT16) 986 # define USCI0 USCI0_NS 987 # define UI2C0 UI2C0_NS 988 # define USPI0 USPI0_NS 989 # define UUART0 UUART0_NS 990 991 #else 992 # define USCI0 USCI0_S 993 # define UI2C0 UI2C0_S 994 # define USPI0 USPI0_S 995 # define UUART0 UUART0_S 996 997 #endif 998 999 #if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT17) 1000 # define USCI1 USCI1_NS 1001 # define USPI1 USPI1_NS 1002 # define UI2C1 UI2C1_NS 1003 # define UUART1 UUART1_NS 1004 1005 #else 1006 # define USCI1 USCI1_S 1007 # define USPI1 USPI1_S 1008 # define UI2C1 UI2C1_S 1009 # define UUART1 UUART1_S 1010 #endif 1011 1012 #define PA ( (__PC() & NS_OFFSET) ? PA_NS : PA_S) 1013 #define PB ( (__PC() & NS_OFFSET) ? PB_NS : PB_S) 1014 #define PC ( (__PC() & NS_OFFSET) ? PC_NS : PC_S) 1015 #define PD ( (__PC() & NS_OFFSET) ? PD_NS : PD_S) 1016 #define PE ( (__PC() & NS_OFFSET) ? PE_NS : PE_S) 1017 #define PF ( (__PC() & NS_OFFSET) ? PF_NS : PF_S) 1018 #define PG ( (__PC() & NS_OFFSET) ? PG_NS : PG_S) 1019 #define PH ( (__PC() & NS_OFFSET) ? PH_NS : PH_S) 1020 1021 /**@}*/ /* end of group PMODULE_SNS */ 1022 1023 /**@}*/ /* end of group PMODULE */ 1024 1025 /* -------------------- End of section using anonymous unions ------------------- */ 1026 #if defined (__CC_ARM) 1027 #pragma pop 1028 #elif defined (__ICCARM__) 1029 /* leave anonymous unions enabled */ 1030 #elif (__ARMCC_VERSION >= 6010050) 1031 #pragma clang diagnostic pop 1032 #elif defined (__GNUC__) 1033 /* anonymous unions are enabled by default */ 1034 #elif defined (__TMS470__) 1035 /* anonymous unions are enabled by default */ 1036 #elif defined (__TASKING__) 1037 #pragma warning restore 1038 #elif defined (__CSMC__) 1039 /* anonymous unions are enabled by default */ 1040 #else 1041 #warning Not supported compiler type 1042 #endif 1043 1044 #ifdef __cplusplus 1045 } 1046 #endif 1047 1048 1049 1050 /******************************************************************************/ 1051 /* Peripheral header files */ 1052 /******************************************************************************/ 1053 #include "sys.h" 1054 #include "clk.h" 1055 #include "dac.h" 1056 #include "eadc.h" 1057 #include "ebi.h" 1058 #include "ecap.h" 1059 #include "fmc.h" 1060 #include "gpio.h" 1061 #include "i2c.h" 1062 #include "i2s.h" 1063 #include "bpwm.h" 1064 #include "epwm.h" 1065 #include "qspi.h" 1066 #include "spi.h" 1067 #include "timer.h" 1068 #include "timer_pwm.h" 1069 #include "wdt.h" 1070 #include "wwdt.h" 1071 #include "rtc.h" 1072 #include "uart.h" 1073 #include "acmp.h" 1074 #include "crc.h" 1075 #include "usbd.h" 1076 #include "otg.h" 1077 #include "pdma.h" 1078 #include "ebi.h" 1079 #include "keystore.h" 1080 #include "crypto.h" 1081 #include "sc.h" 1082 #include "scuart.h" 1083 #include "usci_spi.h" 1084 #include "usci_uart.h" 1085 #include "usci_i2c.h" 1086 #include "sdh.h" 1087 #include "qei.h" 1088 #include "can.h" 1089 #include "scu.h" 1090 #include "tamper.h" 1091 #include "rng.h" 1092 #include "dpm.h" 1093 #include "fvc.h" 1094 #include "ewwdt.h" 1095 #include "ewdt.h" 1096 #include "plm.h" 1097 #include "lcd.h" 1098 1099 #endif /* __M2354_H__ */ 1100
