1 /**************************************************************************//** 2 * @file keystore_reg.h 3 * @version V1.00 4 * @brief Key store register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __KEYSTORE_REG_H__ 10 #define __KEYSTORE_REG_H__ 11 12 13 /** @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 20 /*---------------------- Key Store -------------------------*/ 21 /** 22 @addtogroup KS Key Store(KS) 23 Memory Mapped Structure for KS Controller 24 @{ 25 */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var KS_T::CTL 33 * Offset: 0x00 Key Store Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[0] |START |Key Store Start Control Bit 38 * | | |0 = No operation. 39 * | | |1 = Start the setted operation. 40 * |[3:1] |OPMODE |Key Store Operation Mode 41 * | | |000 = Read operation. 42 * | | |001 = Create operation. 43 * | | |010 = Erase one key operation (only for key is in SRAM). 44 * | | |011 = Erase all keys operation (only for SRAM and Flash). 45 * | | |100 = Revoke key operation. 46 * | | |101 = Data Remanence prevention opertation (only for SRAM). 47 * | | |Others = reserved. 48 * |[7] |CONT |Read/Write Key Continue Bit 49 * | | |0 = Read/Write key operation is not continuous to previous operation. 50 * | | |1 = Read/Write key operation is continuous to previous operation. 51 * |[8] |INIT |Key Store Initialization 52 * | | |User should to check BUSY(KS_STS[2]) is 0, and then write 1 to this bit and START(KS_CTL[0[), the Key Store will start to be initialized. 53 * | | |After KeyStore is initialized, INIT will be cleared. 54 * | | |Note: Before executing INIT, user must to checks KS(SYS_SRAMPC1) is 00. 55 * |[10] |SILENT |Silent Access Enable Bit 56 * | | |0 = Silent Access Disabled. 57 * | | |1 = Silent Access Enabled. 58 * |[11] |SCMB |Data Scramble Enable Bit 59 * | | |0 = Data Scramble Disabled. 60 * | | |1 = Data Scramble Enabled. 61 * |[15] |IEN |Key Store Interrupt Enable Bit 62 * | | |0 = Key Store Interrupt Disabled. 63 * | | |1 = Key Store Interrupt Enabled. 64 * @var KS_T::METADATA 65 * Offset: 0x04 Key Store Metadata Register 66 * --------------------------------------------------------------------------------------------------- 67 * |Bits |Field |Descriptions 68 * | :----: | :----: | :---- | 69 * |[0] |SEC |Secure Key Selection Bit 70 * | | |0 = Set key as the non-secure key. 71 * | | |1 = Set key as the secure key. 72 * |[1] |PRIV |Privilege Key Selection Bit 73 * | | |0 = Set key as the non-privilege key. 74 * | | |1 = Set key as the privilege key. 75 * |[2] |READABLE |Key Readable Control Bit 76 * | | |0 = key is un-readable. 77 * | | |1 = key is readable. 78 * |[3] |RVK |Key Revoke Control Bit 79 * | | |0 = Key current selected will not be changed. 80 * | | |1 = key current selected will be change to revoked state. 81 * |[4] |BS |Booting State Selection Bit 82 * | | |0 = Set key used at all state. 83 * | | |1 = Set key used at boot loader state 1 (BL1 state). 84 * |[12:8] |SIZE |Key Size Selection Bits 85 * | | |00000 = 128 bits. 86 * | | |00001 = 163 bits. 87 * | | |00010 = 192 bits. 88 * | | |00011 = 224 bits. 89 * | | |00100 = 233 bits. 90 * | | |00101 = 255 bits. 91 * | | |00110 = 256 bits. 92 * | | |00111 = 283 bits. 93 * | | |01000 = 384 bits. 94 * | | |01001 = 409 bits. 95 * | | |01010 = 512 bits. 96 * | | |01011 = 521 bits. 97 * | | |01100 = 571 bits. 98 * | | |10000 = 1024 bits. 99 * | | |10001 = 1536 bits. 100 * | | |10010 = 2048 bits. 101 * | | |10011 = 3072 bits. 102 * | | |10100 = 4096 bits. 103 * | | |Others = reserved. 104 * |[18:16] |OWNER |Key Owner Selection Bits 105 * | | |000 = Only for AES used. 106 * | | |001 = Only for HMAC engine used. 107 * | | |010 = Only for RSA engine exponential used (private key). 108 * | | |011 = Only for RSA engine middle data used. 109 * | | |100 = Only for ECC engine used. 110 * | | |101 = Only for CPU engine use. 111 * | | |Others = reserved. 112 * |[25:20] |NUMBER |Key Number 113 * | | |Before read or erase one key operation starts, user should write the key number to be operated 114 * | | |When create operation is finished, user can read these bits to get its key number. 115 * |[31:30] |DST |Key Location Selection Bits 116 * | | |00 = Key is in SRAM. 117 * | | |01 = Key is in Flash. 118 * | | |10 = Key is in OTP. 119 * | | |Others = reserved. 120 * @var KS_T::STS 121 * Offset: 0x08 Key Store Status Register 122 * --------------------------------------------------------------------------------------------------- 123 * |Bits |Field |Descriptions 124 * | :----: | :----: | :---- | 125 * |[0] |IF |Key Store Finish Interrupt Flag 126 * | | |This bit is cleared by writing 1 and it has no effect by writing 0. 127 * | | |0 = No Key Store interrupt. 128 * | | |1 = Key Store operation done interrupt. 129 * |[1] |EIF |Key Store Error Flag 130 * | | |This bit is cleared by writing 1 and it has no effect by writing 0. 131 * | | |0 = No Key Store error. 132 * | | |1 = Key Store error interrupt. 133 * |[2] |BUSY |Key Store Busy Flag (RO) 134 * | | |0 = KeyStore is idle or finished. 135 * | | |1 = KeyStore is busy. 136 * |[3] |SRAMFULL |Key Storage at SRAM Full Status Bit (RO) 137 * | | |0 = Key Storage at SRAM is not full. 138 * | | |1 = Key Storage at SRAM is full. 139 * |[4] |FLASHFULL |Key Storage at Flash Full Status Bit (RO) 140 * | | |0 = Key Storage at Flash is not full. 141 * | | |1 = Key Storage at Flash is full. 142 * |[7] |INITDONE |Key Store Initialization Done Status (RO) 143 * | | |0 = Key Store is un-initialized. 144 * | | |1 = Key Store is initialized. 145 * |[8] |RAMINV |Key Store SRAM Invert Status (RO) 146 * | | |0 = Key Store key in SRAM is normal. 147 * | | |1 = Key Store key in SRAM is inverted. 148 * @var KS_T::REMAIN 149 * Offset: 0x0C Key Store Remaining Space Register 150 * --------------------------------------------------------------------------------------------------- 151 * |Bits |Field |Descriptions 152 * | :----: | :----: | :---- | 153 * |[12:0] |RRMNG |Key Store SRAM Remaining Space 154 * | | |The RRMNG shows the remaining byte count space for SRAM. 155 * |[27:16] |FRMNG |Key Store Flash Remaining Space 156 * | | |The FRMNG shows the remaining byte count space for Flash. 157 * @var KS_T::SCMBKEY 158 * Offset: 0x10-0x1C Key Store Scramble Key Word Register 159 * --------------------------------------------------------------------------------------------------- 160 * |Bits |Field |Descriptions 161 * | :----: | :----: | :---- | 162 * |[31:0] |SCMBKEY |Key Store Scramble Key 163 * | | |When SCMB(KS_CTL[]) is set to 1, user should write the scramble key in this register before new key stores in Key Store 164 * | | |If user does not write the scramble key in this register, the Key Store will use previous scramble key to execute data scramble function. 165 * @var KS_T::KEY 166 * Offset: 0x20-0x3C Key Store Entry Key Word Register 167 * --------------------------------------------------------------------------------------------------- 168 * |Bits |Field |Descriptions 169 * | :----: | :----: | :---- | 170 * |[31:0] |KEY |Key Data 171 * | | |The register will be cleared if the Key Store executes the write operation or CPU completes the reading key. 172 * @var KS_T::OTPSTS 173 * Offset: 0x40 Key Store OTP Keys Status Register 174 * --------------------------------------------------------------------------------------------------- 175 * |Bits |Field |Descriptions 176 * | :----: | :----: | :---- | 177 * |[0] |KEY0 |OTP Key 0 Used Status 178 * | | |0 = OTP key 0 is unused. 179 * | | |1 = OTP key 0 is used. 180 * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 181 * |[1] |KEY1 |OTP Key 1 Used Status 182 * | | |0 = OTP key 1 is unused. 183 * | | |1 = OTP key 1 is used. 184 * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 185 * |[2] |KEY2 |OTP Key 2 Used Status 186 * | | |0 = OTP key 2 is unused. 187 * | | |1 = OTP key 2 is used. 188 * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 189 * |[3] |KEY3 |OTP Key 3 Used Status 190 * | | |0 = OTP key 3 is unused. 191 * | | |1 = OTP key 3 is used. 192 * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 193 * |[4] |KEY4 |OTP Key 4 Used Status 194 * | | |0 = OTP key 4 is unused. 195 * | | |1 = OTP key 4 is used. 196 * | | |Note: If chip is changed to RMA stage, existing key will be revoked after initialization. 197 * |[5] |KEY5 |OTP Key 5 Used Status 198 * | | |0 = OTP key 5 is unused. 199 * | | |1 = OTP key 5 is used. 200 * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 201 * |[6] |KEY6 |OTP Key 6 Used Status 202 * | | |0 = OTP key 6 is unused. 203 * | | |1 = OTP key 6 is used. 204 * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 205 * |[7] |KEY7 |OTP Key 7 Used Status 206 * | | |0 = OTP key 7 is unused. 207 * | | |1 = OTP key 7 is used. 208 * | | |Note: If chip is changed to RMA stage, the existing key will be revoked after initialization. 209 * @var KS_T::REMKCNT 210 * Offset: 0x44 Key Store Remaining Key Count Register 211 * --------------------------------------------------------------------------------------------------- 212 * |Bits |Field |Descriptions 213 * | :----: | :----: | :---- | 214 * |[5:0] |RRMKCNT |Key Store SRAM Remaining Key Count 215 * | | |The RRMKCNT shows the remaining key count for SRAM. 216 * |[21:16] |FRMKCNT |Key Store Flash Remaining Key Count 217 * | | |The FRMKCNT shows the remaining key count for Flash. 218 */ 219 __IO uint32_t CTL; /*!< [0x0000] Key Store Control Register */ 220 __IO uint32_t METADATA; /*!< [0x0004] Key Store Metadata Register */ 221 __IO uint32_t STS; /*!< [0x0008] Key Store Status Register */ 222 __I uint32_t REMAIN; /*!< [0x000c] Key Store Remaining Space Register */ 223 __IO uint32_t SCMBKEY[4]; /*!< [0x0010 ~ 0x001c] Key Store Scramble Key Word 0 Register */ 224 __IO uint32_t KEY[8]; /*!< [0x0020 ~ 0x003c] Key Store Entry Key Word 0 Register */ 225 __I uint32_t OTPSTS; /*!< [0x0040] Key Store OTP Keys Status Register */ 226 __I uint32_t REMKCNT; /*!< [0x0044] Key Store Remaining Key Count Register */ 227 228 } KS_T; 229 230 /** 231 @addtogroup KS_CONST KS Bit Field Definition 232 Constant Definitions for KS Controller 233 @{ 234 */ 235 236 #define KS_CTL_START_Pos (0) /*!< KS_T::CTL: START Position */ 237 #define KS_CTL_START_Msk (0x1ul << KS_CTL_START_Pos) /*!< KS_T::CTL: START Mask */ 238 239 #define KS_CTL_OPMODE_Pos (1) /*!< KS_T::CTL: OPMODE Position */ 240 #define KS_CTL_OPMODE_Msk (0x7ul << KS_CTL_OPMODE_Pos) /*!< KS_T::CTL: OPMODE Mask */ 241 242 #define KS_CTL_CONT_Pos (7) /*!< KS_T::CTL: CONT Position */ 243 #define KS_CTL_CONT_Msk (0x1ul << KS_CTL_CONT_Pos) /*!< KS_T::CTL: CONT Mask */ 244 245 #define KS_CTL_INIT_Pos (8) /*!< KS_T::CTL: INIT Position */ 246 #define KS_CTL_INIT_Msk (0x1ul << KS_CTL_INIT_Pos) /*!< KS_T::CTL: INIT Mask */ 247 248 #define KS_CTL_SILENT_Pos (10) /*!< KS_T::CTL: SILENT Position */ 249 #define KS_CTL_SILENT_Msk (0x1ul << KS_CTL_SILENT_Pos) /*!< KS_T::CTL: SILENT Mask */ 250 251 #define KS_CTL_SCMB_Pos (11) /*!< KS_T::CTL: SCMB Position */ 252 #define KS_CTL_SCMB_Msk (0x1ul << KS_CTL_SCMB_Pos) /*!< KS_T::CTL: SCMB Mask */ 253 254 #define KS_CTL_IEN_Pos (15) /*!< KS_T::CTL: IEN Position */ 255 #define KS_CTL_IEN_Msk (0x1ul << KS_CTL_IEN_Pos) /*!< KS_T::CTL: IEN Mask */ 256 257 #define KS_METADATA_SEC_Pos (0) /*!< KS_T::METADATA: SEC Position */ 258 #define KS_METADATA_SEC_Msk (0x1ul << KS_METADATA_SEC_Pos) /*!< KS_T::METADATA: SEC Mask */ 259 260 #define KS_METADATA_PRIV_Pos (1) /*!< KS_T::METADATA: PRIV Position */ 261 #define KS_METADATA_PRIV_Msk (0x1ul << KS_METADATA_PRIV_Pos) /*!< KS_T::METADATA: PRIV Mask */ 262 263 #define KS_METADATA_READABLE_Pos (2) /*!< KS_T::METADATA: READABLE Position */ 264 #define KS_METADATA_READABLE_Msk (0x1ul << KS_METADATA_READABLE_Pos) /*!< KS_T::METADATA: READABLE Mask */ 265 266 #define KS_METADATA_RVK_Pos (3) /*!< KS_T::METADATA: RVK Position */ 267 #define KS_METADATA_RVK_Msk (0x1ul << KS_METADATA_RVK_Pos) /*!< KS_T::METADATA: RVK Mask */ 268 269 #define KS_METADATA_BS_Pos (4) /*!< KS_T::METADATA: BS Position */ 270 #define KS_METADATA_BS_Msk (0x1ul << KS_METADATA_BS_Pos) /*!< KS_T::METADATA: BS Mask */ 271 272 #define KS_METADATA_SIZE_Pos (8) /*!< KS_T::METADATA: SIZE Position */ 273 #define KS_METADATA_SIZE_Msk (0x1ful << KS_METADATA_SIZE_Pos) /*!< KS_T::METADATA: SIZE Mask */ 274 275 #define KS_METADATA_OWNER_Pos (16) /*!< KS_T::METADATA: OWNER Position */ 276 #define KS_METADATA_OWNER_Msk (0x7ul << KS_METADATA_OWNER_Pos) /*!< KS_T::METADATA: OWNER Mask */ 277 278 #define KS_METADATA_NUMBER_Pos (20) /*!< KS_T::METADATA: NUMBER Position */ 279 #define KS_METADATA_NUMBER_Msk (0x3ful << KS_METADATA_NUMBER_Pos) /*!< KS_T::METADATA: NUMBER Mask */ 280 281 #define KS_METADATA_DST_Pos (30) /*!< KS_T::METADATA: DST Position */ 282 #define KS_METADATA_DST_Msk (0x3ul << KS_METADATA_DST_Pos) /*!< KS_T::METADATA: DST Mask */ 283 284 #define KS_STS_IF_Pos (0) /*!< KS_T::STS: IF Position */ 285 #define KS_STS_IF_Msk (0x1ul << KS_STS_IF_Pos) /*!< KS_T::STS: IF Mask */ 286 287 #define KS_STS_EIF_Pos (1) /*!< KS_T::STS: EIF Position */ 288 #define KS_STS_EIF_Msk (0x1ul << KS_STS_EIF_Pos) /*!< KS_T::STS: EIF Mask */ 289 290 #define KS_STS_BUSY_Pos (2) /*!< KS_T::STS: BUSY Position */ 291 #define KS_STS_BUSY_Msk (0x1ul << KS_STS_BUSY_Pos) /*!< KS_T::STS: BUSY Mask */ 292 293 #define KS_STS_SRAMFULL_Pos (3) /*!< KS_T::STS: SRAMFULL Position */ 294 #define KS_STS_SRAMFULL_Msk (0x1ul << KS_STS_SRAMFULL_Pos) /*!< KS_T::STS: SRAMFULL Mask */ 295 296 #define KS_STS_FLASHFULL_Pos (4) /*!< KS_T::STS: FLASHFULL Position */ 297 #define KS_STS_FLASHFULL_Msk (0x1ul << KS_STS_FLASHFULL_Pos) /*!< KS_T::STS: FLASHFULL Mask */ 298 299 #define KS_STS_INITDONE_Pos (7) /*!< KS_T::STS: INITDONE Position */ 300 #define KS_STS_INITDONE_Msk (0x1ul << KS_STS_INITDONE_Pos) /*!< KS_T::STS: INITDONE Mask */ 301 302 #define KS_STS_RAMINV_Pos (8) /*!< KS_T::STS: RAMINV Position */ 303 #define KS_STS_RAMINV_Msk (0x1ul << KS_STS_RAMINV_Pos) /*!< KS_T::STS: RAMINV Mask */ 304 305 #define KS_REMAIN_RRMNG_Pos (0) /*!< KS_T::REMAIN: RRMNG Position */ 306 #define KS_REMAIN_RRMNG_Msk (0x1ffful << KS_REMAIN_RRMNG_Pos) /*!< KS_T::REMAIN: RRMNG Mask */ 307 308 #define KS_REMAIN_FRMNG_Pos (16) /*!< KS_T::REMAIN: FRMNG Position */ 309 #define KS_REMAIN_FRMNG_Msk (0xffful << KS_REMAIN_FRMNG_Pos) /*!< KS_T::REMAIN: FRMNG Mask */ 310 311 #define KS_SCMBKEY0_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY0: SCMBKEY Position */ 312 #define KS_SCMBKEY0_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY0_SCMBKEY_Pos) /*!< KS_T::SCMBKEY0: SCMBKEY Mask */ 313 314 #define KS_SCMBKEY1_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY1: SCMBKEY Position */ 315 #define KS_SCMBKEY1_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY1_SCMBKEY_Pos) /*!< KS_T::SCMBKEY1: SCMBKEY Mask */ 316 317 #define KS_SCMBKEY2_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY2: SCMBKEY Position */ 318 #define KS_SCMBKEY2_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY2_SCMBKEY_Pos) /*!< KS_T::SCMBKEY2: SCMBKEY Mask */ 319 320 #define KS_SCMBKEY3_SCMBKEY_Pos (0) /*!< KS_T::SCMBKEY3: SCMBKEY Position */ 321 #define KS_SCMBKEY3_SCMBKEY_Msk (0xfffffffful << KS_SCMBKEY3_SCMBKEY_Pos) /*!< KS_T::SCMBKEY3: SCMBKEY Mask */ 322 323 #define KS_KEY0_KEY_Pos (0) /*!< KS_T::KEY0: KEY Position */ 324 #define KS_KEY0_KEY_Msk (0xfffffffful << KS_KEY0_KEY_Pos) /*!< KS_T::KEY0: KEY Mask */ 325 326 #define KS_KEY1_KEY_Pos (0) /*!< KS_T::KEY1: KEY Position */ 327 #define KS_KEY1_KEY_Msk (0xfffffffful << KS_KEY1_KEY_Pos) /*!< KS_T::KEY1: KEY Mask */ 328 329 #define KS_KEY2_KEY_Pos (0) /*!< KS_T::KEY2: KEY Position */ 330 #define KS_KEY2_KEY_Msk (0xfffffffful << KS_KEY2_KEY_Pos) /*!< KS_T::KEY2: KEY Mask */ 331 332 #define KS_KEY3_KEY_Pos (0) /*!< KS_T::KEY3: KEY Position */ 333 #define KS_KEY3_KEY_Msk (0xfffffffful << KS_KEY3_KEY_Pos) /*!< KS_T::KEY3: KEY Mask */ 334 335 #define KS_KEY4_KEY_Pos (0) /*!< KS_T::KEY4: KEY Position */ 336 #define KS_KEY4_KEY_Msk (0xfffffffful << KS_KEY4_KEY_Pos) /*!< KS_T::KEY4: KEY Mask */ 337 338 #define KS_KEY5_KEY_Pos (0) /*!< KS_T::KEY5: KEY Position */ 339 #define KS_KEY5_KEY_Msk (0xfffffffful << KS_KEY5_KEY_Pos) /*!< KS_T::KEY5: KEY Mask */ 340 341 #define KS_KEY6_KEY_Pos (0) /*!< KS_T::KEY6: KEY Position */ 342 #define KS_KEY6_KEY_Msk (0xfffffffful << KS_KEY6_KEY_Pos) /*!< KS_T::KEY6: KEY Mask */ 343 344 #define KS_KEY7_KEY_Pos (0) /*!< KS_T::KEY7: KEY Position */ 345 #define KS_KEY7_KEY_Msk (0xfffffffful << KS_KEY7_KEY_Pos) /*!< KS_T::KEY7: KEY Mask */ 346 347 #define KS_OTPSTS_KEY0_Pos (0) /*!< KS_T::OTPSTS: KEY0 Position */ 348 #define KS_OTPSTS_KEY0_Msk (0x1ul << KS_OTPSTS_KEY0_Pos) /*!< KS_T::OTPSTS: KEY0 Mask */ 349 350 #define KS_OTPSTS_KEY1_Pos (1) /*!< KS_T::OTPSTS: KEY1 Position */ 351 #define KS_OTPSTS_KEY1_Msk (0x1ul << KS_OTPSTS_KEY1_Pos) /*!< KS_T::OTPSTS: KEY1 Mask */ 352 353 #define KS_OTPSTS_KEY2_Pos (2) /*!< KS_T::OTPSTS: KEY2 Position */ 354 #define KS_OTPSTS_KEY2_Msk (0x1ul << KS_OTPSTS_KEY2_Pos) /*!< KS_T::OTPSTS: KEY2 Mask */ 355 356 #define KS_OTPSTS_KEY3_Pos (3) /*!< KS_T::OTPSTS: KEY3 Position */ 357 #define KS_OTPSTS_KEY3_Msk (0x1ul << KS_OTPSTS_KEY3_Pos) /*!< KS_T::OTPSTS: KEY3 Mask */ 358 359 #define KS_OTPSTS_KEY4_Pos (4) /*!< KS_T::OTPSTS: KEY4 Position */ 360 #define KS_OTPSTS_KEY4_Msk (0x1ul << KS_OTPSTS_KEY4_Pos) /*!< KS_T::OTPSTS: KEY4 Mask */ 361 362 #define KS_OTPSTS_KEY5_Pos (5) /*!< KS_T::OTPSTS: KEY5 Position */ 363 #define KS_OTPSTS_KEY5_Msk (0x1ul << KS_OTPSTS_KEY5_Pos) /*!< KS_T::OTPSTS: KEY5 Mask */ 364 365 #define KS_OTPSTS_KEY6_Pos (6) /*!< KS_T::OTPSTS: KEY6 Position */ 366 #define KS_OTPSTS_KEY6_Msk (0x1ul << KS_OTPSTS_KEY6_Pos) /*!< KS_T::OTPSTS: KEY6 Mask */ 367 368 #define KS_OTPSTS_KEY7_Pos (7) /*!< KS_T::OTPSTS: KEY7 Position */ 369 #define KS_OTPSTS_KEY7_Msk (0x1ul << KS_OTPSTS_KEY7_Pos) /*!< KS_T::OTPSTS: KEY7 Mask */ 370 371 #define KS_REMKCNT_RRMKCNT_Pos (0) /*!< KS_T::REMKCNT: RRMKCNT Position */ 372 #define KS_REMKCNT_RRMKCNT_Msk (0x3ful << KS_REMKCNT_RRMKCNT_Pos) /*!< KS_T::REMKCNT: RRMKCNT Mask */ 373 374 #define KS_REMKCNT_FRMKCNT_Pos (16) /*!< KS_T::REMKCNT: FRMKCNT Position */ 375 #define KS_REMKCNT_FRMKCNT_Msk (0x3ful << KS_REMKCNT_FRMKCNT_Pos) /*!< KS_T::REMKCNT: FRMKCNT Mask */ 376 377 378 /**@}*/ /* KS_CONST */ 379 /**@}*/ /* end of KS register group */ 380 381 382 /**@}*/ /* end of REGISTER group */ 383 384 #endif /* __KEYSTORE_REG_H__ */ 385
