1 /**************************************************************************//** 2 * @file ewdt_reg.h 3 * @version V1.00 4 * @brief EWDT register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EWDT_REG_H__ 10 #define __EWDT_REG_H__ 11 12 /** 13 @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 20 /*---------------------- Extra Watch Dog Timer Controller -------------------------*/ 21 /** 22 @addtogroup EWDT Extra Watch Dog Timer Controller(EWDT) 23 Memory Mapped Structure for EWDT Controller 24 @{ 25 */ 26 27 typedef struct 28 { 29 30 31 /** 32 * @var EWDT_T::CTL 33 * Offset: 0x00 EWDT Control Register 34 * --------------------------------------------------------------------------------------------------- 35 * |Bits |Field |Descriptions 36 * | :----: | :----: | :---- | 37 * |[1] |RSTEN |EWDT Time-out Reset Enable Control (Write Protect) 38 * | | |Setting this bit will enable the EWDT time-out reset system function If the EWDT up counter value has not been cleared after the specific EWDT reset delay period expires. 39 * | | |0 = EWDT time-out reset system function Disabled. 40 * | | |1 = EWDT time-out reset system function Enabled. 41 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 42 * |[2] |RSTF |EWDT Time-out Reset Flag 43 * | | |This bit indicates the system has been reset by EWDT time-out reset system event or not. 44 * | | |0 = EWDT time-out reset system event did not occur. 45 * | | |1 = EWDT time-out reset system event has been occurred. 46 * | | |Note: This bit is cleared by writing 1 to it. 47 * |[3] |IF |EWDT Time-out Interrupt Flag 48 * | | |This bit will set to 1 while EWDT up counter value reaches the selected EWDT time-out interval 49 * | | |0 = EWDT time-out interrupt event interrupt did not occur. 50 * | | |1 = EWDT time-out interrupt interrupt event occurred. 51 * | | |Note: This bit is cleared by writing 1 to it. 52 * |[4] |WKEN |EWDT Time-out Wake-up Function Control (Write Protect) 53 * | | |If this bit is set to 1, while EWDT time-out interrupt flag IF (EWDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (EWDT_CTL[6]) is enabled, the EWDT time-out interrupt signal will generate a event to trigger CPU wake-up trigger event to chip. 54 * | | |0 = Trigger Wake-up trigger event function Disabled if EWDT time-out interrupt signal generated. 55 * | | |1 = Trigger Wake-up trigger event function Enabled if EWDT time-out interrupt signal generated. 56 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 57 * | | |Note2: Chip can be woken-up by while EWDT time-out interrupt signal generated only if EWDT clock source is selected to LIRC or LXT (32 kHz). 58 * |[5] |WKF |EWDT Time-out Wake-up Flag (Write Protect) 59 * | | |This bit indicates the EWDT time-out event has triggered interrupt chip wake-up or not.flag status of EWDT 60 * | | |0 = WDT does not cause chip wake-up. 61 * | | |1 = Chip wake-up from Idle or Power-down mode if when WDT time-out interrupt signal is generated. 62 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 63 * | | |Note2: This bit is cleared by writing 1 to it. 64 * |[6] |INTEN |WDT Time-out Interrupt Enable Control (Write Protect) 65 * | | |If this bit is enabled, when WDT time-out event occurs, the IF (WDT_CTL[3]) will be set to 1 and the WDT time-out interrupt signal is generated and inform to CPU. 66 * | | |0 = WDT time-out interrupt Disabled. 67 * | | |1 = WDT time-out interrupt Enabled. 68 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 69 * |[7] |WDTEN |WDT Enable Control (Write Protect) 70 * | | |0 = Set WDT counter stop Disabled, and (This action will reset the internal up counter value will be reset also). 71 * | | |1 = Set WDT counter start Enabled. 72 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 73 * | | |Note2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active, user can read SYNC (WDT_CTL[30]) to check enable/disable command is completed or not. 74 * | | |Note32: If CWDTEN[2:0] (combined by with Config0[31] and Config0[4:3]) bits is not configure to 0x111, this bit is forced as 1 and user cannot change this bit to 0. 75 * | | |Note3: This bit disabled needs 2 * WDT_CLK. 76 * |[11:8] |TOUTSEL |WDT Time-out Interval Selection (Write Protect) 77 * | | |These three bits select the time-out interval period after for the WDT starts counting. 78 * | | |000 = 2^4 * WDT_CLK. 79 * | | |001 = 2^6 * WDT_CLK. 80 * | | |010 = 2^8 * WDT_CLK. 81 * | | |011 = 2^10 * WDT_CLK. 82 * | | |100 = 2^12 * WDT_CLK. 83 * | | |101 = 2^14 * WDT_CLK. 84 * | | |110 = 2^16 * WDT_CLK. 85 * | | |111 = 2^18 * WDT_CLK. 86 * | | |111 = 2^20 * WDT_CLK. 87 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 88 * |[30] |SYNC |WDT Enable Control SYNC SYNC Flag Indicator (Read Only) 89 * | | |If use to synchronization, software er can check execute enable/disable this flag after enable WDTEN (WDT_CTL[7]), this flag can be indicated enable/disable WDTEN function is become completed or not active or not.. 90 * | | |SYNC delay is 91 * | | |0 = Set WDTEN bit is WDT enable control synccompletedhronizing is completion. 92 * | | |1 = Set WDTEN bit WDT enable control is synchronizing and not become active yet.. 93 * | | |Note: Perform enable or disable WDTEN bit 94 * | | |This bit enabled needs 2 * WDT_CLK period to become active. 95 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect) 96 * | | |0 = ICE debug mode acknowledgment affects WDT counting. 97 * | | |WDT up counter will be held while CPU is held by ICE. 98 * | | |1 = ICE debug mode acknowledgment Disabled. 99 * | | |WDT up counter will keep going no matter CPU is held by ICE or not. 100 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 101 * @var EWDT_T::ALTCTL 102 * Offset: 0x04 EWDT Alternative Control Register 103 * --------------------------------------------------------------------------------------------------- 104 * |Bits |Field |Descriptions 105 * | :----: | :----: | :---- | 106 * |[1:0] |RSTDSEL |WDT Reset Delay Period Selection (Write Protect) 107 * | | |When WDT time-out event happened, user has a time named WDT Reset Delay Period to clear execute WDT counter by setting RSTCNT (WDT_CTL[0]) reset to prevent WDT time-out reset system occurred happened 108 * | | |User can select a suitable setting of RSTDSEL for different application program WDT Reset Delay Period. 109 * | | |00 = WDT Reset Delay Period is 1026 * WDT_CLK. 110 * | | |01 = WDT Reset Delay Period is 130 * WDT_CLK. 111 * | | |10 = WDT Reset Delay Period is 18 * WDT_CLK. 112 * | | |11 = WDT Reset Delay Period is 3 * WDT_CLK. 113 * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. 114 * | | |Note2: This register will be reset to 0 if WDT time-out reset system event occurred happened. 115 * @var EWDT_T::RSTCNT 116 * Offset: 0x08 EWDT Reset Counter Register 117 * --------------------------------------------------------------------------------------------------- 118 * |Bits |Field |Descriptions 119 * | :----: | :----: | :---- | 120 * |[31:0] |RSTCNT |WDT Reset Counter Register 121 * | | |Writing 0x00005AA5 to this register field will reset the internal 18-bit WDT up counter value to 0. 122 * | | |Note: This WDT_RSTCNT is not write protected, but this RSTCNT (WDT_CTL[0]) is write protected. 123 * | | |Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active. 124 */ 125 __IO uint32_t CTL; /*!< [0x0000] EWDT Control Register */ 126 __IO uint32_t ALTCTL; /*!< [0x0004] EWDT Alternative Control Register */ 127 __O uint32_t RSTCNT; /*!< [0x0008] EWDT Reset Counter Register */ 128 129 } EWDT_T; 130 131 /** 132 @addtogroup EWDT_CONST WDT Bit Field Definition 133 Constant Definitions for EWDT Controller 134 @{ 135 */ 136 137 #define EWDT_CTL_RSTEN_Pos (1) /*!< EWDT_T::CTL: RSTEN Position */ 138 #define EWDT_CTL_RSTEN_Msk (0x1ul << EWDT_CTL_RSTEN_Pos) /*!< EWDT_T::CTL: RSTEN Mask */ 139 140 #define EWDT_CTL_RSTF_Pos (2) /*!< EWDT_T::CTL: RSTF Position */ 141 #define EWDT_CTL_RSTF_Msk (0x1ul << EWDT_CTL_RSTF_Pos) /*!< EWDT_T::CTL: RSTF Mask */ 142 143 #define EWDT_CTL_IF_Pos (3) /*!< EWDT_T::CTL: IF Position */ 144 #define EWDT_CTL_IF_Msk (0x1ul << EWDT_CTL_IF_Pos) /*!< EWDT_T::CTL: IF Mask */ 145 146 #define EWDT_CTL_WKEN_Pos (4) /*!< EWDT_T::CTL: WKEN Position */ 147 #define EWDT_CTL_WKEN_Msk (0x1ul << EWDT_CTL_WKEN_Pos) /*!< EWDT_T::CTL: WKEN Mask */ 148 149 #define EWDT_CTL_WKF_Pos (5) /*!< EWDT_T::CTL: WKF Position */ 150 #define EWDT_CTL_WKF_Msk (0x1ul << EWDT_CTL_WKF_Pos) /*!< EWDT_T::CTL: WKF Mask */ 151 152 #define EWDT_CTL_INTEN_Pos (6) /*!< EWDT_T::CTL: INTEN Position */ 153 #define EWDT_CTL_INTEN_Msk (0x1ul << EWDT_CTL_INTEN_Pos) /*!< EWDT_T::CTL: INTEN Mask */ 154 155 #define EWDT_CTL_WDTEN_Pos (7) /*!< EWDT_T::CTL: WDTEN Position */ 156 #define EWDT_CTL_WDTEN_Msk (0x1ul << EWDT_CTL_WDTEN_Pos) /*!< EWDT_T::CTL: WDTEN Mask */ 157 158 #define EWDT_CTL_TOUTSEL_Pos (8) /*!< EWDT_T::CTL: TOUTSEL Position */ 159 #define EWDT_CTL_TOUTSEL_Msk (0xful << EWDT_CTL_TOUTSEL_Pos) /*!< EWDT_T::CTL: TOUTSEL Mask */ 160 161 #define EWDT_CTL_SYNC_Pos (30) /*!< EWDT_T::CTL: SYNC Position */ 162 #define EWDT_CTL_SYNC_Msk (0x1ul << EWDT_CTL_SYNC_Pos) /*!< EWDT_T::CTL: SYNC Mask */ 163 164 #define EWDT_CTL_ICEDEBUG_Pos (31) /*!< EWDT_T::CTL: ICEDEBUG Position */ 165 #define EWDT_CTL_ICEDEBUG_Msk (0x1ul << EWDT_CTL_ICEDEBUG_Pos) /*!< EWDT_T::CTL: ICEDEBUG Mask */ 166 167 #define EWDT_ALTCTL_RSTDSEL_Pos (0) /*!< EWDT_T::ALTCTL: RSTDSEL Position */ 168 #define EWDT_ALTCTL_RSTDSEL_Msk (0x3ul << EWDT_ALTCTL_RSTDSEL_Pos) /*!< EWDT_T::ALTCTL: RSTDSEL Mask */ 169 170 #define EWDT_RSTCNT_RSTCNT_Pos (0) /*!< EWDT_T::RSTCNT: RSTCNT Position */ 171 #define EWDT_RSTCNT_RSTCNT_Msk (0xfffffffful << EWDT_RSTCNT_RSTCNT_Pos) /*!< EWDT_T::RSTCNT: RSTCNT Mask */ 172 173 174 /**@}*/ /* EWDT_CONST */ 175 /**@}*/ /* end of EWDT register group */ 176 /**@}*/ /* end of REGISTER group */ 177 178 #endif /* __EWDT_REG_H__ */ 179
