1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DX_CRYS_KERNEL_H__ 8 #define __DX_CRYS_KERNEL_H__ 9 // -------------------------------------- 10 // BLOCK: AES 11 // -------------------------------------- 12 #define DX_AES_KEY_0_0_REG_OFFSET 0x0400UL 13 #define DX_AES_KEY_0_0_VALUE_BIT_SHIFT 0x0UL 14 #define DX_AES_KEY_0_0_VALUE_BIT_SIZE 0x20UL 15 #define DX_AES_KEY_0_1_REG_OFFSET 0x0404UL 16 #define DX_AES_KEY_0_1_VALUE_BIT_SHIFT 0x0UL 17 #define DX_AES_KEY_0_1_VALUE_BIT_SIZE 0x20UL 18 #define DX_AES_KEY_0_2_REG_OFFSET 0x0408UL 19 #define DX_AES_KEY_0_2_VALUE_BIT_SHIFT 0x0UL 20 #define DX_AES_KEY_0_2_VALUE_BIT_SIZE 0x20UL 21 #define DX_AES_KEY_0_3_REG_OFFSET 0x040CUL 22 #define DX_AES_KEY_0_3_VALUE_BIT_SHIFT 0x0UL 23 #define DX_AES_KEY_0_3_VALUE_BIT_SIZE 0x20UL 24 #define DX_AES_KEY_0_4_REG_OFFSET 0x0410UL 25 #define DX_AES_KEY_0_4_VALUE_BIT_SHIFT 0x0UL 26 #define DX_AES_KEY_0_4_VALUE_BIT_SIZE 0x20UL 27 #define DX_AES_KEY_0_5_REG_OFFSET 0x0414UL 28 #define DX_AES_KEY_0_5_VALUE_BIT_SHIFT 0x0UL 29 #define DX_AES_KEY_0_5_VALUE_BIT_SIZE 0x20UL 30 #define DX_AES_KEY_0_6_REG_OFFSET 0x0418UL 31 #define DX_AES_KEY_0_6_VALUE_BIT_SHIFT 0x0UL 32 #define DX_AES_KEY_0_6_VALUE_BIT_SIZE 0x20UL 33 #define DX_AES_KEY_0_7_REG_OFFSET 0x041CUL 34 #define DX_AES_KEY_0_7_VALUE_BIT_SHIFT 0x0UL 35 #define DX_AES_KEY_0_7_VALUE_BIT_SIZE 0x20UL 36 #define DX_AES_KEY_1_0_REG_OFFSET 0x0420UL 37 #define DX_AES_KEY_1_0_VALUE_BIT_SHIFT 0x0UL 38 #define DX_AES_KEY_1_0_VALUE_BIT_SIZE 0x20UL 39 #define DX_AES_KEY_1_1_REG_OFFSET 0x0424UL 40 #define DX_AES_KEY_1_1_VALUE_BIT_SHIFT 0x0UL 41 #define DX_AES_KEY_1_1_VALUE_BIT_SIZE 0x20UL 42 #define DX_AES_KEY_1_2_REG_OFFSET 0x0428UL 43 #define DX_AES_KEY_1_2_VALUE_BIT_SHIFT 0x0UL 44 #define DX_AES_KEY_1_2_VALUE_BIT_SIZE 0x20UL 45 #define DX_AES_KEY_1_3_REG_OFFSET 0x042CUL 46 #define DX_AES_KEY_1_3_VALUE_BIT_SHIFT 0x0UL 47 #define DX_AES_KEY_1_3_VALUE_BIT_SIZE 0x20UL 48 #define DX_AES_KEY_1_4_REG_OFFSET 0x0430UL 49 #define DX_AES_KEY_1_4_VALUE_BIT_SHIFT 0x0UL 50 #define DX_AES_KEY_1_4_VALUE_BIT_SIZE 0x20UL 51 #define DX_AES_KEY_1_5_REG_OFFSET 0x0434UL 52 #define DX_AES_KEY_1_5_VALUE_BIT_SHIFT 0x0UL 53 #define DX_AES_KEY_1_5_VALUE_BIT_SIZE 0x20UL 54 #define DX_AES_KEY_1_6_REG_OFFSET 0x0438UL 55 #define DX_AES_KEY_1_6_VALUE_BIT_SHIFT 0x0UL 56 #define DX_AES_KEY_1_6_VALUE_BIT_SIZE 0x20UL 57 #define DX_AES_KEY_1_7_REG_OFFSET 0x043CUL 58 #define DX_AES_KEY_1_7_VALUE_BIT_SHIFT 0x0UL 59 #define DX_AES_KEY_1_7_VALUE_BIT_SIZE 0x20UL 60 #define DX_AES_IV_0_0_REG_OFFSET 0x0440UL 61 #define DX_AES_IV_0_0_VALUE_BIT_SHIFT 0x0UL 62 #define DX_AES_IV_0_0_VALUE_BIT_SIZE 0x20UL 63 #define DX_AES_IV_0_1_REG_OFFSET 0x0444UL 64 #define DX_AES_IV_0_1_VALUE_BIT_SHIFT 0x0UL 65 #define DX_AES_IV_0_1_VALUE_BIT_SIZE 0x20UL 66 #define DX_AES_IV_0_2_REG_OFFSET 0x0448UL 67 #define DX_AES_IV_0_2_VALUE_BIT_SHIFT 0x0UL 68 #define DX_AES_IV_0_2_VALUE_BIT_SIZE 0x20UL 69 #define DX_AES_IV_0_3_REG_OFFSET 0x044CUL 70 #define DX_AES_IV_0_3_VALUE_BIT_SHIFT 0x0UL 71 #define DX_AES_IV_0_3_VALUE_BIT_SIZE 0x20UL 72 #define DX_AES_IV_1_0_REG_OFFSET 0x0450UL 73 #define DX_AES_IV_1_0_VALUE_BIT_SHIFT 0x0UL 74 #define DX_AES_IV_1_0_VALUE_BIT_SIZE 0x20UL 75 #define DX_AES_IV_1_1_REG_OFFSET 0x0454UL 76 #define DX_AES_IV_1_1_VALUE_BIT_SHIFT 0x0UL 77 #define DX_AES_IV_1_1_VALUE_BIT_SIZE 0x20UL 78 #define DX_AES_IV_1_2_REG_OFFSET 0x0458UL 79 #define DX_AES_IV_1_2_VALUE_BIT_SHIFT 0x0UL 80 #define DX_AES_IV_1_2_VALUE_BIT_SIZE 0x20UL 81 #define DX_AES_IV_1_3_REG_OFFSET 0x045CUL 82 #define DX_AES_IV_1_3_VALUE_BIT_SHIFT 0x0UL 83 #define DX_AES_IV_1_3_VALUE_BIT_SIZE 0x20UL 84 #define DX_AES_CTR_0_0_REG_OFFSET 0x0460UL 85 #define DX_AES_CTR_0_0_VALUE_BIT_SHIFT 0x0UL 86 #define DX_AES_CTR_0_0_VALUE_BIT_SIZE 0x20UL 87 #define DX_AES_CTR_0_1_REG_OFFSET 0x0464UL 88 #define DX_AES_CTR_0_1_VALUE_BIT_SHIFT 0x0UL 89 #define DX_AES_CTR_0_1_VALUE_BIT_SIZE 0x20UL 90 #define DX_AES_CTR_0_2_REG_OFFSET 0x0468UL 91 #define DX_AES_CTR_0_2_VALUE_BIT_SHIFT 0x0UL 92 #define DX_AES_CTR_0_2_VALUE_BIT_SIZE 0x20UL 93 #define DX_AES_CTR_0_3_REG_OFFSET 0x046CUL 94 #define DX_AES_CTR_0_3_VALUE_BIT_SHIFT 0x0UL 95 #define DX_AES_CTR_0_3_VALUE_BIT_SIZE 0x20UL 96 #define DX_AES_BUSY_REG_OFFSET 0x0470UL 97 #define DX_AES_BUSY_VALUE_BIT_SHIFT 0x0UL 98 #define DX_AES_BUSY_VALUE_BIT_SIZE 0x1UL 99 #define DX_AES_SK_REG_OFFSET 0x0478UL 100 #define DX_AES_SK_VALUE_BIT_SHIFT 0x0UL 101 #define DX_AES_SK_VALUE_BIT_SIZE 0x1UL 102 #define DX_AES_CMAC_INIT_REG_OFFSET 0x047CUL 103 #define DX_AES_CMAC_INIT_VALUE_BIT_SHIFT 0x0UL 104 #define DX_AES_CMAC_INIT_VALUE_BIT_SIZE 0x1UL 105 #define DX_AES_SK1_REG_OFFSET 0x04B4UL 106 #define DX_AES_SK1_VALUE_BIT_SHIFT 0x0UL 107 #define DX_AES_SK1_VALUE_BIT_SIZE 0x1UL 108 #define DX_AES_REMAINING_BYTES_REG_OFFSET 0x04BCUL 109 #define DX_AES_REMAINING_BYTES_VALUE_BIT_SHIFT 0x0UL 110 #define DX_AES_REMAINING_BYTES_VALUE_BIT_SIZE 0x20UL 111 #define DX_AES_CONTROL_REG_OFFSET 0x04C0UL 112 #define DX_AES_CONTROL_DEC_KEY0_BIT_SHIFT 0x0UL 113 #define DX_AES_CONTROL_DEC_KEY0_BIT_SIZE 0x1UL 114 #define DX_AES_CONTROL_MODE0_IS_CBC_CTS_BIT_SHIFT 0x1UL 115 #define DX_AES_CONTROL_MODE0_IS_CBC_CTS_BIT_SIZE 0x1UL 116 #define DX_AES_CONTROL_MODE_KEY0_BIT_SHIFT 0x2UL 117 #define DX_AES_CONTROL_MODE_KEY0_BIT_SIZE 0x3UL 118 #define DX_AES_CONTROL_MODE_KEY1_BIT_SHIFT 0x5UL 119 #define DX_AES_CONTROL_MODE_KEY1_BIT_SIZE 0x3UL 120 #define DX_AES_CONTROL_CBC_IS_ESSIV_BIT_SHIFT 0x8UL 121 #define DX_AES_CONTROL_CBC_IS_ESSIV_BIT_SIZE 0x1UL 122 #define DX_AES_CONTROL_AES_TUNNEL_IS_ON_BIT_SHIFT 0xAUL 123 #define DX_AES_CONTROL_AES_TUNNEL_IS_ON_BIT_SIZE 0x1UL 124 #define DX_AES_CONTROL_CBC_IS_BITLOCKER_BIT_SHIFT 0xBUL 125 #define DX_AES_CONTROL_CBC_IS_BITLOCKER_BIT_SIZE 0x1UL 126 #define DX_AES_CONTROL_NK_KEY0_BIT_SHIFT 0xCUL 127 #define DX_AES_CONTROL_NK_KEY0_BIT_SIZE 0x2UL 128 #define DX_AES_CONTROL_NK_KEY1_BIT_SHIFT 0xEUL 129 #define DX_AES_CONTROL_NK_KEY1_BIT_SIZE 0x2UL 130 #define DX_AES_CONTROL_AES_TUNNEL1_DECRYPT_BIT_SHIFT 0x16UL 131 #define DX_AES_CONTROL_AES_TUNNEL1_DECRYPT_BIT_SIZE 0x1UL 132 #define DX_AES_CONTROL_AES_TUN_B1_USES_PADDED_DATA_IN_BIT_SHIFT 0x17UL 133 #define DX_AES_CONTROL_AES_TUN_B1_USES_PADDED_DATA_IN_BIT_SIZE 0x1UL 134 #define DX_AES_CONTROL_AES_TUNNEL0_ENCRYPT_BIT_SHIFT 0x18UL 135 #define DX_AES_CONTROL_AES_TUNNEL0_ENCRYPT_BIT_SIZE 0x1UL 136 #define DX_AES_CONTROL_AES_OUTPUT_MID_TUNNEL_DATA_BIT_SHIFT 0x19UL 137 #define DX_AES_CONTROL_AES_OUTPUT_MID_TUNNEL_DATA_BIT_SIZE 0x1UL 138 #define DX_AES_CONTROL_AES_TUNNEL_B1_PAD_EN_BIT_SHIFT 0x1AUL 139 #define DX_AES_CONTROL_AES_TUNNEL_B1_PAD_EN_BIT_SIZE 0x1UL 140 #define DX_AES_CONTROL_AES_OUT_MID_TUN_TO_HASH_BIT_SHIFT 0x1CUL 141 #define DX_AES_CONTROL_AES_OUT_MID_TUN_TO_HASH_BIT_SIZE 0x1UL 142 #define DX_AES_CONTROL_AES_XOR_CRYPTOKEY_BIT_SHIFT 0x1DUL 143 #define DX_AES_CONTROL_AES_XOR_CRYPTOKEY_BIT_SIZE 0x1UL 144 #define DX_AES_CONTROL_DIRECT_ACCESS_BIT_SHIFT 0x1FUL 145 #define DX_AES_CONTROL_DIRECT_ACCESS_BIT_SIZE 0x1UL 146 #define DX_AES_HW_FLAGS_REG_OFFSET 0x04C8UL 147 #define DX_AES_HW_FLAGS_SUPPORT_256_192_KEY_BIT_SHIFT 0x0UL 148 #define DX_AES_HW_FLAGS_SUPPORT_256_192_KEY_BIT_SIZE 0x1UL 149 #define DX_AES_HW_FLAGS_AES_LARGE_RKEK_BIT_SHIFT 0x1UL 150 #define DX_AES_HW_FLAGS_AES_LARGE_RKEK_BIT_SIZE 0x1UL 151 #define DX_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_BIT_SHIFT 0x2UL 152 #define DX_AES_HW_FLAGS_DPA_CNTRMSR_EXIST_BIT_SIZE 0x1UL 153 #define DX_AES_HW_FLAGS_CTR_EXIST_BIT_SHIFT 0x3UL 154 #define DX_AES_HW_FLAGS_CTR_EXIST_BIT_SIZE 0x1UL 155 #define DX_AES_HW_FLAGS_ONLY_ENCRYPT_BIT_SHIFT 0x4UL 156 #define DX_AES_HW_FLAGS_ONLY_ENCRYPT_BIT_SIZE 0x1UL 157 #define DX_AES_HW_FLAGS_USE_SBOX_TABLE_BIT_SHIFT 0x5UL 158 #define DX_AES_HW_FLAGS_USE_SBOX_TABLE_BIT_SIZE 0x1UL 159 #define DX_AES_HW_FLAGS_USE_5_SBOXES_BIT_SHIFT 0x8UL 160 #define DX_AES_HW_FLAGS_USE_5_SBOXES_BIT_SIZE 0x1UL 161 #define DX_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_BIT_SHIFT 0x9UL 162 #define DX_AES_HW_FLAGS_AES_SUPPORT_PREV_IV_BIT_SIZE 0x1UL 163 #define DX_AES_HW_FLAGS_AES_TUNNEL_EXISTS_BIT_SHIFT 0xAUL 164 #define DX_AES_HW_FLAGS_AES_TUNNEL_EXISTS_BIT_SIZE 0x1UL 165 #define DX_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_BIT_SHIFT 0xBUL 166 #define DX_AES_HW_FLAGS_SECOND_REGS_SET_EXIST_BIT_SIZE 0x1UL 167 #define DX_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_BIT_SHIFT 0xCUL 168 #define DX_AES_HW_FLAGS_DFA_CNTRMSR_EXIST_BIT_SIZE 0x1UL 169 #define DX_AES_CTR_NO_INCREMENT_REG_OFFSET 0x04D8UL 170 #define DX_AES_CTR_NO_INCREMENT_VALUE_BIT_SHIFT 0x0UL 171 #define DX_AES_CTR_NO_INCREMENT_VALUE_BIT_SIZE 0x1UL 172 #define DX_AES_DFA_IS_ON_REG_OFFSET 0x04F0UL 173 #define DX_AES_DFA_IS_ON_VALUE_BIT_SHIFT 0x0UL 174 #define DX_AES_DFA_IS_ON_VALUE_BIT_SIZE 0x1UL 175 #define DX_AES_DFA_ERR_STATUS_REG_OFFSET 0x04F8UL 176 #define DX_AES_DFA_ERR_STATUS_VALUE_BIT_SHIFT 0x0UL 177 #define DX_AES_DFA_ERR_STATUS_VALUE_BIT_SIZE 0x1UL 178 #define DX_AES_CMAC_SIZE0_KICK_REG_OFFSET 0x0524UL 179 #define DX_AES_CMAC_SIZE0_KICK_VALUE_BIT_SHIFT 0x0UL 180 #define DX_AES_CMAC_SIZE0_KICK_VALUE_BIT_SIZE 0x1UL 181 // -------------------------------------- 182 // BLOCK: MISC 183 // -------------------------------------- 184 #define DX_AES_CLK_ENABLE_REG_OFFSET 0x0810UL 185 #define DX_AES_CLK_ENABLE_VALUE_BIT_SHIFT 0x0UL 186 #define DX_AES_CLK_ENABLE_VALUE_BIT_SIZE 0x1UL 187 #define DX_HASH_CLK_ENABLE_REG_OFFSET 0x0818UL 188 #define DX_HASH_CLK_ENABLE_VALUE_BIT_SHIFT 0x0UL 189 #define DX_HASH_CLK_ENABLE_VALUE_BIT_SIZE 0x1UL 190 #define DX_PKA_CLK_ENABLE_REG_OFFSET 0x081CUL 191 #define DX_PKA_CLK_ENABLE_VALUE_BIT_SHIFT 0x0UL 192 #define DX_PKA_CLK_ENABLE_VALUE_BIT_SIZE 0x1UL 193 #define DX_DMA_CLK_ENABLE_REG_OFFSET 0x0820UL 194 #define DX_DMA_CLK_ENABLE_VALUE_BIT_SHIFT 0x0UL 195 #define DX_DMA_CLK_ENABLE_VALUE_BIT_SIZE 0x1UL 196 #define DX_CLK_STATUS_REG_OFFSET 0x0824UL 197 #define DX_CLK_STATUS_AES_CLK_STATUS_BIT_SHIFT 0x0UL 198 #define DX_CLK_STATUS_AES_CLK_STATUS_BIT_SIZE 0x1UL 199 #define DX_CLK_STATUS_HASH_CLK_STATUS_BIT_SHIFT 0x2UL 200 #define DX_CLK_STATUS_HASH_CLK_STATUS_BIT_SIZE 0x1UL 201 #define DX_CLK_STATUS_PKA_CLK_STATUS_BIT_SHIFT 0x3UL 202 #define DX_CLK_STATUS_PKA_CLK_STATUS_BIT_SIZE 0x1UL 203 #define DX_CLK_STATUS_CHACHA_CLK_STATUS_BIT_SHIFT 0x7UL 204 #define DX_CLK_STATUS_CHACHA_CLK_STATUS_BIT_SIZE 0x1UL 205 #define DX_CLK_STATUS_DMA_CLK_STATUS_BIT_SHIFT 0x8UL 206 #define DX_CLK_STATUS_DMA_CLK_STATUS_BIT_SIZE 0x1UL 207 #define DX_CHACHA_CLK_ENABLE_REG_OFFSET 0x0858UL 208 #define DX_CHACHA_CLK_ENABLE_VALUE_BIT_SHIFT 0x0UL 209 #define DX_CHACHA_CLK_ENABLE_VALUE_BIT_SIZE 0x1UL 210 // -------------------------------------- 211 // BLOCK: CC_CTL 212 // -------------------------------------- 213 #define DX_CRYPTO_CTL_REG_OFFSET 0x0900UL 214 #define DX_CRYPTO_CTL_VALUE_BIT_SHIFT 0x0UL 215 #define DX_CRYPTO_CTL_VALUE_BIT_SIZE 0x5UL 216 #define DX_CRYPTO_BUSY_REG_OFFSET 0x0910UL 217 #define DX_CRYPTO_BUSY_VALUE_BIT_SHIFT 0x0UL 218 #define DX_CRYPTO_BUSY_VALUE_BIT_SIZE 0x1UL 219 #define DX_HASH_BUSY_REG_OFFSET 0x091CUL 220 #define DX_HASH_BUSY_VALUE_BIT_SHIFT 0x0UL 221 #define DX_HASH_BUSY_VALUE_BIT_SIZE 0x1UL 222 #define DX_CONTEXT_ID_REG_OFFSET 0x0930UL 223 #define DX_CONTEXT_ID_VALUE_BIT_SHIFT 0x0UL 224 #define DX_CONTEXT_ID_VALUE_BIT_SIZE 0x8UL 225 // -------------------------------------- 226 // BLOCK: DIN 227 // -------------------------------------- 228 #define DX_DIN_BUFFER_REG_OFFSET 0x0C00UL 229 #define DX_DIN_BUFFER_VALUE_BIT_SHIFT 0x0UL 230 #define DX_DIN_BUFFER_VALUE_BIT_SIZE 0x20UL 231 #define DX_DIN_MEM_DMA_BUSY_REG_OFFSET 0x0C20UL 232 #define DX_DIN_MEM_DMA_BUSY_VALUE_BIT_SHIFT 0x0UL 233 #define DX_DIN_MEM_DMA_BUSY_VALUE_BIT_SIZE 0x1UL 234 #define DX_SRC_LLI_WORD0_REG_OFFSET 0x0C28UL 235 #define DX_SRC_LLI_WORD0_VALUE_BIT_SHIFT 0x0UL 236 #define DX_SRC_LLI_WORD0_VALUE_BIT_SIZE 0x20UL 237 #define DX_SRC_LLI_WORD1_REG_OFFSET 0x0C2CUL 238 #define DX_SRC_LLI_WORD1_BYTES_NUM_BIT_SHIFT 0x0UL 239 #define DX_SRC_LLI_WORD1_BYTES_NUM_BIT_SIZE 0x1EUL 240 #define DX_SRC_LLI_WORD1_FIRST_BIT_SHIFT 0x1EUL 241 #define DX_SRC_LLI_WORD1_FIRST_BIT_SIZE 0x1UL 242 #define DX_SRC_LLI_WORD1_LAST_BIT_SHIFT 0x1FUL 243 #define DX_SRC_LLI_WORD1_LAST_BIT_SIZE 0x1UL 244 #define DX_SRAM_SRC_ADDR_REG_OFFSET 0x0C30UL 245 #define DX_SRAM_SRC_ADDR_VALUE_BIT_SHIFT 0x0UL 246 #define DX_SRAM_SRC_ADDR_VALUE_BIT_SIZE 0x20UL 247 #define DX_DIN_SRAM_BYTES_LEN_REG_OFFSET 0x0C34UL 248 #define DX_DIN_SRAM_BYTES_LEN_VALUE_BIT_SHIFT 0x0UL 249 #define DX_DIN_SRAM_BYTES_LEN_VALUE_BIT_SIZE 0x20UL 250 #define DX_DIN_SRAM_DMA_BUSY_REG_OFFSET 0x0C38UL 251 #define DX_DIN_SRAM_DMA_BUSY_VALUE_BIT_SHIFT 0x0UL 252 #define DX_DIN_SRAM_DMA_BUSY_VALUE_BIT_SIZE 0x1UL 253 #define DX_DIN_SRAM_ENDIANNESS_REG_OFFSET 0x0C3CUL 254 #define DX_DIN_SRAM_ENDIANNESS_VALUE_BIT_SHIFT 0x0UL 255 #define DX_DIN_SRAM_ENDIANNESS_VALUE_BIT_SIZE 0x1UL 256 #define DX_DIN_CPU_DATA_SIZE_REG_OFFSET 0x0C48UL 257 #define DX_DIN_CPU_DATA_SIZE_VALUE_BIT_SHIFT 0x0UL 258 #define DX_DIN_CPU_DATA_SIZE_VALUE_BIT_SIZE 0x10UL 259 #define DX_FIFO_IN_EMPTY_REG_OFFSET 0x0C50UL 260 #define DX_FIFO_IN_EMPTY_VALUE_BIT_SHIFT 0x0UL 261 #define DX_FIFO_IN_EMPTY_VALUE_BIT_SIZE 0x1UL 262 #define DX_DIN_FIFO_RST_PNTR_REG_OFFSET 0x0C58UL 263 #define DX_DIN_FIFO_RST_PNTR_VALUE_BIT_SHIFT 0x0UL 264 #define DX_DIN_FIFO_RST_PNTR_VALUE_BIT_SIZE 0x1UL 265 // -------------------------------------- 266 // BLOCK: DOUT 267 // -------------------------------------- 268 #define DX_DOUT_BUFFER_REG_OFFSET 0x0D00UL 269 #define DX_DOUT_BUFFER_VALUE_BIT_SHIFT 0x0UL 270 #define DX_DOUT_BUFFER_VALUE_BIT_SIZE 0x20UL 271 #define DX_DOUT_MEM_DMA_BUSY_REG_OFFSET 0x0D20UL 272 #define DX_DOUT_MEM_DMA_BUSY_VALUE_BIT_SHIFT 0x0UL 273 #define DX_DOUT_MEM_DMA_BUSY_VALUE_BIT_SIZE 0x1UL 274 #define DX_DST_LLI_WORD0_REG_OFFSET 0x0D28UL 275 #define DX_DST_LLI_WORD0_VALUE_BIT_SHIFT 0x0UL 276 #define DX_DST_LLI_WORD0_VALUE_BIT_SIZE 0x20UL 277 #define DX_DST_LLI_WORD1_REG_OFFSET 0x0D2CUL 278 #define DX_DST_LLI_WORD1_BYTES_NUM_BIT_SHIFT 0x0UL 279 #define DX_DST_LLI_WORD1_BYTES_NUM_BIT_SIZE 0x1EUL 280 #define DX_DST_LLI_WORD1_FIRST_BIT_SHIFT 0x1EUL 281 #define DX_DST_LLI_WORD1_FIRST_BIT_SIZE 0x1UL 282 #define DX_DST_LLI_WORD1_LAST_BIT_SHIFT 0x1FUL 283 #define DX_DST_LLI_WORD1_LAST_BIT_SIZE 0x1UL 284 #define DX_SRAM_DEST_ADDR_REG_OFFSET 0x0D30UL 285 #define DX_SRAM_DEST_ADDR_VALUE_BIT_SHIFT 0x0UL 286 #define DX_SRAM_DEST_ADDR_VALUE_BIT_SIZE 0x20UL 287 #define DX_DOUT_SRAM_BYTES_LEN_REG_OFFSET 0x0D34UL 288 #define DX_DOUT_SRAM_BYTES_LEN_VALUE_BIT_SHIFT 0x0UL 289 #define DX_DOUT_SRAM_BYTES_LEN_VALUE_BIT_SIZE 0x20UL 290 #define DX_DOUT_SRAM_DMA_BUSY_REG_OFFSET 0x0D38UL 291 #define DX_DOUT_SRAM_DMA_BUSY_VALUE_BIT_SHIFT 0x0UL 292 #define DX_DOUT_SRAM_DMA_BUSY_VALUE_BIT_SIZE 0x1UL 293 #define DX_DOUT_SRAM_ENDIANNESS_REG_OFFSET 0x0D3CUL 294 #define DX_DOUT_SRAM_ENDIANNESS_VALUE_BIT_SHIFT 0x0UL 295 #define DX_DOUT_SRAM_ENDIANNESS_VALUE_BIT_SIZE 0x1UL 296 #define DX_READ_ALIGN_LAST_REG_OFFSET 0x0D44UL 297 #define DX_READ_ALIGN_LAST_VALUE_BIT_SHIFT 0x0UL 298 #define DX_READ_ALIGN_LAST_VALUE_BIT_SIZE 0x1UL 299 #define DX_DOUT_FIFO_EMPTY_REG_OFFSET 0x0D50UL 300 #define DX_DOUT_FIFO_EMPTY_VALUE_BIT_SHIFT 0x0UL 301 #define DX_DOUT_FIFO_EMPTY_VALUE_BIT_SIZE 0x1UL 302 // -------------------------------------- 303 // BLOCK: HASH 304 // -------------------------------------- 305 #define DX_HASH_H0_REG_OFFSET 0x0640UL 306 #define DX_HASH_H0_VALUE_BIT_SHIFT 0x0UL 307 #define DX_HASH_H0_VALUE_BIT_SIZE 0x20UL 308 #define DX_HASH_H1_REG_OFFSET 0x0644UL 309 #define DX_HASH_H1_VALUE_BIT_SHIFT 0x0UL 310 #define DX_HASH_H1_VALUE_BIT_SIZE 0x20UL 311 #define DX_HASH_H2_REG_OFFSET 0x0648UL 312 #define DX_HASH_H2_VALUE_BIT_SHIFT 0x0UL 313 #define DX_HASH_H2_VALUE_BIT_SIZE 0x20UL 314 #define DX_HASH_H3_REG_OFFSET 0x064CUL 315 #define DX_HASH_H3_VALUE_BIT_SHIFT 0x0UL 316 #define DX_HASH_H3_VALUE_BIT_SIZE 0x20UL 317 #define DX_HASH_H4_REG_OFFSET 0x0650UL 318 #define DX_HASH_H4_VALUE_BIT_SHIFT 0x0UL 319 #define DX_HASH_H4_VALUE_BIT_SIZE 0x20UL 320 #define DX_HASH_H5_REG_OFFSET 0x0654UL 321 #define DX_HASH_H5_VALUE_BIT_SHIFT 0x0UL 322 #define DX_HASH_H5_VALUE_BIT_SIZE 0x20UL 323 #define DX_HASH_H6_REG_OFFSET 0x0658UL 324 #define DX_HASH_H6_VALUE_BIT_SHIFT 0x0UL 325 #define DX_HASH_H6_VALUE_BIT_SIZE 0x20UL 326 #define DX_HASH_H7_REG_OFFSET 0x065CUL 327 #define DX_HASH_H7_VALUE_BIT_SHIFT 0x0UL 328 #define DX_HASH_H7_VALUE_BIT_SIZE 0x20UL 329 #define DX_HASH_H8_REG_OFFSET 0x0660UL 330 #define DX_HASH_H8_VALUE_BIT_SHIFT 0x0UL 331 #define DX_HASH_H8_VALUE_BIT_SIZE 0x20UL 332 #define DX_AUTO_HW_PADDING_REG_OFFSET 0x0684UL 333 #define DX_AUTO_HW_PADDING_VALUE_BIT_SHIFT 0x0UL 334 #define DX_AUTO_HW_PADDING_VALUE_BIT_SIZE 0x1UL 335 #define DX_HASH_XOR_DIN_REG_OFFSET 0x0688UL 336 #define DX_HASH_XOR_DIN_VALUE_BIT_SHIFT 0x0UL 337 #define DX_HASH_XOR_DIN_VALUE_BIT_SIZE 0x20UL 338 #define DX_LOAD_INIT_STATE_REG_OFFSET 0x0694UL 339 #define DX_LOAD_INIT_STATE_VALUE_BIT_SHIFT 0x0UL 340 #define DX_LOAD_INIT_STATE_VALUE_BIT_SIZE 0x1UL 341 #define DX_HASH_SEL_AES_MAC_REG_OFFSET 0x06A4UL 342 #define DX_HASH_SEL_AES_MAC_HASH_SEL_AES_MAC_BIT_SHIFT 0x0UL 343 #define DX_HASH_SEL_AES_MAC_HASH_SEL_AES_MAC_BIT_SIZE 0x1UL 344 #define DX_HASH_SEL_AES_MAC_GHASH_SEL_BIT_SHIFT 0x1UL 345 #define DX_HASH_SEL_AES_MAC_GHASH_SEL_BIT_SIZE 0x1UL 346 #define DX_HASH_VERSION_REG_OFFSET 0x07B0UL 347 #define DX_HASH_VERSION_FIXES_BIT_SHIFT 0x0UL 348 #define DX_HASH_VERSION_FIXES_BIT_SIZE 0x8UL 349 #define DX_HASH_VERSION_MINOR_VERSION_NUMBER_BIT_SHIFT 0x8UL 350 #define DX_HASH_VERSION_MINOR_VERSION_NUMBER_BIT_SIZE 0x4UL 351 #define DX_HASH_VERSION_MAJOR_VERSION_NUMBER_BIT_SHIFT 0xCUL 352 #define DX_HASH_VERSION_MAJOR_VERSION_NUMBER_BIT_SIZE 0x4UL 353 #define DX_HASH_CONTROL_REG_OFFSET 0x07C0UL 354 #define DX_HASH_CONTROL_MODE_0_1_BIT_SHIFT 0x0UL 355 #define DX_HASH_CONTROL_MODE_0_1_BIT_SIZE 0x2UL 356 #define DX_HASH_CONTROL_MODE_3_BIT_SHIFT 0x3UL 357 #define DX_HASH_CONTROL_MODE_3_BIT_SIZE 0x1UL 358 #define DX_HASH_PAD_EN_REG_OFFSET 0x07C4UL 359 #define DX_HASH_PAD_EN_VALUE_BIT_SHIFT 0x0UL 360 #define DX_HASH_PAD_EN_VALUE_BIT_SIZE 0x1UL 361 #define DX_HASH_PAD_CFG_REG_OFFSET 0x07C8UL 362 #define DX_HASH_PAD_CFG_VALUE_BIT_SHIFT 0x2UL 363 #define DX_HASH_PAD_CFG_VALUE_BIT_SIZE 0x1UL 364 #define DX_HASH_CUR_LEN_0_REG_OFFSET 0x07CCUL 365 #define DX_HASH_CUR_LEN_0_VALUE_BIT_SHIFT 0x0UL 366 #define DX_HASH_CUR_LEN_0_VALUE_BIT_SIZE 0x20UL 367 #define DX_HASH_CUR_LEN_1_REG_OFFSET 0x07D0UL 368 #define DX_HASH_CUR_LEN_1_VALUE_BIT_SHIFT 0x0UL 369 #define DX_HASH_CUR_LEN_1_VALUE_BIT_SIZE 0x20UL 370 #define DX_HASH_PARAM_REG_OFFSET 0x07DCUL 371 #define DX_HASH_PARAM_CW_BIT_SHIFT 0x0UL 372 #define DX_HASH_PARAM_CW_BIT_SIZE 0x4UL 373 #define DX_HASH_PARAM_CH_BIT_SHIFT 0x4UL 374 #define DX_HASH_PARAM_CH_BIT_SIZE 0x4UL 375 #define DX_HASH_PARAM_DW_BIT_SHIFT 0x8UL 376 #define DX_HASH_PARAM_DW_BIT_SIZE 0x4UL 377 #define DX_HASH_PARAM_SHA_512_EXISTS_BIT_SHIFT 0xCUL 378 #define DX_HASH_PARAM_SHA_512_EXISTS_BIT_SIZE 0x1UL 379 #define DX_HASH_PARAM_PAD_EXISTS_BIT_SHIFT 0xDUL 380 #define DX_HASH_PARAM_PAD_EXISTS_BIT_SIZE 0x1UL 381 #define DX_HASH_PARAM_MD5_EXISTS_BIT_SHIFT 0xEUL 382 #define DX_HASH_PARAM_MD5_EXISTS_BIT_SIZE 0x1UL 383 #define DX_HASH_PARAM_HMAC_EXISTS_BIT_SHIFT 0xFUL 384 #define DX_HASH_PARAM_HMAC_EXISTS_BIT_SIZE 0x1UL 385 #define DX_HASH_PARAM_SHA_256_EXISTS_BIT_SHIFT 0x10UL 386 #define DX_HASH_PARAM_SHA_256_EXISTS_BIT_SIZE 0x1UL 387 #define DX_HASH_PARAM_HASH_COMPARE_EXISTS_BIT_SHIFT 0x11UL 388 #define DX_HASH_PARAM_HASH_COMPARE_EXISTS_BIT_SIZE 0x1UL 389 #define DX_HASH_PARAM_DUMP_HASH_TO_DOUT_EXISTS_BIT_SHIFT 0x12UL 390 #define DX_HASH_PARAM_DUMP_HASH_TO_DOUT_EXISTS_BIT_SIZE 0x1UL 391 #define DX_HASH_AES_SW_RESET_REG_OFFSET 0x07E4UL 392 #define DX_HASH_AES_SW_RESET_VALUE_BIT_SHIFT 0x0UL 393 #define DX_HASH_AES_SW_RESET_VALUE_BIT_SIZE 0x1UL 394 #define DX_HASH_ENDIANESS_REG_OFFSET 0x07E8UL 395 #define DX_HASH_ENDIANESS_VALUE_BIT_SHIFT 0x0UL 396 #define DX_HASH_ENDIANESS_VALUE_BIT_SIZE 0x1UL 397 // -------------------------------------- 398 // BLOCK: GHASH 399 // -------------------------------------- 400 #define DX_GHASH_SUBKEY_0_0_REG_OFFSET 0x0960UL 401 #define DX_GHASH_SUBKEY_0_0_VALUE_BIT_SHIFT 0x0UL 402 #define DX_GHASH_SUBKEY_0_0_VALUE_BIT_SIZE 0x20UL 403 #define DX_GHASH_SUBKEY_0_1_REG_OFFSET 0x0964UL 404 #define DX_GHASH_SUBKEY_0_1_VALUE_BIT_SHIFT 0x0UL 405 #define DX_GHASH_SUBKEY_0_1_VALUE_BIT_SIZE 0x20UL 406 #define DX_GHASH_SUBKEY_0_2_REG_OFFSET 0x0968UL 407 #define DX_GHASH_SUBKEY_0_2_VALUE_BIT_SHIFT 0x0UL 408 #define DX_GHASH_SUBKEY_0_2_VALUE_BIT_SIZE 0x20UL 409 #define DX_GHASH_SUBKEY_0_3_REG_OFFSET 0x096CUL 410 #define DX_GHASH_SUBKEY_0_3_VALUE_BIT_SHIFT 0x0UL 411 #define DX_GHASH_SUBKEY_0_3_VALUE_BIT_SIZE 0x20UL 412 #define DX_GHASH_IV_0_0_REG_OFFSET 0x0970UL 413 #define DX_GHASH_IV_0_0_VALUE_BIT_SHIFT 0x0UL 414 #define DX_GHASH_IV_0_0_VALUE_BIT_SIZE 0x20UL 415 #define DX_GHASH_IV_0_1_REG_OFFSET 0x0974UL 416 #define DX_GHASH_IV_0_1_VALUE_BIT_SHIFT 0x0UL 417 #define DX_GHASH_IV_0_1_VALUE_BIT_SIZE 0x20UL 418 #define DX_GHASH_IV_0_2_REG_OFFSET 0x0978UL 419 #define DX_GHASH_IV_0_2_VALUE_BIT_SHIFT 0x0UL 420 #define DX_GHASH_IV_0_2_VALUE_BIT_SIZE 0x20UL 421 #define DX_GHASH_IV_0_3_REG_OFFSET 0x097CUL 422 #define DX_GHASH_IV_0_3_VALUE_BIT_SHIFT 0x0UL 423 #define DX_GHASH_IV_0_3_VALUE_BIT_SIZE 0x20UL 424 #define DX_GHASH_BUSY_REG_OFFSET 0x0980UL 425 #define DX_GHASH_BUSY_VALUE_BIT_SHIFT 0x0UL 426 #define DX_GHASH_BUSY_VALUE_BIT_SIZE 0x1UL 427 #define DX_GHASH_INIT_REG_OFFSET 0x0984UL 428 #define DX_GHASH_INIT_VALUE_BIT_SHIFT 0x0UL 429 #define DX_GHASH_INIT_VALUE_BIT_SIZE 0x1UL 430 // -------------------------------------- 431 // BLOCK: PKA 432 // -------------------------------------- 433 #define DX_MEMORY_MAP0_REG_OFFSET 0x0000UL 434 #define DX_MEMORY_MAP0_VALUE_BIT_SHIFT 0x1UL 435 #define DX_MEMORY_MAP0_VALUE_BIT_SIZE 0xAUL 436 #define DX_MEMORY_MAP1_REG_OFFSET 0x0004UL 437 #define DX_MEMORY_MAP1_VALUE_BIT_SHIFT 0x1UL 438 #define DX_MEMORY_MAP1_VALUE_BIT_SIZE 0xAUL 439 #define DX_MEMORY_MAP2_REG_OFFSET 0x0008UL 440 #define DX_MEMORY_MAP2_VALUE_BIT_SHIFT 0x1UL 441 #define DX_MEMORY_MAP2_VALUE_BIT_SIZE 0xAUL 442 #define DX_MEMORY_MAP3_REG_OFFSET 0x000CUL 443 #define DX_MEMORY_MAP3_VALUE_BIT_SHIFT 0x1UL 444 #define DX_MEMORY_MAP3_VALUE_BIT_SIZE 0xAUL 445 #define DX_MEMORY_MAP4_REG_OFFSET 0x0010UL 446 #define DX_MEMORY_MAP4_VALUE_BIT_SHIFT 0x1UL 447 #define DX_MEMORY_MAP4_VALUE_BIT_SIZE 0xAUL 448 #define DX_MEMORY_MAP5_REG_OFFSET 0x0014UL 449 #define DX_MEMORY_MAP5_VALUE_BIT_SHIFT 0x1UL 450 #define DX_MEMORY_MAP5_VALUE_BIT_SIZE 0xAUL 451 #define DX_MEMORY_MAP6_REG_OFFSET 0x0018UL 452 #define DX_MEMORY_MAP6_VALUE_BIT_SHIFT 0x1UL 453 #define DX_MEMORY_MAP6_VALUE_BIT_SIZE 0xAUL 454 #define DX_MEMORY_MAP7_REG_OFFSET 0x001CUL 455 #define DX_MEMORY_MAP7_VALUE_BIT_SHIFT 0x1UL 456 #define DX_MEMORY_MAP7_VALUE_BIT_SIZE 0xAUL 457 #define DX_MEMORY_MAP8_REG_OFFSET 0x0020UL 458 #define DX_MEMORY_MAP8_VALUE_BIT_SHIFT 0x1UL 459 #define DX_MEMORY_MAP8_VALUE_BIT_SIZE 0xAUL 460 #define DX_MEMORY_MAP9_REG_OFFSET 0x0024UL 461 #define DX_MEMORY_MAP9_VALUE_BIT_SHIFT 0x1UL 462 #define DX_MEMORY_MAP9_VALUE_BIT_SIZE 0xAUL 463 #define DX_MEMORY_MAP10_REG_OFFSET 0x0028UL 464 #define DX_MEMORY_MAP10_VALUE_BIT_SHIFT 0x1UL 465 #define DX_MEMORY_MAP10_VALUE_BIT_SIZE 0xAUL 466 #define DX_MEMORY_MAP11_REG_OFFSET 0x002CUL 467 #define DX_MEMORY_MAP11_VALUE_BIT_SHIFT 0x1UL 468 #define DX_MEMORY_MAP11_VALUE_BIT_SIZE 0xAUL 469 #define DX_MEMORY_MAP12_REG_OFFSET 0x0030UL 470 #define DX_MEMORY_MAP12_VALUE_BIT_SHIFT 0x1UL 471 #define DX_MEMORY_MAP12_VALUE_BIT_SIZE 0xAUL 472 #define DX_MEMORY_MAP13_REG_OFFSET 0x0034UL 473 #define DX_MEMORY_MAP13_VALUE_BIT_SHIFT 0x1UL 474 #define DX_MEMORY_MAP13_VALUE_BIT_SIZE 0xAUL 475 #define DX_MEMORY_MAP14_REG_OFFSET 0x0038UL 476 #define DX_MEMORY_MAP14_VALUE_BIT_SHIFT 0x1UL 477 #define DX_MEMORY_MAP14_VALUE_BIT_SIZE 0xAUL 478 #define DX_MEMORY_MAP15_REG_OFFSET 0x003CUL 479 #define DX_MEMORY_MAP15_VALUE_BIT_SHIFT 0x1UL 480 #define DX_MEMORY_MAP15_VALUE_BIT_SIZE 0xAUL 481 #define DX_MEMORY_MAP16_REG_OFFSET 0x0040UL 482 #define DX_MEMORY_MAP16_VALUE_BIT_SHIFT 0x1UL 483 #define DX_MEMORY_MAP16_VALUE_BIT_SIZE 0xAUL 484 #define DX_MEMORY_MAP17_REG_OFFSET 0x0044UL 485 #define DX_MEMORY_MAP17_VALUE_BIT_SHIFT 0x1UL 486 #define DX_MEMORY_MAP17_VALUE_BIT_SIZE 0xAUL 487 #define DX_MEMORY_MAP18_REG_OFFSET 0x0048UL 488 #define DX_MEMORY_MAP18_VALUE_BIT_SHIFT 0x1UL 489 #define DX_MEMORY_MAP18_VALUE_BIT_SIZE 0xAUL 490 #define DX_MEMORY_MAP19_REG_OFFSET 0x004CUL 491 #define DX_MEMORY_MAP19_VALUE_BIT_SHIFT 0x1UL 492 #define DX_MEMORY_MAP19_VALUE_BIT_SIZE 0xAUL 493 #define DX_MEMORY_MAP20_REG_OFFSET 0x0050UL 494 #define DX_MEMORY_MAP20_VALUE_BIT_SHIFT 0x1UL 495 #define DX_MEMORY_MAP20_VALUE_BIT_SIZE 0xAUL 496 #define DX_MEMORY_MAP21_REG_OFFSET 0x0054UL 497 #define DX_MEMORY_MAP21_VALUE_BIT_SHIFT 0x1UL 498 #define DX_MEMORY_MAP21_VALUE_BIT_SIZE 0xAUL 499 #define DX_MEMORY_MAP22_REG_OFFSET 0x0058UL 500 #define DX_MEMORY_MAP22_VALUE_BIT_SHIFT 0x1UL 501 #define DX_MEMORY_MAP22_VALUE_BIT_SIZE 0xAUL 502 #define DX_MEMORY_MAP23_REG_OFFSET 0x005CUL 503 #define DX_MEMORY_MAP23_VALUE_BIT_SHIFT 0x1UL 504 #define DX_MEMORY_MAP23_VALUE_BIT_SIZE 0xAUL 505 #define DX_MEMORY_MAP24_REG_OFFSET 0x0060UL 506 #define DX_MEMORY_MAP24_VALUE_BIT_SHIFT 0x1UL 507 #define DX_MEMORY_MAP24_VALUE_BIT_SIZE 0xAUL 508 #define DX_MEMORY_MAP25_REG_OFFSET 0x0064UL 509 #define DX_MEMORY_MAP25_VALUE_BIT_SHIFT 0x1UL 510 #define DX_MEMORY_MAP25_VALUE_BIT_SIZE 0xAUL 511 #define DX_MEMORY_MAP26_REG_OFFSET 0x0068UL 512 #define DX_MEMORY_MAP26_VALUE_BIT_SHIFT 0x1UL 513 #define DX_MEMORY_MAP26_VALUE_BIT_SIZE 0xAUL 514 #define DX_MEMORY_MAP27_REG_OFFSET 0x006CUL 515 #define DX_MEMORY_MAP27_VALUE_BIT_SHIFT 0x1UL 516 #define DX_MEMORY_MAP27_VALUE_BIT_SIZE 0xAUL 517 #define DX_MEMORY_MAP28_REG_OFFSET 0x0070UL 518 #define DX_MEMORY_MAP28_VALUE_BIT_SHIFT 0x1UL 519 #define DX_MEMORY_MAP28_VALUE_BIT_SIZE 0xAUL 520 #define DX_MEMORY_MAP29_REG_OFFSET 0x0074UL 521 #define DX_MEMORY_MAP29_VALUE_BIT_SHIFT 0x1UL 522 #define DX_MEMORY_MAP29_VALUE_BIT_SIZE 0xAUL 523 #define DX_MEMORY_MAP30_REG_OFFSET 0x0078UL 524 #define DX_MEMORY_MAP30_VALUE_BIT_SHIFT 0x1UL 525 #define DX_MEMORY_MAP30_VALUE_BIT_SIZE 0xAUL 526 #define DX_MEMORY_MAP31_REG_OFFSET 0x007CUL 527 #define DX_MEMORY_MAP31_VALUE_BIT_SHIFT 0x1UL 528 #define DX_MEMORY_MAP31_VALUE_BIT_SIZE 0xAUL 529 #define DX_OPCODE_REG_OFFSET 0x0080UL 530 #define DX_OPCODE_TAG_BIT_SHIFT 0x0UL 531 #define DX_OPCODE_TAG_BIT_SIZE 0x6UL 532 #define DX_OPCODE_REG_R_BIT_SHIFT 0x6UL 533 #define DX_OPCODE_REG_R_BIT_SIZE 0x6UL 534 #define DX_OPCODE_REG_B_BIT_SHIFT 0xCUL 535 #define DX_OPCODE_REG_B_BIT_SIZE 0x6UL 536 #define DX_OPCODE_REG_A_BIT_SHIFT 0x12UL 537 #define DX_OPCODE_REG_A_BIT_SIZE 0x6UL 538 #define DX_OPCODE_LEN_BIT_SHIFT 0x18UL 539 #define DX_OPCODE_LEN_BIT_SIZE 0x3UL 540 #define DX_OPCODE_OPCODE_BIT_SHIFT 0x1BUL 541 #define DX_OPCODE_OPCODE_BIT_SIZE 0x5UL 542 #define DX_N_NP_T0_T1_ADDR_REG_OFFSET 0x0084UL 543 #define DX_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_BIT_SHIFT 0x0UL 544 #define DX_N_NP_T0_T1_ADDR_N_VIRTUAL_ADDR_BIT_SIZE 0x5UL 545 #define DX_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_BIT_SHIFT 0x5UL 546 #define DX_N_NP_T0_T1_ADDR_NP_VIRTUAL_ADDR_BIT_SIZE 0x5UL 547 #define DX_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_BIT_SHIFT 0xAUL 548 #define DX_N_NP_T0_T1_ADDR_T0_VIRTUAL_ADDR_BIT_SIZE 0x5UL 549 #define DX_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_BIT_SHIFT 0xFUL 550 #define DX_N_NP_T0_T1_ADDR_T1_VIRTUAL_ADDR_BIT_SIZE 0x5UL 551 #define DX_PKA_STATUS_REG_OFFSET 0x0088UL 552 #define DX_PKA_STATUS_ALU_MSB_4BITS_BIT_SHIFT 0x0UL 553 #define DX_PKA_STATUS_ALU_MSB_4BITS_BIT_SIZE 0x4UL 554 #define DX_PKA_STATUS_ALU_LSB_4BITS_BIT_SHIFT 0x4UL 555 #define DX_PKA_STATUS_ALU_LSB_4BITS_BIT_SIZE 0x4UL 556 #define DX_PKA_STATUS_ALU_SIGN_OUT_BIT_SHIFT 0x8UL 557 #define DX_PKA_STATUS_ALU_SIGN_OUT_BIT_SIZE 0x1UL 558 #define DX_PKA_STATUS_ALU_CARRY_BIT_SHIFT 0x9UL 559 #define DX_PKA_STATUS_ALU_CARRY_BIT_SIZE 0x1UL 560 #define DX_PKA_STATUS_ALU_CARRY_MOD_BIT_SHIFT 0xAUL 561 #define DX_PKA_STATUS_ALU_CARRY_MOD_BIT_SIZE 0x1UL 562 #define DX_PKA_STATUS_ALU_SUB_IS_ZERO_BIT_SHIFT 0xBUL 563 #define DX_PKA_STATUS_ALU_SUB_IS_ZERO_BIT_SIZE 0x1UL 564 #define DX_PKA_STATUS_ALU_OUT_ZERO_BIT_SHIFT 0xCUL 565 #define DX_PKA_STATUS_ALU_OUT_ZERO_BIT_SIZE 0x1UL 566 #define DX_PKA_STATUS_ALU_MODOVRFLW_BIT_SHIFT 0xDUL 567 #define DX_PKA_STATUS_ALU_MODOVRFLW_BIT_SIZE 0x1UL 568 #define DX_PKA_STATUS_DIV_BY_ZERO_BIT_SHIFT 0xEUL 569 #define DX_PKA_STATUS_DIV_BY_ZERO_BIT_SIZE 0x1UL 570 #define DX_PKA_STATUS_MODINV_OF_ZERO_BIT_SHIFT 0xFUL 571 #define DX_PKA_STATUS_MODINV_OF_ZERO_BIT_SIZE 0x1UL 572 #define DX_PKA_STATUS_OPCODE_BIT_SHIFT 0x10UL 573 #define DX_PKA_STATUS_OPCODE_BIT_SIZE 0x5UL 574 #define DX_PKA_SW_RESET_REG_OFFSET 0x008CUL 575 #define DX_PKA_SW_RESET_VALUE_BIT_SHIFT 0x0UL 576 #define DX_PKA_SW_RESET_VALUE_BIT_SIZE 0x1UL 577 #define DX_PKA_L0_REG_OFFSET 0x0090UL 578 #define DX_PKA_L0_VALUE_BIT_SHIFT 0x0UL 579 #define DX_PKA_L0_VALUE_BIT_SIZE 0xDUL 580 #define DX_PKA_L1_REG_OFFSET 0x0094UL 581 #define DX_PKA_L1_VALUE_BIT_SHIFT 0x0UL 582 #define DX_PKA_L1_VALUE_BIT_SIZE 0xDUL 583 #define DX_PKA_L2_REG_OFFSET 0x0098UL 584 #define DX_PKA_L2_VALUE_BIT_SHIFT 0x0UL 585 #define DX_PKA_L2_VALUE_BIT_SIZE 0xDUL 586 #define DX_PKA_L3_REG_OFFSET 0x009CUL 587 #define DX_PKA_L3_VALUE_BIT_SHIFT 0x0UL 588 #define DX_PKA_L3_VALUE_BIT_SIZE 0xDUL 589 #define DX_PKA_L4_REG_OFFSET 0x00A0UL 590 #define DX_PKA_L4_VALUE_BIT_SHIFT 0x0UL 591 #define DX_PKA_L4_VALUE_BIT_SIZE 0xDUL 592 #define DX_PKA_L5_REG_OFFSET 0x00A4UL 593 #define DX_PKA_L5_VALUE_BIT_SHIFT 0x0UL 594 #define DX_PKA_L5_VALUE_BIT_SIZE 0xDUL 595 #define DX_PKA_L6_REG_OFFSET 0x00A8UL 596 #define DX_PKA_L6_VALUE_BIT_SHIFT 0x0UL 597 #define DX_PKA_L6_VALUE_BIT_SIZE 0xDUL 598 #define DX_PKA_L7_REG_OFFSET 0x00ACUL 599 #define DX_PKA_L7_VALUE_BIT_SHIFT 0x0UL 600 #define DX_PKA_L7_VALUE_BIT_SIZE 0xDUL 601 #define DX_PKA_PIPE_RDY_REG_OFFSET 0x00B0UL 602 #define DX_PKA_PIPE_RDY_VALUE_BIT_SHIFT 0x0UL 603 #define DX_PKA_PIPE_RDY_VALUE_BIT_SIZE 0x1UL 604 #define DX_PKA_DONE_REG_OFFSET 0x00B4UL 605 #define DX_PKA_DONE_VALUE_BIT_SHIFT 0x0UL 606 #define DX_PKA_DONE_VALUE_BIT_SIZE 0x1UL 607 #define DX_PKA_MON_SELECT_REG_OFFSET 0x00B8UL 608 #define DX_PKA_MON_SELECT_VALUE_BIT_SHIFT 0x0UL 609 #define DX_PKA_MON_SELECT_VALUE_BIT_SIZE 0x4UL 610 #define DX_PKA_VERSION_REG_OFFSET 0x00C4UL 611 #define DX_PKA_VERSION_VALUE_BIT_SHIFT 0x0UL 612 #define DX_PKA_VERSION_VALUE_BIT_SIZE 0x20UL 613 #define DX_PKA_MON_READ_REG_OFFSET 0x00D0UL 614 #define DX_PKA_MON_READ_VALUE_BIT_SHIFT 0x0UL 615 #define DX_PKA_MON_READ_VALUE_BIT_SIZE 0x20UL 616 #define DX_PKA_SRAM_ADDR_REG_OFFSET 0x00D4UL 617 #define DX_PKA_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL 618 #define DX_PKA_SRAM_ADDR_VALUE_BIT_SIZE 0x20UL 619 #define DX_PKA_SRAM_WDATA_REG_OFFSET 0x00D8UL 620 #define DX_PKA_SRAM_WDATA_VALUE_BIT_SHIFT 0x0UL 621 #define DX_PKA_SRAM_WDATA_VALUE_BIT_SIZE 0x20UL 622 #define DX_PKA_SRAM_RDATA_REG_OFFSET 0x00DCUL 623 #define DX_PKA_SRAM_RDATA_VALUE_BIT_SHIFT 0x0UL 624 #define DX_PKA_SRAM_RDATA_VALUE_BIT_SIZE 0x20UL 625 #define DX_PKA_SRAM_WR_CLR_REG_OFFSET 0x00E0UL 626 #define DX_PKA_SRAM_WR_CLR_VALUE_BIT_SHIFT 0x0UL 627 #define DX_PKA_SRAM_WR_CLR_VALUE_BIT_SIZE 0x20UL 628 #define DX_PKA_SRAM_RADDR_REG_OFFSET 0x00E4UL 629 #define DX_PKA_SRAM_RADDR_VALUE_BIT_SHIFT 0x0UL 630 #define DX_PKA_SRAM_RADDR_VALUE_BIT_SIZE 0x20UL 631 #define DX_PKA_WORD_ACCESS_REG_OFFSET 0x00F0UL 632 #define DX_PKA_WORD_ACCESS_VALUE_BIT_SHIFT 0x0UL 633 #define DX_PKA_WORD_ACCESS_VALUE_BIT_SIZE 0x20UL 634 #define DX_PKA_BUFF_ADDR_REG_OFFSET 0x00F8UL 635 #define DX_PKA_BUFF_ADDR_PKA_BUF_ADDR_BIT_SHIFT 0x0UL 636 #define DX_PKA_BUFF_ADDR_PKA_BUF_ADDR_BIT_SIZE 0xCUL 637 #define DX_PKA_BUFF_ADDR_RESEREVED1_BIT_SHIFT 0xCUL 638 #define DX_PKA_BUFF_ADDR_RESEREVED1_BIT_SIZE 0x14UL 639 // -------------------------------------- 640 // BLOCK: AHB 641 // -------------------------------------- 642 #define DX_AHBM_SINGLES_REG_OFFSET 0x0B00UL 643 #define DX_AHBM_SINGLES_VALUE_BIT_SHIFT 0x0UL 644 #define DX_AHBM_SINGLES_VALUE_BIT_SIZE 0x1UL 645 #define DX_AHBM_HPROT_REG_OFFSET 0x0B04UL 646 #define DX_AHBM_HPROT_VALUE_BIT_SHIFT 0x0UL 647 #define DX_AHBM_HPROT_VALUE_BIT_SIZE 0x4UL 648 #define DX_AHBM_HMASTLOCK_REG_OFFSET 0x0B08UL 649 #define DX_AHBM_HMASTLOCK_VALUE_BIT_SHIFT 0x0UL 650 #define DX_AHBM_HMASTLOCK_VALUE_BIT_SIZE 0x1UL 651 #define DX_AHBM_HNONSEC_REG_OFFSET 0x0B0CUL 652 #define DX_AHBM_HNONSEC_AHB_WRITE_HNONSEC_BIT_SHIFT 0x0UL 653 #define DX_AHBM_HNONSEC_AHB_WRITE_HNONSEC_BIT_SIZE 0x1UL 654 #define DX_AHBM_HNONSEC_AHB_READ_HNONSEC_BIT_SHIFT 0x1UL 655 #define DX_AHBM_HNONSEC_AHB_READ_HNONSEC_BIT_SIZE 0x1UL 656 // -------------------------------------- 657 // BLOCK: AO 658 // -------------------------------------- 659 #define DX_HOST_DCU_EN0_REG_OFFSET 0x1E00UL 660 #define DX_HOST_DCU_EN0_VALUE_BIT_SHIFT 0x0UL 661 #define DX_HOST_DCU_EN0_VALUE_BIT_SIZE 0x20UL 662 #define DX_HOST_DCU_EN1_REG_OFFSET 0x1E04UL 663 #define DX_HOST_DCU_EN1_VALUE_BIT_SHIFT 0x0UL 664 #define DX_HOST_DCU_EN1_VALUE_BIT_SIZE 0x20UL 665 #define DX_HOST_DCU_EN2_REG_OFFSET 0x1E08UL 666 #define DX_HOST_DCU_EN2_VALUE_BIT_SHIFT 0x0UL 667 #define DX_HOST_DCU_EN2_VALUE_BIT_SIZE 0x20UL 668 #define DX_HOST_DCU_EN3_REG_OFFSET 0x1E0CUL 669 #define DX_HOST_DCU_EN3_VALUE_BIT_SHIFT 0x0UL 670 #define DX_HOST_DCU_EN3_VALUE_BIT_SIZE 0x20UL 671 #define DX_HOST_DCU_LOCK0_REG_OFFSET 0x1E10UL 672 #define DX_HOST_DCU_LOCK0_VALUE_BIT_SHIFT 0x0UL 673 #define DX_HOST_DCU_LOCK0_VALUE_BIT_SIZE 0x20UL 674 #define DX_HOST_DCU_LOCK1_REG_OFFSET 0x1E14UL 675 #define DX_HOST_DCU_LOCK1_VALUE_BIT_SHIFT 0x0UL 676 #define DX_HOST_DCU_LOCK1_VALUE_BIT_SIZE 0x20UL 677 #define DX_HOST_DCU_LOCK2_REG_OFFSET 0x1E18UL 678 #define DX_HOST_DCU_LOCK2_VALUE_BIT_SHIFT 0x0UL 679 #define DX_HOST_DCU_LOCK2_VALUE_BIT_SIZE 0x20UL 680 #define DX_HOST_DCU_LOCK3_REG_OFFSET 0x1E1CUL 681 #define DX_HOST_DCU_LOCK3_VALUE_BIT_SHIFT 0x0UL 682 #define DX_HOST_DCU_LOCK3_VALUE_BIT_SIZE 0x20UL 683 #define DX_AO_ICV_DCU_RESTRICTION_MASK0_REG_OFFSET 0x1E20UL 684 #define DX_AO_ICV_DCU_RESTRICTION_MASK0_VALUE_BIT_SHIFT 0x0UL 685 #define DX_AO_ICV_DCU_RESTRICTION_MASK0_VALUE_BIT_SIZE 0x20UL 686 #define DX_AO_ICV_DCU_RESTRICTION_MASK1_REG_OFFSET 0x1E24UL 687 #define DX_AO_ICV_DCU_RESTRICTION_MASK1_VALUE_BIT_SHIFT 0x0UL 688 #define DX_AO_ICV_DCU_RESTRICTION_MASK1_VALUE_BIT_SIZE 0x20UL 689 #define DX_AO_ICV_DCU_RESTRICTION_MASK2_REG_OFFSET 0x1E28UL 690 #define DX_AO_ICV_DCU_RESTRICTION_MASK2_VALUE_BIT_SHIFT 0x0UL 691 #define DX_AO_ICV_DCU_RESTRICTION_MASK2_VALUE_BIT_SIZE 0x20UL 692 #define DX_AO_ICV_DCU_RESTRICTION_MASK3_REG_OFFSET 0x1E2CUL 693 #define DX_AO_ICV_DCU_RESTRICTION_MASK3_VALUE_BIT_SHIFT 0x0UL 694 #define DX_AO_ICV_DCU_RESTRICTION_MASK3_VALUE_BIT_SIZE 0x20UL 695 #define DX_AO_CC_SEC_DEBUG_RESET_REG_OFFSET 0x1E30UL 696 #define DX_AO_CC_SEC_DEBUG_RESET_VALUE_BIT_SHIFT 0x0UL 697 #define DX_AO_CC_SEC_DEBUG_RESET_VALUE_BIT_SIZE 0x1UL 698 #define DX_HOST_AO_LOCK_BITS_REG_OFFSET 0x1E34UL 699 #define DX_HOST_AO_LOCK_BITS_HOST_FATAL_ERR_BIT_SHIFT 0x0UL 700 #define DX_HOST_AO_LOCK_BITS_HOST_FATAL_ERR_BIT_SIZE 0x1UL 701 #define DX_HOST_AO_LOCK_BITS_HOST_KPICV_LOCK_BIT_SHIFT 0x1UL 702 #define DX_HOST_AO_LOCK_BITS_HOST_KPICV_LOCK_BIT_SIZE 0x1UL 703 #define DX_HOST_AO_LOCK_BITS_HOST_KCEICV_LOCK_BIT_SHIFT 0x2UL 704 #define DX_HOST_AO_LOCK_BITS_HOST_KCEICV_LOCK_BIT_SIZE 0x1UL 705 #define DX_HOST_AO_LOCK_BITS_HOST_KCP_LOCK_BIT_SHIFT 0x3UL 706 #define DX_HOST_AO_LOCK_BITS_HOST_KCP_LOCK_BIT_SIZE 0x1UL 707 #define DX_HOST_AO_LOCK_BITS_HOST_KCE_LOCK_BIT_SHIFT 0x4UL 708 #define DX_HOST_AO_LOCK_BITS_HOST_KCE_LOCK_BIT_SIZE 0x1UL 709 #define DX_HOST_AO_LOCK_BITS_HOST_ICV_RMA_LOCK_BIT_SHIFT 0x5UL 710 #define DX_HOST_AO_LOCK_BITS_HOST_ICV_RMA_LOCK_BIT_SIZE 0x1UL 711 #define DX_HOST_AO_LOCK_BITS_RESET_UPON_DEBUG_DISABLE_BIT_SHIFT 0x6UL 712 #define DX_HOST_AO_LOCK_BITS_RESET_UPON_DEBUG_DISABLE_BIT_SIZE 0x1UL 713 #define DX_HOST_AO_LOCK_BITS_HOST_FORCE_DFA_ENABLE_BIT_SHIFT 0x7UL 714 #define DX_HOST_AO_LOCK_BITS_HOST_FORCE_DFA_ENABLE_BIT_SIZE 0x1UL 715 #define DX_HOST_AO_LOCK_BITS_HOST_DFA_ENABLE_LOCK_BIT_SHIFT 0x8UL 716 #define DX_HOST_AO_LOCK_BITS_HOST_DFA_ENABLE_LOCK_BIT_SIZE 0x1UL 717 #define DX_AO_APB_FILTERING_REG_OFFSET 0x1E38UL 718 #define DX_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOW_BIT_SHIFT 0x0UL 719 #define DX_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOW_BIT_SIZE 0x1UL 720 #define DX_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOW_LOCK_BIT_SHIFT 0x1UL 721 #define DX_AO_APB_FILTERING_ONLY_SEC_ACCESS_ALLOW_LOCK_BIT_SIZE 0x1UL 722 #define DX_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOW_BIT_SHIFT 0x2UL 723 #define DX_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOW_BIT_SIZE 0x1UL 724 #define DX_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOW_LOCK_BIT_SHIFT 0x3UL 725 #define DX_AO_APB_FILTERING_ONLY_PRIV_ACCESS_ALLOW_LOCK_BIT_SIZE 0x1UL 726 #define DX_AO_APB_FILTERING_APBC_ONLY_SEC_ACCESS_ALLOW_BIT_SHIFT 0x4UL 727 #define DX_AO_APB_FILTERING_APBC_ONLY_SEC_ACCESS_ALLOW_BIT_SIZE 0x1UL 728 #define DX_AO_APB_FILTERING_APBC_ONLY_SEC_ACCESS_ALLOW_LOCK_BIT_SHIFT 0x5UL 729 #define DX_AO_APB_FILTERING_APBC_ONLY_SEC_ACCESS_ALLOW_LOCK_BIT_SIZE 0x1UL 730 #define DX_AO_APB_FILTERING_APBC_ONLY_PRIV_ACCESS_ALLOW_BIT_SHIFT 0x6UL 731 #define DX_AO_APB_FILTERING_APBC_ONLY_PRIV_ACCESS_ALLOW_BIT_SIZE 0x1UL 732 #define DX_AO_APB_FILTERING_APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK_BIT_SHIFT 0x7UL 733 #define DX_AO_APB_FILTERING_APBC_ONLY_PRIV_ACCESS_ALLOW_LOCK_BIT_SIZE 0x1UL 734 #define DX_AO_APB_FILTERING_APBC_ONLY_INST_ACCESS_ALLOW_BIT_SHIFT 0x8UL 735 #define DX_AO_APB_FILTERING_APBC_ONLY_INST_ACCESS_ALLOW_BIT_SIZE 0x1UL 736 #define DX_AO_APB_FILTERING_APBC_ONLY_INST_ACCESS_ALLOW_LOCK_BIT_SHIFT 0x9UL 737 #define DX_AO_APB_FILTERING_APBC_ONLY_INST_ACCESS_ALLOW_LOCK_BIT_SIZE 0x1UL 738 #define DX_AO_CC_GPPC_REG_OFFSET 0x1E3CUL 739 #define DX_AO_CC_GPPC_VALUE_BIT_SHIFT 0x0UL 740 #define DX_AO_CC_GPPC_VALUE_BIT_SIZE 0x8UL 741 #define DX_HOST_RGF_CC_SW_RST_REG_OFFSET 0x1E40UL 742 #define DX_HOST_RGF_CC_SW_RST_VALUE_BIT_SHIFT 0x0UL 743 #define DX_HOST_RGF_CC_SW_RST_VALUE_BIT_SIZE 0x1UL 744 // -------------------------------------- 745 // BLOCK: CHACHA 746 // -------------------------------------- 747 #define DX_CHACHA_CONTROL_REG_REG_OFFSET 0x0380UL 748 #define DX_CHACHA_CONTROL_REG_CHACHA_OR_SALSA_BIT_SHIFT 0x0UL 749 #define DX_CHACHA_CONTROL_REG_CHACHA_OR_SALSA_BIT_SIZE 0x1UL 750 #define DX_CHACHA_CONTROL_REG_INIT_FROM_HOST_BIT_SHIFT 0x1UL 751 #define DX_CHACHA_CONTROL_REG_INIT_FROM_HOST_BIT_SIZE 0x1UL 752 #define DX_CHACHA_CONTROL_REG_CALC_KEY_FOR_POLY1305_BIT_SHIFT 0x2UL 753 #define DX_CHACHA_CONTROL_REG_CALC_KEY_FOR_POLY1305_BIT_SIZE 0x1UL 754 #define DX_CHACHA_CONTROL_REG_KEY_LEN_BIT_SHIFT 0x3UL 755 #define DX_CHACHA_CONTROL_REG_KEY_LEN_BIT_SIZE 0x1UL 756 #define DX_CHACHA_CONTROL_REG_NUM_OF_ROUNDS_BIT_SHIFT 0x4UL 757 #define DX_CHACHA_CONTROL_REG_NUM_OF_ROUNDS_BIT_SIZE 0x2UL 758 #define DX_CHACHA_CONTROL_REG_RESET_BLOCK_CNT_BIT_SHIFT 0x9UL 759 #define DX_CHACHA_CONTROL_REG_RESET_BLOCK_CNT_BIT_SIZE 0x1UL 760 #define DX_CHACHA_CONTROL_REG_USE_IV_96BIT_BIT_SHIFT 0xAUL 761 #define DX_CHACHA_CONTROL_REG_USE_IV_96BIT_BIT_SIZE 0x1UL 762 #define DX_CHACHA_VERSION_REG_OFFSET 0x0384UL 763 #define DX_CHACHA_VERSION_VALUE_BIT_SHIFT 0x0UL 764 #define DX_CHACHA_VERSION_VALUE_BIT_SIZE 0x20UL 765 #define DX_CHACHA_KEY0_REG_OFFSET 0x0388UL 766 #define DX_CHACHA_KEY0_VALUE_BIT_SHIFT 0x0UL 767 #define DX_CHACHA_KEY0_VALUE_BIT_SIZE 0x20UL 768 #define DX_CHACHA_KEY1_REG_OFFSET 0x038CUL 769 #define DX_CHACHA_KEY1_VALUE_BIT_SHIFT 0x0UL 770 #define DX_CHACHA_KEY1_VALUE_BIT_SIZE 0x20UL 771 #define DX_CHACHA_KEY2_REG_OFFSET 0x0390UL 772 #define DX_CHACHA_KEY2_VALUE_BIT_SHIFT 0x0UL 773 #define DX_CHACHA_KEY2_VALUE_BIT_SIZE 0x20UL 774 #define DX_CHACHA_KEY3_REG_OFFSET 0x0394UL 775 #define DX_CHACHA_KEY3_VALUE_BIT_SHIFT 0x0UL 776 #define DX_CHACHA_KEY3_VALUE_BIT_SIZE 0x20UL 777 #define DX_CHACHA_KEY4_REG_OFFSET 0x0398UL 778 #define DX_CHACHA_KEY4_VALUE_BIT_SHIFT 0x0UL 779 #define DX_CHACHA_KEY4_VALUE_BIT_SIZE 0x20UL 780 #define DX_CHACHA_KEY5_REG_OFFSET 0x039CUL 781 #define DX_CHACHA_KEY5_VALUE_BIT_SHIFT 0x0UL 782 #define DX_CHACHA_KEY5_VALUE_BIT_SIZE 0x20UL 783 #define DX_CHACHA_KEY6_REG_OFFSET 0x03A0UL 784 #define DX_CHACHA_KEY6_VALUE_BIT_SHIFT 0x0UL 785 #define DX_CHACHA_KEY6_VALUE_BIT_SIZE 0x20UL 786 #define DX_CHACHA_KEY7_REG_OFFSET 0x03A4UL 787 #define DX_CHACHA_KEY7_VALUE_BIT_SHIFT 0x0UL 788 #define DX_CHACHA_KEY7_VALUE_BIT_SIZE 0x20UL 789 #define DX_CHACHA_IV_0_REG_OFFSET 0x03A8UL 790 #define DX_CHACHA_IV_0_VALUE_BIT_SHIFT 0x0UL 791 #define DX_CHACHA_IV_0_VALUE_BIT_SIZE 0x20UL 792 #define DX_CHACHA_IV_1_REG_OFFSET 0x03ACUL 793 #define DX_CHACHA_IV_1_VALUE_BIT_SHIFT 0x0UL 794 #define DX_CHACHA_IV_1_VALUE_BIT_SIZE 0x20UL 795 #define DX_CHACHA_BUSY_REG_OFFSET 0x03B0UL 796 #define DX_CHACHA_BUSY_VALUE_BIT_SHIFT 0x0UL 797 #define DX_CHACHA_BUSY_VALUE_BIT_SIZE 0x1UL 798 #define DX_CHACHA_HW_FLAGS_REG_OFFSET 0x03B4UL 799 #define DX_CHACHA_HW_FLAGS_CHACHA_EXISTS_BIT_SHIFT 0x0UL 800 #define DX_CHACHA_HW_FLAGS_CHACHA_EXISTS_BIT_SIZE 0x1UL 801 #define DX_CHACHA_HW_FLAGS_SALSA_EXISTS_BIT_SHIFT 0x1UL 802 #define DX_CHACHA_HW_FLAGS_SALSA_EXISTS_BIT_SIZE 0x1UL 803 #define DX_CHACHA_HW_FLAGS_FAST_CHACHA_BIT_SHIFT 0x2UL 804 #define DX_CHACHA_HW_FLAGS_FAST_CHACHA_BIT_SIZE 0x1UL 805 #define DX_CHACHA_BLOCK_CNT_LSB_REG_OFFSET 0x03B8UL 806 #define DX_CHACHA_BLOCK_CNT_LSB_VALUE_BIT_SHIFT 0x0UL 807 #define DX_CHACHA_BLOCK_CNT_LSB_VALUE_BIT_SIZE 0x20UL 808 #define DX_CHACHA_BLOCK_CNT_MSB_REG_OFFSET 0x03BCUL 809 #define DX_CHACHA_BLOCK_CNT_MSB_VALUE_BIT_SHIFT 0x0UL 810 #define DX_CHACHA_BLOCK_CNT_MSB_VALUE_BIT_SIZE 0x20UL 811 #define DX_CHACHA_SW_RESET_REG_OFFSET 0x03C0UL 812 #define DX_CHACHA_SW_RESET_VALUE_BIT_SHIFT 0x0UL 813 #define DX_CHACHA_SW_RESET_VALUE_BIT_SIZE 0x1UL 814 #define DX_CHACHA_FOR_POLY_KEY0_REG_OFFSET 0x03C4UL 815 #define DX_CHACHA_FOR_POLY_KEY0_VALUE_BIT_SHIFT 0x0UL 816 #define DX_CHACHA_FOR_POLY_KEY0_VALUE_BIT_SIZE 0x20UL 817 #define DX_CHACHA_FOR_POLY_KEY1_REG_OFFSET 0x03C8UL 818 #define DX_CHACHA_FOR_POLY_KEY1_VALUE_BIT_SHIFT 0x0UL 819 #define DX_CHACHA_FOR_POLY_KEY1_VALUE_BIT_SIZE 0x20UL 820 #define DX_CHACHA_FOR_POLY_KEY2_REG_OFFSET 0x03CCUL 821 #define DX_CHACHA_FOR_POLY_KEY2_VALUE_BIT_SHIFT 0x0UL 822 #define DX_CHACHA_FOR_POLY_KEY2_VALUE_BIT_SIZE 0x20UL 823 #define DX_CHACHA_FOR_POLY_KEY3_REG_OFFSET 0x03D0UL 824 #define DX_CHACHA_FOR_POLY_KEY3_VALUE_BIT_SHIFT 0x0UL 825 #define DX_CHACHA_FOR_POLY_KEY3_VALUE_BIT_SIZE 0x20UL 826 #define DX_CHACHA_FOR_POLY_KEY4_REG_OFFSET 0x03D4UL 827 #define DX_CHACHA_FOR_POLY_KEY4_VALUE_BIT_SHIFT 0x0UL 828 #define DX_CHACHA_FOR_POLY_KEY4_VALUE_BIT_SIZE 0x20UL 829 #define DX_CHACHA_FOR_POLY_KEY5_REG_OFFSET 0x03D8UL 830 #define DX_CHACHA_FOR_POLY_KEY5_VALUE_BIT_SHIFT 0x0UL 831 #define DX_CHACHA_FOR_POLY_KEY5_VALUE_BIT_SIZE 0x20UL 832 #define DX_CHACHA_FOR_POLY_KEY6_REG_OFFSET 0x03DCUL 833 #define DX_CHACHA_FOR_POLY_KEY6_VALUE_BIT_SHIFT 0x0UL 834 #define DX_CHACHA_FOR_POLY_KEY6_VALUE_BIT_SIZE 0x20UL 835 #define DX_CHACHA_FOR_POLY_KEY7_REG_OFFSET 0x03E0UL 836 #define DX_CHACHA_FOR_POLY_KEY7_VALUE_BIT_SHIFT 0x0UL 837 #define DX_CHACHA_FOR_POLY_KEY7_VALUE_BIT_SIZE 0x20UL 838 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_REG_OFFSET 0x03E4UL 839 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DIN_WORD_ORDER_BIT_SHIFT 0x0UL 840 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DIN_WORD_ORDER_BIT_SIZE 0x1UL 841 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DIN_BYTE_ORDER_BIT_SHIFT 0x1UL 842 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DIN_BYTE_ORDER_BIT_SIZE 0x1UL 843 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_CORE_MATRIX_LBE_ORDER_BIT_SHIFT 0x2UL 844 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_CORE_MATRIX_LBE_ORDER_BIT_SIZE 0x1UL 845 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DOUT_WORD_ORDER_BIT_SHIFT 0x3UL 846 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DOUT_WORD_ORDER_BIT_SIZE 0x1UL 847 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DOUT_BYTE_ORDER_BIT_SHIFT 0x4UL 848 #define DX_CHACHA_BYTE_WORD_ORDER_CNTL_REG_CHACHA_DOUT_BYTE_ORDER_BIT_SIZE 0x1UL 849 #define DX_CHACHA_DEBUG_REG_REG_OFFSET 0x03E8UL 850 #define DX_CHACHA_DEBUG_REG_VALUE_BIT_SHIFT 0x0UL 851 #define DX_CHACHA_DEBUG_REG_VALUE_BIT_SIZE 0x2UL 852 853 #endif // __DX_CRYS_KERNEL_H__ 854
