1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal_dma.h 4 * @author MCD Application Team 5 * @brief Header file of DMA HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L5xx_HAL_DMA_H 22 #define STM32L5xx_HAL_DMA_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l5xx_hal_def.h" 30 31 /** @addtogroup STM32L5xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup DMA 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup DMA_Exported_Types DMA Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief DMA Configuration Structure definition 46 */ 47 typedef struct 48 { 49 uint32_t Request; /*!< Specifies the request selected for the specified channel. 50 This parameter can be a value of @ref DMA_request */ 51 52 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 53 from memory to memory or from peripheral to memory. 54 This parameter can be a value of @ref DMA_Data_transfer_direction */ 55 56 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 57 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 58 59 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 60 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 61 62 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 63 This parameter can be a value of @ref DMA_Peripheral_data_size */ 64 65 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 66 This parameter can be a value of @ref DMA_Memory_data_size */ 67 68 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 69 This parameter can be a value of @ref DMA_mode 70 @note The circular buffer mode cannot be used if the memory-to-memory 71 data transfer is configured on the selected Channel */ 72 73 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 74 This parameter can be a value of @ref DMA_Priority_level */ 75 } DMA_InitTypeDef; 76 77 /** 78 * @brief HAL DMA State structures definition 79 */ 80 typedef enum 81 { 82 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 83 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 84 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 85 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 86 }HAL_DMA_StateTypeDef; 87 88 /** 89 * @brief HAL DMA Error Code structure definition 90 */ 91 typedef enum 92 { 93 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 94 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 95 }HAL_DMA_LevelCompleteTypeDef; 96 97 98 /** 99 * @brief HAL DMA Callback ID structure definition 100 */ 101 typedef enum 102 { 103 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 104 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 105 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 106 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 107 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 108 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 109 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 110 111 }HAL_DMA_CallbackIDTypeDef; 112 113 /** 114 * @brief DMA handle Structure definition 115 */ 116 typedef struct __DMA_HandleTypeDef 117 { 118 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 119 120 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 121 122 HAL_LockTypeDef Lock; /*!< DMA locking object */ 123 124 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 125 126 void *Parent; /*!< Parent object state */ 127 128 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 129 130 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 131 132 void (* XferM1CpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 133 134 void (* XferM1HalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 135 136 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 137 138 void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 139 140 __IO uint32_t ErrorCode; /*!< DMA Error code */ 141 142 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 143 144 uint32_t ChannelIndex; /*!< DMA Channel Index */ 145 146 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 147 148 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 149 150 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 151 152 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 153 154 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 155 156 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 157 158 159 }DMA_HandleTypeDef; 160 /** 161 * @} 162 */ 163 164 /* Exported constants --------------------------------------------------------*/ 165 166 /** @defgroup DMA_Exported_Constants DMA Exported Constants 167 * @{ 168 */ 169 170 /** @defgroup DMA_Error_Code DMA Error Code 171 * @{ 172 */ 173 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 174 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 175 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 176 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 177 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 178 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 179 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 180 181 /** 182 * @} 183 */ 184 185 /** @defgroup DMA_request DMA request 186 * @{ 187 */ 188 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 189 190 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 191 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 192 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 193 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 194 195 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ 196 #define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC2 request */ 197 198 #define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */ 199 #define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */ 200 201 #define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */ 202 #define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */ 203 204 #define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */ 205 #define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */ 206 #define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */ 207 #define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */ 208 #define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */ 209 #define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */ 210 211 #define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */ 212 #define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */ 213 #define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */ 214 #define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */ 215 #define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */ 216 #define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */ 217 #define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */ 218 #define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */ 219 220 #define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */ 221 #define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */ 222 #define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */ 223 #define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */ 224 #define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */ 225 #define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */ 226 227 #define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */ 228 #define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */ 229 #define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */ 230 #define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */ 231 232 #define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */ 233 #define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */ 234 235 #define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */ 236 #define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */ 237 #define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */ 238 #define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */ 239 240 #define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */ 241 242 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ 243 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ 244 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ 245 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ 246 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ 247 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ 248 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ 249 250 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ 251 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ 252 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ 253 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ 254 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ 255 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ 256 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ 257 258 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ 259 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ 260 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ 261 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ 262 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ 263 264 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ 265 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ 266 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ 267 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ 268 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ 269 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ 270 271 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ 272 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ 273 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ 274 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ 275 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ 276 277 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ 278 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ 279 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ 280 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ 281 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ 282 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ 283 284 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ 285 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ 286 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ 287 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ 288 289 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ 290 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ 291 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ 292 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ 293 294 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ 295 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ 296 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ 297 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ 298 299 #define DMA_REQUEST_AES_IN 90U /*!< DMAMUX1 AES IN request */ 300 #define DMA_REQUEST_AES_OUT 91U /*!< DMAMUX1 AES OUT request */ 301 302 #define DMA_REQUEST_HASH_IN 92U /*!< DMAMUX1 HASH IN request */ 303 304 #define DMA_REQUEST_UCPD1_TX 93U /*!< DMAMUX1 UCPD1 TX request */ 305 #define DMA_REQUEST_UCPD1_RX 94U /*!< DMAMUX1 UCPD1 RX request */ 306 /** 307 * @} 308 */ 309 310 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 311 * @{ 312 */ 313 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 314 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 315 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 321 * @{ 322 */ 323 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 324 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 325 /** 326 * @} 327 */ 328 329 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 330 * @{ 331 */ 332 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 333 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 334 /** 335 * @} 336 */ 337 338 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 339 * @{ 340 */ 341 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 342 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 343 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 344 /** 345 * @} 346 */ 347 348 /** @defgroup DMA_Memory_data_size DMA Memory data size 349 * @{ 350 */ 351 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 352 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 353 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 354 /** 355 * @} 356 */ 357 358 /** @defgroup DMA_mode DMA mode 359 * @{ 360 */ 361 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 362 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 363 #define DMA_DOUBLE_BUFFER_M0 DMA_CCR_DBM /*!< Double buffer mode with first target memory M0 */ 364 #define DMA_DOUBLE_BUFFER_M1 (DMA_CCR_DBM | DMA_CCR_CT) /*!< Double buffer mode with first target memory M1 */ 365 /** 366 * @} 367 */ 368 369 /** @defgroup DMA_Priority_level DMA Priority level 370 * @{ 371 */ 372 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 373 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 374 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 375 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 376 /** 377 * @} 378 */ 379 380 381 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 382 * @{ 383 */ 384 #define DMA_IT_TC DMA_CCR_TCIE 385 #define DMA_IT_HT DMA_CCR_HTIE 386 #define DMA_IT_TE DMA_CCR_TEIE 387 /** 388 * @} 389 */ 390 391 /** @defgroup DMA_flag_definitions DMA flag definitions 392 * @{ 393 */ 394 #define DMA_FLAG_GL1 DMA_ISR_GIF1 395 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 396 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 397 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 398 #define DMA_FLAG_GL2 DMA_ISR_GIF2 399 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 400 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 401 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 402 #define DMA_FLAG_GL3 DMA_ISR_GIF3 403 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 404 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 405 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 406 #define DMA_FLAG_GL4 DMA_ISR_GIF4 407 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 408 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 409 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 410 #define DMA_FLAG_GL5 DMA_ISR_GIF5 411 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 412 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 413 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 414 #define DMA_FLAG_GL6 DMA_ISR_GIF6 415 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 416 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 417 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 418 #define DMA_FLAG_GL7 DMA_ISR_GIF7 419 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 420 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 421 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 422 #define DMA_FLAG_GL8 DMA_ISR_GIF8 423 #define DMA_FLAG_TC8 DMA_ISR_TCIF8 424 #define DMA_FLAG_HT8 DMA_ISR_HTIF8 425 #define DMA_FLAG_TE8 DMA_ISR_TEIF8 426 427 /** 428 * @} 429 */ 430 431 /** @defgroup DMA_Channel_Attributes DMA Channel Attributes 432 * @brief DMA channel secure or non-secure and privileged or non-privileged attributes 433 * @note Secure and non-secure attributes are only available from secure when the system 434 * implements the security (TZEN=1) 435 * @{ 436 */ 437 438 #define DMA_CHANNEL_ATTR_PRIV_MASK (DMA_CCR_PRIV >> 16U) 439 #define DMA_CHANNEL_ATTR_SEC_MASK (DMA_CCR_SECM >> 16U) 440 #define DMA_CHANNEL_ATTR_SEC_SRC_MASK (DMA_CCR_SSEC >> 16U) 441 #define DMA_CHANNEL_ATTR_SEC_DEST_MASK (DMA_CCR_DSEC >> 16U) 442 443 #define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | DMA_CCR_PRIV) /*!< Channel is privileged */ 444 #define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ 445 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 446 #define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | DMA_CCR_SECM) /*!< Channel is secure */ 447 #define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ 448 #define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | DMA_CCR_SSEC) /*!< Channel source is secure */ 449 #define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ 450 #define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | DMA_CCR_DSEC) /*!< Channel destination is secure */ 451 #define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ 452 #endif /* __ARM_FEATURE_CMSE */ 453 454 /** 455 * @} 456 */ 457 458 /** 459 * @} 460 */ 461 462 /* Exported macros -----------------------------------------------------------*/ 463 /** @defgroup DMA_Exported_Macros DMA Exported Macros 464 * @{ 465 */ 466 467 /** @brief Reset DMA handle state. 468 * @param __HANDLE__ DMA handle 469 * @retval None 470 */ 471 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 472 473 /** 474 * @brief Enable the specified DMA Channel. 475 * @param __HANDLE__ DMA handle 476 * @retval None 477 */ 478 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 479 480 /** 481 * @brief Disable the specified DMA Channel. 482 * @param __HANDLE__ DMA handle 483 * @retval None 484 */ 485 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 486 487 488 /* Interrupt & Flag management */ 489 490 /** 491 * @brief Return the current DMA Channel transfer complete flag. 492 * @param __HANDLE__ DMA handle 493 * @retval The specified transfer complete flag index. 494 */ 495 496 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 497 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\ 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\ 511 DMA_FLAG_TC8) 512 513 /** 514 * @brief Return the current DMA Channel half transfer complete flag. 515 * @param __HANDLE__ DMA handle 516 * @retval The specified half transfer complete flag index. 517 */ 518 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 519 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 527 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 528 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 529 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\ 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\ 533 DMA_FLAG_HT8) 534 535 /** 536 * @brief Return the current DMA Channel transfer error flag. 537 * @param __HANDLE__ DMA handle 538 * @retval The specified transfer error flag index. 539 */ 540 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 541 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 549 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 550 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 551 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 552 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 553 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\ 554 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\ 555 DMA_FLAG_TE8) 556 557 /** 558 * @brief Return the current DMA Channel Global interrupt flag. 559 * @param __HANDLE__ DMA handle 560 * @retval The specified transfer error flag index. 561 */ 562 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 563 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 564 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 565 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 566 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 567 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 568 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 569 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 570 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 571 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 572 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 573 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 574 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 575 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\ 576 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\ 577 DMA_ISR_GIF8) 578 579 /** 580 * @brief Get the DMA Channel pending flags. 581 * @param __HANDLE__ DMA handle 582 * @param __FLAG__ Get the specified flag. 583 * This parameter can be any combination of the following values: 584 * @arg DMA_FLAG_TCx: Transfer complete flag 585 * @arg DMA_FLAG_HTx: Half transfer complete flag 586 * @arg DMA_FLAG_TEx: Transfer error flag 587 * @arg DMA_FLAG_GLx: Global interrupt flag 588 * Where x can be from 1 to 8 to select the DMA Channel x flag. 589 * @retval The state of FLAG (SET or RESET). 590 */ 591 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ 592 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 593 594 /** 595 * @brief Clear the DMA Channel pending flags. 596 * @param __HANDLE__ DMA handle 597 * @param __FLAG__ specifies the flag to clear. 598 * This parameter can be any combination of the following values: 599 * @arg DMA_FLAG_TCx: Transfer complete flag 600 * @arg DMA_FLAG_HTx: Half transfer complete flag 601 * @arg DMA_FLAG_TEx: Transfer error flag 602 * @arg DMA_FLAG_GLx: Global interrupt flag 603 * Where x can be from 1 to 8 to select the DMA Channel x flag. 604 * @retval None 605 */ 606 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \ 607 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 608 609 /** 610 * @brief Enable the specified DMA Channel interrupts. 611 * @param __HANDLE__ DMA handle 612 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 613 * This parameter can be any combination of the following values: 614 * @arg DMA_IT_TC: Transfer complete interrupt mask 615 * @arg DMA_IT_HT: Half transfer complete interrupt mask 616 * @arg DMA_IT_TE: Transfer error interrupt mask 617 * @retval None 618 */ 619 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 620 621 /** 622 * @brief Disable the specified DMA Channel interrupts. 623 * @param __HANDLE__ DMA handle 624 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 625 * This parameter can be any combination of the following values: 626 * @arg DMA_IT_TC: Transfer complete interrupt mask 627 * @arg DMA_IT_HT: Half transfer complete interrupt mask 628 * @arg DMA_IT_TE: Transfer error interrupt mask 629 * @retval None 630 */ 631 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 632 633 /** 634 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 635 * @param __HANDLE__ DMA handle 636 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 637 * This parameter can be one of the following values: 638 * @arg DMA_IT_TC: Transfer complete interrupt mask 639 * @arg DMA_IT_HT: Half transfer complete interrupt mask 640 * @arg DMA_IT_TE: Transfer error interrupt mask 641 * @retval The state of DMA_IT (SET or RESET). 642 */ 643 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 644 645 /** 646 * @brief Return the number of remaining data units in the current DMA Channel transfer. 647 * @param __HANDLE__ DMA handle 648 * @retval The number of remaining data units in the current DMA Channel transfer. 649 */ 650 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 651 652 /** 653 * @} 654 */ 655 656 /* Include DMA HAL Extension module */ 657 #include "stm32l5xx_hal_dma_ex.h" 658 659 /* Exported functions --------------------------------------------------------*/ 660 661 /** @addtogroup DMA_Exported_Functions 662 * @{ 663 */ 664 665 /** @addtogroup DMA_Exported_Functions_Group1 666 * @{ 667 */ 668 /* Initialization and de-initialization functions *****************************/ 669 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 670 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 671 /** 672 * @} 673 */ 674 675 /** @addtogroup DMA_Exported_Functions_Group2 676 * @{ 677 */ 678 /* IO operation functions *****************************************************/ 679 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 680 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 681 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 682 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 683 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 684 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 685 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 686 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 687 688 /** 689 * @} 690 */ 691 692 /** @addtogroup DMA_Exported_Functions_Group3 693 * @{ 694 */ 695 /* Peripheral State and Error functions ***************************************/ 696 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 697 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 698 /** 699 * @} 700 */ 701 702 /** @addtogroup DMA_Exported_Functions_Group4 703 * @{ 704 */ 705 /* DMA Attributes functions ********************************************/ 706 HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t ChannelAttributes); 707 HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, uint32_t *ChannelAttributes); 708 /** 709 * @} 710 */ 711 712 /** 713 * @} 714 */ 715 716 /* Private macros ------------------------------------------------------------*/ 717 /** @defgroup DMA_Private_Macros DMA Private Macros 718 * @{ 719 */ 720 721 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 722 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 723 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 724 725 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U)) 726 727 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 728 ((STATE) == DMA_PINC_DISABLE)) 729 730 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 731 ((STATE) == DMA_MINC_DISABLE)) 732 733 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_UCPD1_RX) 734 735 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 736 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 737 ((SIZE) == DMA_PDATAALIGN_WORD)) 738 739 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 740 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 741 ((SIZE) == DMA_MDATAALIGN_WORD )) 742 743 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 744 ((MODE) == DMA_CIRCULAR) || \ 745 ((MODE) == DMA_DOUBLE_BUFFER_M0) || \ 746 ((MODE) == DMA_DOUBLE_BUFFER_M1)) 747 748 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 749 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 750 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 751 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 752 753 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 754 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U)) 755 #else 756 #define IS_DMA_ATTRIBUTES(ATTRIBUTE) (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ 757 ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) 758 #endif 759 760 /** 761 * @} 762 */ 763 764 /* Private functions ---------------------------------------------------------*/ 765 766 /** 767 * @} 768 */ 769 770 /** 771 * @} 772 */ 773 774 #ifdef __cplusplus 775 } 776 #endif 777 778 #endif /* STM32L5xx_HAL_DMA_H */ 779 780 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 781
