Searched refs:DMA_CTR1_DDW_LOG2 (Results 1 – 5 of 5) sorted by relevance
1422 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_OSPI_Transmit_DMA()1603 data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in HAL_OSPI_Receive_DMA()
3929 …DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in DMA_List_GetNodeConfig()
3927 …DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; in DMA_List_GetNodeConfig()
6715 #define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary log… macro
8114 #define DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk /*!< Binary log… macro