1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 8 #ifndef _DRIVER_DEFS_H_ 9 #define _DRIVER_DEFS_H_ 10 11 #include "cc_pal_types.h" 12 13 #ifdef __KERNEL__ 14 #include <linux/types.h> 15 #define INT32_MAX 0x7FFFFFFFL 16 #else 17 #include <stdint.h> 18 #endif 19 20 #ifndef min 21 #define min(a, b) ((a) < (b) ? (a) : (b)) 22 #endif 23 24 #define CPU_DIN_MAX_SIZE 0xFFFFUL 25 /****************************************************************************** 26 * TYPE DEFINITIONS 27 ******************************************************************************/ 28 typedef uint32_t drvError_t; 29 30 typedef enum aesMode { 31 CIPHER_NULL_MODE = -1, 32 CIPHER_ECB = 0, 33 CIPHER_CBC = 1, 34 CIPHER_CTR = 2, 35 CIPHER_CBC_MAC = 3, 36 CIPHER_OFB = 6, 37 CIPHER_CMAC = 7, 38 CIPHER_CCMA = 8, 39 CIPHER_CCMPE = 9, 40 CIPHER_CCMPD = 10, 41 CIPHER_RESERVE32B = INT32_MAX 42 }aesMode_t; 43 44 typedef enum hashMode { 45 HASH_NULL_MODE = -1, 46 HASH_SHA1 = 0, 47 HASH_SHA256 = 1, 48 HASH_SHA224 = 2, 49 HASH_SHA512 = 3, 50 HASH_SHA384 = 4, 51 HASH_RESERVE32B = INT32_MAX 52 }hashMode_t; 53 54 typedef enum DataBlockType { 55 FIRST_BLOCK, 56 MIDDLE_BLOCK, 57 LAST_BLOCK, 58 RESERVE32B_BLOCK = INT32_MAX 59 }DataBlockType_t; 60 61 typedef enum dataAddrType { 62 SRAM_ADDR = 0, 63 DLLI_ADDR = 1, 64 ADDR_RESERVE32B = INT32_MAX 65 }dataAddrType_t; 66 67 typedef enum cryptoDirection { 68 CRYPTO_DIRECTION_ENCRYPT = 0, 69 CRYPTO_DIRECTION_DECRYPT = 1, 70 CRYPTO_DIRECTION_NUM_OF_ENC_MODES, 71 CRYPTO_DIRECTION_RESERVE32B = INT32_MAX 72 }cryptoDirection_t; 73 74 typedef enum keySizeId { 75 KEY_SIZE_128_BIT = 0, 76 KEY_SIZE_192_BIT = 1, 77 KEY_SIZE_256_BIT = 2, 78 KEY_SIZE_ID_RESERVE32B = INT32_MAX, 79 }keySizeId_t; 80 81 typedef enum cryptoKeyType { 82 RKEK_KEY = 0, 83 USER_KEY = 1, 84 KCP_KEY = 2, 85 KCE_KEY = 3, 86 KPICV_KEY = 4, 87 KCEICV_KEY = 5, 88 RTL_KEY, 89 END_OF_KEYS = INT32_MAX, 90 }cryptoKeyType_t; 91 92 typedef enum cryptoPaddingType { 93 CRYPTO_PADDING_NONE = 0, 94 CRYPTO_PADDING_PKCS7 = 1, 95 CRYPTO_PADDING_RESERVE32B = INT32_MAX 96 }cryptoPaddingType_t; 97 98 typedef enum chachaNonceSize { 99 NONCE_SIZE_64 = 0, 100 NONCE_SIZE_96 = 1, 101 NONCE_SIZE_RESERVE32B = INT32_MAX 102 }chachaNonceSize_t; 103 104 typedef enum hashSelAesMacModule { 105 HASH_SEL_HASH_MOD = 0, 106 HASH_SEL_AES_MAC_MOD = 1, 107 HASH_SEL_RESERVE32B = INT32_MAX 108 }hashSelAesMacModule_t; 109 110 typedef enum ghashSelModule { 111 GHASH_SEL_HASH_MOD = 0, 112 GHASH_SEL_GHASH_MOD = 1, 113 GHASH_SEL_RESERVE32B = INT32_MAX 114 }ghashSelModule_t; 115 116 /****************************************************************************** 117 * Buffer Information 118 ******************************************************************************/ 119 /*! User buffer type (input for read / output for write). */ 120 #define INPUT_DATA_BUFFER 1 121 #define OUTPUT_DATA_BUFFER 0 122 123 124 /*! User buffer buffer information. */ 125 typedef struct { 126 uint32_t dataBuffAddr; /*!< Address of data buffer.*/ 127 uint8_t dataBuffNs; /*!< HNONSEC buffer attribute (0 for secure, 1 for non-secure) */ 128 }CCBuffInfo_t; 129 130 /****************************************************************************** 131 * Driver's Errors base address 132 ******************************************************************************/ 133 #define DRV_MODULE_ERROR_BASE 0x00F00000 134 #define AES_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x10000UL) 135 #define AEAD_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x20000UL) 136 #define HASH_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x30000UL) 137 #define HMAC_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x40000UL) 138 #define BYPASS_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x50000UL) 139 #define CHACHA_DRV_MODULE_ERROR_BASE (DRV_MODULE_ERROR_BASE + 0x60000UL) 140 141 /****************************************************************************** 142 * CRYPTOGRAPHIC FLOW DEFINITIONS 143 ******************************************************************************/ 144 #define CONFIG_DIN_AES_DOUT_VAL 0x1UL 145 #define CONFIG_DIN_AES_AND_HASH_VAL 0x3UL 146 #define CONFIG_HASH_MODE_VAL 0x7UL 147 #define CONFIG_AES_TO_HASH_AND_DOUT_VAL 0xAUL 148 149 /****************************************************************************** 150 * Data Buffer Attributes for secure/non-secure 151 ******************************************************************************/ 152 #define OUTPUT_BUFFER_HNONSEC_BIT_SHIFT 0x0UL 153 #define OUTPUT_BUFFER_HNONSEC_BIT_SIZE 0x1UL 154 #define INPUT_BUFFER_HNONSEC_BIT_SHIFT 0x1UL 155 #define INPUT_BUFFER_HNONSEC_BIT_SIZE 0x1UL 156 157 /****************************************************************************** 158 * AES DEFINITIONS 159 ******************************************************************************/ 160 161 #define AES_BLOCK_SIZE 16 162 #define AES_BLOCK_SIZE_WORDS (AES_BLOCK_SIZE >> 2) 163 #define AES_IV_SIZE 16 164 #define AES_IV_SIZE_WORDS (AES_IV_SIZE >> 2) 165 #define AES_128_BIT_KEY_SIZE 16 166 #define AES_128_BIT_KEY_SIZE_WORDS (AES_128_BIT_KEY_SIZE >> 2) 167 #define AES_192_BIT_KEY_SIZE 24 168 #define AES_192_BIT_KEY_SIZE_WORDS (AES_192_BIT_KEY_SIZE >> 2) 169 #define AES_256_BIT_KEY_SIZE 32 170 #define AES_256_BIT_KEY_SIZE_WORDS (AES_256_BIT_KEY_SIZE >> 2) 171 172 173 #define SET_CLOCK_ENABLE 0x1UL 174 #define SET_CLOCK_DISABLE 0x0UL 175 176 /* The CC AES file errors */ 177 #define AES_DRV_OK 0 178 #define AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x00UL) 179 #define AES_DRV_ILLEGAL_OPERATION_MODE_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x01UL) 180 #define AES_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x02UL) 181 #define AES_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x03UL) 182 #define AES_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x04UL) 183 #define AES_DRV_ILLEGAL_MEM_SIZE_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x05UL) 184 #define AES_DRV_ILLEGAL_KEY_SIZE_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x06UL) 185 #define AES_DRV_ILLEGAL_KEY_LOCK_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x07UL) 186 #define AES_DRV_ILLEGAL_KEY_INTEGRITY_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x08UL) 187 #define AES_DRV_ILLEGAL_KEY_USE_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x09UL) 188 #define AES_DRV_ILLEGAL_FATAL_ERR_BIT_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x0AUL) 189 #define AES_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR (AES_DRV_MODULE_ERROR_BASE + 0x0BUL) 190 191 192 /****************************************************************************** 193 * GHASH DEFINITIONS 194 ******************************************************************************/ 195 #define GHASH_INIT_SET_VAL 0x1UL 196 197 /****************************************************************************** 198 * HASH & HMAC DEFINITIONS 199 ******************************************************************************/ 200 201 /************************ Typedefs ****************************/ 202 typedef drvError_t (*llf_hash_init_operation_func)(void *); 203 typedef drvError_t (*llf_hash_update_operation_func)(void *, CCBuffInfo_t *pInputBuffInfo, uint32_t dataInSize); 204 typedef drvError_t (*llf_hash_finish_operation_func)(void *); 205 206 207 /* The SHA-1 digest result size */ 208 #define SHA1_DIGEST_SIZE_IN_WORDS 5 209 #define SHA1_DIGEST_SIZE_IN_BYTES (SHA1_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t)) 210 211 /* The SHA-256 digest result size*/ 212 #define SHA224_DIGEST_SIZE_IN_WORDS 7 213 #define SHA224_DIGEST_SIZE_IN_BYTES (SHA224_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t)) 214 215 /* The SHA-256 digest result size */ 216 #define SHA256_DIGEST_SIZE_IN_WORDS 8 217 #define SHA256_DIGEST_SIZE_IN_BYTES (SHA256_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t)) 218 219 /* The SHA-384 digest result size*/ 220 #define SHA384_DIGEST_SIZE_IN_WORDS 12 221 #define SHA384_DIGEST_SIZE_IN_BYTES (SHA384_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t)) 222 223 /* The SHA-512 digest result size in bytes */ 224 #define SHA512_DIGEST_SIZE_IN_WORDS 16 225 #define SHA512_DIGEST_SIZE_IN_BYTES (SHA512_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t)) 226 227 228 #define MAX_DIGEST_SIZE_WORDS SHA512_DIGEST_SIZE_IN_WORDS 229 230 #define HW_HASH_CTL_SHA1_VAL 0x0001UL 231 #define HW_HASH_CTL_SHA256_VAL 0x0002UL 232 #define HW_HASH_LE_MODE_VAL 0x0001UL 233 #define HW_HASH_PAD_EN_VAL 0x1UL 234 235 /* The SHA1 hash block size in words */ 236 #define HASH_BLOCK_SIZE_IN_WORDS 16 237 #define HASH_BLOCK_SIZE_IN_BYTES (HASH_BLOCK_SIZE_IN_WORDS * sizeof(uint32_t)) 238 239 /* The SHA2 hash block size in words */ 240 #define HASH_SHA512_BLOCK_SIZE_IN_WORDS 32 241 #define HASH_SHA512_BLOCK_SIZE_IN_BYTES (HASH_SHA512_BLOCK_SIZE_IN_WORDS * sizeof(uint32_t)) 242 243 /* the MAC key IPAD and OPAD bytes */ 244 #define MAC_KEY_IPAD_BYTE 0x36 245 #define MAC_KEY_OPAD_BYTE 0x5C 246 247 #define HMAC_CONTEXT_VALIDATION_TAG 0x23456789 248 249 /* The CC HASH file errors */ 250 #define HASH_DRV_OK 0 251 #define HASH_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (HASH_DRV_MODULE_ERROR_BASE + 0x00UL) 252 #define HASH_DRV_ILLEGAL_OPERATION_MODE_ERROR (HASH_DRV_MODULE_ERROR_BASE + 0x01UL) 253 #define HASH_DRV_USER_CONTEXT_CORRUPTED_ERROR (HASH_DRV_MODULE_ERROR_BASE + 0x02UL) 254 #define HASH_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR (HASH_DRV_MODULE_ERROR_BASE + 0x03UL) 255 256 /* The CC HMAC file errors */ 257 #define HMAC_DRV_OK 0 258 #define HMAC_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (HMAC_DRV_MODULE_ERROR_BASE + 0x00UL) 259 260 261 /* SHA512 soft driver */ 262 263 /* The first padding byte */ 264 #define LLF_HASH_FIRST_PADDING_BYTE 0x80 265 /* The size at the end of the padding for SHA384 and SHA512 */ 266 #define LLF_HASH_SHA2_COUNTER_SIZE_ON_END_OF_PADDING_IN_BYTES (4 * sizeof(uint32_t)) 267 #define LLF_HASH_SHA2_COUNTER_SIZE_ON_END_OF_PADDING_IN_WORDS 4 268 269 /* the HASH user context validity TAG */ 270 #define HASH_CONTEXT_VALIDATION_TAG 0x12345678 271 272 /* the HASH XOR data value */ 273 #define HASH_XOR_DATA_VAL 0x0UL 274 275 /****************************************************************************** 276 * BYPASS DEFINITIONS 277 ******************************************************************************/ 278 279 #define CONFIG_DIN_BYPASS_DOUT_VAL 0 280 281 /* The CC BYPASS file errors */ 282 #define BYPASS_DRV_OK 0 283 #define BYPASS_DRV_ILLEGAL_BLOCK_SIZE_ERROR (BYPASS_DRV_MODULE_ERROR_BASE + 0x01UL) 284 #define BYPASS_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR (BYPASS_DRV_MODULE_ERROR_BASE + 0x02UL) 285 #define BYPASS_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR (BYPASS_DRV_MODULE_ERROR_BASE + 0x03UL) 286 #define BYPASS_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR (BYPASS_DRV_MODULE_ERROR_BASE + 0x04UL) 287 288 /****************************************************************************** 289 * CHACHA DEFINITIONS 290 ******************************************************************************/ 291 292 #define CHACHA_BLOCK_SIZE_BYTES 64 293 #define CHACHA_BLOCK_SIZE_WORDS (CHACHA_BLOCK_SIZE_BYTES >> 2) 294 #define CHACHA_IV_64_SIZE_BYTES 8 295 #define CHACHA_IV_64_SIZE_WORDS (CHACHA_IV_64_SIZE_BYTES >> 2) 296 #define CHACHA_IV_96_SIZE_BYTES 12 297 #define CHACHA_IV_96_SIZE_WORDS (CHACHA_IV_96_SIZE_BYTES >> 2) 298 #define CHACHA_256_BIT_KEY_SIZE 32 299 #define CHACHA_256_BIT_KEY_SIZE_WORDS (CHACHA_256_BIT_KEY_SIZE >> 2) 300 301 #define ENABLE_CHACHA_CLOCK 0x1UL 302 #define DISABLE_CHACHA_CLOCK 0x0UL 303 304 #define CONFIG_DIN_CHACHA_DOUT_VAL 0x10UL 305 306 /* The CC CHACHA file errors */ 307 #define CHACHA_DRV_OK 0 308 #define CHACHA_DRV_INVALID_USER_CONTEXT_POINTER_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x00UL) 309 #define CHACHA_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x01UL) 310 #define CHACHA_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x02UL) 311 #define CHACHA_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x03UL) 312 #define CHACHA_DRV_ILLEGAL_MEM_SIZE_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x04UL) 313 #define CHACHA_DRV_ILLEGAL_NONCE_SIZE_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x05UL) 314 #define CHACHA_DRV_INVALID_USER_DATA_BUFF_POINTER_ERROR (CHACHA_DRV_MODULE_ERROR_BASE + 0x06UL) 315 316 317 /****************************************************************************** 318 * MACROS 319 ******************************************************************************/ 320 /* This MACRO purpose is to switch from CryptoCell definitions to crypto driver definitions, the MACRO assumes that the value is legal (encrypt or decrypt only) */ 321 #define CC_2_DRIVER_DIRECTION(ssiDirection) ((ssiDirection == CC_AES_ENCRYPT) ? (CRYPTO_DIRECTION_ENCRYPT) : (CRYPTO_DIRECTION_DECRYPT)) 322 /* This MACRO purpose is to switch from MBEDTLS definitions to crypto driver definitions, the MACRO assumes that the value is legal (encrypt or decrypt only) */ 323 #define MBEDTLS_2_DRIVER_DIRECTION(mbedtlsDir) ((mbedtlsDir == 1) ? (CRYPTO_DIRECTION_ENCRYPT) : (CRYPTO_DIRECTION_DECRYPT)) 324 325 326 /* Poll on the crypto busy till it is = 0 */ 327 #define CC_HAL_WAIT_ON_CRYPTO_BUSY()\ 328 do {\ 329 uint32_t regVal=1;\ 330 do {\ 331 regVal = CC_HAL_READ_REGISTER( CC_REG_OFFSET(HOST_RGF, CRYPTO_BUSY));\ 332 }while( regVal );\ 333 }while(0) 334 335 336 337 /* check HUK, Kcp, Kce, Kpicv, Kceicv error bit in LCS register */ 338 #define CC_IS_KEY_ERROR(keyType, rc)\ 339 do {\ 340 uint32_t regVal = 0; \ 341 regVal = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, LCS_REG));\ 342 rc = CC_REG_FLD_GET(0, LCS_REG, ERROR_## keyType ##_ZERO_CNT, regVal);\ 343 rc = (rc == 1)?CC_TRUE:CC_FALSE;\ 344 }while(0) 345 346 347 /* check if key is locked for Kpicv, Kceicv, Kcp, Kce */ 348 #define CC_IS_KEY_LOCKED(keyType, rc)\ 349 do {\ 350 uint32_t regVal = 0;\ 351 regVal = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_AO_LOCK_BITS));\ 352 rc = CC_REG_FLD_GET(0, HOST_AO_LOCK_BITS, HOST_## keyType ##_LOCK, regVal);\ 353 rc = (rc == 1)?CC_TRUE:CC_FALSE;\ 354 }while(0) 355 356 /* Verifies if one of teh keys: Kpicv, Kceicv, HBK0, Kcp or Kce is in use */ 357 #define CC_IS_OTP_KEY_IN_USE(owner, keyType, rc, isKeyInUse)\ 358 do {\ 359 uint32_t otpVal = 0;\ 360 uint32_t notInUse = 0;\ 361 rc = mbedtls_mng_otpWordRead(CC_OTP_## owner ##_FLAG_OFFSET, &otpVal);\ 362 if (rc == CC_OK) {\ 363 notInUse = BITFIELD_GET(otpVal, CC_OTP_## owner ##_FLAG_## keyType ##_NOT_IN_USE_BIT_SHIFT,\ 364 CC_OTP_## owner ##_FLAG_## keyType ##_NOT_IN_USE_BIT_SIZE);\ 365 isKeyInUse = (notInUse ==0)?CC_TRUE:CC_FALSE;\ 366 }\ 367 }while(0) 368 369 /*! 370 * This function is used to wrap the input and output data buffers to 2 info structs. 371 * The function call a PAL function to verify each buffer validity memory. 372 * It also get the buffer attribute (secure / non-secure) from the PAL function. 373 * 374 * \param pDataIn A pointer to the input data buffer. 375 * \param dataInSize - number bytes of input data buffer. 376 * \param pInputBuffInfo A structure which represents the data input buffer. 377 * \param pDataOut A pointer to the output data buffer. 378 * \param dataOutSize - number bytes of output data buffer. 379 * \param pOutputBuffInfo A structure which represents the data output buffer. 380 * 381 * \return drvError_t defined in cc_error.h. 382 */ 383 drvError_t SetDataBuffersInfo(const uint8_t *pDataIn, size_t dataInSize, CCBuffInfo_t *pInputBuffInfo, 384 const uint8_t *pDataOut, size_t dataOutSize, CCBuffInfo_t *pOutputBuffInfo); 385 386 #endif /* _DRIVER_DEFS_H_ */ 387 388
