| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/hal/Inc/ |
| D | stm32u5xx_hal_rcc_ex.h | 248 #if defined(CRS)
718 #if defined(CRS)
1765 #if defined(CRS)
1777 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
1789 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
1800 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) …
1818 WRITE_REG(CRS->ICR, CRS_ICR_ERRC |\
1823 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
1840 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
1863 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/hal/Inc/ |
| D | stm32l5xx_hal_rcc_ex.h | 187 #if defined(CRS)
562 #if defined(CRS)
1721 #if defined(CRS)
1737 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
1749 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
1760 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1…
1780 … WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
1784 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
1801 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
1825 … WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/hal/Inc/ |
| D | stm32h5xx_hal_rcc_ex.h | 364 #if defined(CRS)
1258 #if defined(CRS)
3010 #if defined(CRS)
3022 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
3034 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
3045 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? 1…
3065 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \
3070 WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
3087 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
3112 WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/hal/Src/ |
| D | stm32l5xx_hal_rcc_ex.c | 2045 #if defined(CRS)
2142 WRITE_REG(CRS->CFGR, value); in HAL_RCCEx_CRSConfig()
2146 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); in HAL_RCCEx_CRSConfig()
2151 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); in HAL_RCCEx_CRSConfig()
2160 SET_BIT(CRS->CR, CRS_CR_SWSYNC); in HAL_RCCEx_CRSSoftwareSynchronizationGenerate()
2174 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in HAL_RCCEx_CRSGetSynchronizationInfo()
2177 …pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos… in HAL_RCCEx_CRSGetSynchronizationInfo()
2180 …pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos… in HAL_RCCEx_CRSGetSynchronizationInfo()
2183 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); in HAL_RCCEx_CRSGetSynchronizationInfo()
2294 uint32_t itflags = READ_REG(CRS->ISR); in HAL_RCCEx_CRS_IRQHandler()
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/hal/Src/ |
| D | stm32u5xx_hal_rcc_ex.c | 248 #if defined(CRS)
2913 #if defined(CRS)
3010 WRITE_REG(CRS->CFGR, value); in HAL_RCCEx_CRSConfig()
3014 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); in HAL_RCCEx_CRSConfig()
3019 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); in HAL_RCCEx_CRSConfig()
3028 SET_BIT(CRS->CR, CRS_CR_SWSYNC); in HAL_RCCEx_CRSSoftwareSynchronizationGenerate()
3042 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in HAL_RCCEx_CRSGetSynchronizationInfo()
3045 …pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos… in HAL_RCCEx_CRSGetSynchronizationInfo()
3048 …pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos… in HAL_RCCEx_CRSGetSynchronizationInfo()
3051 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); in HAL_RCCEx_CRSGetSynchronizationInfo()
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/hal/Src/ |
| D | stm32h5xx_hal_rcc_ex.c | 5699 #if defined(CRS)
5796 WRITE_REG(CRS->CFGR, value); in HAL_RCCEx_CRSConfig()
5800 MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); in HAL_RCCEx_CRSConfig()
5805 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); in HAL_RCCEx_CRSConfig()
5814 SET_BIT(CRS->CR, CRS_CR_SWSYNC); in HAL_RCCEx_CRSSoftwareSynchronizationGenerate()
5828 pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); in HAL_RCCEx_CRSGetSynchronizationInfo()
5831 …pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos… in HAL_RCCEx_CRSGetSynchronizationInfo()
5834 …pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos… in HAL_RCCEx_CRSGetSynchronizationInfo()
5837 pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); in HAL_RCCEx_CRSGetSynchronizationInfo()
5942 uint32_t itflags = READ_REG(CRS->ISR); in HAL_RCCEx_CRS_IRQHandler()
[all …]
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32l5xx/Device/Include/ |
| D | stm32l552xx.h | 2337 #define CRS CRS_S macro
2751 #define CRS CRS_NS macro
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| D | stm32l562xx.h | 2439 #define CRS CRS_S macro
2874 #define CRS CRS_NS macro
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32u5xx/Device/Include/ |
| D | stm32u585xx.h | 2787 #define CRS CRS_S macro
3267 #define CRS CRS_NS macro
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| /trusted-firmware-m-3.7.0/platform/ext/target/stm/common/stm32h5xx/Device/Include/ |
| D | stm32h573xx.h | 2981 #define CRS CRS_S macro
3426 #define CRS CRS_NS macro
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