1 /**************************************************************************//** 2 * @file epwm_reg.h 3 * @version V1.00 4 * @brief EPWM register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EPWM_REG_H__ 10 #define __EPWM_REG_H__ 11 12 /** 13 @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 20 /*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/ 21 /** 22 @addtogroup EPWM Enhanced Pulse Width Modulation Controller(EPWM) 23 Memory Mapped Structure for EPWM Controller 24 @{ 25 */ 26 27 typedef struct 28 { 29 /** 30 * @var ECAPDAT_T::RCAPDAT 31 * Offset: 0x20C EPWM Rising Capture Data Register 0~5 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[15:0] |RCAPDAT |EPWM Rising Capture Data (Read Only) 36 * | | |When rising capture condition happened, the EPWM counter value will be saved in this register. 37 * @var ECAPDAT_T::FCAPDAT 38 * Offset: 0x210 EPWM Falling Capture Data Register 0~5 39 * --------------------------------------------------------------------------------------------------- 40 * |Bits |Field |Descriptions 41 * | :----: | :----: | :---- | 42 * |[15:0] |FCAPDAT |EPWM Falling Capture Data (Read Only) 43 * | | |When falling capture condition happened, the EPWM counter value will be saved in this register. 44 */ 45 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] EPWM Rising Capture Data Register 0~5 */ 46 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] EPWM Falling Capture Data Register 0~5 */ 47 } ECAPDAT_T; 48 49 typedef struct 50 { 51 52 53 /** 54 * @var EPWM_T::CTL0 55 * Offset: 0x00 EPWM Control Register 0 56 * --------------------------------------------------------------------------------------------------- 57 * |Bits |Field |Descriptions 58 * | :----: | :----: | :---- | 59 * |[0] |CTRLD0 |Center Re-load 60 * | | |In up-down counter type, PERIOD0 register will load to PBUF0 register at the end point of each period. 61 * | | |CMPDAT0 register will load to CMPBUF0 register at the center point of a period. 62 * |[1] |CTRLD1 |Center Re-load 63 * | | |In up-down counter type, PERIOD1 register will load to PBUF1 register at the end point of each period. 64 * | | |CMPDAT1 register will load to CMPBUF1 register at the center point of a period. 65 * |[2] |CTRLD2 |Center Re-load 66 * | | |In up-down counter type, PERIOD2 register will load to PBUF2 register at the end point of each period. 67 * | | |CMPDAT2 register will load to CMPBUF2 register at the center point of a period. 68 * |[3] |CTRLD3 |Center Re-load 69 * | | |In up-down counter type, PERIOD3 register will load to PBUF3 register at the end point of each period. 70 * | | |CMPDAT3 register will load to CMPBUF3 register at the center point of a period. 71 * |[4] |CTRLD4 |Center Re-load 72 * | | |In up-down counter type, PERIOD4 register will load to PBUF4 register at the end point of each period. 73 * | | |CMPDAT4 register will load to CMPBUF4 register at the center point of a period. 74 * |[5] |CTRLD5 |Center Re-load 75 * | | |In up-down counter type, PERIOD5 register will load to PBUF5 register at the end point of each period. 76 * | | |CMPDAT5 register will load to CMPBUF5 register at the center point of a period. 77 * |[8] |WINLDEN0 |Window Load Enable Bits 78 * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. 79 * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. 80 * | | |1 = PERIOD0 register will load to PBUF0 and CMPDAT0 registers will load to CMPBUF0 register at the end point of each period when valid reload window is set. 81 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. 82 * |[9] |WINLDEN1 |Window Load Enable Bits 83 * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. 84 * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. 85 * | | |1 = PERIOD1 register will load to PBUF1 and CMPDAT1 registers will load to CMPBUF1 register at the end point of each period when valid reload window is set. 86 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. 87 * |[10] |WINLDEN2 |Window Load Enable Bits 88 * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. 89 * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. 90 * | | |1 = PERIOD2 register will load to PBUF2 and CMPDAT2 registers will load to CMPBUF2 register at the end point of each period when valid reload window is set. 91 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. 92 * |[11] |WINLDEN3 |Window Load Enable Bits 93 * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. 94 * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. 95 * | | |1 = PERIOD3 register will load to PBUF3 and CMPDAT3 registers will load to CMPBUF3 register at the end point of each period when valid reload window is set. 96 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. 97 * |[12] |WINLDEN4 |Window Load Enable Bits 98 * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. 99 * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. 100 * | | |1 = PERIOD4 register will load to PBUF4 and CMPDAT4 registers will load to CMPBUF4 register at the end point of each period when valid reload window is set. 101 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. 102 * |[13] |WINLDEN5 |Window Load Enable Bits 103 * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. 104 * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. 105 * | | |1 = PERIOD5 register will load to PBUF5 and CMPDAT5 registers will load to CMPBUF5 register at the end point of each period when valid reload window is set. 106 * | | |The valid reload window is set by software write 1 to EPWM_LOAD register, and cleared by hardware after load success. 107 * |[16] |IMMLDEN0 |Immediately Load Enable Bits 108 * | | |0 = PERIOD0 register will load to PBUF0 register at the end point of each period. 109 * | | |CMPDAT0 register will load to CMPBUF0 register at the end point or center point of each period by setting CTRLD0 bit. 110 * | | |1 = PERIOD0/CMPDAT0 registers will load to PBUF0 and CMPBUF0 register immediately when software update PERIOD0/CMPDAT0 register. 111 * | | |Note: If IMMLDEN0 bit is enabled, WINLDEN0 bit and CTRLD0 bits will be invalid. 112 * |[17] |IMMLDEN1 |Immediately Load Enable Bits 113 * | | |0 = PERIOD1 register will load to PBUF1 register at the end point of each period. 114 * | | |CMPDAT1 register will load to CMPBUF1 register at the end point or center point of each period by setting CTRLD1 bit. 115 * | | |1 = PERIOD1/CMPDAT1 registers will load to PBUF1 and CMPBUF1 register immediately when software update PERIOD1/CMPDAT1 register. 116 * | | |Note: If IMMLDEN1 bit is enabled, WINLDEN1 bit and CTRLD1 bits will be invalid. 117 * |[18] |IMMLDEN2 |Immediately Load Enable Bits 118 * | | |0 = PERIOD2 register will load to PBUF2 register at the end point of each period. 119 * | | |CMPDAT2 register will load to CMPBUF2 register at the end point or center point of each period by setting CTRLD2 bit. 120 * | | |1 = PERIOD2/CMPDAT2 registers will load to PBUF2 and CMPBUF2 register immediately when software update PERIOD2/CMPDAT2 register. 121 * | | |Note: If IMMLDEN2 bit is enabled, WINLDEN2 bit and CTRLD2 bits will be invalid. 122 * |[19] |IMMLDEN3 |Immediately Load Enable Bits 123 * | | |0 = PERIOD3 register will load to PBUF3 register at the end point of each period. 124 * | | |CMPDAT3 register will load to CMPBUF3 register at the end point or center point of each period by setting CTRLD3 bit. 125 * | | |1 = PERIOD3/CMPDAT3 registers will load to PBUF3 and CMPBUF3 register immediately when software update PERIOD3/CMPDAT3 register. 126 * | | |Note: If IMMLDEN3 bit is enabled, WINLDEN3 bit and CTRLD3 bits will be invalid. 127 * |[20] |IMMLDEN4 |Immediately Load Enable Bits 128 * | | |0 = PERIOD4 register will load to PBUF4 register at the end point of each period. 129 * | | |CMPDAT4 register will load to CMPBUF4 register at the end point or center point of each period by setting CTRLD4 bit. 130 * | | |1 = PERIOD4/CMPDAT4 registers will load to PBUF4 and CMPBUF4 register immediately when software update PERIOD4/CMPDAT4 register. 131 * | | |Note: If IMMLDEN4 bit is enabled, WINLDEN4 bit and CTRLD4 bits will be invalid. 132 * |[21] |IMMLDEN5 |Immediately Load Enable Bits 133 * | | |0 = PERIOD5 register will load to PBUF5 register at the end point of each period. 134 * | | |CMPDAT5 register will load to CMPBUF5 register at the end point or center point of each period by setting CTRLD5 bit. 135 * | | |1 = PERIOD5/CMPDAT5 registers will load to PBUF5 and CMPBUF5 register immediately when software update PERIOD5/CMPDAT5 register. 136 * | | |Note: If IMMLDEN5 bit is enabled, WINLDEN5 bit and CTRLD5 bits will be invalid. 137 * |[24] |GROUPEN |Group Function Enable Bit 138 * | | |0 = The output waveform of each EPWM channel are independent. 139 * | | |1 = Unify the EPWMx_CH2 and EPWMx_CH4 to output the same waveform as EPWMx_CH0 and unify the EPWMx_CH3 and EPWMx_CH5 to output the same waveform as EPWMx_CH1. 140 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 141 * | | |If counter halt is enabled, EPWM all counters will keep current value until exit ICE debug mode. 142 * | | |0 = ICE debug mode counter halt disable. 143 * | | |1 = ICE debug mode counter halt enable. 144 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 145 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) 146 * | | |0 = ICE debug mode acknowledgement effects EPWM output. 147 * | | |EPWM pin will be forced as tri-state while ICE debug mode acknowledged. 148 * | | |1 = ICE debug mode acknowledgement disabled. 149 * | | |EPWM pin will keep output no matter ICE debug mode acknowledged or not. 150 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 151 * @var EPWM_T::CTL1 152 * Offset: 0x04 EPWM Control Register 1 153 * --------------------------------------------------------------------------------------------------- 154 * |Bits |Field |Descriptions 155 * | :----: | :----: | :---- | 156 * |[1:0] |CNTTYPE0 |EPWM Counter Behavior Type 157 * | | |00 = Up counter type (supports in capture mode). 158 * | | |01 = Down count type (supports in capture mode). 159 * | | |10 = Up-down counter type. 160 * | | |11 = Reserved. 161 * |[3:2] |CNTTYPE1 |EPWM Counter Behavior Type 162 * | | |00 = Up counter type (supports in capture mode). 163 * | | |01 = Down count type (supports in capture mode). 164 * | | |10 = Up-down counter type. 165 * | | |11 = Reserved. 166 * |[5:4] |CNTTYPE2 |EPWM Counter Behavior Type 167 * | | |00 = Up counter type (supports in capture mode). 168 * | | |01 = Down count type (supports in capture mode). 169 * | | |10 = Up-down counter type. 170 * | | |11 = Reserved. 171 * |[7:6] |CNTTYPE3 |EPWM Counter Behavior Type 172 * | | |00 = Up counter type (supports in capture mode). 173 * | | |01 = Down count type (supports in capture mode). 174 * | | |10 = Up-down counter type. 175 * | | |11 = Reserved. 176 * |[9:8] |CNTTYPE4 |EPWM Counter Behavior Type 177 * | | |00 = Up counter type (supports in capture mode). 178 * | | |01 = Down count type (supports in capture mode). 179 * | | |10 = Up-down counter type. 180 * | | |11 = Reserved. 181 * |[11:10] |CNTTYPE5 |EPWM Counter Behavior Type 182 * | | |00 = Up counter type (supports in capture mode). 183 * | | |01 = Down count type (supports in capture mode). 184 * | | |10 = Up-down counter type. 185 * | | |11 = Reserved. 186 * |[16] |CNTMODE0 |EPWM Counter Mode 187 * | | |0 = Auto-reload mode. 188 * | | |1 = One-shot mode. 189 * |[17] |CNTMODE1 |EPWM Counter Mode 190 * | | |0 = Auto-reload mode. 191 * | | |1 = One-shot mode. 192 * |[18] |CNTMODE2 |EPWM Counter Mode 193 * | | |0 = Auto-reload mode. 194 * | | |1 = One-shot mode. 195 * |[19] |CNTMODE3 |EPWM Counter Mode 196 * | | |0 = Auto-reload mode. 197 * | | |1 = One-shot mode. 198 * |[20] |CNTMODE4 |EPWM Counter Mode 199 * | | |0 = Auto-reload mode. 200 * | | |1 = One-shot mode. 201 * |[21] |CNTMODE5 |EPWM Counter Mode 202 * | | |0 = Auto-reload mode. 203 * | | |1 = One-shot mode. 204 * |[24] |OUTMODE0 |EPWM Output Mode 205 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 206 * | | |0 = EPWM independent mode. 207 * | | |1 = EPWM complementary mode. 208 * | | |Note: When operating in group function, these bits must all set to the same mode. 209 * |[25] |OUTMODE2 |EPWM Output Mode 210 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 211 * | | |0 = EPWM independent mode. 212 * | | |1 = EPWM complementary mode. 213 * | | |Note: When operating in group function, these bits must all set to the same mode. 214 * |[26] |OUTMODE4 |EPWM Output Mode 215 * | | |Each bit n controls the output mode of corresponding EPWM channel n. 216 * | | |0 = EPWM independent mode. 217 * | | |1 = EPWM complementary mode. 218 * | | |Note: When operating in group function, these bits must all set to the same mode. 219 * @var EPWM_T::SYNC 220 * Offset: 0x08 EPWM Synchronization Register 221 * --------------------------------------------------------------------------------------------------- 222 * |Bits |Field |Descriptions 223 * | :----: | :----: | :---- | 224 * |[0] |PHSEN0 |SYNC Phase Enable Bits 225 * | | |0 = EPWM counter disable to load PHS value. 226 * | | |1 = EPWM counter enable to load PHS value. 227 * |[1] |PHSEN2 |SYNC Phase Enable Bits 228 * | | |0 = EPWM counter disable to load PHS value. 229 * | | |1 = EPWM counter enable to load PHS value. 230 * |[2] |PHSEN4 |SYNC Phase Enable Bits 231 * | | |0 = EPWM counter disable to load PHS value. 232 * | | |1 = EPWM counter enable to load PHS value. 233 * |[9:8] |SINSRC0 |EPWM0_SYNC_IN Source Selection 234 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 235 * | | |01 = Counter equal to 0. 236 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 237 * | | |11 = SYNC_OUT will not be generated. 238 * |[11:10] |SINSRC2 |EPWM0_SYNC_IN Source Selection 239 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 240 * | | |01 = Counter equal to 0. 241 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 242 * | | |11 = SYNC_OUT will not be generated. 243 * |[13:12] |SINSRC4 |EPWM0_SYNC_IN Source Selection 244 * | | |00 = Synchronize source from SYNC_IN or SWSYNC. 245 * | | |01 = Counter equal to 0. 246 * | | |10 = Counter equal to EPWM_CMPDATm, m denotes 1, 3, 5. 247 * | | |11 = SYNC_OUT will not be generated. 248 * |[16] |SNFLTEN |EPWM0_SYNC_IN Noise Filter Enable Bits 249 * | | |0 = Noise filter of input pin EPWM0_SYNC_IN is Disabled. 250 * | | |1 = Noise filter of input pin EPWM0_SYNC_IN is Enabled. 251 * |[19:17] |SFLTCSEL |SYNC Edge Detector Filter Clock Selection 252 * | | |000 = Filter clock = HCLK. 253 * | | |001 = Filter clock = HCLK/2. 254 * | | |010 = Filter clock = HCLK/4. 255 * | | |011 = Filter clock = HCLK/8. 256 * | | |100 = Filter clock = HCLK/16. 257 * | | |101 = Filter clock = HCLK/32. 258 * | | |110 = Filter clock = HCLK/64. 259 * | | |111 = Filter clock = HCLK/128. 260 * |[22:20] |SFLTCNT |SYNC Edge Detector Filter Count 261 * | | |The register bits control the counter number of edge detector. 262 * |[23] |SINPINV |SYNC Input Pin Inverse 263 * | | |0 = The state of pin EPWM0_SYNC_IN is passed to the negative edge detector. 264 * | | |1 = The inverse state of pin EPWM0_SYNC_IN is passed to the negative edge detector. 265 * |[24] |PHSDIR0 |EPWM Phase Direction Control 266 * | | |0 = Control EPWM counter count decrement after synchronizing. 267 * | | |1 = Control EPWM counter count increment after synchronizing. 268 * |[25] |PHSDIR2 |EPWM Phase Direction Control 269 * | | |0 = Control EPWM counter count decrement after synchronizing. 270 * | | |1 = Control EPWM counter count increment after synchronizing. 271 * |[26] |PHSDIR4 |EPWM Phase Direction Control 272 * | | |0 = Control EPWM counter count decrement after synchronizing. 273 * | | |1 = Control EPWM counter count increment after synchronizing. 274 * @var EPWM_T::SWSYNC 275 * Offset: 0x0C EPWM Software Control Synchronization Register 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[0] |SWSYNC0 |Software SYNC Function 280 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 281 * |[1] |SWSYNC2 |Software SYNC Function 282 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 283 * |[2] |SWSYNC4 |Software SYNC Function 284 * | | |When SINSRCn (EPWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit. 285 * @var EPWM_T::CLKSRC 286 * Offset: 0x10 EPWM Clock Source Register 287 * --------------------------------------------------------------------------------------------------- 288 * |Bits |Field |Descriptions 289 * | :----: | :----: | :---- | 290 * |[2:0] |ECLKSRC0 |EPWM_CH01 External Clock Source Select 291 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 292 * | | |001 = TIMER0 overflow. 293 * | | |010 = TIMER1 overflow. 294 * | | |011 = TIMER2 overflow. 295 * | | |100 = TIMER3 overflow. 296 * | | |Others = Reserved. 297 * |[10:8] |ECLKSRC2 |EPWM_CH23 External Clock Source Select 298 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 299 * | | |001 = TIMER0 overflow. 300 * | | |010 = TIMER1 overflow. 301 * | | |011 = TIMER2 overflow. 302 * | | |100 = TIMER3 overflow. 303 * | | |Others = Reserved. 304 * |[18:16] |ECLKSRC4 |EPWM_CH45 External Clock Source Select 305 * | | |000 = EPWMx_CLK, x denotes 0 or 1. 306 * | | |001 = TIMER0 overflow. 307 * | | |010 = TIMER1 overflow. 308 * | | |011 = TIMER2 overflow. 309 * | | |100 = TIMER3 overflow. 310 * | | |Others = Reserved. 311 * @var EPWM_T::CLKPSC[3] 312 * Offset: 0x14 EPWM Clock Prescale Register 0/1, 2/3, 4/5 313 * --------------------------------------------------------------------------------------------------- 314 * |Bits |Field |Descriptions 315 * | :----: | :----: | :---- | 316 * |[11:0] |CLKPSC |EPWM Counter Clock Prescale 317 * | | |The clock of EPWM counter is decided by clock prescaler 318 * | | |Each EPWM pair share one EPWM counter clock prescaler 319 * | | |The clock of EPWM counter is divided by (CLKPSC+ 1) 320 * @var EPWM_T::CNTEN 321 * Offset: 0x20 EPWM Counter Enable Register 322 * --------------------------------------------------------------------------------------------------- 323 * |Bits |Field |Descriptions 324 * | :----: | :----: | :---- | 325 * |[0] |CNTEN0 |EPWM Counter Enable Bits 326 * | | |0 = EPWM Counter and clock prescaler Stop Running. 327 * | | |1 = EPWM Counter and clock prescaler Start Running. 328 * |[1] |CNTEN1 |EPWM Counter Enable Bits 329 * | | |0 = EPWM Counter and clock prescaler Stop Running. 330 * | | |1 = EPWM Counter and clock prescaler Start Running. 331 * |[2] |CNTEN2 |EPWM Counter Enable Bits 332 * | | |0 = EPWM Counter and clock prescaler Stop Running. 333 * | | |1 = EPWM Counter and clock prescaler Start Running. 334 * |[3] |CNTEN3 |EPWM Counter Enable Bits 335 * | | |0 = EPWM Counter and clock prescaler Stop Running. 336 * | | |1 = EPWM Counter and clock prescaler Start Running. 337 * |[4] |CNTEN4 |EPWM Counter Enable Bits 338 * | | |0 = EPWM Counter and clock prescaler Stop Running. 339 * | | |1 = EPWM Counter and clock prescaler Start Running. 340 * |[5] |CNTEN5 |EPWM Counter Enable Bits 341 * | | |0 = EPWM Counter and clock prescaler Stop Running. 342 * | | |1 = EPWM Counter and clock prescaler Start Running. 343 * @var EPWM_T::CNTCLR 344 * Offset: 0x24 EPWM Clear Counter Register 345 * --------------------------------------------------------------------------------------------------- 346 * |Bits |Field |Descriptions 347 * | :----: | :----: | :---- | 348 * |[0] |CNTCLR0 |Clear EPWM Counter Control Bit 349 * | | |It is automatically cleared by hardware. 350 * | | |0 = No effect. 351 * | | |1 = Clear 16-bit EPWM counter to 0000H. 352 * |[1] |CNTCLR1 |Clear EPWM Counter Control Bit 353 * | | |It is automatically cleared by hardware. 354 * | | |0 = No effect. 355 * | | |1 = Clear 16-bit EPWM counter to 0000H. 356 * |[2] |CNTCLR2 |Clear EPWM Counter Control Bit 357 * | | |It is automatically cleared by hardware. 358 * | | |0 = No effect. 359 * | | |1 = Clear 16-bit EPWM counter to 0000H. 360 * |[3] |CNTCLR3 |Clear EPWM Counter Control Bit 361 * | | |It is automatically cleared by hardware. 362 * | | |0 = No effect. 363 * | | |1 = Clear 16-bit EPWM counter to 0000H. 364 * |[4] |CNTCLR4 |Clear EPWM Counter Control Bit 365 * | | |It is automatically cleared by hardware. 366 * | | |0 = No effect. 367 * | | |1 = Clear 16-bit EPWM counter to 0000H. 368 * |[5] |CNTCLR5 |Clear EPWM Counter Control Bit 369 * | | |It is automatically cleared by hardware. 370 * | | |0 = No effect. 371 * | | |1 = Clear 16-bit EPWM counter to 0000H. 372 * @var EPWM_T::LOAD 373 * Offset: 0x28 EPWM Load Register 374 * --------------------------------------------------------------------------------------------------- 375 * |Bits |Field |Descriptions 376 * | :----: | :----: | :---- | 377 * |[0] |LOAD0 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 378 * | | |This bit is software write, hardware clear when current EPWM period end. 379 * | | |Write Operation: 380 * | | |0 = No effect. 381 * | | |1 = Set load window of window loading mode. 382 * | | |Read Operation: 383 * | | |0 = No load window is set. 384 * | | |1 = Load window is set. 385 * | | |Note: This bit only use in window loading mode, WINLDEN0(EPWM_CTL0[13:8]) = 1. 386 * |[1] |LOAD1 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 387 * | | |This bit is software write, hardware clear when current EPWM period end. 388 * | | |Write Operation: 389 * | | |0 = No effect. 390 * | | |1 = Set load window of window loading mode. 391 * | | |Read Operation: 392 * | | |0 = No load window is set. 393 * | | |1 = Load window is set. 394 * | | |Note: This bit only use in window loading mode, WINLDEN1(EPWM_CTL0[13:8]) = 1. 395 * |[2] |LOAD2 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 396 * | | |This bit is software write, hardware clear when current EPWM period end. 397 * | | |Write Operation: 398 * | | |0 = No effect. 399 * | | |1 = Set load window of window loading mode. 400 * | | |Read Operation: 401 * | | |0 = No load window is set. 402 * | | |1 = Load window is set. 403 * | | |Note: This bit only use in window loading mode, WINLDEN2(EPWM_CTL0[13:8]) = 1. 404 * |[3] |LOAD3 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 405 * | | |This bit is software write, hardware clear when current EPWM period end. 406 * | | |Write Operation: 407 * | | |0 = No effect. 408 * | | |1 = Set load window of window loading mode. 409 * | | |Read Operation: 410 * | | |0 = No load window is set. 411 * | | |1 = Load window is set. 412 * | | |Note: This bit only use in window loading mode, WINLDEN3(EPWM_CTL0[13:8]) = 1. 413 * |[4] |LOAD4 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 414 * | | |This bit is software write, hardware clear when current EPWM period end. 415 * | | |Write Operation: 416 * | | |0 = No effect. 417 * | | |1 = Set load window of window loading mode. 418 * | | |Read Operation: 419 * | | |0 = No load window is set. 420 * | | |1 = Load window is set. 421 * | | |Note: This bit only use in window loading mode, WINLDEN4(EPWM_CTL0[13:8]) = 1. 422 * |[5] |LOAD5 |Re-load EPWM Comparator Register (CMPDAT) Control Bit 423 * | | |This bit is software write, hardware clear when current EPWM period end. 424 * | | |Write Operation: 425 * | | |0 = No effect. 426 * | | |1 = Set load window of window loading mode. 427 * | | |Read Operation: 428 * | | |0 = No load window is set. 429 * | | |1 = Load window is set. 430 * | | |Note: This bit only use in window loading mode, WINLDENn(EPWM_CTL0[13:8]) = 1. 431 * @var EPWM_T::PERIOD[6] 432 * Offset: 0x30 EPWM Period Register 0~5 433 * --------------------------------------------------------------------------------------------------- 434 * |Bits |Field |Descriptions 435 * | :----: | :----: | :---- | 436 * |[15:0] |PERIOD |EPWM Period Register 437 * | | |Up-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, and restarts from 0. 438 * | | |Down-Count mode: In this mode, EPWM counter counts from PERIOD to 0, and restarts from PERIOD. 439 * | | |EPWM period time = (PERIOD+1) * EPWM_CLK period. 440 * | | |Up-Down-Count mode: In this mode, EPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 441 * | | |EPWM period time = 2 * PERIOD * EPWM_CLK period. 442 * @var EPWM_T::CMPDAT[6] 443 * Offset: 0x50 EPWM Comparator Register 0 444 * --------------------------------------------------------------------------------------------------- 445 * |Bits |Field |Descriptions 446 * | :----: | :----: | :---- | 447 * |[15:0] |CMP |EPWM Comparator Register 448 * | | |CMP use to compare with CNTR to generate EPWM waveform, interrupt and trigger EADC/DAC. 449 * | | |In independent mode, CMPDAT0~5 denote as 6 independent EPWM_CH0~5 compared point. 450 * | | |In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 451 * @var EPWM_T::DTCTL[3] 452 * Offset: 0x70 EPWM Dead-Time Control Register 0/1,2/3,4/5 453 * --------------------------------------------------------------------------------------------------- 454 * |Bits |Field |Descriptions 455 * | :----: | :----: | :---- | 456 * |[11:0] |DTCNT |Dead-time Counter (Write Protect) 457 * | | |The dead-time can be calculated from the following formula: 458 * | | |Dead-time = (DTCNT[11:0]+1) * EPWM_CLK period. 459 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 460 * |[16] |DTEN |Enable Dead-time Insertion for EPWM Pair (EPWM_CH0, EPWM_CH1) (EPWM_CH2, EPWM_CH3) (EPWM_CH4, EPWM_CH5) (Write Protect) 461 * | | |Dead-time insertion is only active when this pair of complementary EPWM is enabled 462 * | | |If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay. 463 * | | |0 = Dead-time insertion Disabled on the pin pair. 464 * | | |1 = Dead-time insertion Enabled on the pin pair. 465 * | | |Note: This register is write protected. Refer toSYS_REGLCTL register. 466 * |[24] |DTCKSEL |Dead-time Clock Select (Write Protect) 467 * | | |0 = Dead-time clock source from EPWM_CLK. 468 * | | |1 = Dead-time clock source from prescaler output. 469 * | | |Note: This register is write protected. Refer toREGWRPROT register. 470 * @var EPWM_T::PHS[3] 471 * Offset: 0x80 EPWM Counter Phase Register 0/1,2/3,4/5 472 * --------------------------------------------------------------------------------------------------- 473 * |Bits |Field |Descriptions 474 * | :----: | :----: | :---- | 475 * |[15:0] |PHS |EPWM Synchronous Start Phase Bits 476 * | | |PHS determines the EPWM synchronous start phase value. These bits only use in synchronous function. 477 * @var EPWM_T::CNT[6] 478 * Offset: 0x90 EPWM Counter Register 0~5 479 * --------------------------------------------------------------------------------------------------- 480 * |Bits |Field |Descriptions 481 * | :----: | :----: | :---- | 482 * |[15:0] |CNT |EPWM Data Register (Read Only) 483 * | | |User can monitor CNTR to know the current value in 16-bit period counter. 484 * |[16] |DIRF |EPWM Direction Indicator Flag (Read Only) 485 * | | |0 = Counter is Down count. 486 * | | |1 = Counter is UP count. 487 * @var EPWM_T::WGCTL0 488 * Offset: 0xB0 EPWM Generation Register 0 489 * --------------------------------------------------------------------------------------------------- 490 * |Bits |Field |Descriptions 491 * | :----: | :----: | :---- | 492 * |[1:0] |ZPCTL0 |EPWM Zero Point Control 493 * | | |00 = Do nothing. 494 * | | |01 = EPWM zero point output Low. 495 * | | |10 = EPWM zero point output High. 496 * | | |11 = EPWM zero point output Toggle. 497 * | | |EPWM can control output level when EPWM counter count to zero. 498 * |[3:2] |ZPCTL1 |EPWM Zero Point Control 499 * | | |00 = Do nothing. 500 * | | |01 = EPWM zero point output Low. 501 * | | |10 = EPWM zero point output High. 502 * | | |11 = EPWM zero point output Toggle. 503 * | | |EPWM can control output level when EPWM counter count to zero. 504 * |[5:4] |ZPCTL2 |EPWM Zero Point Control 505 * | | |00 = Do nothing. 506 * | | |01 = EPWM zero point output Low. 507 * | | |10 = EPWM zero point output High. 508 * | | |11 = EPWM zero point output Toggle. 509 * | | |EPWM can control output level when EPWM counter count to zero. 510 * |[7:6] |ZPCTL3 |EPWM Zero Point Control 511 * | | |00 = Do nothing. 512 * | | |01 = EPWM zero point output Low. 513 * | | |10 = EPWM zero point output High. 514 * | | |11 = EPWM zero point output Toggle. 515 * | | |EPWM can control output level when EPWM counter count to zero. 516 * |[9:8] |ZPCTL4 |EPWM Zero Point Control 517 * | | |00 = Do nothing. 518 * | | |01 = EPWM zero point output Low. 519 * | | |10 = EPWM zero point output High. 520 * | | |11 = EPWM zero point output Toggle. 521 * | | |EPWM can control output level when EPWM counter count to zero. 522 * |[11:10] |ZPCTL5 |EPWM Zero Point Control 523 * | | |00 = Do nothing. 524 * | | |01 = EPWM zero point output Low. 525 * | | |10 = EPWM zero point output High. 526 * | | |11 = EPWM zero point output Toggle. 527 * | | |EPWM can control output level when EPWM counter count to zero. 528 * |[17:16] |PRDPCTL0 |EPWM Period (Center) Point Control 529 * | | |00 = Do nothing. 530 * | | |01 = EPWM period (center) point output Low. 531 * | | |10 = EPWM period (center) point output High. 532 * | | |11 = EPWM period (center) point output Toggle. 533 * | | |EPWM can control output level when EPWM counter count to (PERIOD0+1). 534 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 535 * |[19:18] |PRDPCTL1 |EPWM Period (Center) Point Control 536 * | | |00 = Do nothing. 537 * | | |01 = EPWM period (center) point output Low. 538 * | | |10 = EPWM period (center) point output High. 539 * | | |11 = EPWM period (center) point output Toggle. 540 * | | |EPWM can control output level when EPWM counter count to (PERIOD1+1). 541 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 542 * |[21:20] |PRDPCTL2 |EPWM Period (Center) Point Control 543 * | | |00 = Do nothing. 544 * | | |01 = EPWM period (center) point output Low. 545 * | | |10 = EPWM period (center) point output High. 546 * | | |11 = EPWM period (center) point output Toggle. 547 * | | |EPWM can control output level when EPWM counter count to (PERIOD2+1). 548 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 549 * |[23:22] |PRDPCTL3 |EPWM Period (Center) Point Control 550 * | | |00 = Do nothing. 551 * | | |01 = EPWM period (center) point output Low. 552 * | | |10 = EPWM period (center) point output High. 553 * | | |11 = EPWM period (center) point output Toggle. 554 * | | |EPWM can control output level when EPWM counter count to (PERIOD3+1). 555 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 556 * |[25:24] |PRDPCTL4 |EPWM Period (Center) Point Control 557 * | | |00 = Do nothing. 558 * | | |01 = EPWM period (center) point output Low. 559 * | | |10 = EPWM period (center) point output High. 560 * | | |11 = EPWM period (center) point output Toggle. 561 * | | |EPWM can control output level when EPWM counter count to (PERIOD4+1). 562 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 563 * |[27:26] |PRDPCTL5 |EPWM Period (Center) Point Control 564 * | | |00 = Do nothing. 565 * | | |01 = EPWM period (center) point output Low. 566 * | | |10 = EPWM period (center) point output High. 567 * | | |11 = EPWM period (center) point output Toggle. 568 * | | |EPWM can control output level when EPWM counter count to (PERIOD5+1). 569 * | | |Note: This bit is center point control when EPWM counter operating in up-down counter type. 570 * @var EPWM_T::WGCTL1 571 * Offset: 0xB4 EPWM Generation Register 1 572 * --------------------------------------------------------------------------------------------------- 573 * |Bits |Field |Descriptions 574 * | :----: | :----: | :---- | 575 * |[1:0] |CMPUCTL0 |EPWM Compare Up Point Control 576 * | | |00 = Do nothing. 577 * | | |01 = EPWM compare up point output Low. 578 * | | |10 = EPWM compare up point output High. 579 * | | |11 = EPWM compare up point output Toggle. 580 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 581 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 582 * |[3:2] |CMPUCTL1 |EPWM Compare Up Point Control 583 * | | |00 = Do nothing. 584 * | | |01 = EPWM compare up point output Low. 585 * | | |10 = EPWM compare up point output High. 586 * | | |11 = EPWM compare up point output Toggle. 587 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 588 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 589 * |[5:4] |CMPUCTL2 |EPWM Compare Up Point Control 590 * | | |00 = Do nothing. 591 * | | |01 = EPWM compare up point output Low. 592 * | | |10 = EPWM compare up point output High. 593 * | | |11 = EPWM compare up point output Toggle. 594 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 595 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 596 * |[7:6] |CMPUCTL3 |EPWM Compare Up Point Control 597 * | | |00 = Do nothing. 598 * | | |01 = EPWM compare up point output Low. 599 * | | |10 = EPWM compare up point output High. 600 * | | |11 = EPWM compare up point output Toggle. 601 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 602 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 603 * |[9:8] |CMPUCTL4 |EPWM Compare Up Point Control 604 * | | |00 = Do nothing. 605 * | | |01 = EPWM compare up point output Low. 606 * | | |10 = EPWM compare up point output High. 607 * | | |11 = EPWM compare up point output Toggle. 608 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 609 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 610 * |[11:10] |CMPUCTL5 |EPWM Compare Up Point Control 611 * | | |00 = Do nothing. 612 * | | |01 = EPWM compare up point output Low. 613 * | | |10 = EPWM compare up point output High. 614 * | | |11 = EPWM compare up point output Toggle. 615 * | | |EPWM can control output level when EPWM counter up count to CMPDAT. 616 * | | |Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4. 617 * |[17:16] |CMPDCTL0 |EPWM Compare Down Point Control 618 * | | |00 = Do nothing. 619 * | | |01 = EPWM compare down point output Low. 620 * | | |10 = EPWM compare down point output High. 621 * | | |11 = EPWM compare down point output Toggle. 622 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 623 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 624 * |[19:18] |CMPDCTL1 |EPWM Compare Down Point Control 625 * | | |00 = Do nothing. 626 * | | |01 = EPWM compare down point output Low. 627 * | | |10 = EPWM compare down point output High. 628 * | | |11 = EPWM compare down point output Toggle. 629 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 630 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 631 * |[21:20] |CMPDCTL2 |EPWM Compare Down Point Control 632 * | | |00 = Do nothing. 633 * | | |01 = EPWM compare down point output Low. 634 * | | |10 = EPWM compare down point output High. 635 * | | |11 = EPWM compare down point output Toggle. 636 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 637 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 638 * |[23:22] |CMPDCTL3 |EPWM Compare Down Point Control 639 * | | |00 = Do nothing. 640 * | | |01 = EPWM compare down point output Low. 641 * | | |10 = EPWM compare down point output High. 642 * | | |11 = EPWM compare down point output Toggle. 643 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 644 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 645 * |[25:24] |CMPDCTL4 |EPWM Compare Down Point Control 646 * | | |00 = Do nothing. 647 * | | |01 = EPWM compare down point output Low. 648 * | | |10 = EPWM compare down point output High. 649 * | | |11 = EPWM compare down point output Toggle. 650 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 651 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 652 * |[27:26] |CMPDCTL5 |EPWM Compare Down Point Control 653 * | | |00 = Do nothing. 654 * | | |01 = EPWM compare down point output Low. 655 * | | |10 = EPWM compare down point output High. 656 * | | |11 = EPWM compare down point output Toggle. 657 * | | |EPWM can control output level when EPWM counter down count to CMPDAT. 658 * | | |Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4. 659 * @var EPWM_T::MSKEN 660 * Offset: 0xB8 EPWM Mask Enable Register 661 * --------------------------------------------------------------------------------------------------- 662 * |Bits |Field |Descriptions 663 * | :----: | :----: | :---- | 664 * |[0] |MSKEN0 |EPWM Mask Enable Bits 665 * | | |The EPWM output signal will be masked when this bit is enabled. 666 * | | |The corresponding EPWM channel 0 will output MSKDAT0 (EPWM_MSK[5:0]) data. 667 * | | |0 = EPWM output signal is non-masked. 668 * | | |1 = EPWM output signal is masked and output MSKDAT0 data. 669 * |[1] |MSKEN1 |EPWM Mask Enable Bits 670 * | | |The EPWM output signal will be masked when this bit is enabled. 671 * | | |The corresponding EPWM channel 1 will output MSKDAT1 (EPWM_MSK[5:0]) data. 672 * | | |0 = EPWM output signal is non-masked. 673 * | | |1 = EPWM output signal is masked and output MSKDAT1 data. 674 * |[2] |MSKEN2 |EPWM Mask Enable Bits 675 * | | |The EPWM output signal will be masked when this bit is enabled. 676 * | | |The corresponding EPWM channel 2 will output MSKDAT2 (EPWM_MSK[5:0]) data. 677 * | | |0 = EPWM output signal is non-masked. 678 * | | |1 = EPWM output signal is masked and output MSKDAT2 data. 679 * |[3] |MSKEN3 |EPWM Mask Enable Bits 680 * | | |The EPWM output signal will be masked when this bit is enabled. 681 * | | |The corresponding EPWM channel 3 will output MSKDAT3 (EPWM_MSK[5:0]) data. 682 * | | |0 = EPWM output signal is non-masked. 683 * | | |1 = EPWM output signal is masked and output MSKDAT3 data. 684 * |[4] |MSKEN4 |EPWM Mask Enable Bits 685 * | | |The EPWM output signal will be masked when this bit is enabled. 686 * | | |The corresponding EPWM channel 4 will output MSKDAT4 (EPWM_MSK[5:0]) data. 687 * | | |0 = EPWM output signal is non-masked. 688 * | | |1 = EPWM output signal is masked and output MSKDAT4 data. 689 * |[5] |MSKEN5 |EPWM Mask Enable Bits 690 * | | |The EPWM output signal will be masked when this bit is enabled. 691 * | | |The corresponding EPWM channel 5 will output MSKDAT5 (EPWM_MSK[5:0]) data. 692 * | | |0 = EPWM output signal is non-masked. 693 * | | |1 = EPWM output signal is masked and output MSKDAT5 data. 694 * @var EPWM_T::MSK 695 * Offset: 0xBC EPWM Mask Data Register 696 * --------------------------------------------------------------------------------------------------- 697 * |Bits |Field |Descriptions 698 * | :----: | :----: | :---- | 699 * |[0] |MSKDAT0 |EPWM Mask Data Bit 700 * | | |This data bit control the state of EPWM_CH0 output pin, if corresponding mask function is enabled. 701 * | | |0 = Output logic low to EPWM_CH0. 702 * | | |1 = Output logic high to EPWM_CH0. 703 * |[1] |MSKDAT1 |EPWM Mask Data Bit 704 * | | |This data bit control the state of EPWM_CH1 output pin, if corresponding mask function is enabled. 705 * | | |0 = Output logic low to EPWM_CH1. 706 * | | |1 = Output logic high to EPWM_CH1. 707 * |[2] |MSKDAT2 |EPWM Mask Data Bit 708 * | | |This data bit control the state of EPWM_CH2 output pin, if corresponding mask function is enabled. 709 * | | |0 = Output logic low to EPWM_CH2. 710 * | | |1 = Output logic high to EPWM_CH2. 711 * |[3] |MSKDAT3 |EPWM Mask Data Bit 712 * | | |This data bit control the state of EPWM_CH3 output pin, if corresponding mask function is enabled. 713 * | | |0 = Output logic low to EPWM_CH3. 714 * | | |1 = Output logic high to EPWM_CH3. 715 * |[4] |MSKDAT4 |EPWM Mask Data Bit 716 * | | |This data bit control the state of EPWM_CH4 output pin, if corresponding mask function is enabled. 717 * | | |0 = Output logic low to EPWM_CH4. 718 * | | |1 = Output logic high to EPWM_CH4. 719 * |[5] |MSKDAT5 |EPWM Mask Data Bit 720 * | | |This data bit control the state of EPWM_CH5 output pin, if corresponding mask function is enabled. 721 * | | |0 = Output logic low to EPWM_CH5. 722 * | | |1 = Output logic high to EPWM_CH5. 723 * @var EPWM_T::BNF 724 * Offset: 0xC0 EPWM Brake Noise Filter Register 725 * --------------------------------------------------------------------------------------------------- 726 * |Bits |Field |Descriptions 727 * | :----: | :----: | :---- | 728 * |[0] |BRK0NFEN |EPWM Brake 0 Noise Filter Enable Bit 729 * | | |0 = Noise filter of EPWM Brake 0 Disabled. 730 * | | |1 = Noise filter of EPWM Brake 0 Enabled. 731 * |[3:1] |BRK0NFSEL |Brake 0 Edge Detector Filter Clock Selection 732 * | | |000 = Filter clock = HCLK. 733 * | | |001 = Filter clock = HCLK/2. 734 * | | |010 = Filter clock = HCLK/4. 735 * | | |011 = Filter clock = HCLK/8. 736 * | | |100 = Filter clock = HCLK/16. 737 * | | |101 = Filter clock = HCLK/32. 738 * | | |110 = Filter clock = HCLK/64. 739 * | | |111 = Filter clock = HCLK/128. 740 * |[6:4] |BRK0FCNT |Brake 0 Edge Detector Filter Count 741 * | | |The register bits control the Brake0 filter counter to count from 0 to BRK0FCNT. 742 * |[7] |BRK0PINV |Brake 0 Pin Inverse 743 * | | |0 = The state of pin EPWMx_BRAKE0 is passed to the negative edge detector. 744 * | | |1 = The inversed state of pin EPWMx_BRAKE0 is passed to the negative edge detector. 745 * |[8] |BRK1NFEN |EPWM Brake 1 Noise Filter Enable Bit 746 * | | |0 = Noise filter of EPWM Brake 1 Disabled. 747 * | | |1 = Noise filter of EPWM Brake 1 Enabled. 748 * |[11:9] |BRK1NFSEL |Brake 1 Edge Detector Filter Clock Selection 749 * | | |000 = Filter clock = HCLK. 750 * | | |001 = Filter clock = HCLK/2. 751 * | | |010 = Filter clock = HCLK/4. 752 * | | |011 = Filter clock = HCLK/8. 753 * | | |100 = Filter clock = HCLK/16. 754 * | | |101 = Filter clock = HCLK/32. 755 * | | |110 = Filter clock = HCLK/64. 756 * | | |111 = Filter clock = HCLK/128. 757 * |[14:12] |BRK1FCNT |Brake 1 Edge Detector Filter Count 758 * | | |The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT. 759 * |[15] |BRK1PINV |Brake 1 Pin Inverse 760 * | | |0 = The state of pin EPWMx_BRAKE1 is passed to the negative edge detector. 761 * | | |1 = The inversed state of pin EPWMx_BRAKE1 is passed to the negative edge detector. 762 * |[16] |BK0SRC |Brake 0 Pin Source Select 763 * | | |For EPWM0 setting: 764 * | | |0 = Brake 0 pin source come from EPWM0_BRAKE0. 765 * | | |1 = Brake 0 pin source come from EPWM1_BRAKE0. 766 * | | |For EPWM1 setting: 767 * | | |0 = Brake 0 pin source come from EPWM1_BRAKE0. 768 * | | |1 = Brake 0 pin source come from EPWM0_BRAKE0. 769 * |[24] |BK1SRC |Brake 1 Pin Source Select 770 * | | |For EPWM0 setting: 771 * | | |0 = Brake 1 pin source come from EPWM0_BRAKE1. 772 * | | |1 = Brake 1 pin source come from EPWM1_BRAKE1. 773 * | | |For EPWM1 setting: 774 * | | |0 = Brake 1 pin source come from EPWM1_BRAKE1. 775 * | | |1 = Brake 1 pin source come from EPWM0_BRAKE1. 776 * @var EPWM_T::FAILBRK 777 * Offset: 0xC4 EPWM System Fail Brake Control Register 778 * --------------------------------------------------------------------------------------------------- 779 * |Bits |Field |Descriptions 780 * | :----: | :----: | :---- | 781 * |[0] |CSSBRKEN |Clock Security System Detection Trigger EPWM Brake Function 0 Enable Bit 782 * | | |0 = Brake Function triggered by CSS detection Disabled. 783 * | | |1 = Brake Function triggered by CSS detection Enabled. 784 * |[1] |BODBRKEN |Brown-out Detection Trigger EPWM Brake Function 0 Enable Bit 785 * | | |0 = Brake Function triggered by BOD Disabled. 786 * | | |1 = Brake Function triggered by BOD Enabled. 787 * |[2] |RAMBRKEN |SRAM Parity Error Detection Trigger EPWM Brake Function 0 Enable Bit 788 * | | |0 = Brake Function triggered by SRAM parity error detection Disabled. 789 * | | |1 = Brake Function triggered by SRAM parity error detection Enabled. 790 * |[3] |CORBRKEN |Core Lockup Detection Trigger EPWM Brake Function 0 Enable Bit 791 * | | |0 = Brake Function triggered by Core lockup detection Disabled. 792 * | | |1 = Brake Function triggered by Core lockup detection Enabled. 793 * @var EPWM_T::BRKCTL[3] 794 * Offset: 0xC8 EPWM Brake Edge Detect Control Register 0/1,2/3,4/5 795 * --------------------------------------------------------------------------------------------------- 796 * |Bits |Field |Descriptions 797 * | :----: | :----: | :---- | 798 * |[0] |CPO0EBEN |Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect) 799 * | | |0 = ACMP0_O as edge-detect brake source Disabled. 800 * | | |1 = ACMP0_O as edge-detect brake source Enabled. 801 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 802 * |[1] |CPO1EBEN |Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect) 803 * | | |0 = ACMP1_O as edge-detect brake source Disabled. 804 * | | |1 = ACMP1_O as edge-detect brake source Enabled. 805 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 806 * |[4] |BRKP0EEN |Enable EPWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect) 807 * | | |0 = EPWMx_BRAKE0 pin as edge-detect brake source Disabled. 808 * | | |1 = EPWMx_BRAKE0 pin as edge-detect brake source Enabled. 809 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 810 * |[5] |BRKP1EEN |Enable EPWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect) 811 * | | |0 = EPWMx_BRAKE1 pin as edge-detect brake source Disabled. 812 * | | |1 = EPWMx_BRAKE1 pin as edge-detect brake source Enabled. 813 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 814 * |[7] |SYSEBEN |Enable System Fail As Edge-detect Brake Source (Write Protect) 815 * | | |0 = System Fail condition as edge-detect brake source Disabled. 816 * | | |1 = System Fail condition as edge-detect brake source Enabled. 817 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 818 * |[8] |CPO0LBEN |Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect) 819 * | | |0 = ACMP0_O as level-detect brake source Disabled. 820 * | | |1 = ACMP0_O as level-detect brake source Enabled. 821 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 822 * |[9] |CPO1LBEN |Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect) 823 * | | |0 = ACMP1_O as level-detect brake source Disabled. 824 * | | |1 = ACMP1_O as level-detect brake source Enabled. 825 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 826 * |[12] |BRKP0LEN |Enable BKP0 Pin As Level-detect Brake Source (Write Protect) 827 * | | |0 = EPWMx_BRAKE0 pin as level-detect brake source Disabled. 828 * | | |1 = EPWMx_BRAKE0 pin as level-detect brake source Enabled. 829 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 830 * |[13] |BRKP1LEN |Enable BKP1 Pin As Level-detect Brake Source (Write Protect) 831 * | | |0 = EPWMx_BRAKE1 pin as level-detect brake source Disabled. 832 * | | |1 = EPWMx_BRAKE1 pin as level-detect brake source Enabled. 833 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 834 * |[15] |SYSLBEN |Enable System Fail As Level-detect Brake Source (Write Protect) 835 * | | |0 = System Fail condition as level-detect brake source Disabled. 836 * | | |1 = System Fail condition as level-detect brake source Enabled. 837 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 838 * |[17:16] |BRKAEVEN |EPWM Brake Action Select for Even Channel (Write Protect) 839 * | | |00 = EPWMx brake event will not affect even channels output. 840 * | | |01 = EPWM even channel output tri-state when EPWMx brake event happened. 841 * | | |10 = EPWM even channel output low level when EPWMx brake event happened. 842 * | | |11 = EPWM even channel output high level when EPWMx brake event happened. 843 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 844 * |[19:18] |BRKAODD |EPWM Brake Action Select for Odd Channel (Write Protect) 845 * | | |00 = EPWMx brake event will not affect odd channels output. 846 * | | |01 = EPWM odd channel output tri-state when EPWMx brake event happened. 847 * | | |10 = EPWM odd channel output low level when EPWMx brake event happened. 848 * | | |11 = EPWM odd channel output high level when EPWMx brake event happened. 849 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 850 * |[20] |EADCEBEN |Enable EADC Result Monitor (EADCRM) As Edge-detect Brake Source (Write Protect) 851 * | | |0 = EADCRM as edge-detect brake source Disabled. 852 * | | |1 = EADCRM as edge-detect brake source Enabled. 853 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 854 * |[28] |EADCLBEN |Enable EADC Result Monitor (EADCRM) As Level-detect Brake Source (Write Protect) 855 * | | |0 = EADCRM as level-detect brake source Disabled. 856 * | | |1 = EADCRM as level-detect brake source Enabled. 857 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 858 * @var EPWM_T::POLCTL 859 * Offset: 0xD4 EPWM Pin Polar Inverse Register 860 * --------------------------------------------------------------------------------------------------- 861 * |Bits |Field |Descriptions 862 * | :----: | :----: | :---- | 863 * |[0] |PINV0 |EPWM_CH0 PIN Polar Inverse Control 864 * | | |The register controls polarity state of EPWM_CH0 output. 865 * | | |0 = EPWM_CH0 output polar inverse Disabled. 866 * | | |1 = EPWM_CH0 output polar inverse Enabled. 867 * |[1] |PINV1 |EPWM_CH1 PIN Polar Inverse Control 868 * | | |The register controls polarity state of EPWM_CH1 output. 869 * | | |0 = EPWM_CH1 output polar inverse Disabled. 870 * | | |1 = EPWM_CH1 output polar inverse Enabled. 871 * |[2] |PINV2 |EPWM_CH2 PIN Polar Inverse Control 872 * | | |The register controls polarity state of EPWM_CH2 output. 873 * | | |0 = EPWM_CH2 output polar inverse Disabled. 874 * | | |1 = EPWM_CH2 output polar inverse Enabled. 875 * |[3] |PINV3 |EPWM_CH3 PIN Polar Inverse Control 876 * | | |The register controls polarity state of EPWM_CH3 output. 877 * | | |0 = EPWM_CH3 output polar inverse Disabled. 878 * | | |1 = EPWM_CH3 output polar inverse Enabled. 879 * |[4] |PINV4 |EPWM_CH4 PIN Polar Inverse Control 880 * | | |The register controls polarity state of EPWM_CH4 output. 881 * | | |0 = EPWM_CH4 output polar inverse Disabled. 882 * | | |1 = EPWM_CH4 output polar inverse Enabled. 883 * |[5] |PINV5 |EPWM_CH5 PIN Polar Inverse Control 884 * | | |The register controls polarity state of EPWM_CH5 output. 885 * | | |0 = EPWM_CH5 output polar inverse Disabled. 886 * | | |1 = EPWM_CH5 output polar inverse Enabled. 887 * @var EPWM_T::POEN 888 * Offset: 0xD8 EPWM Output Enable Register 889 * --------------------------------------------------------------------------------------------------- 890 * |Bits |Field |Descriptions 891 * | :----: | :----: | :---- | 892 * |[0] |POEN0 |EPWM_CH0 Pin Output Enable Bits 893 * | | |0 = EPWM_CH0 pin at tri-state. 894 * | | |1 = EPWM_CH0 pin in output mode. 895 * |[1] |POEN1 |EPWM_CH1 Pin Output Enable Bits 896 * | | |0 = EPWM_CH1 pin at tri-state. 897 * | | |1 = EPWM_CH1 pin in output mode. 898 * |[2] |POEN2 |EPWM_CH2 Pin Output Enable Bits 899 * | | |0 = EPWM_CH2 pin at tri-state. 900 * | | |1 = EPWM_CH2 pin in output mode. 901 * |[3] |POEN3 |EPWM_CH3 Pin Output Enable Bits 902 * | | |0 = EPWM_CH3 pin at tri-state. 903 * | | |1 = EPWM_CH3 pin in output mode. 904 * |[4] |POEN4 |EPWM_CH4 Pin Output Enable Bits 905 * | | |0 = EPWM_CH4 pin at tri-state. 906 * | | |1 = EPWM_CH4 pin in output mode. 907 * |[5] |POEN5 |EPWM_CH5 Pin Output Enable Bits 908 * | | |0 = EPWM_CH5 pin at tri-state. 909 * | | |1 = EPWM_CH5 pin in output mode. 910 * @var EPWM_T::SWBRK 911 * Offset: 0xDC EPWM Software Brake Control Register 912 * --------------------------------------------------------------------------------------------------- 913 * |Bits |Field |Descriptions 914 * | :----: | :----: | :---- | 915 * |[0] |BRKETRG0 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 916 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF0 to 1 in EPWM_INTSTS1 register. 917 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 918 * |[1] |BRKETRG2 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 919 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF2 to 1 in EPWM_INTSTS1 register. 920 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 921 * |[2] |BRKETRG4 |EPWM Edge Brake Software Trigger (Write Only) (Write Protect) 922 * | | |Write 1 to this bit will trigger edge brake, and set BRKEIF4 to 1 in EPWM_INTSTS1 register. 923 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 924 * |[8] |BRKLTRG0 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 925 * | | |Write 1 to this bit will trigger level brake, and set BRKLIF0 to 1 in EPWM_INTSTS1 register. 926 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 927 * |[9] |BRKLTRG2 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 928 * | | |Write 1 to this bit will trigger level brake, and set BRKLIF2 to 1 in EPWM_INTSTS1 register. 929 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 930 * |[10] |BRKLTRG4 |EPWM Level Brake Software Trigger (Write Only) (Write Protect) 931 * | | |Write 1 to this bit will trigger level brake, and set BRKLIF4 to 1 in EPWM_INTSTS1 register. 932 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 933 * @var EPWM_T::INTEN0 934 * Offset: 0xE0 EPWM Interrupt Enable Register 0 935 * --------------------------------------------------------------------------------------------------- 936 * |Bits |Field |Descriptions 937 * | :----: | :----: | :---- | 938 * |[0] |ZIEN0 |EPWM Zero Point Interrupt Enable Bits 939 * | | |0 = Zero point interrupt Disabled. 940 * | | |1 = Zero point interrupt Enabled. 941 * | | |Note: Odd channels will read always 0 at complementary mode. 942 * |[1] |ZIEN1 |EPWM Zero Point Interrupt Enable Bits 943 * | | |0 = Zero point interrupt Disabled. 944 * | | |1 = Zero point interrupt Enabled. 945 * | | |Note: Odd channels will read always 0 at complementary mode. 946 * |[2] |ZIEN2 |EPWM Zero Point Interrupt Enable Bits 947 * | | |0 = Zero point interrupt Disabled. 948 * | | |1 = Zero point interrupt Enabled. 949 * | | |Note: Odd channels will read always 0 at complementary mode. 950 * |[3] |ZIEN3 |EPWM Zero Point Interrupt Enable Bits 951 * | | |0 = Zero point interrupt Disabled. 952 * | | |1 = Zero point interrupt Enabled. 953 * | | |Note: Odd channels will read always 0 at complementary mode. 954 * |[4] |ZIEN4 |EPWM Zero Point Interrupt Enable Bits 955 * | | |0 = Zero point interrupt Disabled. 956 * | | |1 = Zero point interrupt Enabled. 957 * | | |Note: Odd channels will read always 0 at complementary mode. 958 * |[5] |ZIEN5 |EPWM Zero Point Interrupt Enable Bits 959 * | | |0 = Zero point interrupt Disabled. 960 * | | |1 = Zero point interrupt Enabled. 961 * | | |Note: Odd channels will read always 0 at complementary mode. 962 * |[8] |PIEN0 |EPWM Period Point Interrupt Enable Bits 963 * | | |0 = Period point interrupt Disabled. 964 * | | |1 = Period point interrupt Enabled. 965 * | | |Note1: When up-down counter type period point means center point. 966 * | | |Note2: Odd channels will read always 0 at complementary mode. 967 * |[9] |PIEN1 |EPWM Period Point Interrupt Enable Bits 968 * | | |0 = Period point interrupt Disabled. 969 * | | |1 = Period point interrupt Enabled. 970 * | | |Note1: When up-down counter type period point means center point. 971 * | | |Note2: Odd channels will read always 0 at complementary mode. 972 * |[10] |PIEN2 |EPWM Period Point Interrupt Enable Bits 973 * | | |0 = Period point interrupt Disabled. 974 * | | |1 = Period point interrupt Enabled. 975 * | | |Note1: When up-down counter type period point means center point. 976 * | | |Note2: Odd channels will read always 0 at complementary mode. 977 * |[11] |PIEN3 |EPWM Period Point Interrupt Enable Bits 978 * | | |0 = Period point interrupt Disabled. 979 * | | |1 = Period point interrupt Enabled. 980 * | | |Note1: When up-down counter type period point means center point. 981 * | | |Note2: Odd channels will read always 0 at complementary mode. 982 * |[12] |PIEN4 |EPWM Period Point Interrupt Enable Bits 983 * | | |0 = Period point interrupt Disabled. 984 * | | |1 = Period point interrupt Enabled. 985 * | | |Note1: When up-down counter type period point means center point. 986 * | | |Note2: Odd channels will read always 0 at complementary mode. 987 * |[13] |PIEN5 |EPWM Period Point Interrupt Enable Bits 988 * | | |0 = Period point interrupt Disabled. 989 * | | |1 = Period point interrupt Enabled. 990 * | | |Note1: When up-down counter type period point means center point. 991 * | | |Note2: Odd channels will read always 0 at complementary mode. 992 * |[16] |CMPUIEN0 |EPWM Compare Up Count Interrupt Enable Bits 993 * | | |0 = Compare up count interrupt Disabled. 994 * | | |1 = Compare up count interrupt Enabled. 995 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 996 * |[17] |CMPUIEN1 |EPWM Compare Up Count Interrupt Enable Bits 997 * | | |0 = Compare up count interrupt Disabled. 998 * | | |1 = Compare up count interrupt Enabled. 999 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1000 * |[18] |CMPUIEN2 |EPWM Compare Up Count Interrupt Enable Bits 1001 * | | |0 = Compare up count interrupt Disabled. 1002 * | | |1 = Compare up count interrupt Enabled. 1003 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1004 * |[19] |CMPUIEN3 |EPWM Compare Up Count Interrupt Enable Bits 1005 * | | |0 = Compare up count interrupt Disabled. 1006 * | | |1 = Compare up count interrupt Enabled. 1007 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1008 * |[20] |CMPUIEN4 |EPWM Compare Up Count Interrupt Enable Bits 1009 * | | |0 = Compare up count interrupt Disabled. 1010 * | | |1 = Compare up count interrupt Enabled. 1011 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1012 * |[21] |CMPUIEN5 |EPWM Compare Up Count Interrupt Enable Bits 1013 * | | |0 = Compare up count interrupt Disabled. 1014 * | | |1 = Compare up count interrupt Enabled. 1015 * | | |Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4. 1016 * |[24] |CMPDIEN0 |EPWM Compare Down Count Interrupt Enable Bits 1017 * | | |0 = Compare down count interrupt Disabled. 1018 * | | |1 = Compare down count interrupt Enabled. 1019 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1020 * |[25] |CMPDIEN1 |EPWM Compare Down Count Interrupt Enable Bits 1021 * | | |0 = Compare down count interrupt Disabled. 1022 * | | |1 = Compare down count interrupt Enabled. 1023 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1024 * |[26] |CMPDIEN2 |EPWM Compare Down Count Interrupt Enable Bits 1025 * | | |0 = Compare down count interrupt Disabled. 1026 * | | |1 = Compare down count interrupt Enabled. 1027 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1028 * |[27] |CMPDIEN3 |EPWM Compare Down Count Interrupt Enable Bits 1029 * | | |0 = Compare down count interrupt Disabled. 1030 * | | |1 = Compare down count interrupt Enabled. 1031 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1032 * |[28] |CMPDIEN4 |EPWM Compare Down Count Interrupt Enable Bits 1033 * | | |0 = Compare down count interrupt Disabled. 1034 * | | |1 = Compare down count interrupt Enabled. 1035 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1036 * |[29] |CMPDIEN5 |EPWM Compare Down Count Interrupt Enable Bits 1037 * | | |0 = Compare down count interrupt Disabled. 1038 * | | |1 = Compare down count interrupt Enabled. 1039 * | | |Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4. 1040 * @var EPWM_T::INTEN1 1041 * Offset: 0xE4 EPWM Interrupt Enable Register 1 1042 * --------------------------------------------------------------------------------------------------- 1043 * |Bits |Field |Descriptions 1044 * | :----: | :----: | :---- | 1045 * |[0] |BRKEIEN0_1|EPWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1046 * | | |0 = Edge-detect Brake interrupt for channel0/1 Disabled. 1047 * | | |1 = Edge-detect Brake interrupt for channel0/1 Enabled. 1048 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1049 * |[1] |BRKEIEN2_3|EPWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1050 * | | |0 = Edge-detect Brake interrupt for channel2/3 Disabled. 1051 * | | |1 = Edge-detect Brake interrupt for channel2/3 Enabled. 1052 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1053 * |[2] |BRKEIEN4_5|EPWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1054 * | | |0 = Edge-detect Brake interrupt for channel4/5 Disabled. 1055 * | | |1 = Edge-detect Brake interrupt for channel4/5 Enabled. 1056 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1057 * |[8] |BRKLIEN0_1|EPWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect) 1058 * | | |0 = Level-detect Brake interrupt for channel0/1 Disabled. 1059 * | | |1 = Level-detect Brake interrupt for channel0/1 Enabled. 1060 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1061 * |[9] |BRKLIEN2_3|EPWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect) 1062 * | | |0 = Level-detect Brake interrupt for channel2/3 Disabled. 1063 * | | |1 = Level-detect Brake interrupt for channel2/3 Enabled. 1064 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1065 * |[10] |BRKLIEN4_5|EPWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect) 1066 * | | |0 = Level-detect Brake interrupt for channel4/5 Disabled. 1067 * | | |1 = Level-detect Brake interrupt for channel4/5 Enabled. 1068 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1069 * @var EPWM_T::INTSTS0 1070 * Offset: 0xE8 EPWM Interrupt Flag Register 0 1071 * --------------------------------------------------------------------------------------------------- 1072 * |Bits |Field |Descriptions 1073 * | :----: | :----: | :---- | 1074 * |[0] |ZIF0 |EPWM Zero Point Interrupt Flag 1075 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1076 * |[1] |ZIF1 |EPWM Zero Point Interrupt Flag 1077 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1078 * |[2] |ZIF2 |EPWM Zero Point Interrupt Flag 1079 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1080 * |[3] |ZIF3 |EPWM Zero Point Interrupt Flag 1081 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1082 * |[4] |ZIF4 |EPWM Zero Point Interrupt Flag 1083 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1084 * |[5] |ZIF5 |EPWM Zero Point Interrupt Flag 1085 * | | |This bit is set by hardware when EPWM counter reaches zero, software can write 1 to clear this bit to zero. 1086 * |[8] |PIF0 |EPWM Period Point Interrupt Flag 1087 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD0, software can write 1 to clear this bit to zero 1088 * |[9] |PIF1 |EPWM Period Point Interrupt Flag 1089 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD1, software can write 1 to clear this bit to zero 1090 * |[10] |PIF2 |EPWM Period Point Interrupt Flag 1091 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD2, software can write 1 to clear this bit to zero 1092 * |[11] |PIF3 |EPWM Period Point Interrupt Flag 1093 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD4, software can write 1 to clear this bit to zero 1094 * |[12] |PIF4 |EPWM Period Point Interrupt Flag 1095 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIOD5, software can write 1 to clear this bit to zero 1096 * |[13] |PIF5 |EPWM Period Point Interrupt Flag 1097 * | | |This bit is set by hardware when EPWM counter reaches EPWM_PERIODn, software can write 1 to clear this bit to zero. 1098 * |[16] |CMPUIF0 |EPWM Compare Up Count Interrupt Flag 1099 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. 1100 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1101 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1102 * |[17] |CMPUIF1 |EPWM Compare Up Count Interrupt Flag 1103 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. 1104 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1105 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1106 * |[18] |CMPUIF2 |EPWM Compare Up Count Interrupt Flag 1107 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. 1108 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1109 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1110 * |[19] |CMPUIF3 |EPWM Compare Up Count Interrupt Flag 1111 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. 1112 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1113 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1114 * |[20] |CMPUIF4 |EPWM Compare Up Count Interrupt Flag 1115 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. 1116 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1117 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1118 * |[21] |CMPUIF5 |EPWM Compare Up Count Interrupt Flag 1119 * | | |Flag is set by hardware when EPWM counter up count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. 1120 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 1121 * | | |Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4. 1122 * |[24] |CMPDIF0 |EPWM Compare Down Count Interrupt Flag 1123 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT0, software can clear this bit by writing 1 to it. 1124 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1125 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1126 * |[25] |CMPDIF1 |EPWM Compare Down Count Interrupt Flag 1127 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT1, software can clear this bit by writing 1 to it. 1128 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1129 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1130 * |[26] |CMPDIF2 |EPWM Compare Down Count Interrupt Flag 1131 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT2, software can clear this bit by writing 1 to it. 1132 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1133 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1134 * |[27] |CMPDIF3 |EPWM Compare Down Count Interrupt Flag 1135 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT3, software can clear this bit by writing 1 to it. 1136 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1137 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1138 * |[28] |CMPDIF4 |EPWM Compare Down Count Interrupt Flag 1139 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT4, software can clear this bit by writing 1 to it. 1140 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1141 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1142 * |[29] |CMPDIF5 |EPWM Compare Down Count Interrupt Flag 1143 * | | |Flag is set by hardware when EPWM counter down count and reaches EPWM_CMPDAT5, software can clear this bit by writing 1 to it. 1144 * | | |Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 1145 * | | |Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4. 1146 * @var EPWM_T::INTSTS1 1147 * Offset: 0xEC EPWM Interrupt Flag Register 1 1148 * --------------------------------------------------------------------------------------------------- 1149 * |Bits |Field |Descriptions 1150 * | :----: | :----: | :---- | 1151 * |[0] |BRKEIF0 |EPWM Channel0 Edge-detect Brake Interrupt Flag (Write Protect) 1152 * | | |0 = EPWM channel0 edge-detect brake event do not happened. 1153 * | | |1 = When EPWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1154 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1155 * |[1] |BRKEIF1 |EPWM Channel1 Edge-detect Brake Interrupt Flag (Write Protect) 1156 * | | |0 = EPWM channel1 edge-detect brake event do not happened. 1157 * | | |1 = When EPWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1158 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1159 * |[2] |BRKEIF2 |EPWM Channel2 Edge-detect Brake Interrupt Flag (Write Protect) 1160 * | | |0 = EPWM channel2 edge-detect brake event do not happened. 1161 * | | |1 = When EPWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1162 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1163 * |[3] |BRKEIF3 |EPWM Channel3 Edge-detect Brake Interrupt Flag (Write Protect) 1164 * | | |0 = EPWM channel3 edge-detect brake event do not happened. 1165 * | | |1 = When EPWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1166 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1167 * |[4] |BRKEIF4 |EPWM Channel4 Edge-detect Brake Interrupt Flag (Write Protect) 1168 * | | |0 = EPWM channel4 edge-detect brake event do not happened. 1169 * | | |1 = When EPWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1170 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1171 * |[5] |BRKEIF5 |EPWM Channel5 Edge-detect Brake Interrupt Flag (Write Protect) 1172 * | | |0 = EPWM channel5 edge-detect brake event do not happened. 1173 * | | |1 = When EPWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear. 1174 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1175 * |[8] |BRKLIF0 |EPWM Channel0 Level-detect Brake Interrupt Flag (Write Protect) 1176 * | | |0 = EPWM channel0 level-detect brake event do not happened. 1177 * | | |1 = When EPWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1178 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1179 * |[9] |BRKLIF1 |EPWM Channel1 Level-detect Brake Interrupt Flag (Write Protect) 1180 * | | |0 = EPWM channel1 level-detect brake event do not happened. 1181 * | | |1 = When EPWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1182 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1183 * |[10] |BRKLIF2 |EPWM Channel2 Level-detect Brake Interrupt Flag (Write Protect) 1184 * | | |0 = EPWM channel2 level-detect brake event do not happened. 1185 * | | |1 = When EPWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1186 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1187 * |[11] |BRKLIF3 |EPWM Channel3 Level-detect Brake Interrupt Flag (Write Protect) 1188 * | | |0 = EPWM channel3 level-detect brake event do not happened. 1189 * | | |1 = When EPWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1190 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1191 * |[12] |BRKLIF4 |EPWM Channel4 Level-detect Brake Interrupt Flag (Write Protect) 1192 * | | |0 = EPWM channel4 level-detect brake event do not happened. 1193 * | | |1 = When EPWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1194 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1195 * |[13] |BRKLIF5 |EPWM Channel5 Level-detect Brake Interrupt Flag (Write Protect) 1196 * | | |0 = EPWM channel5 level-detect brake event do not happened. 1197 * | | |1 = When EPWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear. 1198 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 1199 * |[16] |BRKESTS0 |EPWM Channel0 Edge-detect Brake Status (Read Only) 1200 * | | |0 = EPWM channel0 edge-detect brake state is released. 1201 * | | |1 = When EPWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state, writing 1 to clear. 1202 * |[17] |BRKESTS1 |EPWM Channel1 Edge-detect Brake Status (Read Only) 1203 * | | |0 = EPWM channel1 edge-detect brake state is released. 1204 * | | |1 = When EPWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state, writing 1 to clear. 1205 * |[18] |BRKESTS2 |EPWM Channel2 Edge-detect Brake Status (Read Only) 1206 * | | |0 = EPWM channel2 edge-detect brake state is released. 1207 * | | |1 = When EPWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state, writing 1 to clear. 1208 * |[19] |BRKESTS3 |EPWM Channel3 Edge-detect Brake Status (Read Only) 1209 * | | |0 = EPWM channel3 edge-detect brake state is released. 1210 * | | |1 = When EPWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state, writing 1 to clear. 1211 * |[20] |BRKESTS4 |EPWM Channel4 Edge-detect Brake Status (Read Only) 1212 * | | |0 = EPWM channel4 edge-detect brake state is released. 1213 * | | |1 = When EPWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state, writing 1 to clear. 1214 * |[21] |BRKESTS5 |EPWM Channel5 Edge-detect Brake Status (Read Only) 1215 * | | |0 = EPWM channel5 edge-detect brake state is released. 1216 * | | |1 = When EPWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state, writing 1 to clear. 1217 * |[24] |BRKLSTS0 |EPWM Channel0 Level-detect Brake Status (Read Only) 1218 * | | |0 = EPWM channel0 level-detect brake state is released. 1219 * | | |1 = When EPWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel0 at brake state. 1220 * | | |Note: This bit is read only and auto cleared by hardware 1221 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1222 * | | |The EPWM waveform will start output from next full EPWM period. 1223 * |[25] |BRKLSTS1 |EPWM Channel1 Level-detect Brake Status (Read Only) 1224 * | | |0 = EPWM channel1 level-detect brake state is released. 1225 * | | |1 = When EPWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel1 at brake state. 1226 * | | |Note: This bit is read only and auto cleared by hardware 1227 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1228 * | | |The EPWM waveform will start output from next full EPWM period. 1229 * |[26] |BRKLSTS2 |EPWM Channel2 Level-detect Brake Status (Read Only) 1230 * | | |0 = EPWM channel2 level-detect brake state is released. 1231 * | | |1 = When EPWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel2 at brake state. 1232 * | | |Note: This bit is read only and auto cleared by hardware 1233 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1234 * | | |The EPWM waveform will start output from next full EPWM period. 1235 * |[27] |BRKLSTS3 |EPWM Channel3 Level-detect Brake Status (Read Only) 1236 * | | |0 = EPWM channel3 level-detect brake state is released. 1237 * | | |1 = When EPWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel3 at brake state. 1238 * | | |Note: This bit is read only and auto cleared by hardware 1239 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1240 * | | |The EPWM waveform will start output from next full EPWM period. 1241 * |[28] |BRKLSTS4 |EPWM Channel4 Level-detect Brake Status (Read Only) 1242 * | | |0 = EPWM channel4 level-detect brake state is released. 1243 * | | |1 = When EPWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel4 at brake state. 1244 * | | |Note: This bit is read only and auto cleared by hardware 1245 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1246 * | | |The EPWM waveform will start output from next full EPWM period. 1247 * |[29] |BRKLSTS5 |EPWM Channel5 Level-detect Brake Status (Read Only) 1248 * | | |0 = EPWM channel5 level-detect brake state is released. 1249 * | | |1 = When EPWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the EPWM channel5 at brake state. 1250 * | | |Note: This bit is read only and auto cleared by hardware 1251 * | | |When enabled brake source return to high level, EPWM will release brake state until current EPWM period finished 1252 * | | |The EPWM waveform will start output from next full EPWM period. 1253 * @var EPWM_T::DACTRGEN 1254 * Offset: 0xF4 EPWM Trigger DAC Enable Register 1255 * --------------------------------------------------------------------------------------------------- 1256 * |Bits |Field |Descriptions 1257 * | :----: | :----: | :---- | 1258 * |[0] |ZTE0 |EPWM Zero Point Trigger DAC Enable Bits 1259 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1260 * | | |0 = EPWM period point trigger DAC function Disabled. 1261 * | | |1 = EPWM period point trigger DAC function Enabled. 1262 * |[1] |ZTE1 |EPWM Zero Point Trigger DAC Enable Bits 1263 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1264 * | | |0 = EPWM period point trigger DAC function Disabled. 1265 * | | |1 = EPWM period point trigger DAC function Enabled. 1266 * |[2] |ZTE2 |EPWM Zero Point Trigger DAC Enable Bits 1267 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1268 * | | |0 = EPWM period point trigger DAC function Disabled. 1269 * | | |1 = EPWM period point trigger DAC function Enabled. 1270 * |[3] |ZTE3 |EPWM Zero Point Trigger DAC Enable Bits 1271 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1272 * | | |0 = EPWM period point trigger DAC function Disabled. 1273 * | | |1 = EPWM period point trigger DAC function Enabled. 1274 * |[4] |ZTE4 |EPWM Zero Point Trigger DAC Enable Bits 1275 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1276 * | | |0 = EPWM period point trigger DAC function Disabled. 1277 * | | |1 = EPWM period point trigger DAC function Enabled. 1278 * |[5] |ZTE5 |EPWM Zero Point Trigger DAC Enable Bits 1279 * | | |EPWM can trigger EADC/DAC/DMA to start action when EPWM counter down count to zero if this bit is set to1. 1280 * | | |0 = EPWM period point trigger DAC function Disabled. 1281 * | | |1 = EPWM period point trigger DAC function Enabled. 1282 * |[8] |PTE0 |EPWM Period Point Trigger DAC Enable Bits 1283 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1284 * | | |0 = EPWM period point trigger DAC function Disabled. 1285 * | | |1 = EPWM period point trigger DAC function Enabled. 1286 * |[9] |PTE1 |EPWM Period Point Trigger DAC Enable Bits 1287 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1288 * | | |0 = EPWM period point trigger DAC function Disabled. 1289 * | | |1 = EPWM period point trigger DAC function Enabled. 1290 * |[10] |PTE2 |EPWM Period Point Trigger DAC Enable Bits 1291 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1292 * | | |0 = EPWM period point trigger DAC function Disabled. 1293 * | | |1 = EPWM period point trigger DAC function Enabled. 1294 * |[11] |PTE3 |EPWM Period Point Trigger DAC Enable Bits 1295 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1296 * | | |0 = EPWM period point trigger DAC function Disabled. 1297 * | | |1 = EPWM period point trigger DAC function Enabled. 1298 * |[12] |PTE4 |EPWM Period Point Trigger DAC Enable Bits 1299 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1300 * | | |0 = EPWM period point trigger DAC function Disabled. 1301 * | | |1 = EPWM period point trigger DAC function Enabled. 1302 * |[13] |PTE5 |EPWM Period Point Trigger DAC Enable Bits 1303 * | | |EPWM can trigger DAC to start action when EPWM counter up count to (PERIODn+1) if this bit is set to1. 1304 * | | |0 = EPWM period point trigger DAC function Disabled. 1305 * | | |1 = EPWM period point trigger DAC function Enabled. 1306 * |[16] |CUTRGE0 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1307 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1308 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1309 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1310 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1311 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1312 * |[17] |CUTRGE1 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1313 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1314 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1315 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1316 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1317 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1318 * |[18] |CUTRGE2 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1319 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1320 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1321 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1322 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1323 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1324 * |[19] |CUTRGE3 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1325 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1326 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1327 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1328 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1329 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1330 * |[20] |CUTRGE4 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1331 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1332 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1333 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1334 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1335 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1336 * |[21] |CUTRGE5 |EPWM Compare Up Count Point Trigger DAC Enable Bits 1337 * | | |EPWM can trigger DAC to start action when EPWM counter up count to CMPDAT if this bit is set to1. 1338 * | | |0 = EPWM Compare Up point trigger DAC function Disabled. 1339 * | | |1 = EPWM Compare Up point trigger DAC function Enabled. 1340 * | | |Note1: This bit should keep at 0 when EPWM counter operating in down counter type. 1341 * | | |Note2: In complementary mode, CUTRGE1, 3, 5 use as another CUTRGE for channel 0, 2, 4. 1342 * |[24] |CDTRGE0 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1343 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1344 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1345 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1346 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1347 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1348 * |[25] |CDTRGE1 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1349 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1350 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1351 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1352 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1353 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1354 * |[26] |CDTRGE2 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1355 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1356 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1357 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1358 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1359 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1360 * |[27] |CDTRGE3 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1361 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1362 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1363 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1364 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1365 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1366 * |[28] |CDTRGE4 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1367 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1368 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1369 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1370 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1371 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1372 * |[29] |CDTRGE5 |EPWM Compare Down Count Point Trigger DAC Enable Bits 1373 * | | |EPWM can trigger DAC to start action when EPWM counter down count to CMPDAT if this bit is set to1. 1374 * | | |0 = EPWM Compare Down count point trigger DAC function Disabled. 1375 * | | |1 = EPWM Compare Down count point trigger DAC function Enabled. 1376 * | | |Note1: This bit should keep at 0 when EPWM counter operating in up counter type. 1377 * | | |Note2: In complementary mode, CDTRGE1, 3, 5 use as another CDTRGE for channel 0, 2, 4. 1378 * @var EPWM_T::EADCTS0 1379 * Offset: 0xF8 EPWM Trigger EADC Source Select Register 0 1380 * --------------------------------------------------------------------------------------------------- 1381 * |Bits |Field |Descriptions 1382 * | :----: | :----: | :---- | 1383 * |[3:0] |TRGSEL0 |EPWM_CH0 Trigger EADC Source Select 1384 * | | |0000 = EPWM_CH0 zero point. 1385 * | | |0001 = EPWM_CH0 period point. 1386 * | | |0010 = EPWM_CH0 zero or period point. 1387 * | | |0011 = EPWM_CH0 up-count CMPDAT point. 1388 * | | |0100 = EPWM_CH0 down-count CMPDAT point. 1389 * | | |0101 = EPWM_CH1 zero point. 1390 * | | |0110 = EPWM_CH1 period point. 1391 * | | |0111 = EPWM_CH1 zero or period point. 1392 * | | |1000 = EPWM_CH1 up-count CMPDAT point. 1393 * | | |1001 = EPWM_CH1 down-count CMPDAT point. 1394 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1395 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1396 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1397 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1398 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1399 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1400 * |[7] |TRGEN0 |EPWM_CH0 Trigger EADC enable bit 1401 * |[11:8] |TRGSEL1 |EPWM_CH1 Trigger EADC Source Select 1402 * | | |0000 = EPWM_CH0 zero point. 1403 * | | |0001 = EPWM_CH0 period point. 1404 * | | |0010 = EPWM_CH0 zero or period point. 1405 * | | |0011 = EPWM_CH0 up-count CMPDAT point. 1406 * | | |0100 = EPWM_CH0 down-count CMPDAT point. 1407 * | | |0101 = EPWM_CH1 zero point. 1408 * | | |0110 = EPWM_CH1 period point. 1409 * | | |0111 = EPWM_CH1 zero or period point. 1410 * | | |1000 = EPWM_CH1 up-count CMPDAT point. 1411 * | | |1001 = EPWM_CH1 down-count CMPDAT point. 1412 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1413 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1414 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1415 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1416 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1417 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1418 * |[15] |TRGEN1 |EPWM_CH1 Trigger EADC enable bit 1419 * |[19:16] |TRGSEL2 |EPWM_CH2 Trigger EADC Source Select 1420 * | | |0000 = EPWM_CH2 zero point. 1421 * | | |0001 = EPWM_CH2 period point. 1422 * | | |0010 = EPWM_CH2 zero or period point. 1423 * | | |0011 = EPWM_CH2 up-count CMPDAT point. 1424 * | | |0100 = EPWM_CH2 down-count CMPDAT point. 1425 * | | |0101 = EPWM_CH3 zero point. 1426 * | | |0110 = EPWM_CH3 period point. 1427 * | | |0111 = EPWM_CH3 zero or period point. 1428 * | | |1000 = EPWM_CH3 up-count CMPDAT point. 1429 * | | |1001 = EPWM_CH3 down-count CMPDAT point. 1430 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1431 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1432 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1433 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1434 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1435 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1436 * |[23] |TRGEN2 |EPWM_CH2 Trigger EADC enable bit 1437 * |[27:24] |TRGSEL3 |EPWM_CH3 Trigger EADC Source Select 1438 * | | |0000 = EPWM_CH2 zero point. 1439 * | | |0001 = EPWM_CH2 period point. 1440 * | | |0010 = EPWM_CH2 zero or period point. 1441 * | | |0011 = EPWM_CH2 up-count CMPDAT point. 1442 * | | |0100 = EPWM_CH2 down-count CMPDAT point. 1443 * | | |0101 = EPWM_CH3 zero point. 1444 * | | |0110 = EPWM_CH3 period point. 1445 * | | |0111 = EPWM_CH3 zero or period point. 1446 * | | |1000 = EPWM_CH3 up-count CMPDAT point. 1447 * | | |1001 = EPWM_CH3 down-count CMPDAT point. 1448 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1449 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1450 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1451 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1452 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1453 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1454 * |[31] |TRGEN3 |EPWM_CH3 Trigger EADC enable bit 1455 * @var EPWM_T::EADCTS1 1456 * Offset: 0xFC EPWM Trigger EADC Source Select Register 1 1457 * --------------------------------------------------------------------------------------------------- 1458 * |Bits |Field |Descriptions 1459 * | :----: | :----: | :---- | 1460 * |[3:0] |TRGSEL4 |EPWM_CH4 Trigger EADC Source Select 1461 * | | |0000 = EPWM_CH4 zero point. 1462 * | | |0001 = EPWM_CH4 period point. 1463 * | | |0010 = EPWM_CH4 zero or period point. 1464 * | | |0011 = EPWM_CH4 up-count CMPDAT point. 1465 * | | |0100 = EPWM_CH4 down-count CMPDAT point. 1466 * | | |0101 = EPWM_CH5 zero point. 1467 * | | |0110 = EPWM_CH5 period point. 1468 * | | |0111 = EPWM_CH5 zero or period point. 1469 * | | |1000 = EPWM_CH5 up-count CMPDAT point. 1470 * | | |1001 = EPWM_CH5 down-count CMPDAT point. 1471 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1472 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1473 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1474 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1475 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1476 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1477 * |[7] |TRGEN4 |EPWM_CH4 Trigger EADC enable bit 1478 * |[11:8] |TRGSEL5 |EPWM_CH5 Trigger EADC Source Select 1479 * | | |0000 = EPWM_CH4 zero point. 1480 * | | |0001 = EPWM_CH4 period point. 1481 * | | |0010 = EPWM_CH4 zero or period point. 1482 * | | |0011 = EPWM_CH4 up-count CMPDAT point. 1483 * | | |0100 = EPWM_CH4 down-count CMPDAT point. 1484 * | | |0101 = EPWM_CH5 zero point. 1485 * | | |0110 = EPWM_CH5 period point. 1486 * | | |0111 = EPWM_CH5 zero or period point. 1487 * | | |1000 = EPWM_CH5 up-count CMPDAT point. 1488 * | | |1001 = EPWM_CH5 down-count CMPDAT point. 1489 * | | |1010 = EPWM_CH0 up-count free CMPDAT point. 1490 * | | |1011 = EPWM_CH0 down-count free CMPDAT point. 1491 * | | |1100 = EPWM_CH2 up-count free CMPDAT point. 1492 * | | |1101 = EPWM_CH2 down-count free CMPDAT point. 1493 * | | |1110 = EPWM_CH4 up-count free CMPDAT point. 1494 * | | |1111 = EPWM_CH4 down-count free CMPDAT point. 1495 * |[15] |TRGEN5 |EPWM_CH5 Trigger EADC enable bit 1496 * @var EPWM_T::FTCMPDAT[3] 1497 * Offset: 0x100 EPWM Free Trigger Compare Register 0/1,2/3,4/5 1498 * --------------------------------------------------------------------------------------------------- 1499 * |Bits |Field |Descriptions 1500 * | :----: | :----: | :---- | 1501 * |[15:0] |FTCMP |EPWM Free Trigger Compare Register 1502 * | | |FTCMP use to compare with even CNTR to trigger EADC 1503 * | | |FTCMPDAT0, 2, 4 corresponding complementary pairs EPWM_CH0 and EPWM_CH1, EPWM_CH2 and EPWM_CH3, EPWM_CH4 and EPWM_CH5. 1504 * @var EPWM_T::SSCTL 1505 * Offset: 0x110 EPWM Synchronous Start Control Register 1506 * --------------------------------------------------------------------------------------------------- 1507 * |Bits |Field |Descriptions 1508 * | :----: | :----: | :---- | 1509 * |[0] |SSEN0 |EPWM Synchronous Start Function Enable Bits 1510 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1511 * | | |0 = EPWM synchronous start function Disabled. 1512 * | | |1 = EPWM synchronous start function Enabled. 1513 * |[1] |SSEN1 |EPWM Synchronous Start Function Enable Bits 1514 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1515 * | | |0 = EPWM synchronous start function Disabled. 1516 * | | |1 = EPWM synchronous start function Enabled. 1517 * |[2] |SSEN2 |EPWM Synchronous Start Function Enable Bits 1518 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1519 * | | |0 = EPWM synchronous start function Disabled. 1520 * | | |1 = EPWM synchronous start function Enabled. 1521 * |[3] |SSEN3 |EPWM Synchronous Start Function Enable Bits 1522 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1523 * | | |0 = EPWM synchronous start function Disabled. 1524 * | | |1 = EPWM synchronous start function Enabled. 1525 * |[4] |SSEN4 |EPWM Synchronous Start Function Enable Bits 1526 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1527 * | | |0 = EPWM synchronous start function Disabled. 1528 * | | |1 = EPWM synchronous start function Enabled. 1529 * |[5] |SSEN5 |EPWM Synchronous Start Function Enable Bits 1530 * | | |When synchronous start function is enabled, the EPWM counter enable register (EPWM_CNTEN) can be enabled by writing EPWM synchronous start trigger bit (CNTSEN). 1531 * | | |0 = EPWM synchronous start function Disabled. 1532 * | | |1 = EPWM synchronous start function Enabled. 1533 * |[9:8] |SSRC |EPWM Synchronous Start Source Select Bits 1534 * | | |00 = Synchronous start source come from EPWM0. 1535 * | | |01 = Synchronous start source come from EPWM1. 1536 * | | |10 = Synchronous start source come from BPWM0. 1537 * | | |11 = Synchronous start source come from BPWM1. 1538 * @var EPWM_T::SSTRG 1539 * Offset: 0x114 EPWM Synchronous Start Trigger Register 1540 * --------------------------------------------------------------------------------------------------- 1541 * |Bits |Field |Descriptions 1542 * | :----: | :----: | :---- | 1543 * |[0] |CNTSEN |EPWM Counter Synchronous Start Enable (Write Only) 1544 * | | |PMW counter synchronous enable function is used to make selected EPWM channels (include EPWM0_CHx and EPWM1_CHx) start counting at the same time. 1545 * | | |Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated EPWM channel counter synchronous start function is enabled. 1546 * @var EPWM_T::LEBCTL 1547 * Offset: 0x118 EPWM Leading Edge Blanking Control Register 1548 * --------------------------------------------------------------------------------------------------- 1549 * |Bits |Field |Descriptions 1550 * | :----: | :----: | :---- | 1551 * |[0] |LEBEN |EPWM Leading Edge Blanking Enable Bit 1552 * | | |0 = EPWM Leading Edge Blanking Disabled. 1553 * | | |1 = EPWM Leading Edge Blanking Enabled. 1554 * |[8] |SRCEN0 |EPWM Leading Edge Blanking Source From EPWM_CH0 Enable Bit 1555 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH0 Disabled. 1556 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH0 Enabled. 1557 * |[9] |SRCEN2 |EPWM Leading Edge Blanking Source From EPWM_CH2 Enable Bit 1558 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH2 Disabled. 1559 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH2 Enabled. 1560 * |[10] |SRCEN4 |EPWM Leading Edge Blanking Source From EPWM_CH4 Enable Bit 1561 * | | |0 = EPWM Leading Edge Blanking Source from EPWM_CH4 Disabled. 1562 * | | |1 = EPWM Leading Edge Blanking Source from EPWM_CH4 Enabled. 1563 * |[17:16] |TRGTYPE |EPWM Leading Edge Blanking Trigger Type 1564 * | | |0 = When detect leading edge blanking source rising edge, blanking counter start counting. 1565 * | | |1 = When detect leading edge blanking source falling edge, blanking counter start counting. 1566 * | | |2 = When detect leading edge blanking source rising or falling edge, blanking counter start counting. 1567 * | | |3 = Reserved. 1568 * @var EPWM_T::LEBCNT 1569 * Offset: 0x11C EPWM Leading Edge Blanking Counter Register 1570 * --------------------------------------------------------------------------------------------------- 1571 * |Bits |Field |Descriptions 1572 * | :----: | :----: | :---- | 1573 * |[8:0] |LEBCNT |EPWM Leading Edge Blanking Counter 1574 * | | |This counter value decides leading edge blanking window size. 1575 * | | |Blanking window size = LEBCNT+1, and LEB counter clock base is ECLK. 1576 * @var EPWM_T::STATUS 1577 * Offset: 0x120 EPWM Status Register 1578 * --------------------------------------------------------------------------------------------------- 1579 * |Bits |Field |Descriptions 1580 * | :----: | :----: | :---- | 1581 * |[0] |CNTMAXF0 |Time-base Counter Equal to 0xFFFF Latched Flag 1582 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1583 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1584 * |[1] |CNTMAXF1 |Time-base Counter Equal to 0xFFFF Latched Flag 1585 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1586 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1587 * |[2] |CNTMAXF2 |Time-base Counter Equal to 0xFFFF Latched Flag 1588 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1589 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1590 * |[3] |CNTMAXF3 |Time-base Counter Equal to 0xFFFF Latched Flag 1591 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1592 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1593 * |[4] |CNTMAXF4 |Time-base Counter Equal to 0xFFFF Latched Flag 1594 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1595 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1596 * |[5] |CNTMAXF5 |Time-base Counter Equal to 0xFFFF Latched Flag 1597 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 1598 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 1599 * |[8] |SYNCINF0 |Input Synchronization Latched Flag 1600 * | | |0 = Indicates no SYNC_IN event has occurred. 1601 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. 1602 * |[9] |SYNCINF2 |Input Synchronization Latched Flag 1603 * | | |0 = Indicates no SYNC_IN event has occurred. 1604 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. 1605 * |[10] |SYNCINF4 |Input Synchronization Latched Flag 1606 * | | |0 = Indicates no SYNC_IN event has occurred. 1607 * | | |1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit. 1608 * |[16] |EADCTRGF0 |EADC Start of Conversion Flag 1609 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1610 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1611 * |[17] |EADCTRGF1 |EADC Start of Conversion Flag 1612 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1613 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1614 * |[18] |EADCTRGF2 |EADC Start of Conversion Flag 1615 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1616 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1617 * |[19] |EADCTRGF3 |EADC Start of Conversion Flag 1618 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1619 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1620 * |[20] |EADCTRGF4 |EADC Start of Conversion Flag 1621 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1622 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1623 * |[21] |EADCTRGF5 |EADC Start of Conversion Flag 1624 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 1625 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 1626 * |[24] |DACTRGF |DAC Start of Conversion Flag 1627 * | | |0 = Indicates no DAC start of conversion trigger event has occurred. 1628 * | | |1 = Indicates an DAC start of conversion trigger event has occurred, software can write 1 to clear this bit 1629 * @var EPWM_T::IFA[6] 1630 * Offset: 0x130 EPWM Interrupt Flag Accumulator Register 0~5 1631 * --------------------------------------------------------------------------------------------------- 1632 * |Bits |Field |Descriptions 1633 * | :----: | :----: | :---- | 1634 * |[15:0] |IFACNT |EPWM_CHn Interrupt Flag Counter 1635 * | | |The register sets the count number which defines how many times of EPWM_CHn period occurs to set bit IFAIFn to request the EPWM period interrupt. 1636 * | | |EPWM flag will be set in every IFACNT[15:0] times of EPWM period. 1637 * |[24] |STPMOD |EPWM_CHn Interrupt Flag Accumulator Stop Mode Enable Bits 1638 * | | |0 = EPWM_CHn interrupt flag accumulator stop mode disable. 1639 * | | |1 = EPWM_CHn interrupt flag accumulator stop mode enable. 1640 * |[29:28] |IFASEL |EPWM_CHn Interrupt Flag Accumulator Source Select 1641 * | | |00 = CNT equal to Zero in channel n. 1642 * | | |01 = CNT equal to PERIOD in channel n. 1643 * | | |10 = CNT equal to CMPU in channel n. 1644 * | | |11 = CNT equal to CMPD in channel n. 1645 * |[31] |IFAEN |EPWM_CHn Interrupt Flag Accumulator Enable Bits 1646 * | | |0 = EPWM_CHn interrupt flag accumulator disable. 1647 * | | |1 = EPWM_CHn interrupt flag accumulator enable. 1648 * @var EPWM_T::AINTSTS 1649 * Offset: 0x150 EPWM Accumulator Interrupt Flag Register 1650 * --------------------------------------------------------------------------------------------------- 1651 * |Bits |Field |Descriptions 1652 * | :----: | :----: | :---- | 1653 * |[0] |IFAIF0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1654 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1655 * |[1] |IFAIF1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1656 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1657 * |[2] |IFAIF2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1658 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1659 * |[3] |IFAIF3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1660 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1661 * |[4] |IFAIF4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1662 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1663 * |[5] |IFAIF5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Flag 1664 * | | |Flag is set by hardware when condition match IFASEL in EPWM_IFAn register, software can clear this bit by writing 1 to it. 1665 * @var EPWM_T::AINTEN 1666 * Offset: 0x154 EPWM Accumulator Interrupt Enable Register 1667 * --------------------------------------------------------------------------------------------------- 1668 * |Bits |Field |Descriptions 1669 * | :----: | :----: | :---- | 1670 * |[0] |IFAIEN0 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1671 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1672 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1673 * |[1] |IFAIEN1 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1674 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1675 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1676 * |[2] |IFAIEN2 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1677 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1678 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1679 * |[3] |IFAIEN3 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1680 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1681 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1682 * |[4] |IFAIEN4 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1683 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1684 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1685 * |[5] |IFAIEN5 |EPWM_CHn Interrupt Flag Accumulator Interrupt Enable Bits 1686 * | | |0 = Interrupt Flag accumulator interrupt Disabled. 1687 * | | |1 = Interrupt Flag accumulator interrupt Enabled. 1688 * @var EPWM_T::APDMACTL 1689 * Offset: 0x158 EPWM Accumulator PDMA Control Register 1690 * --------------------------------------------------------------------------------------------------- 1691 * |Bits |Field |Descriptions 1692 * | :----: | :----: | :---- | 1693 * |[0] |APDMAEN0 |Channel N Accumulator PDMA Enable Bits 1694 * | | |0 = Channel n PDMA function Disabled. 1695 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1696 * |[1] |APDMAEN1 |Channel N Accumulator PDMA Enable Bits 1697 * | | |0 = Channel n PDMA function Disabled. 1698 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1699 * |[2] |APDMAEN2 |Channel N Accumulator PDMA Enable Bits 1700 * | | |0 = Channel n PDMA function Disabled. 1701 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1702 * |[3] |APDMAEN3 |Channel N Accumulator PDMA Enable Bits 1703 * | | |0 = Channel n PDMA function Disabled. 1704 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1705 * |[4] |APDMAEN4 |Channel N Accumulator PDMA Enable Bits 1706 * | | |0 = Channel n PDMA function Disabled. 1707 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1708 * |[5] |APDMAEN5 |Channel N Accumulator PDMA Enable Bits 1709 * | | |0 = Channel n PDMA function Disabled. 1710 * | | |1 = Channel n PDMA function Enabled for the channel n to trigger PDMA to transfer memory data to register. 1711 * @var EPWM_T::CAPINEN 1712 * Offset: 0x200 EPWM Capture Input Enable Register 1713 * --------------------------------------------------------------------------------------------------- 1714 * |Bits |Field |Descriptions 1715 * | :----: | :----: | :---- | 1716 * |[0] |CAPINEN0 |Capture Input Enable Bits 1717 * | | |0 = EPWM Channel capture input path Disabled 1718 * | | |The input of EPWM channel capture function is always regarded as 0. 1719 * | | |1 = EPWM Channel capture input path Enabled 1720 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1721 * |[1] |CAPINEN1 |Capture Input Enable Bits 1722 * | | |0 = EPWM Channel capture input path Disabled 1723 * | | |The input of EPWM channel capture function is always regarded as 0. 1724 * | | |1 = EPWM Channel capture input path Enabled 1725 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1726 * |[2] |CAPINEN2 |Capture Input Enable Bits 1727 * | | |0 = EPWM Channel capture input path Disabled 1728 * | | |The input of EPWM channel capture function is always regarded as 0. 1729 * | | |1 = EPWM Channel capture input path Enabled 1730 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1731 * |[3] |CAPINEN3 |Capture Input Enable Bits 1732 * | | |0 = EPWM Channel capture input path Disabled 1733 * | | |The input of EPWM channel capture function is always regarded as 0. 1734 * | | |1 = EPWM Channel capture input path Enabled 1735 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1736 * |[4] |CAPINEN4 |Capture Input Enable Bits 1737 * | | |0 = EPWM Channel capture input path Disabled 1738 * | | |The input of EPWM channel capture function is always regarded as 0. 1739 * | | |1 = EPWM Channel capture input path Enabled 1740 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1741 * |[5] |CAPINEN5 |Capture Input Enable Bits 1742 * | | |0 = EPWM Channel capture input path Disabled 1743 * | | |The input of EPWM channel capture function is always regarded as 0. 1744 * | | |1 = EPWM Channel capture input path Enabled 1745 * | | |The input of EPWM channel capture function comes from correlative multifunction pin. 1746 * @var EPWM_T::CAPCTL 1747 * Offset: 0x204 EPWM Capture Control Register 1748 * --------------------------------------------------------------------------------------------------- 1749 * |Bits |Field |Descriptions 1750 * | :----: | :----: | :---- | 1751 * |[0] |CAPEN0 |Capture Function Enable Bits 1752 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1753 * | | |1 = Capture function Enabled 1754 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1755 * |[1] |CAPEN1 |Capture Function Enable Bits 1756 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1757 * | | |1 = Capture function Enabled 1758 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1759 * |[2] |CAPEN2 |Capture Function Enable Bits 1760 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1761 * | | |1 = Capture function Enabled 1762 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1763 * |[3] |CAPEN3 |Capture Function Enable Bits 1764 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1765 * | | |1 = Capture function Enabled 1766 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1767 * |[4] |CAPEN4 |Capture Function Enable Bits 1768 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1769 * | | |1 = Capture function Enabled 1770 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1771 * |[5] |CAPEN5 |Capture Function Enable Bits 1772 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 1773 * | | |1 = Capture function Enabled 1774 * | | |Capture latched the EPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 1775 * |[8] |CAPINV0 |Capture Inverter Enable Bits 1776 * | | |0 = Capture source inverter Disabled. 1777 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1778 * |[9] |CAPINV1 |Capture Inverter Enable Bits 1779 * | | |0 = Capture source inverter Disabled. 1780 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1781 * |[10] |CAPINV2 |Capture Inverter Enable Bits 1782 * | | |0 = Capture source inverter Disabled. 1783 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1784 * |[11] |CAPINV3 |Capture Inverter Enable Bits 1785 * | | |0 = Capture source inverter Disabled. 1786 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1787 * |[12] |CAPINV4 |Capture Inverter Enable Bits 1788 * | | |0 = Capture source inverter Disabled. 1789 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1790 * |[13] |CAPINV5 |Capture Inverter Enable Bits 1791 * | | |0 = Capture source inverter Disabled. 1792 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 1793 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits 1794 * | | |0 = Rising capture reload counter Disabled. 1795 * | | |1 = Rising capture reload counter Enabled. 1796 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits 1797 * | | |0 = Rising capture reload counter Disabled. 1798 * | | |1 = Rising capture reload counter Enabled. 1799 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits 1800 * | | |0 = Rising capture reload counter Disabled. 1801 * | | |1 = Rising capture reload counter Enabled. 1802 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits 1803 * | | |0 = Rising capture reload counter Disabled. 1804 * | | |1 = Rising capture reload counter Enabled. 1805 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits 1806 * | | |0 = Rising capture reload counter Disabled. 1807 * | | |1 = Rising capture reload counter Enabled. 1808 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits 1809 * | | |0 = Rising capture reload counter Disabled. 1810 * | | |1 = Rising capture reload counter Enabled. 1811 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits 1812 * | | |0 = Falling capture reload counter Disabled. 1813 * | | |1 = Falling capture reload counter Enabled. 1814 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits 1815 * | | |0 = Falling capture reload counter Disabled. 1816 * | | |1 = Falling capture reload counter Enabled. 1817 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits 1818 * | | |0 = Falling capture reload counter Disabled. 1819 * | | |1 = Falling capture reload counter Enabled. 1820 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits 1821 * | | |0 = Falling capture reload counter Disabled. 1822 * | | |1 = Falling capture reload counter Enabled. 1823 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits 1824 * | | |0 = Falling capture reload counter Disabled. 1825 * | | |1 = Falling capture reload counter Enabled. 1826 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits 1827 * | | |0 = Falling capture reload counter Disabled. 1828 * | | |1 = Falling capture reload counter Enabled. 1829 * @var EPWM_T::CAPSTS 1830 * Offset: 0x208 EPWM Capture Status Register 1831 * --------------------------------------------------------------------------------------------------- 1832 * |Bits |Field |Descriptions 1833 * | :----: | :----: | :---- | 1834 * |[0] |CRLIFOV0 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1835 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1836 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1837 * |[1] |CRLIFOV1 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1838 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1839 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1840 * |[2] |CRLIFOV2 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1841 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1842 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1843 * |[3] |CRLIFOV3 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1844 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1845 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1846 * |[4] |CRLIFOV4 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1847 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1848 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1849 * |[5] |CRLIFOV5 |Capture Rising Latch Interrupt Flag Overrun Status (Read Only) 1850 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1. 1851 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF. 1852 * |[8] |CFLIFOV0 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1853 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1854 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1855 * |[9] |CFLIFOV1 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1856 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1857 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1858 * |[10] |CFLIFOV2 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1859 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1860 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1861 * |[11] |CFLIFOV3 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1862 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1863 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1864 * |[12] |CFLIFOV4 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1865 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1866 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1867 * |[13] |CFLIFOV5 |Capture Falling Latch Interrupt Flag Overrun Status (Read Only) 1868 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1. 1869 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF. 1870 * @var EPWM_T::PDMACTL 1871 * Offset: 0x23C EPWM PDMA Control Register 1872 * --------------------------------------------------------------------------------------------------- 1873 * |Bits |Field |Descriptions 1874 * | :----: | :----: | :---- | 1875 * |[0] |CHEN0_1 |Channel 0/1 PDMA Enable 1876 * | | |0 = Channel 0/1 PDMA function Disabled. 1877 * | | |1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory. 1878 * |[2:1] |CAPMOD0_1 |Select EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 to Do PDMA Transfer 1879 * | | |00 = Reserved. 1880 * | | |01 = EPWM_RCAPDAT0/1 register. 1881 * | | |10 = EPWM_FCAPDAT0/1 register. 1882 * | | |11 = Both EPWM_RCAPDAT0/1 and EPWM_FCAPDAT0/1 registers. 1883 * |[3] |CAPORD0_1 |Capture Channel 0/1 Rising/Falling Order 1884 * | | |Set this bit to determine whether the EPWM_RCAPDAT0/1 or EPWM_FCAPDAT0/1 register is the first captured data transferred to memory through PDMA when CAPMOD0_1 bits are set to = 0x3. 1885 * | | |0 = EPWM_FCAPDAT0/1 register is the first captured data to memory. 1886 * | | |1 = EPWM_RCAPDAT0/1 register is the first captured data to memory. 1887 * |[4] |CHSEL0_1 |Select Channel 0/1 to Do PDMA Transfer 1888 * | | |0 = Channel0. 1889 * | | |1 = Channel1. 1890 * |[8] |CHEN2_3 |Channel 2/3 PDMA Enable 1891 * | | |0 = Channel 2/3 PDMA function Disabled. 1892 * | | |1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory. 1893 * |[10:9] |CAPMOD2_3 |Select EPWM_RCAPDAT2/3 or EPWM_FCAODAT2/3 to Do PDMA Transfer 1894 * | | |00 = Reserved. 1895 * | | |01 = EPWM_RCAPDAT2/3 register. 1896 * | | |10 = EPWM_FCAPDAT2/3 register. 1897 * | | |11 = Both EPWM_RCAPDAT2/3 and EPWM_FCAPDAT2/3 registers. 1898 * |[11] |CAPORD2_3 |Capture Channel 2/3 Rising/Falling Order 1899 * | | |Set this bit to determine whether the EPWM_RCAPDAT2/3 or EPWM_FCAPDAT2/3 register is the first captured data transferred to memory through PDMA when CAPMOD2_3 bits are set to =0x3. 1900 * | | |0 = EPWM_FCAPDAT2/3 register is the first captured data to memory. 1901 * | | |1 = EPWM_RCAPDAT2/3 register is the first captured data to memory. 1902 * |[12] |CHSEL2_3 |Select Channel 2/3 to Do PDMA Transfer 1903 * | | |0 = Channel2. 1904 * | | |1 = Channel3. 1905 * |[16] |CHEN4_5 |Channel 4/5 PDMA Enable 1906 * | | |0 = Channel 4/5 PDMA function Disabled. 1907 * | | |1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory. 1908 * |[18:17] |CAPMOD4_5 |Select EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 to Do PDMA Transfer 1909 * | | |00 = Reserved. 1910 * | | |01 = EPWM_RCAPDAT4/5 register. 1911 * | | |10 = EPWM_FCAPDAT4/5 register. 1912 * | | |11 = Both EPWM_RCAPDAT4/5 and EPWM_FCAPDAT4/5 registers. 1913 * |[19] |CAPORD4_5 |Capture Channel 4/5 Rising/Falling Order 1914 * | | |Set this bit to determine whether the EPWM_RCAPDAT4/5 or EPWM_FCAPDAT4/5 register is the first captured data transferred to memory through PDMA when CAPMOD4_5 bits =are set to 0x3. 1915 * | | |0 = EPWM_FCAPDAT4/5 register is the first captured data to memory. 1916 * | | |1 = EPWM_RCAPDAT4/5 register is the first captured data to memory. 1917 * |[20] |CHSEL4_5 |Select Channel 4/5 to Do PDMA Transfer 1918 * | | |0 = Channel4. 1919 * | | |1 = Channel5. 1920 * @var EPWM_T::PDMACAP[3] 1921 * Offset: 0x240 EPWM Capture Channel 01 PDMA Register 1922 * --------------------------------------------------------------------------------------------------- 1923 * |Bits |Field |Descriptions 1924 * | :----: | :----: | :---- | 1925 * |[15:0] |CAPBUF |EPWM Capture PDMA Register (Read Only) 1926 * | | |This register is use as a buffer to transfer EPWM capture rising or falling data to memory by PDMA. 1927 * @var EPWM_T::CAPIEN 1928 * Offset: 0x250 EPWM Capture Interrupt Enable Register 1929 * --------------------------------------------------------------------------------------------------- 1930 * |Bits |Field |Descriptions 1931 * | :----: | :----: | :---- | 1932 * |[0] |CAPRIEN0 |EPWM Capture Rising Latch Interrupt Enable Bits 1933 * | | |0 = Capture rising edge latch interrupt Disabled. 1934 * | | |1 = Capture rising edge latch interrupt Enabled. 1935 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN0 bit must be disabled. 1936 * |[1] |CAPRIEN1 |EPWM Capture Rising Latch Interrupt Enable Bits 1937 * | | |0 = Capture rising edge latch interrupt Disabled. 1938 * | | |1 = Capture rising edge latch interrupt Enabled. 1939 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN1 bit must be disabled. 1940 * |[2] |CAPRIEN2 |EPWM Capture Rising Latch Interrupt Enable Bits 1941 * | | |0 = Capture rising edge latch interrupt Disabled. 1942 * | | |1 = Capture rising edge latch interrupt Enabled. 1943 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN2 bit must be disabled. 1944 * |[3] |CAPRIEN3 |EPWM Capture Rising Latch Interrupt Enable Bits 1945 * | | |0 = Capture rising edge latch interrupt Disabled. 1946 * | | |1 = Capture rising edge latch interrupt Enabled. 1947 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN3 bit must be disabled. 1948 * |[4] |CAPRIEN4 |EPWM Capture Rising Latch Interrupt Enable Bits 1949 * | | |0 = Capture rising edge latch interrupt Disabled. 1950 * | | |1 = Capture rising edge latch interrupt Enabled. 1951 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN4 bit must be disabled. 1952 * |[5] |CAPRIEN5 |EPWM Capture Rising Latch Interrupt Enable Bits 1953 * | | |0 = Capture rising edge latch interrupt Disabled. 1954 * | | |1 = Capture rising edge latch interrupt Enabled. 1955 * | | |Note: When Capture with PDMA operating, corresponding channel CAPRIEN5 bit must be disabled. 1956 * |[8] |CAPFIEN0 |EPWM Capture Falling Latch Interrupt Enable Bits 1957 * | | |0 = Capture falling edge latch interrupt Disabled. 1958 * | | |1 = Capture falling edge latch interrupt Enabled. 1959 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN0 bit must be disabled. 1960 * |[9] |CAPFIEN1 |EPWM Capture Falling Latch Interrupt Enable Bits 1961 * | | |0 = Capture falling edge latch interrupt Disabled. 1962 * | | |1 = Capture falling edge latch interrupt Enabled. 1963 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN1 bit must be disabled. 1964 * |[10] |CAPFIEN2 |EPWM Capture Falling Latch Interrupt Enable Bits 1965 * | | |0 = Capture falling edge latch interrupt Disabled. 1966 * | | |1 = Capture falling edge latch interrupt Enabled. 1967 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN2 bit must be disabled. 1968 * |[11] |CAPFIEN3 |EPWM Capture Falling Latch Interrupt Enable Bits 1969 * | | |0 = Capture falling edge latch interrupt Disabled. 1970 * | | |1 = Capture falling edge latch interrupt Enabled. 1971 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN3 bit must be disabled. 1972 * |[12] |CAPFIEN4 |EPWM Capture Falling Latch Interrupt Enable Bits 1973 * | | |0 = Capture falling edge latch interrupt Disabled. 1974 * | | |1 = Capture falling edge latch interrupt Enabled. 1975 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN4 bit must be disabled. 1976 * |[13] |CAPFIEN5 |EPWM Capture Falling Latch Interrupt Enable Bits 1977 * | | |0 = Capture falling edge latch interrupt Disabled. 1978 * | | |1 = Capture falling edge latch interrupt Enabled. 1979 * | | |Note: When Capture with PDMA operating, corresponding channel CAPFIEN5 bit must be disabled. 1980 * @var EPWM_T::CAPIF 1981 * Offset: 0x254 EPWM Capture Interrupt Flag Register 1982 * --------------------------------------------------------------------------------------------------- 1983 * |Bits |Field |Descriptions 1984 * | :----: | :----: | :---- | 1985 * |[0] |CRLIF0 |EPWM Capture Rising Latch Interrupt Flag 1986 * | | |This bit is writing 1 to clear. 1987 * | | |0 = No capture rising latch condition happened. 1988 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1989 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF0 bit will cleared by hardware after PDMA transfer data. 1990 * |[1] |CRLIF1 |EPWM Capture Rising Latch Interrupt Flag 1991 * | | |This bit is writing 1 to clear. 1992 * | | |0 = No capture rising latch condition happened. 1993 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1994 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF1 bit will cleared by hardware after PDMA transfer data. 1995 * |[2] |CRLIF2 |EPWM Capture Rising Latch Interrupt Flag 1996 * | | |This bit is writing 1 to clear. 1997 * | | |0 = No capture rising latch condition happened. 1998 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1999 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF2 bit will cleared by hardware after PDMA transfer data. 2000 * |[3] |CRLIF3 |EPWM Capture Rising Latch Interrupt Flag 2001 * | | |This bit is writing 1 to clear. 2002 * | | |0 = No capture rising latch condition happened. 2003 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2004 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF3 bit will cleared by hardware after PDMA transfer data. 2005 * |[4] |CRLIF4 |EPWM Capture Rising Latch Interrupt Flag 2006 * | | |This bit is writing 1 to clear. 2007 * | | |0 = No capture rising latch condition happened. 2008 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2009 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF4 bit will cleared by hardware after PDMA transfer data. 2010 * |[5] |CRLIF5 |EPWM Capture Rising Latch Interrupt Flag 2011 * | | |This bit is writing 1 to clear. 2012 * | | |0 = No capture rising latch condition happened. 2013 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 2014 * | | |Note: When Capture with PDMA operating, corresponding channel CRLIF5 bit will cleared by hardware after PDMA transfer data. 2015 * |[8] |CFLIF0 |EPWM Capture Falling Latch Interrupt Flag 2016 * | | |This bit is writing 1 to clear. 2017 * | | |0 = No capture falling latch condition happened. 2018 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2019 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF0 bit will cleared by hardware after PDMA transfer data. 2020 * |[9] |CFLIF1 |EPWM Capture Falling Latch Interrupt Flag 2021 * | | |This bit is writing 1 to clear. 2022 * | | |0 = No capture falling latch condition happened. 2023 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2024 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF1 bit will cleared by hardware after PDMA transfer data. 2025 * |[10] |CFLIF2 |EPWM Capture Falling Latch Interrupt Flag 2026 * | | |This bit is writing 1 to clear. 2027 * | | |0 = No capture falling latch condition happened. 2028 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2029 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF2 bit will cleared by hardware after PDMA transfer data. 2030 * |[11] |CFLIF3 |EPWM Capture Falling Latch Interrupt Flag 2031 * | | |This bit is writing 1 to clear. 2032 * | | |0 = No capture falling latch condition happened. 2033 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2034 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF3 bit will cleared by hardware after PDMA transfer data. 2035 * |[12] |CFLIF4 |EPWM Capture Falling Latch Interrupt Flag 2036 * | | |This bit is writing 1 to clear. 2037 * | | |0 = No capture falling latch condition happened. 2038 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2039 * | | |Note: When Capture with PDMA operating, corresponding channel CFLIF4 bit will cleared by hardware after PDMA transfer data. 2040 * |[13] |CFLIF5 |EPWM Capture Falling Latch Interrupt Flag 2041 * | | |This bit is writing 1 to clear. 2042 * | | |0 = No capture falling latch condition happened. 2043 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 2044 * | | |Note: When Capture with PDMA operating, CAPIF corresponding channel CFLIF will cleared by hardware after PDMA transfer data. 2045 * @var EPWM_T::PBUF[6] 2046 * Offset: 0x304 EPWM PERIOD0~5 Buffer 2047 * --------------------------------------------------------------------------------------------------- 2048 * |Bits |Field |Descriptions 2049 * | :----: | :----: | :---- | 2050 * |[15:0] |PBUF |EPWM Period Register Buffer (Read Only) 2051 * | | |Used as PERIOD active register. 2052 * @var EPWM_T::CMPBUF[6] 2053 * Offset: 0x31C EPWM CMPDAT0~5 Buffer 2054 * --------------------------------------------------------------------------------------------------- 2055 * |Bits |Field |Descriptions 2056 * | :----: | :----: | :---- | 2057 * |[15:0] |CMPBUF |EPWM Comparator Register Buffer (Read Only) 2058 * | | |Used as CMP active register. 2059 * @var EPWM_T::CPSCBUF[3] 2060 * Offset: 0x334 EPWM CLKPSC0_1/2_3/4_5 Buffer 2061 * --------------------------------------------------------------------------------------------------- 2062 * |Bits |Field |Descriptions 2063 * | :----: | :----: | :---- | 2064 * |[11:0] |CPSCBUF |EPWM Counter Clock Prescale Buffer 2065 * | | |Use as EPWM counter clock prescale active register. 2066 * @var EPWM_T::FTCBUF[3] 2067 * Offset: 0x340 EPWM FTCMPDAT0_1/2_3/4_5 Buffer 2068 * --------------------------------------------------------------------------------------------------- 2069 * |Bits |Field |Descriptions 2070 * | :----: | :----: | :---- | 2071 * |[15:0] |FTCMPBUF |EPWM FTCMPDAT Buffer (Read Only) 2072 * | | |Used as FTCMPDAT active register. 2073 * @var EPWM_T::FTCI 2074 * Offset: 0x34C EPWM FTCMPDAT Indicator Register 2075 * --------------------------------------------------------------------------------------------------- 2076 * |Bits |Field |Descriptions 2077 * | :----: | :----: | :---- | 2078 * |[0] |FTCMU0 |EPWM FTCMPDAT Up Indicator 2079 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. 2080 * |[1] |FTCMU2 |EPWM FTCMPDAT Up Indicator 2081 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. 2082 * |[2] |FTCMU4 |EPWM FTCMPDAT Up Indicator 2083 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=1, software can write 1 to clear this bit. 2084 * |[8] |FTCMD0 |EPWM FTCMPDAT Down Indicator 2085 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. 2086 * |[9] |FTCMD2 |EPWM FTCMPDAT Down Indicator 2087 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. 2088 * |[10] |FTCMD4 |EPWM FTCMPDAT Down Indicator 2089 * | | |Indicator will be set to high when FTCMPDATn equal to CNTn and DIRF=0, software can write 1 to clear this bit. 2090 */ 2091 __IO uint32_t CTL0; /*!< [0x0000] EPWM Control Register 0 */ 2092 __IO uint32_t CTL1; /*!< [0x0004] EPWM Control Register 1 */ 2093 __IO uint32_t SYNC; /*!< [0x0008] EPWM Synchronization Register */ 2094 __IO uint32_t SWSYNC; /*!< [0x000c] EPWM Software Control Synchronization Register */ 2095 __IO uint32_t CLKSRC; /*!< [0x0010] EPWM Clock Source Register */ 2096 __IO uint32_t CLKPSC[3]; /*!< [0x0014~0x001c] EPWM Clock Prescale Register 0_1,2_3,4_5 */ 2097 __IO uint32_t CNTEN; /*!< [0x0020] EPWM Counter Enable Register */ 2098 __IO uint32_t CNTCLR; /*!< [0x0024] EPWM Clear Counter Register */ 2099 __IO uint32_t LOAD; /*!< [0x0028] EPWM Load Register */ 2100 __I uint32_t RESERVE0[1]; 2101 __IO uint32_t PERIOD[6]; /*!< [0x0030~0x0044] EPWM Period Register 0~5 */ 2102 __I uint32_t RESERVE1[2]; 2103 __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] EPWM Comparator Register 0~5 */ 2104 __I uint32_t RESERVE2[2]; 2105 __IO uint32_t DTCTL[3]; /*!< [0x0070~0x0078] EPWM Dead-Time Control Register 0_1,2_3,4_5 */ 2106 __I uint32_t RESERVE3[1]; 2107 __IO uint32_t PHS[3]; /*!< [0x0080~0x0088] EPWM Counter Phase Register 0_1,2_3,4_5 */ 2108 __I uint32_t RESERVE4[1]; 2109 __I uint32_t CNT[6]; /*!< [0x0090~0x00A4 EPWM Counter Register 0~5 */ 2110 __I uint32_t RESERVE5[2]; 2111 __IO uint32_t WGCTL0; /*!< [0x00b0] EPWM Generation Register 0 */ 2112 __IO uint32_t WGCTL1; /*!< [0x00b4] EPWM Generation Register 1 */ 2113 __IO uint32_t MSKEN; /*!< [0x00b8] EPWM Mask Enable Register */ 2114 __IO uint32_t MSK; /*!< [0x00bc] EPWM Mask Data Register */ 2115 __IO uint32_t BNF; /*!< [0x00c0] EPWM Brake Noise Filter Register */ 2116 __IO uint32_t FAILBRK; /*!< [0x00c4] EPWM System Fail Brake Control Register */ 2117 __IO uint32_t BRKCTL[3]; /*!< [0x00c8~0x00d0] EPWM Brake Edge Detect Control Register 0_1,2_3,4_5 */ 2118 __IO uint32_t POLCTL; /*!< [0x00d4] EPWM Pin Polar Inverse Register */ 2119 __IO uint32_t POEN; /*!< [0x00d8] EPWM Output Enable Register */ 2120 __O uint32_t SWBRK; /*!< [0x00dc] EPWM Software Brake Control Register */ 2121 __IO uint32_t INTEN0; /*!< [0x00e0] EPWM Interrupt Enable Register 0 */ 2122 __IO uint32_t INTEN1; /*!< [0x00e4] EPWM Interrupt Enable Register 1 */ 2123 __IO uint32_t INTSTS0; /*!< [0x00e8] EPWM Interrupt Flag Register 0 */ 2124 __IO uint32_t INTSTS1; /*!< [0x00ec] EPWM Interrupt Flag Register 1 */ 2125 __I uint32_t RESERVE6[1]; 2126 __IO uint32_t DACTRGEN; /*!< [0x00f4] EPWM Trigger DAC Enable Register */ 2127 __IO uint32_t EADCTS0; /*!< [0x00f8] EPWM Trigger EADC Source Select Register 0 */ 2128 __IO uint32_t EADCTS1; /*!< [0x00fc] EPWM Trigger EADC Source Select Register 1 */ 2129 __IO uint32_t FTCMPDAT[3]; /*!< [0x0100~0x108] EPWM Free Trigger Compare Register 0_1,2_3,4_5 */ 2130 __I uint32_t RESERVE7[1]; 2131 __IO uint32_t SSCTL; /*!< [0x0110] EPWM Synchronous Start Control Register */ 2132 __O uint32_t SSTRG; /*!< [0x0114] EPWM Synchronous Start Trigger Register */ 2133 __IO uint32_t LEBCTL; /*!< [0x0118] EPWM Leading Edge Blanking Control Register */ 2134 __IO uint32_t LEBCNT; /*!< [0x011c] EPWM Leading Edge Blanking Counter Register */ 2135 __IO uint32_t STATUS; /*!< [0x0120] EPWM Status Register */ 2136 __I uint32_t RESERVE8[3]; 2137 __IO uint32_t IFA[6]; /*!< [0x0130~0x144] EPWM Interrupt Flag Accumulator Register 0~5 */ 2138 __I uint32_t RESERVE9[2]; 2139 __IO uint32_t AINTSTS; /*!< [0x0150] EPWM Accumulator Interrupt Flag Register */ 2140 __IO uint32_t AINTEN; /*!< [0x0154] EPWM Accumulator Interrupt Enable Register */ 2141 __IO uint32_t APDMACTL; /*!< [0x0158] EPWM Accumulator PDMA Control Register */ 2142 __I uint32_t RESERVE10[1]; 2143 __IO uint32_t FDEN; /*!< [0x0160] EPWM Fault Detect Enable Register */ 2144 __IO uint32_t FDCTL[6]; /*!< [0x0164~0x178] EPWM Fault Detect Control Register 0~5 */ 2145 __IO uint32_t FDIEN; /*!< [0x017C] EPWM Fault Detect Interrupt Enable Register */ 2146 __IO uint32_t FDSTS; /*!< [0x0180] EPWM Fault Detect Interrupt Flag Register */ 2147 __IO uint32_t EADCPSCCTL; /*!< [0x0184] EPWM Trigger EADC Prescale Control Register */ 2148 __IO uint32_t EADCPSC0; /*!< [0x0188] EPWM Trigger EADC Prescale Register 0 */ 2149 __IO uint32_t EADCPSC1; /*!< [0x018C] EPWM Trigger EADC Prescale Register 1 */ 2150 __IO uint32_t EADCPSCNT0; /*!< [0x0190] EPWM Trigger EADC Prescale Counter Register 0 */ 2151 __IO uint32_t EADCPSCNT1; /*!< [0x0194] EPWM Trigger EADC Prescale Counter Register 1 */ 2152 __I uint32_t RESERVE11[26]; 2153 __IO uint32_t CAPINEN; /*!< [0x0200] EPWM Capture Input Enable Register */ 2154 __IO uint32_t CAPCTL; /*!< [0x0204] EPWM Capture Control Register */ 2155 __I uint32_t CAPSTS; /*!< [0x0208] EPWM Capture Status Register */ 2156 ECAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] EPWM Rising and Falling Capture Data Register 0~5 */ 2157 __IO uint32_t PDMACTL; /*!< [0x023c] EPWM PDMA Control Register */ 2158 __I uint32_t PDMACAP[3]; /*!< [0x0240~0x248] EPWM Capture Channel 0_1,2_3,4_5 PDMA Register */ 2159 __I uint32_t RESERVE12[1]; 2160 __IO uint32_t CAPIEN; /*!< [0x0250] EPWM Capture Interrupt Enable Register */ 2161 __IO uint32_t CAPIF; /*!< [0x0254] EPWM Capture Interrupt Flag Register */ 2162 __I uint32_t RESERVE13[43]; 2163 __I uint32_t PBUF[6]; /*!< [0x0304~0x0318 EPWM PERIOD0~5 Buffer */ 2164 __I uint32_t CMPBUF[6]; /*!< [0x031C~0x0330 EPWM CMPDAT0~5 Buffer */ 2165 __I uint32_t CPSCBUF[3]; /*!< [0x0334~0x33c] EPWM CLKPSC0_1,2_3,4_5 Buffer */ 2166 __I uint32_t FTCBUF[3]; /*!< [0x0340~0x348] EPWM FTCMPDAT0_1,2_3,4_5 Buffer */ 2167 __IO uint32_t FTCI; /*!< [0x034c] EPWM FTCMPDAT Indicator Register */ 2168 2169 } EPWM_T; 2170 2171 /** 2172 @addtogroup EPWM_CONST EPWM Bit Field Definition 2173 Constant Definitions for EPWM Controller 2174 @{ 2175 */ 2176 2177 #define EPWM_CTL0_CTRLD0_Pos (0) /*!< EPWM_T::CTL0: CTRLD0 Position */ 2178 #define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) /*!< EPWM_T::CTL0: CTRLD0 Mask */ 2179 2180 #define EPWM_CTL0_CTRLD1_Pos (1) /*!< EPWM_T::CTL0: CTRLD1 Position */ 2181 #define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) /*!< EPWM_T::CTL0: CTRLD1 Mask */ 2182 2183 #define EPWM_CTL0_CTRLD2_Pos (2) /*!< EPWM_T::CTL0: CTRLD2 Position */ 2184 #define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) /*!< EPWM_T::CTL0: CTRLD2 Mask */ 2185 2186 #define EPWM_CTL0_CTRLD3_Pos (3) /*!< EPWM_T::CTL0: CTRLD3 Position */ 2187 #define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) /*!< EPWM_T::CTL0: CTRLD3 Mask */ 2188 2189 #define EPWM_CTL0_CTRLD4_Pos (4) /*!< EPWM_T::CTL0: CTRLD4 Position */ 2190 #define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) /*!< EPWM_T::CTL0: CTRLD4 Mask */ 2191 2192 #define EPWM_CTL0_CTRLD5_Pos (5) /*!< EPWM_T::CTL0: CTRLD5 Position */ 2193 #define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) /*!< EPWM_T::CTL0: CTRLD5 Mask */ 2194 2195 #define EPWM_CTL0_WINLDEN0_Pos (8) /*!< EPWM_T::CTL0: WINLDEN0 Position */ 2196 #define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) /*!< EPWM_T::CTL0: WINLDEN0 Mask */ 2197 2198 #define EPWM_CTL0_WINLDEN1_Pos (9) /*!< EPWM_T::CTL0: WINLDEN1 Position */ 2199 #define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) /*!< EPWM_T::CTL0: WINLDEN1 Mask */ 2200 2201 #define EPWM_CTL0_WINLDEN2_Pos (10) /*!< EPWM_T::CTL0: WINLDEN2 Position */ 2202 #define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) /*!< EPWM_T::CTL0: WINLDEN2 Mask */ 2203 2204 #define EPWM_CTL0_WINLDEN3_Pos (11) /*!< EPWM_T::CTL0: WINLDEN3 Position */ 2205 #define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) /*!< EPWM_T::CTL0: WINLDEN3 Mask */ 2206 2207 #define EPWM_CTL0_WINLDEN4_Pos (12) /*!< EPWM_T::CTL0: WINLDEN4 Position */ 2208 #define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) /*!< EPWM_T::CTL0: WINLDEN4 Mask */ 2209 2210 #define EPWM_CTL0_WINLDEN5_Pos (13) /*!< EPWM_T::CTL0: WINLDEN5 Position */ 2211 #define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) /*!< EPWM_T::CTL0: WINLDEN5 Mask */ 2212 2213 #define EPWM_CTL0_IMMLDEN0_Pos (16) /*!< EPWM_T::CTL0: IMMLDEN0 Position */ 2214 #define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) /*!< EPWM_T::CTL0: IMMLDEN0 Mask */ 2215 2216 #define EPWM_CTL0_IMMLDEN1_Pos (17) /*!< EPWM_T::CTL0: IMMLDEN1 Position */ 2217 #define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) /*!< EPWM_T::CTL0: IMMLDEN1 Mask */ 2218 2219 #define EPWM_CTL0_IMMLDEN2_Pos (18) /*!< EPWM_T::CTL0: IMMLDEN2 Position */ 2220 #define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) /*!< EPWM_T::CTL0: IMMLDEN2 Mask */ 2221 2222 #define EPWM_CTL0_IMMLDEN3_Pos (19) /*!< EPWM_T::CTL0: IMMLDEN3 Position */ 2223 #define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) /*!< EPWM_T::CTL0: IMMLDEN3 Mask */ 2224 2225 #define EPWM_CTL0_IMMLDEN4_Pos (20) /*!< EPWM_T::CTL0: IMMLDEN4 Position */ 2226 #define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) /*!< EPWM_T::CTL0: IMMLDEN4 Mask */ 2227 2228 #define EPWM_CTL0_IMMLDEN5_Pos (21) /*!< EPWM_T::CTL0: IMMLDEN5 Position */ 2229 #define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) /*!< EPWM_T::CTL0: IMMLDEN5 Mask */ 2230 2231 #define EPWM_CTL0_GROUPEN_Pos (24) /*!< EPWM_T::CTL0: GROUPEN Position */ 2232 #define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) /*!< EPWM_T::CTL0: GROUPEN Mask */ 2233 2234 #define EPWM_CTL0_DBGHALT_Pos (30) /*!< EPWM_T::CTL0: DBGHALT Position */ 2235 #define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) /*!< EPWM_T::CTL0: DBGHALT Mask */ 2236 2237 #define EPWM_CTL0_DBGTRIOFF_Pos (31) /*!< EPWM_T::CTL0: DBGTRIOFF Position */ 2238 #define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) /*!< EPWM_T::CTL0: DBGTRIOFF Mask */ 2239 2240 #define EPWM_CTL1_CNTTYPE0_Pos (0) /*!< EPWM_T::CTL1: CNTTYPE0 Position */ 2241 #define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) /*!< EPWM_T::CTL1: CNTTYPE0 Mask */ 2242 2243 #define EPWM_CTL1_CNTTYPE1_Pos (2) /*!< EPWM_T::CTL1: CNTTYPE1 Position */ 2244 #define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) /*!< EPWM_T::CTL1: CNTTYPE1 Mask */ 2245 2246 #define EPWM_CTL1_CNTTYPE2_Pos (4) /*!< EPWM_T::CTL1: CNTTYPE2 Position */ 2247 #define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) /*!< EPWM_T::CTL1: CNTTYPE2 Mask */ 2248 2249 #define EPWM_CTL1_CNTTYPE3_Pos (6) /*!< EPWM_T::CTL1: CNTTYPE3 Position */ 2250 #define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) /*!< EPWM_T::CTL1: CNTTYPE3 Mask */ 2251 2252 #define EPWM_CTL1_CNTTYPE4_Pos (8) /*!< EPWM_T::CTL1: CNTTYPE4 Position */ 2253 #define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) /*!< EPWM_T::CTL1: CNTTYPE4 Mask */ 2254 2255 #define EPWM_CTL1_CNTTYPE5_Pos (10) /*!< EPWM_T::CTL1: CNTTYPE5 Position */ 2256 #define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) /*!< EPWM_T::CTL1: CNTTYPE5 Mask */ 2257 2258 #define EPWM_CTL1_CNTMODE0_Pos (16) /*!< EPWM_T::CTL1: CNTMODE0 Position */ 2259 #define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) /*!< EPWM_T::CTL1: CNTMODE0 Mask */ 2260 2261 #define EPWM_CTL1_CNTMODE1_Pos (17) /*!< EPWM_T::CTL1: CNTMODE1 Position */ 2262 #define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) /*!< EPWM_T::CTL1: CNTMODE1 Mask */ 2263 2264 #define EPWM_CTL1_CNTMODE2_Pos (18) /*!< EPWM_T::CTL1: CNTMODE2 Position */ 2265 #define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) /*!< EPWM_T::CTL1: CNTMODE2 Mask */ 2266 2267 #define EPWM_CTL1_CNTMODE3_Pos (19) /*!< EPWM_T::CTL1: CNTMODE3 Position */ 2268 #define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) /*!< EPWM_T::CTL1: CNTMODE3 Mask */ 2269 2270 #define EPWM_CTL1_CNTMODE4_Pos (20) /*!< EPWM_T::CTL1: CNTMODE4 Position */ 2271 #define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) /*!< EPWM_T::CTL1: CNTMODE4 Mask */ 2272 2273 #define EPWM_CTL1_CNTMODE5_Pos (21) /*!< EPWM_T::CTL1: CNTMODE5 Position */ 2274 #define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) /*!< EPWM_T::CTL1: CNTMODE5 Mask */ 2275 2276 #define EPWM_CTL1_OUTMODE0_Pos (24) /*!< EPWM_T::CTL1: OUTMODE0 Position */ 2277 #define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) /*!< EPWM_T::CTL1: OUTMODE0 Mask */ 2278 2279 #define EPWM_CTL1_OUTMODE2_Pos (25) /*!< EPWM_T::CTL1: OUTMODE2 Position */ 2280 #define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) /*!< EPWM_T::CTL1: OUTMODE2 Mask */ 2281 2282 #define EPWM_CTL1_OUTMODE4_Pos (26) /*!< EPWM_T::CTL1: OUTMODE4 Position */ 2283 #define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) /*!< EPWM_T::CTL1: OUTMODE4 Mask */ 2284 2285 #define EPWM_SYNC_PHSEN0_Pos (0) /*!< EPWM_T::SYNC: PHSEN0 Position */ 2286 #define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) /*!< EPWM_T::SYNC: PHSEN0 Mask */ 2287 2288 #define EPWM_SYNC_PHSEN2_Pos (1) /*!< EPWM_T::SYNC: PHSEN2 Position */ 2289 #define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) /*!< EPWM_T::SYNC: PHSEN2 Mask */ 2290 2291 #define EPWM_SYNC_PHSEN4_Pos (2) /*!< EPWM_T::SYNC: PHSEN4 Position */ 2292 #define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) /*!< EPWM_T::SYNC: PHSEN4 Mask */ 2293 2294 #define EPWM_SYNC_SINSRC0_Pos (8) /*!< EPWM_T::SYNC: SINSRC0 Position */ 2295 #define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) /*!< EPWM_T::SYNC: SINSRC0 Mask */ 2296 2297 #define EPWM_SYNC_SINSRC2_Pos (10) /*!< EPWM_T::SYNC: SINSRC2 Position */ 2298 #define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) /*!< EPWM_T::SYNC: SINSRC2 Mask */ 2299 2300 #define EPWM_SYNC_SINSRC4_Pos (12) /*!< EPWM_T::SYNC: SINSRC4 Position */ 2301 #define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) /*!< EPWM_T::SYNC: SINSRC4 Mask */ 2302 2303 #define EPWM_SYNC_SNFLTEN_Pos (16) /*!< EPWM_T::SYNC: SNFLTEN Position */ 2304 #define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) /*!< EPWM_T::SYNC: SNFLTEN Mask */ 2305 2306 #define EPWM_SYNC_SFLTCSEL_Pos (17) /*!< EPWM_T::SYNC: SFLTCSEL Position */ 2307 #define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) /*!< EPWM_T::SYNC: SFLTCSEL Mask */ 2308 2309 #define EPWM_SYNC_SFLTCNT_Pos (20) /*!< EPWM_T::SYNC: SFLTCNT Position */ 2310 #define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) /*!< EPWM_T::SYNC: SFLTCNT Mask */ 2311 2312 #define EPWM_SYNC_SINPINV_Pos (23) /*!< EPWM_T::SYNC: SINPINV Position */ 2313 #define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) /*!< EPWM_T::SYNC: SINPINV Mask */ 2314 2315 #define EPWM_SYNC_PHSDIR0_Pos (24) /*!< EPWM_T::SYNC: PHSDIR0 Position */ 2316 #define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) /*!< EPWM_T::SYNC: PHSDIR0 Mask */ 2317 2318 #define EPWM_SYNC_PHSDIR2_Pos (25) /*!< EPWM_T::SYNC: PHSDIR2 Position */ 2319 #define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) /*!< EPWM_T::SYNC: PHSDIR2 Mask */ 2320 2321 #define EPWM_SYNC_PHSDIR4_Pos (26) /*!< EPWM_T::SYNC: PHSDIR4 Position */ 2322 #define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) /*!< EPWM_T::SYNC: PHSDIR4 Mask */ 2323 2324 #define EPWM_SWSYNC_SWSYNC0_Pos (0) /*!< EPWM_T::SWSYNC: SWSYNC0 Position */ 2325 #define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) /*!< EPWM_T::SWSYNC: SWSYNC0 Mask */ 2326 2327 #define EPWM_SWSYNC_SWSYNC2_Pos (1) /*!< EPWM_T::SWSYNC: SWSYNC2 Position */ 2328 #define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) /*!< EPWM_T::SWSYNC: SWSYNC2 Mask */ 2329 2330 #define EPWM_SWSYNC_SWSYNC4_Pos (2) /*!< EPWM_T::SWSYNC: SWSYNC4 Position */ 2331 #define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) /*!< EPWM_T::SWSYNC: SWSYNC4 Mask */ 2332 2333 #define EPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< EPWM_T::CLKSRC: ECLKSRC0 Position */ 2334 #define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC0 Mask */ 2335 2336 #define EPWM_CLKSRC_ECLKSRC2_Pos (8) /*!< EPWM_T::CLKSRC: ECLKSRC2 Position */ 2337 #define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC2 Mask */ 2338 2339 #define EPWM_CLKSRC_ECLKSRC4_Pos (16) /*!< EPWM_T::CLKSRC: ECLKSRC4 Position */ 2340 #define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) /*!< EPWM_T::CLKSRC: ECLKSRC4 Mask */ 2341 2342 #define EPWM_CLKPSC0_1_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC0_1: CLKPSC Position */ 2343 #define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) /*!< EPWM_T::CLKPSC0_1: CLKPSC Mask */ 2344 2345 #define EPWM_CLKPSC2_3_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC2_3: CLKPSC Position */ 2346 #define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) /*!< EPWM_T::CLKPSC2_3: CLKPSC Mask */ 2347 2348 #define EPWM_CLKPSC4_5_CLKPSC_Pos (0) /*!< EPWM_T::CLKPSC4_5: CLKPSC Position */ 2349 #define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) /*!< EPWM_T::CLKPSC4_5: CLKPSC Mask */ 2350 2351 #define EPWM_CNTEN_CNTEN0_Pos (0) /*!< EPWM_T::CNTEN: CNTEN0 Position */ 2352 #define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) /*!< EPWM_T::CNTEN: CNTEN0 Mask */ 2353 2354 #define EPWM_CNTEN_CNTEN1_Pos (1) /*!< EPWM_T::CNTEN: CNTEN1 Position */ 2355 #define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) /*!< EPWM_T::CNTEN: CNTEN1 Mask */ 2356 2357 #define EPWM_CNTEN_CNTEN2_Pos (2) /*!< EPWM_T::CNTEN: CNTEN2 Position */ 2358 #define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) /*!< EPWM_T::CNTEN: CNTEN2 Mask */ 2359 2360 #define EPWM_CNTEN_CNTEN3_Pos (3) /*!< EPWM_T::CNTEN: CNTEN3 Position */ 2361 #define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) /*!< EPWM_T::CNTEN: CNTEN3 Mask */ 2362 2363 #define EPWM_CNTEN_CNTEN4_Pos (4) /*!< EPWM_T::CNTEN: CNTEN4 Position */ 2364 #define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) /*!< EPWM_T::CNTEN: CNTEN4 Mask */ 2365 2366 #define EPWM_CNTEN_CNTEN5_Pos (5) /*!< EPWM_T::CNTEN: CNTEN5 Position */ 2367 #define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) /*!< EPWM_T::CNTEN: CNTEN5 Mask */ 2368 2369 #define EPWM_CNTCLR_CNTCLR0_Pos (0) /*!< EPWM_T::CNTCLR: CNTCLR0 Position */ 2370 #define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) /*!< EPWM_T::CNTCLR: CNTCLR0 Mask */ 2371 2372 #define EPWM_CNTCLR_CNTCLR1_Pos (1) /*!< EPWM_T::CNTCLR: CNTCLR1 Position */ 2373 #define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) /*!< EPWM_T::CNTCLR: CNTCLR1 Mask */ 2374 2375 #define EPWM_CNTCLR_CNTCLR2_Pos (2) /*!< EPWM_T::CNTCLR: CNTCLR2 Position */ 2376 #define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) /*!< EPWM_T::CNTCLR: CNTCLR2 Mask */ 2377 2378 #define EPWM_CNTCLR_CNTCLR3_Pos (3) /*!< EPWM_T::CNTCLR: CNTCLR3 Position */ 2379 #define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) /*!< EPWM_T::CNTCLR: CNTCLR3 Mask */ 2380 2381 #define EPWM_CNTCLR_CNTCLR4_Pos (4) /*!< EPWM_T::CNTCLR: CNTCLR4 Position */ 2382 #define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) /*!< EPWM_T::CNTCLR: CNTCLR4 Mask */ 2383 2384 #define EPWM_CNTCLR_CNTCLR5_Pos (5) /*!< EPWM_T::CNTCLR: CNTCLR5 Position */ 2385 #define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) /*!< EPWM_T::CNTCLR: CNTCLR5 Mask */ 2386 2387 #define EPWM_LOAD_LOAD0_Pos (0) /*!< EPWM_T::LOAD: LOAD0 Position */ 2388 #define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) /*!< EPWM_T::LOAD: LOAD0 Mask */ 2389 2390 #define EPWM_LOAD_LOAD1_Pos (1) /*!< EPWM_T::LOAD: LOAD1 Position */ 2391 #define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) /*!< EPWM_T::LOAD: LOAD1 Mask */ 2392 2393 #define EPWM_LOAD_LOAD2_Pos (2) /*!< EPWM_T::LOAD: LOAD2 Position */ 2394 #define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) /*!< EPWM_T::LOAD: LOAD2 Mask */ 2395 2396 #define EPWM_LOAD_LOAD3_Pos (3) /*!< EPWM_T::LOAD: LOAD3 Position */ 2397 #define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) /*!< EPWM_T::LOAD: LOAD3 Mask */ 2398 2399 #define EPWM_LOAD_LOAD4_Pos (4) /*!< EPWM_T::LOAD: LOAD4 Position */ 2400 #define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) /*!< EPWM_T::LOAD: LOAD4 Mask */ 2401 2402 #define EPWM_LOAD_LOAD5_Pos (5) /*!< EPWM_T::LOAD: LOAD5 Position */ 2403 #define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) /*!< EPWM_T::LOAD: LOAD5 Mask */ 2404 2405 #define EPWM_PERIOD0_PERIOD_Pos (0) /*!< EPWM_T::PERIOD0: PERIOD Position */ 2406 #define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) /*!< EPWM_T::PERIOD0: PERIOD Mask */ 2407 2408 #define EPWM_PERIOD1_PERIOD_Pos (0) /*!< EPWM_T::PERIOD1: PERIOD Position */ 2409 #define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) /*!< EPWM_T::PERIOD1: PERIOD Mask */ 2410 2411 #define EPWM_PERIOD2_PERIOD_Pos (0) /*!< EPWM_T::PERIOD2: PERIOD Position */ 2412 #define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) /*!< EPWM_T::PERIOD2: PERIOD Mask */ 2413 2414 #define EPWM_PERIOD3_PERIOD_Pos (0) /*!< EPWM_T::PERIOD3: PERIOD Position */ 2415 #define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) /*!< EPWM_T::PERIOD3: PERIOD Mask */ 2416 2417 #define EPWM_PERIOD4_PERIOD_Pos (0) /*!< EPWM_T::PERIOD4: PERIOD Position */ 2418 #define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) /*!< EPWM_T::PERIOD4: PERIOD Mask */ 2419 2420 #define EPWM_PERIOD5_PERIOD_Pos (0) /*!< EPWM_T::PERIOD5: PERIOD Position */ 2421 #define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) /*!< EPWM_T::PERIOD5: PERIOD Mask */ 2422 2423 #define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM_T::CMPDAT0: CMP Position */ 2424 #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM_T::CMPDAT0: CMP Mask */ 2425 2426 #define EPWM_CMPDAT1_CMP_Pos (0) /*!< EPWM_T::CMPDAT1: CMP Position */ 2427 #define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) /*!< EPWM_T::CMPDAT1: CMP Mask */ 2428 2429 #define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM_T::CMPDAT2: CMP Position */ 2430 #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM_T::CMPDAT2: CMP Mask */ 2431 2432 #define EPWM_CMPDAT3_CMP_Pos (0) /*!< EPWM_T::CMPDAT3: CMP Position */ 2433 #define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) /*!< EPWM_T::CMPDAT3: CMP Mask */ 2434 2435 #define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM_T::CMPDAT4: CMP Position */ 2436 #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM_T::CMPDAT4: CMP Mask */ 2437 2438 #define EPWM_CMPDAT5_CMP_Pos (0) /*!< EPWM_T::CMPDAT5: CMP Position */ 2439 #define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) /*!< EPWM_T::CMPDAT5: CMP Mask */ 2440 2441 #define EPWM_DTCTL0_1_DTCNT_Pos (0) /*!< EPWM_T::DTCTL0_1: DTCNT Position */ 2442 #define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) /*!< EPWM_T::DTCTL0_1: DTCNT Mask */ 2443 2444 #define EPWM_DTCTL0_1_DTEN_Pos (16) /*!< EPWM_T::DTCTL0_1: DTEN Position */ 2445 #define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) /*!< EPWM_T::DTCTL0_1: DTEN Mask */ 2446 2447 #define EPWM_DTCTL0_1_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL0_1: DTCKSEL Position */ 2448 #define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) /*!< EPWM_T::DTCTL0_1: DTCKSEL Mask */ 2449 2450 #define EPWM_DTCTL2_3_DTCNT_Pos (0) /*!< EPWM_T::DTCTL2_3: DTCNT Position */ 2451 #define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) /*!< EPWM_T::DTCTL2_3: DTCNT Mask */ 2452 2453 #define EPWM_DTCTL2_3_DTEN_Pos (16) /*!< EPWM_T::DTCTL2_3: DTEN Position */ 2454 #define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) /*!< EPWM_T::DTCTL2_3: DTEN Mask */ 2455 2456 #define EPWM_DTCTL2_3_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL2_3: DTCKSEL Position */ 2457 #define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) /*!< EPWM_T::DTCTL2_3: DTCKSEL Mask */ 2458 2459 #define EPWM_DTCTL4_5_DTCNT_Pos (0) /*!< EPWM_T::DTCTL4_5: DTCNT Position */ 2460 #define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) /*!< EPWM_T::DTCTL4_5: DTCNT Mask */ 2461 2462 #define EPWM_DTCTL4_5_DTEN_Pos (16) /*!< EPWM_T::DTCTL4_5: DTEN Position */ 2463 #define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) /*!< EPWM_T::DTCTL4_5: DTEN Mask */ 2464 2465 #define EPWM_DTCTL4_5_DTCKSEL_Pos (24) /*!< EPWM_T::DTCTL4_5: DTCKSEL Position */ 2466 #define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) /*!< EPWM_T::DTCTL4_5: DTCKSEL Mask */ 2467 2468 #define EPWM_PHS0_1_PHS_Pos (0) /*!< EPWM_T::PHS0_1: PHS Position */ 2469 #define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) /*!< EPWM_T::PHS0_1: PHS Mask */ 2470 2471 #define EPWM_PHS2_3_PHS_Pos (0) /*!< EPWM_T::PHS2_3: PHS Position */ 2472 #define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) /*!< EPWM_T::PHS2_3: PHS Mask */ 2473 2474 #define EPWM_PHS4_5_PHS_Pos (0) /*!< EPWM_T::PHS4_5: PHS Position */ 2475 #define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) /*!< EPWM_T::PHS4_5: PHS Mask */ 2476 2477 #define EPWM_CNT0_CNT_Pos (0) /*!< EPWM_T::CNT0: CNT Position */ 2478 #define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) /*!< EPWM_T::CNT0: CNT Mask */ 2479 2480 #define EPWM_CNT0_DIRF_Pos (16) /*!< EPWM_T::CNT0: DIRF Position */ 2481 #define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) /*!< EPWM_T::CNT0: DIRF Mask */ 2482 2483 #define EPWM_CNT1_CNT_Pos (0) /*!< EPWM_T::CNT1: CNT Position */ 2484 #define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) /*!< EPWM_T::CNT1: CNT Mask */ 2485 2486 #define EPWM_CNT1_DIRF_Pos (16) /*!< EPWM_T::CNT1: DIRF Position */ 2487 #define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) /*!< EPWM_T::CNT1: DIRF Mask */ 2488 2489 #define EPWM_CNT2_CNT_Pos (0) /*!< EPWM_T::CNT2: CNT Position */ 2490 #define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) /*!< EPWM_T::CNT2: CNT Mask */ 2491 2492 #define EPWM_CNT2_DIRF_Pos (16) /*!< EPWM_T::CNT2: DIRF Position */ 2493 #define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) /*!< EPWM_T::CNT2: DIRF Mask */ 2494 2495 #define EPWM_CNT3_CNT_Pos (0) /*!< EPWM_T::CNT3: CNT Position */ 2496 #define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) /*!< EPWM_T::CNT3: CNT Mask */ 2497 2498 #define EPWM_CNT3_DIRF_Pos (16) /*!< EPWM_T::CNT3: DIRF Position */ 2499 #define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) /*!< EPWM_T::CNT3: DIRF Mask */ 2500 2501 #define EPWM_CNT4_CNT_Pos (0) /*!< EPWM_T::CNT4: CNT Position */ 2502 #define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) /*!< EPWM_T::CNT4: CNT Mask */ 2503 2504 #define EPWM_CNT4_DIRF_Pos (16) /*!< EPWM_T::CNT4: DIRF Position */ 2505 #define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) /*!< EPWM_T::CNT4: DIRF Mask */ 2506 2507 #define EPWM_CNT5_CNT_Pos (0) /*!< EPWM_T::CNT5: CNT Position */ 2508 #define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) /*!< EPWM_T::CNT5: CNT Mask */ 2509 2510 #define EPWM_CNT5_DIRF_Pos (16) /*!< EPWM_T::CNT5: DIRF Position */ 2511 #define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) /*!< EPWM_T::CNT5: DIRF Mask */ 2512 2513 #define EPWM_WGCTL0_ZPCTL0_Pos (0) /*!< EPWM_T::WGCTL0: ZPCTL0 Position */ 2514 #define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) /*!< EPWM_T::WGCTL0: ZPCTL0 Mask */ 2515 2516 #define EPWM_WGCTL0_ZPCTL1_Pos (2) /*!< EPWM_T::WGCTL0: ZPCTL1 Position */ 2517 #define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) /*!< EPWM_T::WGCTL0: ZPCTL1 Mask */ 2518 2519 #define EPWM_WGCTL0_ZPCTL2_Pos (4) /*!< EPWM_T::WGCTL0: ZPCTL2 Position */ 2520 #define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) /*!< EPWM_T::WGCTL0: ZPCTL2 Mask */ 2521 2522 #define EPWM_WGCTL0_ZPCTL3_Pos (6) /*!< EPWM_T::WGCTL0: ZPCTL3 Position */ 2523 #define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) /*!< EPWM_T::WGCTL0: ZPCTL3 Mask */ 2524 2525 #define EPWM_WGCTL0_ZPCTL4_Pos (8) /*!< EPWM_T::WGCTL0: ZPCTL4 Position */ 2526 #define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) /*!< EPWM_T::WGCTL0: ZPCTL4 Mask */ 2527 2528 #define EPWM_WGCTL0_ZPCTL5_Pos (10) /*!< EPWM_T::WGCTL0: ZPCTL5 Position */ 2529 #define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) /*!< EPWM_T::WGCTL0: ZPCTL5 Mask */ 2530 2531 #define EPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< EPWM_T::WGCTL0: PRDPCTL0 Position */ 2532 #define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL0 Mask */ 2533 2534 #define EPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< EPWM_T::WGCTL0: PRDPCTL1 Position */ 2535 #define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL1 Mask */ 2536 2537 #define EPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< EPWM_T::WGCTL0: PRDPCTL2 Position */ 2538 #define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL2 Mask */ 2539 2540 #define EPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< EPWM_T::WGCTL0: PRDPCTL3 Position */ 2541 #define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL3 Mask */ 2542 2543 #define EPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< EPWM_T::WGCTL0: PRDPCTL4 Position */ 2544 #define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL4 Mask */ 2545 2546 #define EPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< EPWM_T::WGCTL0: PRDPCTL5 Position */ 2547 #define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) /*!< EPWM_T::WGCTL0: PRDPCTL5 Mask */ 2548 2549 #define EPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< EPWM_T::WGCTL1: CMPUCTL0 Position */ 2550 #define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL0 Mask */ 2551 2552 #define EPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< EPWM_T::WGCTL1: CMPUCTL1 Position */ 2553 #define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL1 Mask */ 2554 2555 #define EPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< EPWM_T::WGCTL1: CMPUCTL2 Position */ 2556 #define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL2 Mask */ 2557 2558 #define EPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< EPWM_T::WGCTL1: CMPUCTL3 Position */ 2559 #define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL3 Mask */ 2560 2561 #define EPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< EPWM_T::WGCTL1: CMPUCTL4 Position */ 2562 #define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL4 Mask */ 2563 2564 #define EPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< EPWM_T::WGCTL1: CMPUCTL5 Position */ 2565 #define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPUCTL5 Mask */ 2566 2567 #define EPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< EPWM_T::WGCTL1: CMPDCTL0 Position */ 2568 #define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL0 Mask */ 2569 2570 #define EPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< EPWM_T::WGCTL1: CMPDCTL1 Position */ 2571 #define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL1 Mask */ 2572 2573 #define EPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< EPWM_T::WGCTL1: CMPDCTL2 Position */ 2574 #define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL2 Mask */ 2575 2576 #define EPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< EPWM_T::WGCTL1: CMPDCTL3 Position */ 2577 #define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL3 Mask */ 2578 2579 #define EPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< EPWM_T::WGCTL1: CMPDCTL4 Position */ 2580 #define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL4 Mask */ 2581 2582 #define EPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< EPWM_T::WGCTL1: CMPDCTL5 Position */ 2583 #define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) /*!< EPWM_T::WGCTL1: CMPDCTL5 Mask */ 2584 2585 #define EPWM_MSKEN_MSKEN0_Pos (0) /*!< EPWM_T::MSKEN: MSKEN0 Position */ 2586 #define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) /*!< EPWM_T::MSKEN: MSKEN0 Mask */ 2587 2588 #define EPWM_MSKEN_MSKEN1_Pos (1) /*!< EPWM_T::MSKEN: MSKEN1 Position */ 2589 #define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) /*!< EPWM_T::MSKEN: MSKEN1 Mask */ 2590 2591 #define EPWM_MSKEN_MSKEN2_Pos (2) /*!< EPWM_T::MSKEN: MSKEN2 Position */ 2592 #define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) /*!< EPWM_T::MSKEN: MSKEN2 Mask */ 2593 2594 #define EPWM_MSKEN_MSKEN3_Pos (3) /*!< EPWM_T::MSKEN: MSKEN3 Position */ 2595 #define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) /*!< EPWM_T::MSKEN: MSKEN3 Mask */ 2596 2597 #define EPWM_MSKEN_MSKEN4_Pos (4) /*!< EPWM_T::MSKEN: MSKEN4 Position */ 2598 #define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) /*!< EPWM_T::MSKEN: MSKEN4 Mask */ 2599 2600 #define EPWM_MSKEN_MSKEN5_Pos (5) /*!< EPWM_T::MSKEN: MSKEN5 Position */ 2601 #define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) /*!< EPWM_T::MSKEN: MSKEN5 Mask */ 2602 2603 #define EPWM_MSK_MSKDAT0_Pos (0) /*!< EPWM_T::MSK: MSKDAT0 Position */ 2604 #define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) /*!< EPWM_T::MSK: MSKDAT0 Mask */ 2605 2606 #define EPWM_MSK_MSKDAT1_Pos (1) /*!< EPWM_T::MSK: MSKDAT1 Position */ 2607 #define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) /*!< EPWM_T::MSK: MSKDAT1 Mask */ 2608 2609 #define EPWM_MSK_MSKDAT2_Pos (2) /*!< EPWM_T::MSK: MSKDAT2 Position */ 2610 #define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) /*!< EPWM_T::MSK: MSKDAT2 Mask */ 2611 2612 #define EPWM_MSK_MSKDAT3_Pos (3) /*!< EPWM_T::MSK: MSKDAT3 Position */ 2613 #define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) /*!< EPWM_T::MSK: MSKDAT3 Mask */ 2614 2615 #define EPWM_MSK_MSKDAT4_Pos (4) /*!< EPWM_T::MSK: MSKDAT4 Position */ 2616 #define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) /*!< EPWM_T::MSK: MSKDAT4 Mask */ 2617 2618 #define EPWM_MSK_MSKDAT5_Pos (5) /*!< EPWM_T::MSK: MSKDAT5 Position */ 2619 #define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) /*!< EPWM_T::MSK: MSKDAT5 Mask */ 2620 2621 #define EPWM_BNF_BRK0NFEN_Pos (0) /*!< EPWM_T::BNF: BRK0NFEN Position */ 2622 #define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) /*!< EPWM_T::BNF: BRK0NFEN Mask */ 2623 2624 #define EPWM_BNF_BRK0NFSEL_Pos (1) /*!< EPWM_T::BNF: BRK0NFSEL Position */ 2625 #define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) /*!< EPWM_T::BNF: BRK0NFSEL Mask */ 2626 2627 #define EPWM_BNF_BRK0FCNT_Pos (4) /*!< EPWM_T::BNF: BRK0FCNT Position */ 2628 #define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) /*!< EPWM_T::BNF: BRK0FCNT Mask */ 2629 2630 #define EPWM_BNF_BRK0PINV_Pos (7) /*!< EPWM_T::BNF: BRK0PINV Position */ 2631 #define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) /*!< EPWM_T::BNF: BRK0PINV Mask */ 2632 2633 #define EPWM_BNF_BRK1NFEN_Pos (8) /*!< EPWM_T::BNF: BRK1NFEN Position */ 2634 #define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) /*!< EPWM_T::BNF: BRK1NFEN Mask */ 2635 2636 #define EPWM_BNF_BRK1NFSEL_Pos (9) /*!< EPWM_T::BNF: BRK1NFSEL Position */ 2637 #define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) /*!< EPWM_T::BNF: BRK1NFSEL Mask */ 2638 2639 #define EPWM_BNF_BRK1FCNT_Pos (12) /*!< EPWM_T::BNF: BRK1FCNT Position */ 2640 #define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) /*!< EPWM_T::BNF: BRK1FCNT Mask */ 2641 2642 #define EPWM_BNF_BRK1PINV_Pos (15) /*!< EPWM_T::BNF: BRK1PINV Position */ 2643 #define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) /*!< EPWM_T::BNF: BRK1PINV Mask */ 2644 2645 #define EPWM_BNF_BK0SRC_Pos (16) /*!< EPWM_T::BNF: BK0SRC Position */ 2646 #define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) /*!< EPWM_T::BNF: BK0SRC Mask */ 2647 2648 #define EPWM_BNF_BK1SRC_Pos (24) /*!< EPWM_T::BNF: BK1SRC Position */ 2649 #define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) /*!< EPWM_T::BNF: BK1SRC Mask */ 2650 2651 #define EPWM_FAILBRK_CSSBRKEN_Pos (0) /*!< EPWM_T::FAILBRK: CSSBRKEN Position */ 2652 #define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) /*!< EPWM_T::FAILBRK: CSSBRKEN Mask */ 2653 2654 #define EPWM_FAILBRK_BODBRKEN_Pos (1) /*!< EPWM_T::FAILBRK: BODBRKEN Position */ 2655 #define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) /*!< EPWM_T::FAILBRK: BODBRKEN Mask */ 2656 2657 #define EPWM_FAILBRK_RAMBRKEN_Pos (2) /*!< EPWM_T::FAILBRK: RAMBRKEN Position */ 2658 #define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) /*!< EPWM_T::FAILBRK: RAMBRKEN Mask */ 2659 2660 #define EPWM_FAILBRK_CORBRKEN_Pos (3) /*!< EPWM_T::FAILBRK: CORBRKEN Position */ 2661 #define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) /*!< EPWM_T::FAILBRK: CORBRKEN Mask */ 2662 2663 #define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Position */ 2664 #define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0EBEN Mask */ 2665 2666 #define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Position */ 2667 #define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1EBEN Mask */ 2668 2669 #define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Position */ 2670 #define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0EEN Mask */ 2671 2672 #define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Position */ 2673 #define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1EEN Mask */ 2674 2675 #define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Position */ 2676 #define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSEBEN Mask */ 2677 2678 #define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Position */ 2679 #define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO0LBEN Mask */ 2680 2681 #define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Position */ 2682 #define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL0_1: CPO1LBEN Mask */ 2683 2684 #define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Position */ 2685 #define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP0LEN Mask */ 2686 2687 #define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Position */ 2688 #define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKP1LEN Mask */ 2689 2690 #define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Position */ 2691 #define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: SYSLBEN Mask */ 2692 2693 #define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Position */ 2694 #define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAEVEN Mask */ 2695 2696 #define EPWM_BRKCTL0_1_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL0_1: BRKAODD Position */ 2697 #define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) /*!< EPWM_T::BRKCTL0_1: BRKAODD Mask */ 2698 2699 #define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Position */ 2700 #define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCEBEN Mask */ 2701 2702 #define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Position */ 2703 #define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL0_1: EADCLBEN Mask */ 2704 2705 #define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Position */ 2706 #define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0EBEN Mask */ 2707 2708 #define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Position */ 2709 #define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1EBEN Mask */ 2710 2711 #define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Position */ 2712 #define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0EEN Mask */ 2713 2714 #define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Position */ 2715 #define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1EEN Mask */ 2716 2717 #define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Position */ 2718 #define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSEBEN Mask */ 2719 2720 #define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Position */ 2721 #define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO0LBEN Mask */ 2722 2723 #define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Position */ 2724 #define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL2_3: CPO1LBEN Mask */ 2725 2726 #define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Position */ 2727 #define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP0LEN Mask */ 2728 2729 #define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Position */ 2730 #define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKP1LEN Mask */ 2731 2732 #define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Position */ 2733 #define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: SYSLBEN Mask */ 2734 2735 #define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Position */ 2736 #define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAEVEN Mask */ 2737 2738 #define EPWM_BRKCTL2_3_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL2_3: BRKAODD Position */ 2739 #define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) /*!< EPWM_T::BRKCTL2_3: BRKAODD Mask */ 2740 2741 #define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Position */ 2742 #define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCEBEN Mask */ 2743 2744 #define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Position */ 2745 #define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL2_3: EADCLBEN Mask */ 2746 2747 #define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Position */ 2748 #define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0EBEN Mask */ 2749 2750 #define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Position */ 2751 #define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1EBEN Mask */ 2752 2753 #define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Position */ 2754 #define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0EEN Mask */ 2755 2756 #define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Position */ 2757 #define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1EEN Mask */ 2758 2759 #define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Position */ 2760 #define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSEBEN Mask */ 2761 2762 #define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Position */ 2763 #define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO0LBEN Mask */ 2764 2765 #define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Position */ 2766 #define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) /*!< EPWM_T::BRKCTL4_5: CPO1LBEN Mask */ 2767 2768 #define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Position */ 2769 #define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP0LEN Mask */ 2770 2771 #define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Position */ 2772 #define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKP1LEN Mask */ 2773 2774 #define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Position */ 2775 #define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: SYSLBEN Mask */ 2776 2777 #define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Position */ 2778 #define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAEVEN Mask */ 2779 2780 #define EPWM_BRKCTL4_5_BRKAODD_Pos (18) /*!< EPWM_T::BRKCTL4_5: BRKAODD Position */ 2781 #define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) /*!< EPWM_T::BRKCTL4_5: BRKAODD Mask */ 2782 2783 #define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Position */ 2784 #define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCEBEN Mask */ 2785 2786 #define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Position */ 2787 #define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) /*!< EPWM_T::BRKCTL4_5: EADCLBEN Mask */ 2788 2789 #define EPWM_POLCTL_PINV0_Pos (0) /*!< EPWM_T::POLCTL: PINV0 Position */ 2790 #define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) /*!< EPWM_T::POLCTL: PINV0 Mask */ 2791 2792 #define EPWM_POLCTL_PINV1_Pos (1) /*!< EPWM_T::POLCTL: PINV1 Position */ 2793 #define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) /*!< EPWM_T::POLCTL: PINV1 Mask */ 2794 2795 #define EPWM_POLCTL_PINV2_Pos (2) /*!< EPWM_T::POLCTL: PINV2 Position */ 2796 #define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) /*!< EPWM_T::POLCTL: PINV2 Mask */ 2797 2798 #define EPWM_POLCTL_PINV3_Pos (3) /*!< EPWM_T::POLCTL: PINV3 Position */ 2799 #define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) /*!< EPWM_T::POLCTL: PINV3 Mask */ 2800 2801 #define EPWM_POLCTL_PINV4_Pos (4) /*!< EPWM_T::POLCTL: PINV4 Position */ 2802 #define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) /*!< EPWM_T::POLCTL: PINV4 Mask */ 2803 2804 #define EPWM_POLCTL_PINV5_Pos (5) /*!< EPWM_T::POLCTL: PINV5 Position */ 2805 #define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) /*!< EPWM_T::POLCTL: PINV5 Mask */ 2806 2807 #define EPWM_POEN_POEN0_Pos (0) /*!< EPWM_T::POEN: POEN0 Position */ 2808 #define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) /*!< EPWM_T::POEN: POEN0 Mask */ 2809 2810 #define EPWM_POEN_POEN1_Pos (1) /*!< EPWM_T::POEN: POEN1 Position */ 2811 #define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) /*!< EPWM_T::POEN: POEN1 Mask */ 2812 2813 #define EPWM_POEN_POEN2_Pos (2) /*!< EPWM_T::POEN: POEN2 Position */ 2814 #define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) /*!< EPWM_T::POEN: POEN2 Mask */ 2815 2816 #define EPWM_POEN_POEN3_Pos (3) /*!< EPWM_T::POEN: POEN3 Position */ 2817 #define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) /*!< EPWM_T::POEN: POEN3 Mask */ 2818 2819 #define EPWM_POEN_POEN4_Pos (4) /*!< EPWM_T::POEN: POEN4 Position */ 2820 #define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) /*!< EPWM_T::POEN: POEN4 Mask */ 2821 2822 #define EPWM_POEN_POEN5_Pos (5) /*!< EPWM_T::POEN: POEN5 Position */ 2823 #define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) /*!< EPWM_T::POEN: POEN5 Mask */ 2824 2825 #define EPWM_SWBRK_BRKETRG0_Pos (0) /*!< EPWM_T::SWBRK: BRKETRG0 Position */ 2826 #define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) /*!< EPWM_T::SWBRK: BRKETRG0 Mask */ 2827 2828 #define EPWM_SWBRK_BRKETRG2_Pos (1) /*!< EPWM_T::SWBRK: BRKETRG2 Position */ 2829 #define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) /*!< EPWM_T::SWBRK: BRKETRG2 Mask */ 2830 2831 #define EPWM_SWBRK_BRKETRG4_Pos (2) /*!< EPWM_T::SWBRK: BRKETRG4 Position */ 2832 #define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) /*!< EPWM_T::SWBRK: BRKETRG4 Mask */ 2833 2834 #define EPWM_SWBRK_BRKLTRG0_Pos (8) /*!< EPWM_T::SWBRK: BRKLTRG0 Position */ 2835 #define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) /*!< EPWM_T::SWBRK: BRKLTRG0 Mask */ 2836 2837 #define EPWM_SWBRK_BRKLTRG2_Pos (9) /*!< EPWM_T::SWBRK: BRKLTRG2 Position */ 2838 #define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) /*!< EPWM_T::SWBRK: BRKLTRG2 Mask */ 2839 2840 #define EPWM_SWBRK_BRKLTRG4_Pos (10) /*!< EPWM_T::SWBRK: BRKLTRG4 Position */ 2841 #define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) /*!< EPWM_T::SWBRK: BRKLTRG4 Mask */ 2842 2843 #define EPWM_INTEN0_ZIEN0_Pos (0) /*!< EPWM_T::INTEN0: ZIEN0 Position */ 2844 #define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) /*!< EPWM_T::INTEN0: ZIEN0 Mask */ 2845 2846 #define EPWM_INTEN0_ZIEN1_Pos (1) /*!< EPWM_T::INTEN0: ZIEN1 Position */ 2847 #define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) /*!< EPWM_T::INTEN0: ZIEN1 Mask */ 2848 2849 #define EPWM_INTEN0_ZIEN2_Pos (2) /*!< EPWM_T::INTEN0: ZIEN2 Position */ 2850 #define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) /*!< EPWM_T::INTEN0: ZIEN2 Mask */ 2851 2852 #define EPWM_INTEN0_ZIEN3_Pos (3) /*!< EPWM_T::INTEN0: ZIEN3 Position */ 2853 #define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) /*!< EPWM_T::INTEN0: ZIEN3 Mask */ 2854 2855 #define EPWM_INTEN0_ZIEN4_Pos (4) /*!< EPWM_T::INTEN0: ZIEN4 Position */ 2856 #define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) /*!< EPWM_T::INTEN0: ZIEN4 Mask */ 2857 2858 #define EPWM_INTEN0_ZIEN5_Pos (5) /*!< EPWM_T::INTEN0: ZIEN5 Position */ 2859 #define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) /*!< EPWM_T::INTEN0: ZIEN5 Mask */ 2860 2861 #define EPWM_INTEN0_PIEN0_Pos (8) /*!< EPWM_T::INTEN0: PIEN0 Position */ 2862 #define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) /*!< EPWM_T::INTEN0: PIEN0 Mask */ 2863 2864 #define EPWM_INTEN0_PIEN1_Pos (9) /*!< EPWM_T::INTEN0: PIEN1 Position */ 2865 #define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) /*!< EPWM_T::INTEN0: PIEN1 Mask */ 2866 2867 #define EPWM_INTEN0_PIEN2_Pos (10) /*!< EPWM_T::INTEN0: PIEN2 Position */ 2868 #define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) /*!< EPWM_T::INTEN0: PIEN2 Mask */ 2869 2870 #define EPWM_INTEN0_PIEN3_Pos (11) /*!< EPWM_T::INTEN0: PIEN3 Position */ 2871 #define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) /*!< EPWM_T::INTEN0: PIEN3 Mask */ 2872 2873 #define EPWM_INTEN0_PIEN4_Pos (12) /*!< EPWM_T::INTEN0: PIEN4 Position */ 2874 #define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) /*!< EPWM_T::INTEN0: PIEN4 Mask */ 2875 2876 #define EPWM_INTEN0_PIEN5_Pos (13) /*!< EPWM_T::INTEN0: PIEN5 Position */ 2877 #define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) /*!< EPWM_T::INTEN0: PIEN5 Mask */ 2878 2879 #define EPWM_INTEN0_CMPUIEN0_Pos (16) /*!< EPWM_T::INTEN0: CMPUIEN0 Position */ 2880 #define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) /*!< EPWM_T::INTEN0: CMPUIEN0 Mask */ 2881 2882 #define EPWM_INTEN0_CMPUIEN1_Pos (17) /*!< EPWM_T::INTEN0: CMPUIEN1 Position */ 2883 #define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) /*!< EPWM_T::INTEN0: CMPUIEN1 Mask */ 2884 2885 #define EPWM_INTEN0_CMPUIEN2_Pos (18) /*!< EPWM_T::INTEN0: CMPUIEN2 Position */ 2886 #define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) /*!< EPWM_T::INTEN0: CMPUIEN2 Mask */ 2887 2888 #define EPWM_INTEN0_CMPUIEN3_Pos (19) /*!< EPWM_T::INTEN0: CMPUIEN3 Position */ 2889 #define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) /*!< EPWM_T::INTEN0: CMPUIEN3 Mask */ 2890 2891 #define EPWM_INTEN0_CMPUIEN4_Pos (20) /*!< EPWM_T::INTEN0: CMPUIEN4 Position */ 2892 #define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) /*!< EPWM_T::INTEN0: CMPUIEN4 Mask */ 2893 2894 #define EPWM_INTEN0_CMPUIEN5_Pos (21) /*!< EPWM_T::INTEN0: CMPUIEN5 Position */ 2895 #define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) /*!< EPWM_T::INTEN0: CMPUIEN5 Mask */ 2896 2897 #define EPWM_INTEN0_CMPDIEN0_Pos (24) /*!< EPWM_T::INTEN0: CMPDIEN0 Position */ 2898 #define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) /*!< EPWM_T::INTEN0: CMPDIEN0 Mask */ 2899 2900 #define EPWM_INTEN0_CMPDIEN1_Pos (25) /*!< EPWM_T::INTEN0: CMPDIEN1 Position */ 2901 #define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) /*!< EPWM_T::INTEN0: CMPDIEN1 Mask */ 2902 2903 #define EPWM_INTEN0_CMPDIEN2_Pos (26) /*!< EPWM_T::INTEN0: CMPDIEN2 Position */ 2904 #define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) /*!< EPWM_T::INTEN0: CMPDIEN2 Mask */ 2905 2906 #define EPWM_INTEN0_CMPDIEN3_Pos (27) /*!< EPWM_T::INTEN0: CMPDIEN3 Position */ 2907 #define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) /*!< EPWM_T::INTEN0: CMPDIEN3 Mask */ 2908 2909 #define EPWM_INTEN0_CMPDIEN4_Pos (28) /*!< EPWM_T::INTEN0: CMPDIEN4 Position */ 2910 #define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) /*!< EPWM_T::INTEN0: CMPDIEN4 Mask */ 2911 2912 #define EPWM_INTEN0_CMPDIEN5_Pos (29) /*!< EPWM_T::INTEN0: CMPDIEN5 Position */ 2913 #define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) /*!< EPWM_T::INTEN0: CMPDIEN5 Mask */ 2914 2915 #define EPWM_INTEN1_BRKEIEN0_1_Pos (0) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Position */ 2916 #define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKEIEN0_1 Mask */ 2917 2918 #define EPWM_INTEN1_BRKEIEN2_3_Pos (1) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Position */ 2919 #define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKEIEN2_3 Mask */ 2920 2921 #define EPWM_INTEN1_BRKEIEN4_5_Pos (2) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Position */ 2922 #define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKEIEN4_5 Mask */ 2923 2924 #define EPWM_INTEN1_BRKLIEN0_1_Pos (8) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Position */ 2925 #define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) /*!< EPWM_T::INTEN1: BRKLIEN0_1 Mask */ 2926 2927 #define EPWM_INTEN1_BRKLIEN2_3_Pos (9) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Position */ 2928 #define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) /*!< EPWM_T::INTEN1: BRKLIEN2_3 Mask */ 2929 2930 #define EPWM_INTEN1_BRKLIEN4_5_Pos (10) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Position */ 2931 #define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) /*!< EPWM_T::INTEN1: BRKLIEN4_5 Mask */ 2932 2933 #define EPWM_INTSTS0_ZIF0_Pos (0) /*!< EPWM_T::INTSTS0: ZIF0 Position */ 2934 #define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) /*!< EPWM_T::INTSTS0: ZIF0 Mask */ 2935 2936 #define EPWM_INTSTS0_ZIF1_Pos (1) /*!< EPWM_T::INTSTS0: ZIF1 Position */ 2937 #define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) /*!< EPWM_T::INTSTS0: ZIF1 Mask */ 2938 2939 #define EPWM_INTSTS0_ZIF2_Pos (2) /*!< EPWM_T::INTSTS0: ZIF2 Position */ 2940 #define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) /*!< EPWM_T::INTSTS0: ZIF2 Mask */ 2941 2942 #define EPWM_INTSTS0_ZIF3_Pos (3) /*!< EPWM_T::INTSTS0: ZIF3 Position */ 2943 #define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) /*!< EPWM_T::INTSTS0: ZIF3 Mask */ 2944 2945 #define EPWM_INTSTS0_ZIF4_Pos (4) /*!< EPWM_T::INTSTS0: ZIF4 Position */ 2946 #define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) /*!< EPWM_T::INTSTS0: ZIF4 Mask */ 2947 2948 #define EPWM_INTSTS0_ZIF5_Pos (5) /*!< EPWM_T::INTSTS0: ZIF5 Position */ 2949 #define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) /*!< EPWM_T::INTSTS0: ZIF5 Mask */ 2950 2951 #define EPWM_INTSTS0_PIF0_Pos (8) /*!< EPWM_T::INTSTS0: PIF0 Position */ 2952 #define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) /*!< EPWM_T::INTSTS0: PIF0 Mask */ 2953 2954 #define EPWM_INTSTS0_PIF1_Pos (9) /*!< EPWM_T::INTSTS0: PIF1 Position */ 2955 #define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) /*!< EPWM_T::INTSTS0: PIF1 Mask */ 2956 2957 #define EPWM_INTSTS0_PIF2_Pos (10) /*!< EPWM_T::INTSTS0: PIF2 Position */ 2958 #define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) /*!< EPWM_T::INTSTS0: PIF2 Mask */ 2959 2960 #define EPWM_INTSTS0_PIF3_Pos (11) /*!< EPWM_T::INTSTS0: PIF3 Position */ 2961 #define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) /*!< EPWM_T::INTSTS0: PIF3 Mask */ 2962 2963 #define EPWM_INTSTS0_PIF4_Pos (12) /*!< EPWM_T::INTSTS0: PIF4 Position */ 2964 #define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) /*!< EPWM_T::INTSTS0: PIF4 Mask */ 2965 2966 #define EPWM_INTSTS0_PIF5_Pos (13) /*!< EPWM_T::INTSTS0: PIF5 Position */ 2967 #define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) /*!< EPWM_T::INTSTS0: PIF5 Mask */ 2968 2969 #define EPWM_INTSTS0_CMPUIF0_Pos (16) /*!< EPWM_T::INTSTS0: CMPUIF0 Position */ 2970 #define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) /*!< EPWM_T::INTSTS0: CMPUIF0 Mask */ 2971 2972 #define EPWM_INTSTS0_CMPUIF1_Pos (17) /*!< EPWM_T::INTSTS0: CMPUIF1 Position */ 2973 #define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) /*!< EPWM_T::INTSTS0: CMPUIF1 Mask */ 2974 2975 #define EPWM_INTSTS0_CMPUIF2_Pos (18) /*!< EPWM_T::INTSTS0: CMPUIF2 Position */ 2976 #define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) /*!< EPWM_T::INTSTS0: CMPUIF2 Mask */ 2977 2978 #define EPWM_INTSTS0_CMPUIF3_Pos (19) /*!< EPWM_T::INTSTS0: CMPUIF3 Position */ 2979 #define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) /*!< EPWM_T::INTSTS0: CMPUIF3 Mask */ 2980 2981 #define EPWM_INTSTS0_CMPUIF4_Pos (20) /*!< EPWM_T::INTSTS0: CMPUIF4 Position */ 2982 #define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) /*!< EPWM_T::INTSTS0: CMPUIF4 Mask */ 2983 2984 #define EPWM_INTSTS0_CMPUIF5_Pos (21) /*!< EPWM_T::INTSTS0: CMPUIF5 Position */ 2985 #define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) /*!< EPWM_T::INTSTS0: CMPUIF5 Mask */ 2986 2987 #define EPWM_INTSTS0_CMPDIF0_Pos (24) /*!< EPWM_T::INTSTS0: CMPDIF0 Position */ 2988 #define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) /*!< EPWM_T::INTSTS0: CMPDIF0 Mask */ 2989 2990 #define EPWM_INTSTS0_CMPDIF1_Pos (25) /*!< EPWM_T::INTSTS0: CMPDIF1 Position */ 2991 #define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) /*!< EPWM_T::INTSTS0: CMPDIF1 Mask */ 2992 2993 #define EPWM_INTSTS0_CMPDIF2_Pos (26) /*!< EPWM_T::INTSTS0: CMPDIF2 Position */ 2994 #define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) /*!< EPWM_T::INTSTS0: CMPDIF2 Mask */ 2995 2996 #define EPWM_INTSTS0_CMPDIF3_Pos (27) /*!< EPWM_T::INTSTS0: CMPDIF3 Position */ 2997 #define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) /*!< EPWM_T::INTSTS0: CMPDIF3 Mask */ 2998 2999 #define EPWM_INTSTS0_CMPDIF4_Pos (28) /*!< EPWM_T::INTSTS0: CMPDIF4 Position */ 3000 #define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) /*!< EPWM_T::INTSTS0: CMPDIF4 Mask */ 3001 3002 #define EPWM_INTSTS0_CMPDIF5_Pos (29) /*!< EPWM_T::INTSTS0: CMPDIF5 Position */ 3003 #define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) /*!< EPWM_T::INTSTS0: CMPDIF5 Mask */ 3004 3005 #define EPWM_INTSTS1_BRKEIF0_Pos (0) /*!< EPWM_T::INTSTS1: BRKEIF0 Position */ 3006 #define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) /*!< EPWM_T::INTSTS1: BRKEIF0 Mask */ 3007 3008 #define EPWM_INTSTS1_BRKEIF1_Pos (1) /*!< EPWM_T::INTSTS1: BRKEIF1 Position */ 3009 #define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) /*!< EPWM_T::INTSTS1: BRKEIF1 Mask */ 3010 3011 #define EPWM_INTSTS1_BRKEIF2_Pos (2) /*!< EPWM_T::INTSTS1: BRKEIF2 Position */ 3012 #define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) /*!< EPWM_T::INTSTS1: BRKEIF2 Mask */ 3013 3014 #define EPWM_INTSTS1_BRKEIF3_Pos (3) /*!< EPWM_T::INTSTS1: BRKEIF3 Position */ 3015 #define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) /*!< EPWM_T::INTSTS1: BRKEIF3 Mask */ 3016 3017 #define EPWM_INTSTS1_BRKEIF4_Pos (4) /*!< EPWM_T::INTSTS1: BRKEIF4 Position */ 3018 #define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) /*!< EPWM_T::INTSTS1: BRKEIF4 Mask */ 3019 3020 #define EPWM_INTSTS1_BRKEIF5_Pos (5) /*!< EPWM_T::INTSTS1: BRKEIF5 Position */ 3021 #define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) /*!< EPWM_T::INTSTS1: BRKEIF5 Mask */ 3022 3023 #define EPWM_INTSTS1_BRKLIF0_Pos (8) /*!< EPWM_T::INTSTS1: BRKLIF0 Position */ 3024 #define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) /*!< EPWM_T::INTSTS1: BRKLIF0 Mask */ 3025 3026 #define EPWM_INTSTS1_BRKLIF1_Pos (9) /*!< EPWM_T::INTSTS1: BRKLIF1 Position */ 3027 #define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) /*!< EPWM_T::INTSTS1: BRKLIF1 Mask */ 3028 3029 #define EPWM_INTSTS1_BRKLIF2_Pos (10) /*!< EPWM_T::INTSTS1: BRKLIF2 Position */ 3030 #define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) /*!< EPWM_T::INTSTS1: BRKLIF2 Mask */ 3031 3032 #define EPWM_INTSTS1_BRKLIF3_Pos (11) /*!< EPWM_T::INTSTS1: BRKLIF3 Position */ 3033 #define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) /*!< EPWM_T::INTSTS1: BRKLIF3 Mask */ 3034 3035 #define EPWM_INTSTS1_BRKLIF4_Pos (12) /*!< EPWM_T::INTSTS1: BRKLIF4 Position */ 3036 #define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) /*!< EPWM_T::INTSTS1: BRKLIF4 Mask */ 3037 3038 #define EPWM_INTSTS1_BRKLIF5_Pos (13) /*!< EPWM_T::INTSTS1: BRKLIF5 Position */ 3039 #define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) /*!< EPWM_T::INTSTS1: BRKLIF5 Mask */ 3040 3041 #define EPWM_INTSTS1_BRKESTS0_Pos (16) /*!< EPWM_T::INTSTS1: BRKESTS0 Position */ 3042 #define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) /*!< EPWM_T::INTSTS1: BRKESTS0 Mask */ 3043 3044 #define EPWM_INTSTS1_BRKESTS1_Pos (17) /*!< EPWM_T::INTSTS1: BRKESTS1 Position */ 3045 #define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) /*!< EPWM_T::INTSTS1: BRKESTS1 Mask */ 3046 3047 #define EPWM_INTSTS1_BRKESTS2_Pos (18) /*!< EPWM_T::INTSTS1: BRKESTS2 Position */ 3048 #define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) /*!< EPWM_T::INTSTS1: BRKESTS2 Mask */ 3049 3050 #define EPWM_INTSTS1_BRKESTS3_Pos (19) /*!< EPWM_T::INTSTS1: BRKESTS3 Position */ 3051 #define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) /*!< EPWM_T::INTSTS1: BRKESTS3 Mask */ 3052 3053 #define EPWM_INTSTS1_BRKESTS4_Pos (20) /*!< EPWM_T::INTSTS1: BRKESTS4 Position */ 3054 #define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) /*!< EPWM_T::INTSTS1: BRKESTS4 Mask */ 3055 3056 #define EPWM_INTSTS1_BRKESTS5_Pos (21) /*!< EPWM_T::INTSTS1: BRKESTS5 Position */ 3057 #define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) /*!< EPWM_T::INTSTS1: BRKESTS5 Mask */ 3058 3059 #define EPWM_INTSTS1_BRKLSTS0_Pos (24) /*!< EPWM_T::INTSTS1: BRKLSTS0 Position */ 3060 #define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS0 Mask */ 3061 3062 #define EPWM_INTSTS1_BRKLSTS1_Pos (25) /*!< EPWM_T::INTSTS1: BRKLSTS1 Position */ 3063 #define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS1 Mask */ 3064 3065 #define EPWM_INTSTS1_BRKLSTS2_Pos (26) /*!< EPWM_T::INTSTS1: BRKLSTS2 Position */ 3066 #define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS2 Mask */ 3067 3068 #define EPWM_INTSTS1_BRKLSTS3_Pos (27) /*!< EPWM_T::INTSTS1: BRKLSTS3 Position */ 3069 #define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS3 Mask */ 3070 3071 #define EPWM_INTSTS1_BRKLSTS4_Pos (28) /*!< EPWM_T::INTSTS1: BRKLSTS4 Position */ 3072 #define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS4 Mask */ 3073 3074 #define EPWM_INTSTS1_BRKLSTS5_Pos (29) /*!< EPWM_T::INTSTS1: BRKLSTS5 Position */ 3075 #define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) /*!< EPWM_T::INTSTS1: BRKLSTS5 Mask */ 3076 3077 #define EPWM_DACTRGEN_ZTE0_Pos (0) /*!< EPWM_T::DACTRGEN: ZTE0 Position */ 3078 #define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) /*!< EPWM_T::DACTRGEN: ZTE0 Mask */ 3079 3080 #define EPWM_DACTRGEN_ZTE1_Pos (1) /*!< EPWM_T::DACTRGEN: ZTE1 Position */ 3081 #define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) /*!< EPWM_T::DACTRGEN: ZTE1 Mask */ 3082 3083 #define EPWM_DACTRGEN_ZTE2_Pos (2) /*!< EPWM_T::DACTRGEN: ZTE2 Position */ 3084 #define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) /*!< EPWM_T::DACTRGEN: ZTE2 Mask */ 3085 3086 #define EPWM_DACTRGEN_ZTE3_Pos (3) /*!< EPWM_T::DACTRGEN: ZTE3 Position */ 3087 #define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) /*!< EPWM_T::DACTRGEN: ZTE3 Mask */ 3088 3089 #define EPWM_DACTRGEN_ZTE4_Pos (4) /*!< EPWM_T::DACTRGEN: ZTE4 Position */ 3090 #define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) /*!< EPWM_T::DACTRGEN: ZTE4 Mask */ 3091 3092 #define EPWM_DACTRGEN_ZTE5_Pos (5) /*!< EPWM_T::DACTRGEN: ZTE5 Position */ 3093 #define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) /*!< EPWM_T::DACTRGEN: ZTE5 Mask */ 3094 3095 #define EPWM_DACTRGEN_PTE0_Pos (8) /*!< EPWM_T::DACTRGEN: PTE0 Position */ 3096 #define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) /*!< EPWM_T::DACTRGEN: PTE0 Mask */ 3097 3098 #define EPWM_DACTRGEN_PTE1_Pos (9) /*!< EPWM_T::DACTRGEN: PTE1 Position */ 3099 #define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) /*!< EPWM_T::DACTRGEN: PTE1 Mask */ 3100 3101 #define EPWM_DACTRGEN_PTE2_Pos (10) /*!< EPWM_T::DACTRGEN: PTE2 Position */ 3102 #define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) /*!< EPWM_T::DACTRGEN: PTE2 Mask */ 3103 3104 #define EPWM_DACTRGEN_PTE3_Pos (11) /*!< EPWM_T::DACTRGEN: PTE3 Position */ 3105 #define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) /*!< EPWM_T::DACTRGEN: PTE3 Mask */ 3106 3107 #define EPWM_DACTRGEN_PTE4_Pos (12) /*!< EPWM_T::DACTRGEN: PTE4 Position */ 3108 #define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) /*!< EPWM_T::DACTRGEN: PTE4 Mask */ 3109 3110 #define EPWM_DACTRGEN_PTE5_Pos (13) /*!< EPWM_T::DACTRGEN: PTE5 Position */ 3111 #define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) /*!< EPWM_T::DACTRGEN: PTE5 Mask */ 3112 3113 #define EPWM_DACTRGEN_CUTRGE0_Pos (16) /*!< EPWM_T::DACTRGEN: CUTRGE0 Position */ 3114 #define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE0 Mask */ 3115 3116 #define EPWM_DACTRGEN_CUTRGE1_Pos (17) /*!< EPWM_T::DACTRGEN: CUTRGE1 Position */ 3117 #define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE1 Mask */ 3118 3119 #define EPWM_DACTRGEN_CUTRGE2_Pos (18) /*!< EPWM_T::DACTRGEN: CUTRGE2 Position */ 3120 #define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE2 Mask */ 3121 3122 #define EPWM_DACTRGEN_CUTRGE3_Pos (19) /*!< EPWM_T::DACTRGEN: CUTRGE3 Position */ 3123 #define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE3 Mask */ 3124 3125 #define EPWM_DACTRGEN_CUTRGE4_Pos (20) /*!< EPWM_T::DACTRGEN: CUTRGE4 Position */ 3126 #define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE4 Mask */ 3127 3128 #define EPWM_DACTRGEN_CUTRGE5_Pos (21) /*!< EPWM_T::DACTRGEN: CUTRGE5 Position */ 3129 #define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CUTRGE5 Mask */ 3130 3131 #define EPWM_DACTRGEN_CDTRGE0_Pos (24) /*!< EPWM_T::DACTRGEN: CDTRGE0 Position */ 3132 #define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE0 Mask */ 3133 3134 #define EPWM_DACTRGEN_CDTRGE1_Pos (25) /*!< EPWM_T::DACTRGEN: CDTRGE1 Position */ 3135 #define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE1 Mask */ 3136 3137 #define EPWM_DACTRGEN_CDTRGE2_Pos (26) /*!< EPWM_T::DACTRGEN: CDTRGE2 Position */ 3138 #define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE2 Mask */ 3139 3140 #define EPWM_DACTRGEN_CDTRGE3_Pos (27) /*!< EPWM_T::DACTRGEN: CDTRGE3 Position */ 3141 #define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE3 Mask */ 3142 3143 #define EPWM_DACTRGEN_CDTRGE4_Pos (28) /*!< EPWM_T::DACTRGEN: CDTRGE4 Position */ 3144 #define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE4 Mask */ 3145 3146 #define EPWM_DACTRGEN_CDTRGE5_Pos (29) /*!< EPWM_T::DACTRGEN: CDTRGE5 Position */ 3147 #define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) /*!< EPWM_T::DACTRGEN: CDTRGE5 Mask */ 3148 3149 #define EPWM_EADCTS0_TRGSEL0_Pos (0) /*!< EPWM_T::EADCTS0: TRGSEL0 Position */ 3150 #define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) /*!< EPWM_T::EADCTS0: TRGSEL0 Mask */ 3151 3152 #define EPWM_EADCTS0_TRGEN0_Pos (7) /*!< EPWM_T::EADCTS0: TRGEN0 Position */ 3153 #define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) /*!< EPWM_T::EADCTS0: TRGEN0 Mask */ 3154 3155 #define EPWM_EADCTS0_TRGSEL1_Pos (8) /*!< EPWM_T::EADCTS0: TRGSEL1 Position */ 3156 #define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) /*!< EPWM_T::EADCTS0: TRGSEL1 Mask */ 3157 3158 #define EPWM_EADCTS0_TRGEN1_Pos (15) /*!< EPWM_T::EADCTS0: TRGEN1 Position */ 3159 #define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) /*!< EPWM_T::EADCTS0: TRGEN1 Mask */ 3160 3161 #define EPWM_EADCTS0_TRGSEL2_Pos (16) /*!< EPWM_T::EADCTS0: TRGSEL2 Position */ 3162 #define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) /*!< EPWM_T::EADCTS0: TRGSEL2 Mask */ 3163 3164 #define EPWM_EADCTS0_TRGEN2_Pos (23) /*!< EPWM_T::EADCTS0: TRGEN2 Position */ 3165 #define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) /*!< EPWM_T::EADCTS0: TRGEN2 Mask */ 3166 3167 #define EPWM_EADCTS0_TRGSEL3_Pos (24) /*!< EPWM_T::EADCTS0: TRGSEL3 Position */ 3168 #define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) /*!< EPWM_T::EADCTS0: TRGSEL3 Mask */ 3169 3170 #define EPWM_EADCTS0_TRGEN3_Pos (31) /*!< EPWM_T::EADCTS0: TRGEN3 Position */ 3171 #define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) /*!< EPWM_T::EADCTS0: TRGEN3 Mask */ 3172 3173 #define EPWM_EADCTS1_TRGSEL4_Pos (0) /*!< EPWM_T::EADCTS1: TRGSEL4 Position */ 3174 #define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) /*!< EPWM_T::EADCTS1: TRGSEL4 Mask */ 3175 3176 #define EPWM_EADCTS1_TRGEN4_Pos (7) /*!< EPWM_T::EADCTS1: TRGEN4 Position */ 3177 #define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) /*!< EPWM_T::EADCTS1: TRGEN4 Mask */ 3178 3179 #define EPWM_EADCTS1_TRGSEL5_Pos (8) /*!< EPWM_T::EADCTS1: TRGSEL5 Position */ 3180 #define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) /*!< EPWM_T::EADCTS1: TRGSEL5 Mask */ 3181 3182 #define EPWM_EADCTS1_TRGEN5_Pos (15) /*!< EPWM_T::EADCTS1: TRGEN5 Position */ 3183 #define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) /*!< EPWM_T::EADCTS1: TRGEN5 Mask */ 3184 3185 #define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Position */ 3186 #define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT0_1: FTCMP Mask */ 3187 3188 #define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Position */ 3189 #define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT2_3: FTCMP Mask */ 3190 3191 #define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Position */ 3192 #define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) /*!< EPWM_T::FTCMPDAT4_5: FTCMP Mask */ 3193 3194 #define EPWM_SSCTL_SSEN0_Pos (0) /*!< EPWM_T::SSCTL: SSEN0 Position */ 3195 #define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) /*!< EPWM_T::SSCTL: SSEN0 Mask */ 3196 3197 #define EPWM_SSCTL_SSEN1_Pos (1) /*!< EPWM_T::SSCTL: SSEN1 Position */ 3198 #define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) /*!< EPWM_T::SSCTL: SSEN1 Mask */ 3199 3200 #define EPWM_SSCTL_SSEN2_Pos (2) /*!< EPWM_T::SSCTL: SSEN2 Position */ 3201 #define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) /*!< EPWM_T::SSCTL: SSEN2 Mask */ 3202 3203 #define EPWM_SSCTL_SSEN3_Pos (3) /*!< EPWM_T::SSCTL: SSEN3 Position */ 3204 #define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) /*!< EPWM_T::SSCTL: SSEN3 Mask */ 3205 3206 #define EPWM_SSCTL_SSEN4_Pos (4) /*!< EPWM_T::SSCTL: SSEN4 Position */ 3207 #define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) /*!< EPWM_T::SSCTL: SSEN4 Mask */ 3208 3209 #define EPWM_SSCTL_SSEN5_Pos (5) /*!< EPWM_T::SSCTL: SSEN5 Position */ 3210 #define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) /*!< EPWM_T::SSCTL: SSEN5 Mask */ 3211 3212 #define EPWM_SSCTL_SSRC_Pos (8) /*!< EPWM_T::SSCTL: SSRC Position */ 3213 #define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) /*!< EPWM_T::SSCTL: SSRC Mask */ 3214 3215 #define EPWM_SSTRG_CNTSEN_Pos (0) /*!< EPWM_T::SSTRG: CNTSEN Position */ 3216 #define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) /*!< EPWM_T::SSTRG: CNTSEN Mask */ 3217 3218 #define EPWM_LEBCTL_LEBEN_Pos (0) /*!< EPWM_T::LEBCTL: LEBEN Position */ 3219 #define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) /*!< EPWM_T::LEBCTL: LEBEN Mask */ 3220 3221 #define EPWM_LEBCTL_SRCEN0_Pos (8) /*!< EPWM_T::LEBCTL: SRCEN0 Position */ 3222 #define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) /*!< EPWM_T::LEBCTL: SRCEN0 Mask */ 3223 3224 #define EPWM_LEBCTL_SRCEN2_Pos (9) /*!< EPWM_T::LEBCTL: SRCEN2 Position */ 3225 #define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) /*!< EPWM_T::LEBCTL: SRCEN2 Mask */ 3226 3227 #define EPWM_LEBCTL_SRCEN4_Pos (10) /*!< EPWM_T::LEBCTL: SRCEN4 Position */ 3228 #define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) /*!< EPWM_T::LEBCTL: SRCEN4 Mask */ 3229 3230 #define EPWM_LEBCTL_TRGTYPE_Pos (16) /*!< EPWM_T::LEBCTL: TRGTYPE Position */ 3231 #define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) /*!< EPWM_T::LEBCTL: TRGTYPE Mask */ 3232 3233 #define EPWM_LEBCNT_LEBCNT_Pos (0) /*!< EPWM_T::LEBCNT: LEBCNT Position */ 3234 #define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) /*!< EPWM_T::LEBCNT: LEBCNT Mask */ 3235 3236 #define EPWM_STATUS_CNTMAXF0_Pos (0) /*!< EPWM_T::STATUS: CNTMAXF0 Position */ 3237 #define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) /*!< EPWM_T::STATUS: CNTMAXF0 Mask */ 3238 3239 #define EPWM_STATUS_CNTMAXF1_Pos (1) /*!< EPWM_T::STATUS: CNTMAXF1 Position */ 3240 #define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) /*!< EPWM_T::STATUS: CNTMAXF1 Mask */ 3241 3242 #define EPWM_STATUS_CNTMAXF2_Pos (2) /*!< EPWM_T::STATUS: CNTMAXF2 Position */ 3243 #define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) /*!< EPWM_T::STATUS: CNTMAXF2 Mask */ 3244 3245 #define EPWM_STATUS_CNTMAXF3_Pos (3) /*!< EPWM_T::STATUS: CNTMAXF3 Position */ 3246 #define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) /*!< EPWM_T::STATUS: CNTMAXF3 Mask */ 3247 3248 #define EPWM_STATUS_CNTMAXF4_Pos (4) /*!< EPWM_T::STATUS: CNTMAXF4 Position */ 3249 #define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) /*!< EPWM_T::STATUS: CNTMAXF4 Mask */ 3250 3251 #define EPWM_STATUS_CNTMAXF5_Pos (5) /*!< EPWM_T::STATUS: CNTMAXF5 Position */ 3252 #define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) /*!< EPWM_T::STATUS: CNTMAXF5 Mask */ 3253 3254 #define EPWM_STATUS_SYNCINF0_Pos (8) /*!< EPWM_T::STATUS: SYNCINF0 Position */ 3255 #define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) /*!< EPWM_T::STATUS: SYNCINF0 Mask */ 3256 3257 #define EPWM_STATUS_SYNCINF2_Pos (9) /*!< EPWM_T::STATUS: SYNCINF2 Position */ 3258 #define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) /*!< EPWM_T::STATUS: SYNCINF2 Mask */ 3259 3260 #define EPWM_STATUS_SYNCINF4_Pos (10) /*!< EPWM_T::STATUS: SYNCINF4 Position */ 3261 #define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) /*!< EPWM_T::STATUS: SYNCINF4 Mask */ 3262 3263 #define EPWM_STATUS_EADCTRGF0_Pos (16) /*!< EPWM_T::STATUS: EADCTRGF0 Position */ 3264 #define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) /*!< EPWM_T::STATUS: EADCTRGF0 Mask */ 3265 3266 #define EPWM_STATUS_EADCTRGF1_Pos (17) /*!< EPWM_T::STATUS: EADCTRGF1 Position */ 3267 #define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) /*!< EPWM_T::STATUS: EADCTRGF1 Mask */ 3268 3269 #define EPWM_STATUS_EADCTRGF2_Pos (18) /*!< EPWM_T::STATUS: EADCTRGF2 Position */ 3270 #define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) /*!< EPWM_T::STATUS: EADCTRGF2 Mask */ 3271 3272 #define EPWM_STATUS_EADCTRGF3_Pos (19) /*!< EPWM_T::STATUS: EADCTRGF3 Position */ 3273 #define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) /*!< EPWM_T::STATUS: EADCTRGF3 Mask */ 3274 3275 #define EPWM_STATUS_EADCTRGF4_Pos (20) /*!< EPWM_T::STATUS: EADCTRGF4 Position */ 3276 #define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) /*!< EPWM_T::STATUS: EADCTRGF4 Mask */ 3277 3278 #define EPWM_STATUS_EADCTRGF5_Pos (21) /*!< EPWM_T::STATUS: EADCTRGF5 Position */ 3279 #define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) /*!< EPWM_T::STATUS: EADCTRGF5 Mask */ 3280 3281 #define EPWM_STATUS_DACTRGF_Pos (24) /*!< EPWM_T::STATUS: DACTRGF Position */ 3282 #define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) /*!< EPWM_T::STATUS: DACTRGF Mask */ 3283 3284 #define EPWM_IFA0_IFACNT_Pos (0) /*!< EPWM_T::IFA0: IFACNT Position */ 3285 #define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) /*!< EPWM_T::IFA0: IFACNT Mask */ 3286 3287 #define EPWM_IFA0_STPMOD_Pos (24) /*!< EPWM_T::IFA0: STPMOD Position */ 3288 #define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) /*!< EPWM_T::IFA0: STPMOD Mask */ 3289 3290 #define EPWM_IFA0_IFASEL_Pos (28) /*!< EPWM_T::IFA0: IFASEL Position */ 3291 #define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) /*!< EPWM_T::IFA0: IFASEL Mask */ 3292 3293 #define EPWM_IFA0_IFAEN_Pos (31) /*!< EPWM_T::IFA0: IFAEN Position */ 3294 #define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) /*!< EPWM_T::IFA0: IFAEN Mask */ 3295 3296 #define EPWM_IFA1_IFACNT_Pos (0) /*!< EPWM_T::IFA1: IFACNT Position */ 3297 #define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) /*!< EPWM_T::IFA1: IFACNT Mask */ 3298 3299 #define EPWM_IFA1_STPMOD_Pos (24) /*!< EPWM_T::IFA1: STPMOD Position */ 3300 #define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) /*!< EPWM_T::IFA1: STPMOD Mask */ 3301 3302 #define EPWM_IFA1_IFASEL_Pos (28) /*!< EPWM_T::IFA1: IFASEL Position */ 3303 #define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) /*!< EPWM_T::IFA1: IFASEL Mask */ 3304 3305 #define EPWM_IFA1_IFAEN_Pos (31) /*!< EPWM_T::IFA1: IFAEN Position */ 3306 #define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) /*!< EPWM_T::IFA1: IFAEN Mask */ 3307 3308 #define EPWM_IFA2_IFACNT_Pos (0) /*!< EPWM_T::IFA2: IFACNT Position */ 3309 #define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) /*!< EPWM_T::IFA2: IFACNT Mask */ 3310 3311 #define EPWM_IFA2_STPMOD_Pos (24) /*!< EPWM_T::IFA2: STPMOD Position */ 3312 #define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) /*!< EPWM_T::IFA2: STPMOD Mask */ 3313 3314 #define EPWM_IFA2_IFASEL_Pos (28) /*!< EPWM_T::IFA2: IFASEL Position */ 3315 #define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) /*!< EPWM_T::IFA2: IFASEL Mask */ 3316 3317 #define EPWM_IFA2_IFAEN_Pos (31) /*!< EPWM_T::IFA2: IFAEN Position */ 3318 #define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) /*!< EPWM_T::IFA2: IFAEN Mask */ 3319 3320 #define EPWM_IFA3_IFACNT_Pos (0) /*!< EPWM_T::IFA3: IFACNT Position */ 3321 #define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) /*!< EPWM_T::IFA3: IFACNT Mask */ 3322 3323 #define EPWM_IFA3_STPMOD_Pos (24) /*!< EPWM_T::IFA3: STPMOD Position */ 3324 #define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) /*!< EPWM_T::IFA3: STPMOD Mask */ 3325 3326 #define EPWM_IFA3_IFASEL_Pos (28) /*!< EPWM_T::IFA3: IFASEL Position */ 3327 #define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) /*!< EPWM_T::IFA3: IFASEL Mask */ 3328 3329 #define EPWM_IFA3_IFAEN_Pos (31) /*!< EPWM_T::IFA3: IFAEN Position */ 3330 #define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) /*!< EPWM_T::IFA3: IFAEN Mask */ 3331 3332 #define EPWM_IFA4_IFACNT_Pos (0) /*!< EPWM_T::IFA4: IFACNT Position */ 3333 #define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) /*!< EPWM_T::IFA4: IFACNT Mask */ 3334 3335 #define EPWM_IFA4_STPMOD_Pos (24) /*!< EPWM_T::IFA4: STPMOD Position */ 3336 #define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) /*!< EPWM_T::IFA4: STPMOD Mask */ 3337 3338 #define EPWM_IFA4_IFASEL_Pos (28) /*!< EPWM_T::IFA4: IFASEL Position */ 3339 #define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) /*!< EPWM_T::IFA4: IFASEL Mask */ 3340 3341 #define EPWM_IFA4_IFAEN_Pos (31) /*!< EPWM_T::IFA4: IFAEN Position */ 3342 #define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) /*!< EPWM_T::IFA4: IFAEN Mask */ 3343 3344 #define EPWM_IFA5_IFACNT_Pos (0) /*!< EPWM_T::IFA5: IFACNT Position */ 3345 #define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) /*!< EPWM_T::IFA5: IFACNT Mask */ 3346 3347 #define EPWM_IFA5_STPMOD_Pos (24) /*!< EPWM_T::IFA5: STPMOD Position */ 3348 #define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) /*!< EPWM_T::IFA5: STPMOD Mask */ 3349 3350 #define EPWM_IFA5_IFASEL_Pos (28) /*!< EPWM_T::IFA5: IFASEL Position */ 3351 #define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) /*!< EPWM_T::IFA5: IFASEL Mask */ 3352 3353 #define EPWM_IFA5_IFAEN_Pos (31) /*!< EPWM_T::IFA5: IFAEN Position */ 3354 #define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) /*!< EPWM_T::IFA5: IFAEN Mask */ 3355 3356 #define EPWM_AINTSTS_IFAIF0_Pos (0) /*!< EPWM_T::AINTSTS: IFAIF0 Position */ 3357 #define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) /*!< EPWM_T::AINTSTS: IFAIF0 Mask */ 3358 3359 #define EPWM_AINTSTS_IFAIF1_Pos (1) /*!< EPWM_T::AINTSTS: IFAIF1 Position */ 3360 #define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) /*!< EPWM_T::AINTSTS: IFAIF1 Mask */ 3361 3362 #define EPWM_AINTSTS_IFAIF2_Pos (2) /*!< EPWM_T::AINTSTS: IFAIF2 Position */ 3363 #define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) /*!< EPWM_T::AINTSTS: IFAIF2 Mask */ 3364 3365 #define EPWM_AINTSTS_IFAIF3_Pos (3) /*!< EPWM_T::AINTSTS: IFAIF3 Position */ 3366 #define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) /*!< EPWM_T::AINTSTS: IFAIF3 Mask */ 3367 3368 #define EPWM_AINTSTS_IFAIF4_Pos (4) /*!< EPWM_T::AINTSTS: IFAIF4 Position */ 3369 #define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) /*!< EPWM_T::AINTSTS: IFAIF4 Mask */ 3370 3371 #define EPWM_AINTSTS_IFAIF5_Pos (5) /*!< EPWM_T::AINTSTS: IFAIF5 Position */ 3372 #define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) /*!< EPWM_T::AINTSTS: IFAIF5 Mask */ 3373 3374 #define EPWM_AINTEN_IFAIEN0_Pos (0) /*!< EPWM_T::AINTEN: IFAIEN0 Position */ 3375 #define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) /*!< EPWM_T::AINTEN: IFAIEN0 Mask */ 3376 3377 #define EPWM_AINTEN_IFAIEN1_Pos (1) /*!< EPWM_T::AINTEN: IFAIEN1 Position */ 3378 #define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) /*!< EPWM_T::AINTEN: IFAIEN1 Mask */ 3379 3380 #define EPWM_AINTEN_IFAIEN2_Pos (2) /*!< EPWM_T::AINTEN: IFAIEN2 Position */ 3381 #define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) /*!< EPWM_T::AINTEN: IFAIEN2 Mask */ 3382 3383 #define EPWM_AINTEN_IFAIEN3_Pos (3) /*!< EPWM_T::AINTEN: IFAIEN3 Position */ 3384 #define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) /*!< EPWM_T::AINTEN: IFAIEN3 Mask */ 3385 3386 #define EPWM_AINTEN_IFAIEN4_Pos (4) /*!< EPWM_T::AINTEN: IFAIEN4 Position */ 3387 #define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) /*!< EPWM_T::AINTEN: IFAIEN4 Mask */ 3388 3389 #define EPWM_AINTEN_IFAIEN5_Pos (5) /*!< EPWM_T::AINTEN: IFAIEN5 Position */ 3390 #define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) /*!< EPWM_T::AINTEN: IFAIEN5 Mask */ 3391 3392 #define EPWM_APDMACTL_APDMAEN0_Pos (0) /*!< EPWM_T::APDMACTL: APDMAEN0 Position */ 3393 #define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) /*!< EPWM_T::APDMACTL: APDMAEN0 Mask */ 3394 3395 #define EPWM_APDMACTL_APDMAEN1_Pos (1) /*!< EPWM_T::APDMACTL: APDMAEN1 Position */ 3396 #define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) /*!< EPWM_T::APDMACTL: APDMAEN1 Mask */ 3397 3398 #define EPWM_APDMACTL_APDMAEN2_Pos (2) /*!< EPWM_T::APDMACTL: APDMAEN2 Position */ 3399 #define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) /*!< EPWM_T::APDMACTL: APDMAEN2 Mask */ 3400 3401 #define EPWM_APDMACTL_APDMAEN3_Pos (3) /*!< EPWM_T::APDMACTL: APDMAEN3 Position */ 3402 #define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) /*!< EPWM_T::APDMACTL: APDMAEN3 Mask */ 3403 3404 #define EPWM_APDMACTL_APDMAEN4_Pos (4) /*!< EPWM_T::APDMACTL: APDMAEN4 Position */ 3405 #define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) /*!< EPWM_T::APDMACTL: APDMAEN4 Mask */ 3406 3407 #define EPWM_APDMACTL_APDMAEN5_Pos (5) /*!< EPWM_T::APDMACTL: APDMAEN5 Position */ 3408 #define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) /*!< EPWM_T::APDMACTL: APDMAEN5 Mask */ 3409 3410 #define EPWM_FDEN_FDEN0_Pos (0) /*!< EPWM_T::FDEN: FDEN0 Position */ 3411 #define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) /*!< EPWM_T::FDEN: FDEN0 Mask */ 3412 3413 #define EPWM_FDEN_FDEN1_Pos (1) /*!< EPWM_T::FDEN: FDEN1 Position */ 3414 #define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) /*!< EPWM_T::FDEN: FDEN1 Mask */ 3415 3416 #define EPWM_FDEN_FDEN2_Pos (2) /*!< EPWM_T::FDEN: FDEN2 Position */ 3417 #define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) /*!< EPWM_T::FDEN: FDEN2 Mask */ 3418 3419 #define EPWM_FDEN_FDEN3_Pos (3) /*!< EPWM_T::FDEN: FDEN3 Position */ 3420 #define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) /*!< EPWM_T::FDEN: FDEN3 Mask */ 3421 3422 #define EPWM_FDEN_FDEN4_Pos (4) /*!< EPWM_T::FDEN: FDEN4 Position */ 3423 #define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) /*!< EPWM_T::FDEN: FDEN4 Mask */ 3424 3425 #define EPWM_FDEN_FDEN5_Pos (5) /*!< EPWM_T::FDEN: FDEN5 Position */ 3426 #define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) /*!< EPWM_T::FDEN: FDEN5 Mask */ 3427 3428 #define EPWM_FDEN_FDODIS0_Pos (8) /*!< EPWM_T::FDEN: FDODIS0 Position */ 3429 #define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) /*!< EPWM_T::FDEN: FDODIS0 Mask */ 3430 3431 #define EPWM_FDEN_FDODIS1_Pos (9) /*!< EPWM_T::FDEN: FDODIS1 Position */ 3432 #define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) /*!< EPWM_T::FDEN: FDODIS1 Mask */ 3433 3434 #define EPWM_FDEN_FDODIS2_Pos (10) /*!< EPWM_T::FDEN: FDODIS2 Position */ 3435 #define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) /*!< EPWM_T::FDEN: FDODIS2 Mask */ 3436 3437 #define EPWM_FDEN_FDODIS3_Pos (11) /*!< EPWM_T::FDEN: FDODIS3 Position */ 3438 #define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) /*!< EPWM_T::FDEN: FDODIS3 Mask */ 3439 3440 #define EPWM_FDEN_FDODIS4_Pos (12) /*!< EPWM_T::FDEN: FDODIS4 Position */ 3441 #define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) /*!< EPWM_T::FDEN: FDODIS4 Mask */ 3442 3443 #define EPWM_FDEN_FDODIS5_Pos (13) /*!< EPWM_T::FDEN: FDODIS5 Position */ 3444 #define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) /*!< EPWM_T::FDEN: FDODIS5 Mask */ 3445 3446 #define EPWM_FDEN_FDCKS0_Pos (16) /*!< EPWM_T::FDEN: FDCKS0 Position */ 3447 #define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) /*!< EPWM_T::FDEN: FDCKS0 Mask */ 3448 3449 #define EPWM_FDEN_FDCKS1_Pos (17) /*!< EPWM_T::FDEN: FDCKS1 Position */ 3450 #define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) /*!< EPWM_T::FDEN: FDCKS1 Mask */ 3451 3452 #define EPWM_FDEN_FDCKS2_Pos (18) /*!< EPWM_T::FDEN: FDCKS2 Position */ 3453 #define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) /*!< EPWM_T::FDEN: FDCKS2 Mask */ 3454 3455 #define EPWM_FDEN_FDCKS3_Pos (19) /*!< EPWM_T::FDEN: FDCKS3 Position */ 3456 #define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) /*!< EPWM_T::FDEN: FDCKS3 Mask */ 3457 3458 #define EPWM_FDEN_FDCKS4_Pos (20) /*!< EPWM_T::FDEN: FDCKS4 Position */ 3459 #define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) /*!< EPWM_T::FDEN: FDCKS4 Mask */ 3460 3461 #define EPWM_FDEN_FDCKS5_Pos (21) /*!< EPWM_T::FDEN: FDCKS5 Position */ 3462 #define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) /*!< EPWM_T::FDEN: FDCKS5 Mask */ 3463 3464 #define EPWM_FDCTL0_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL0: TRMSKCNT Position */ 3465 #define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL0: TRMSKCNT Mask */ 3466 3467 #define EPWM_FDCTL0_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL0: FDMSKEN Position */ 3468 #define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) /*!< EPWM_T::FDCTL0: FDMSKEN Mask */ 3469 3470 #define EPWM_FDCTL0_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL0: DGSMPCYC Position */ 3471 #define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL0: DGSMPCYC Mask */ 3472 3473 #define EPWM_FDCTL0_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL0: FDCKSEL Position */ 3474 #define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) /*!< EPWM_T::FDCTL0: FDCKSEL Mask */ 3475 3476 #define EPWM_FDCTL0_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL0: FDDGEN Position */ 3477 #define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) /*!< EPWM_T::FDCTL0: FDDGEN Mask */ 3478 3479 #define EPWM_FDCTL1_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL1: TRMSKCNT Position */ 3480 #define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL1: TRMSKCNT Mask */ 3481 3482 #define EPWM_FDCTL1_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL1: FDMSKEN Position */ 3483 #define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) /*!< EPWM_T::FDCTL1: FDMSKEN Mask */ 3484 3485 #define EPWM_FDCTL1_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL1: DGSMPCYC Position */ 3486 #define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL1: DGSMPCYC Mask */ 3487 3488 #define EPWM_FDCTL1_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL1: FDCKSEL Position */ 3489 #define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) /*!< EPWM_T::FDCTL1: FDCKSEL Mask */ 3490 3491 #define EPWM_FDCTL1_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL1: FDDGEN Position */ 3492 #define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) /*!< EPWM_T::FDCTL1: FDDGEN Mask */ 3493 3494 #define EPWM_FDCTL2_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL2: TRMSKCNT Position */ 3495 #define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL2: TRMSKCNT Mask */ 3496 3497 #define EPWM_FDCTL2_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL2: FDMSKEN Position */ 3498 #define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) /*!< EPWM_T::FDCTL2: FDMSKEN Mask */ 3499 3500 #define EPWM_FDCTL2_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL2: DGSMPCYC Position */ 3501 #define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL2: DGSMPCYC Mask */ 3502 3503 #define EPWM_FDCTL2_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL2: FDCKSEL Position */ 3504 #define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) /*!< EPWM_T::FDCTL2: FDCKSEL Mask */ 3505 3506 #define EPWM_FDCTL2_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL2: FDDGEN Position */ 3507 #define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) /*!< EPWM_T::FDCTL2: FDDGEN Mask */ 3508 3509 #define EPWM_FDCTL3_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL3: TRMSKCNT Position */ 3510 #define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL3: TRMSKCNT Mask */ 3511 3512 #define EPWM_FDCTL3_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL3: FDMSKEN Position */ 3513 #define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) /*!< EPWM_T::FDCTL3: FDMSKEN Mask */ 3514 3515 #define EPWM_FDCTL3_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL3: DGSMPCYC Position */ 3516 #define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL3: DGSMPCYC Mask */ 3517 3518 #define EPWM_FDCTL3_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL3: FDCKSEL Position */ 3519 #define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) /*!< EPWM_T::FDCTL3: FDCKSEL Mask */ 3520 3521 #define EPWM_FDCTL3_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL3: FDDGEN Position */ 3522 #define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) /*!< EPWM_T::FDCTL3: FDDGEN Mask */ 3523 3524 #define EPWM_FDCTL4_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL4: TRMSKCNT Position */ 3525 #define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL4: TRMSKCNT Mask */ 3526 3527 #define EPWM_FDCTL4_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL4: FDMSKEN Position */ 3528 #define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) /*!< EPWM_T::FDCTL4: FDMSKEN Mask */ 3529 3530 #define EPWM_FDCTL4_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL4: DGSMPCYC Position */ 3531 #define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL4: DGSMPCYC Mask */ 3532 3533 #define EPWM_FDCTL4_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL4: FDCKSEL Position */ 3534 #define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) /*!< EPWM_T::FDCTL4: FDCKSEL Mask */ 3535 3536 #define EPWM_FDCTL4_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL4: FDDGEN Position */ 3537 #define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) /*!< EPWM_T::FDCTL4: FDDGEN Mask */ 3538 3539 #define EPWM_FDCTL5_TRMSKCNT_Pos (0) /*!< EPWM_T::FDCTL5: TRMSKCNT Position */ 3540 #define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) /*!< EPWM_T::FDCTL5: TRMSKCNT Mask */ 3541 3542 #define EPWM_FDCTL5_FDMSKEN_Pos (15) /*!< EPWM_T::FDCTL5: FDMSKEN Position */ 3543 #define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) /*!< EPWM_T::FDCTL5: FDMSKEN Mask */ 3544 3545 #define EPWM_FDCTL5_DGSMPCYC_Pos (16) /*!< EPWM_T::FDCTL5: DGSMPCYC Position */ 3546 #define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) /*!< EPWM_T::FDCTL5: DGSMPCYC Mask */ 3547 3548 #define EPWM_FDCTL5_FDCKSEL_Pos (28) /*!< EPWM_T::FDCTL5: FDCKSEL Position */ 3549 #define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) /*!< EPWM_T::FDCTL5: FDCKSEL Mask */ 3550 3551 #define EPWM_FDCTL5_FDDGEN_Pos (31) /*!< EPWM_T::FDCTL5: FDDGEN Position */ 3552 #define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) /*!< EPWM_T::FDCTL5: FDDGEN Mask */ 3553 3554 #define EPWM_FDIEN_FDIEN0_Pos (0) /*!< EPWM_T::FDIEN: FDIEN0 Position */ 3555 #define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) /*!< EPWM_T::FDIEN: FDIEN0 Mask */ 3556 3557 #define EPWM_FDIEN_FDIEN1_Pos (1) /*!< EPWM_T::FDIEN: FDIEN1 Position */ 3558 #define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) /*!< EPWM_T::FDIEN: FDIEN1 Mask */ 3559 3560 #define EPWM_FDIEN_FDIEN2_Pos (2) /*!< EPWM_T::FDIEN: FDIEN2 Position */ 3561 #define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) /*!< EPWM_T::FDIEN: FDIEN2 Mask */ 3562 3563 #define EPWM_FDIEN_FDIEN3_Pos (3) /*!< EPWM_T::FDIEN: FDIEN3 Position */ 3564 #define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) /*!< EPWM_T::FDIEN: FDIEN3 Mask */ 3565 3566 #define EPWM_FDIEN_FDIEN4_Pos (4) /*!< EPWM_T::FDIEN: FDIEN4 Position */ 3567 #define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) /*!< EPWM_T::FDIEN: FDIEN4 Mask */ 3568 3569 #define EPWM_FDIEN_FDIEN5_Pos (5) /*!< EPWM_T::FDIEN: FDIEN5 Position */ 3570 #define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) /*!< EPWM_T::FDIEN: FDIEN5 Mask */ 3571 3572 #define EPWM_FDSTS_FDIF0_Pos (0) /*!< EPWM_T::FDSTS: FDIF0 Position */ 3573 #define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) /*!< EPWM_T::FDSTS: FDIF0 Mask */ 3574 3575 #define EPWM_FDSTS_FDIF1_Pos (1) /*!< EPWM_T::FDSTS: FDIF1 Position */ 3576 #define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) /*!< EPWM_T::FDSTS: FDIF1 Mask */ 3577 3578 #define EPWM_FDSTS_FDIF2_Pos (2) /*!< EPWM_T::FDSTS: FDIF2 Position */ 3579 #define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) /*!< EPWM_T::FDSTS: FDIF2 Mask */ 3580 3581 #define EPWM_FDSTS_FDIF3_Pos (3) /*!< EPWM_T::FDSTS: FDIF3 Position */ 3582 #define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) /*!< EPWM_T::FDSTS: FDIF3 Mask */ 3583 3584 #define EPWM_FDSTS_FDIF4_Pos (4) /*!< EPWM_T::FDSTS: FDIF4 Position */ 3585 #define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) /*!< EPWM_T::FDSTS: FDIF4 Mask */ 3586 3587 #define EPWM_FDSTS_FDIF5_Pos (5) /*!< EPWM_T::FDSTS: FDIF5 Position */ 3588 #define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) /*!< EPWM_T::FDSTS: FDIF5 Mask */ 3589 3590 #define EPWM_EADCPSCCTL_PSCEN0_Pos (0) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Position */ 3591 #define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN0 Mask */ 3592 3593 #define EPWM_EADCPSCCTL_PSCEN1_Pos (1) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Position */ 3594 #define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN1 Mask */ 3595 3596 #define EPWM_EADCPSCCTL_PSCEN2_Pos (2) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Position */ 3597 #define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN2 Mask */ 3598 3599 #define EPWM_EADCPSCCTL_PSCEN3_Pos (3) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Position */ 3600 #define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN3 Mask */ 3601 3602 #define EPWM_EADCPSCCTL_PSCEN4_Pos (4) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Position */ 3603 #define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN4 Mask */ 3604 3605 #define EPWM_EADCPSCCTL_PSCEN5_Pos (5) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Position */ 3606 #define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) /*!< EPWM_T::EADCPSCCTL: PSCEN5 Mask */ 3607 3608 #define EPWM_EADCPSC0_EADCPSC0_Pos (0) /*!< EPWM_T::EADCPSC0: EADCPSC0 Position */ 3609 #define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC0 Mask */ 3610 3611 #define EPWM_EADCPSC0_EADCPSC1_Pos (8) /*!< EPWM_T::EADCPSC0: EADCPSC1 Position */ 3612 #define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC1 Mask */ 3613 3614 #define EPWM_EADCPSC0_EADCPSC2_Pos (16) /*!< EPWM_T::EADCPSC0: EADCPSC2 Position */ 3615 #define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC2 Mask */ 3616 3617 #define EPWM_EADCPSC0_EADCPSC3_Pos (24) /*!< EPWM_T::EADCPSC0: EADCPSC3 Position */ 3618 #define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) /*!< EPWM_T::EADCPSC0: EADCPSC3 Mask */ 3619 3620 #define EPWM_EADCPSC1_EADCPSC4_Pos (0) /*!< EPWM_T::EADCPSC1: EADCPSC4 Position */ 3621 #define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC4 Mask */ 3622 3623 #define EPWM_EADCPSC1_EADCPSC5_Pos (8) /*!< EPWM_T::EADCPSC1: EADCPSC5 Position */ 3624 #define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) /*!< EPWM_T::EADCPSC1: EADCPSC5 Mask */ 3625 3626 #define EPWM_EADCPSCNT0_PSCNT0_Pos (0) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Position */ 3627 #define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT0 Mask */ 3628 3629 #define EPWM_EADCPSCNT0_PSCNT1_Pos (8) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Position */ 3630 #define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT1 Mask */ 3631 3632 #define EPWM_EADCPSCNT0_PSCNT2_Pos (16) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Position */ 3633 #define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT2 Mask */ 3634 3635 #define EPWM_EADCPSCNT0_PSCNT3_Pos (24) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Position */ 3636 #define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) /*!< EPWM_T::EADCPSCNT0: PSCNT3 Mask */ 3637 3638 #define EPWM_EADCPSCNT1_PSCNT4_Pos (0) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Position */ 3639 #define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT4 Mask */ 3640 3641 #define EPWM_EADCPSCNT1_PSCNT5_Pos (8) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Position */ 3642 #define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) /*!< EPWM_T::EADCPSCNT1: PSCNT5 Mask */ 3643 3644 #define EPWM_CAPINEN_CAPINEN0_Pos (0) /*!< EPWM_T::CAPINEN: CAPINEN0 Position */ 3645 #define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) /*!< EPWM_T::CAPINEN: CAPINEN0 Mask */ 3646 3647 #define EPWM_CAPINEN_CAPINEN1_Pos (1) /*!< EPWM_T::CAPINEN: CAPINEN1 Position */ 3648 #define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) /*!< EPWM_T::CAPINEN: CAPINEN1 Mask */ 3649 3650 #define EPWM_CAPINEN_CAPINEN2_Pos (2) /*!< EPWM_T::CAPINEN: CAPINEN2 Position */ 3651 #define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) /*!< EPWM_T::CAPINEN: CAPINEN2 Mask */ 3652 3653 #define EPWM_CAPINEN_CAPINEN3_Pos (3) /*!< EPWM_T::CAPINEN: CAPINEN3 Position */ 3654 #define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) /*!< EPWM_T::CAPINEN: CAPINEN3 Mask */ 3655 3656 #define EPWM_CAPINEN_CAPINEN4_Pos (4) /*!< EPWM_T::CAPINEN: CAPINEN4 Position */ 3657 #define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) /*!< EPWM_T::CAPINEN: CAPINEN4 Mask */ 3658 3659 #define EPWM_CAPINEN_CAPINEN5_Pos (5) /*!< EPWM_T::CAPINEN: CAPINEN5 Position */ 3660 #define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) /*!< EPWM_T::CAPINEN: CAPINEN5 Mask */ 3661 3662 #define EPWM_CAPCTL_CAPEN0_Pos (0) /*!< EPWM_T::CAPCTL: CAPEN0 Position */ 3663 #define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) /*!< EPWM_T::CAPCTL: CAPEN0 Mask */ 3664 3665 #define EPWM_CAPCTL_CAPEN1_Pos (1) /*!< EPWM_T::CAPCTL: CAPEN1 Position */ 3666 #define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) /*!< EPWM_T::CAPCTL: CAPEN1 Mask */ 3667 3668 #define EPWM_CAPCTL_CAPEN2_Pos (2) /*!< EPWM_T::CAPCTL: CAPEN2 Position */ 3669 #define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) /*!< EPWM_T::CAPCTL: CAPEN2 Mask */ 3670 3671 #define EPWM_CAPCTL_CAPEN3_Pos (3) /*!< EPWM_T::CAPCTL: CAPEN3 Position */ 3672 #define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) /*!< EPWM_T::CAPCTL: CAPEN3 Mask */ 3673 3674 #define EPWM_CAPCTL_CAPEN4_Pos (4) /*!< EPWM_T::CAPCTL: CAPEN4 Position */ 3675 #define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) /*!< EPWM_T::CAPCTL: CAPEN4 Mask */ 3676 3677 #define EPWM_CAPCTL_CAPEN5_Pos (5) /*!< EPWM_T::CAPCTL: CAPEN5 Position */ 3678 #define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) /*!< EPWM_T::CAPCTL: CAPEN5 Mask */ 3679 3680 #define EPWM_CAPCTL_CAPINV0_Pos (8) /*!< EPWM_T::CAPCTL: CAPINV0 Position */ 3681 #define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) /*!< EPWM_T::CAPCTL: CAPINV0 Mask */ 3682 3683 #define EPWM_CAPCTL_CAPINV1_Pos (9) /*!< EPWM_T::CAPCTL: CAPINV1 Position */ 3684 #define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) /*!< EPWM_T::CAPCTL: CAPINV1 Mask */ 3685 3686 #define EPWM_CAPCTL_CAPINV2_Pos (10) /*!< EPWM_T::CAPCTL: CAPINV2 Position */ 3687 #define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) /*!< EPWM_T::CAPCTL: CAPINV2 Mask */ 3688 3689 #define EPWM_CAPCTL_CAPINV3_Pos (11) /*!< EPWM_T::CAPCTL: CAPINV3 Position */ 3690 #define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) /*!< EPWM_T::CAPCTL: CAPINV3 Mask */ 3691 3692 #define EPWM_CAPCTL_CAPINV4_Pos (12) /*!< EPWM_T::CAPCTL: CAPINV4 Position */ 3693 #define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) /*!< EPWM_T::CAPCTL: CAPINV4 Mask */ 3694 3695 #define EPWM_CAPCTL_CAPINV5_Pos (13) /*!< EPWM_T::CAPCTL: CAPINV5 Position */ 3696 #define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) /*!< EPWM_T::CAPCTL: CAPINV5 Mask */ 3697 3698 #define EPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< EPWM_T::CAPCTL: RCRLDEN0 Position */ 3699 #define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN0 Mask */ 3700 3701 #define EPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< EPWM_T::CAPCTL: RCRLDEN1 Position */ 3702 #define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN1 Mask */ 3703 3704 #define EPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< EPWM_T::CAPCTL: RCRLDEN2 Position */ 3705 #define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN2 Mask */ 3706 3707 #define EPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< EPWM_T::CAPCTL: RCRLDEN3 Position */ 3708 #define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN3 Mask */ 3709 3710 #define EPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< EPWM_T::CAPCTL: RCRLDEN4 Position */ 3711 #define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN4 Mask */ 3712 3713 #define EPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< EPWM_T::CAPCTL: RCRLDEN5 Position */ 3714 #define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: RCRLDEN5 Mask */ 3715 3716 #define EPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< EPWM_T::CAPCTL: FCRLDEN0 Position */ 3717 #define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN0 Mask */ 3718 3719 #define EPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< EPWM_T::CAPCTL: FCRLDEN1 Position */ 3720 #define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN1 Mask */ 3721 3722 #define EPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< EPWM_T::CAPCTL: FCRLDEN2 Position */ 3723 #define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN2 Mask */ 3724 3725 #define EPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< EPWM_T::CAPCTL: FCRLDEN3 Position */ 3726 #define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN3 Mask */ 3727 3728 #define EPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< EPWM_T::CAPCTL: FCRLDEN4 Position */ 3729 #define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN4 Mask */ 3730 3731 #define EPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< EPWM_T::CAPCTL: FCRLDEN5 Position */ 3732 #define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) /*!< EPWM_T::CAPCTL: FCRLDEN5 Mask */ 3733 3734 #define EPWM_CAPSTS_CRLIFOV0_Pos (0) /*!< EPWM_T::CAPSTS: CRLIFOV0 Position */ 3735 #define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV0 Mask */ 3736 3737 #define EPWM_CAPSTS_CRLIFOV1_Pos (1) /*!< EPWM_T::CAPSTS: CRLIFOV1 Position */ 3738 #define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV1 Mask */ 3739 3740 #define EPWM_CAPSTS_CRLIFOV2_Pos (2) /*!< EPWM_T::CAPSTS: CRLIFOV2 Position */ 3741 #define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV2 Mask */ 3742 3743 #define EPWM_CAPSTS_CRLIFOV3_Pos (3) /*!< EPWM_T::CAPSTS: CRLIFOV3 Position */ 3744 #define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV3 Mask */ 3745 3746 #define EPWM_CAPSTS_CRLIFOV4_Pos (4) /*!< EPWM_T::CAPSTS: CRLIFOV4 Position */ 3747 #define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV4 Mask */ 3748 3749 #define EPWM_CAPSTS_CRLIFOV5_Pos (5) /*!< EPWM_T::CAPSTS: CRLIFOV5 Position */ 3750 #define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CRLIFOV5 Mask */ 3751 3752 #define EPWM_CAPSTS_CFLIFOV0_Pos (8) /*!< EPWM_T::CAPSTS: CFLIFOV0 Position */ 3753 #define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV0 Mask */ 3754 3755 #define EPWM_CAPSTS_CFLIFOV1_Pos (9) /*!< EPWM_T::CAPSTS: CFLIFOV1 Position */ 3756 #define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV1 Mask */ 3757 3758 #define EPWM_CAPSTS_CFLIFOV2_Pos (10) /*!< EPWM_T::CAPSTS: CFLIFOV2 Position */ 3759 #define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV2 Mask */ 3760 3761 #define EPWM_CAPSTS_CFLIFOV3_Pos (11) /*!< EPWM_T::CAPSTS: CFLIFOV3 Position */ 3762 #define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV3 Mask */ 3763 3764 #define EPWM_CAPSTS_CFLIFOV4_Pos (12) /*!< EPWM_T::CAPSTS: CFLIFOV4 Position */ 3765 #define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV4 Mask */ 3766 3767 #define EPWM_CAPSTS_CFLIFOV5_Pos (13) /*!< EPWM_T::CAPSTS: CFLIFOV5 Position */ 3768 #define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) /*!< EPWM_T::CAPSTS: CFLIFOV5 Mask */ 3769 3770 #define EPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT0: RCAPDAT Position */ 3771 #define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT0: RCAPDAT Mask */ 3772 3773 #define EPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT0: FCAPDAT Position */ 3774 #define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT0: FCAPDAT Mask */ 3775 3776 #define EPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT1: RCAPDAT Position */ 3777 #define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT1: RCAPDAT Mask */ 3778 3779 #define EPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT1: FCAPDAT Position */ 3780 #define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT1: FCAPDAT Mask */ 3781 3782 #define EPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT2: RCAPDAT Position */ 3783 #define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT2: RCAPDAT Mask */ 3784 3785 #define EPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT2: FCAPDAT Position */ 3786 #define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT2: FCAPDAT Mask */ 3787 3788 #define EPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT3: RCAPDAT Position */ 3789 #define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT3: RCAPDAT Mask */ 3790 3791 #define EPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT3: FCAPDAT Position */ 3792 #define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT3: FCAPDAT Mask */ 3793 3794 #define EPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT4: RCAPDAT Position */ 3795 #define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT4: RCAPDAT Mask */ 3796 3797 #define EPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT4: FCAPDAT Position */ 3798 #define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT4: FCAPDAT Mask */ 3799 3800 #define EPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< EPWM_T::RCAPDAT5: RCAPDAT Position */ 3801 #define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) /*!< EPWM_T::RCAPDAT5: RCAPDAT Mask */ 3802 3803 #define EPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< EPWM_T::FCAPDAT5: FCAPDAT Position */ 3804 #define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) /*!< EPWM_T::FCAPDAT5: FCAPDAT Mask */ 3805 3806 #define EPWM_PDMACTL_CHEN0_1_Pos (0) /*!< EPWM_T::PDMACTL: CHEN0_1 Position */ 3807 #define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) /*!< EPWM_T::PDMACTL: CHEN0_1 Mask */ 3808 3809 #define EPWM_PDMACTL_CAPMOD0_1_Pos (1) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Position */ 3810 #define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPMOD0_1 Mask */ 3811 3812 #define EPWM_PDMACTL_CAPORD0_1_Pos (3) /*!< EPWM_T::PDMACTL: CAPORD0_1 Position */ 3813 #define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) /*!< EPWM_T::PDMACTL: CAPORD0_1 Mask */ 3814 3815 #define EPWM_PDMACTL_CHSEL0_1_Pos (4) /*!< EPWM_T::PDMACTL: CHSEL0_1 Position */ 3816 #define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) /*!< EPWM_T::PDMACTL: CHSEL0_1 Mask */ 3817 3818 #define EPWM_PDMACTL_CHEN2_3_Pos (8) /*!< EPWM_T::PDMACTL: CHEN2_3 Position */ 3819 #define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) /*!< EPWM_T::PDMACTL: CHEN2_3 Mask */ 3820 3821 #define EPWM_PDMACTL_CAPMOD2_3_Pos (9) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Position */ 3822 #define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPMOD2_3 Mask */ 3823 3824 #define EPWM_PDMACTL_CAPORD2_3_Pos (11) /*!< EPWM_T::PDMACTL: CAPORD2_3 Position */ 3825 #define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) /*!< EPWM_T::PDMACTL: CAPORD2_3 Mask */ 3826 3827 #define EPWM_PDMACTL_CHSEL2_3_Pos (12) /*!< EPWM_T::PDMACTL: CHSEL2_3 Position */ 3828 #define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) /*!< EPWM_T::PDMACTL: CHSEL2_3 Mask */ 3829 3830 #define EPWM_PDMACTL_CHEN4_5_Pos (16) /*!< EPWM_T::PDMACTL: CHEN4_5 Position */ 3831 #define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) /*!< EPWM_T::PDMACTL: CHEN4_5 Mask */ 3832 3833 #define EPWM_PDMACTL_CAPMOD4_5_Pos (17) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Position */ 3834 #define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPMOD4_5 Mask */ 3835 3836 #define EPWM_PDMACTL_CAPORD4_5_Pos (19) /*!< EPWM_T::PDMACTL: CAPORD4_5 Position */ 3837 #define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) /*!< EPWM_T::PDMACTL: CAPORD4_5 Mask */ 3838 3839 #define EPWM_PDMACTL_CHSEL4_5_Pos (20) /*!< EPWM_T::PDMACTL: CHSEL4_5 Position */ 3840 #define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) /*!< EPWM_T::PDMACTL: CHSEL4_5 Mask */ 3841 3842 #define EPWM_PDMACAP0_1_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP0_1: CAPBUF Position */ 3843 #define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) /*!< EPWM_T::PDMACAP0_1: CAPBUF Mask */ 3844 3845 #define EPWM_PDMACAP2_3_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP2_3: CAPBUF Position */ 3846 #define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) /*!< EPWM_T::PDMACAP2_3: CAPBUF Mask */ 3847 3848 #define EPWM_PDMACAP4_5_CAPBUF_Pos (0) /*!< EPWM_T::PDMACAP4_5: CAPBUF Position */ 3849 #define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) /*!< EPWM_T::PDMACAP4_5: CAPBUF Mask */ 3850 3851 #define EPWM_CAPIEN_CAPRIEN0_Pos (0) /*!< EPWM_T::CAPIEN: CAPRIEN0 Position */ 3852 #define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN0 Mask */ 3853 3854 #define EPWM_CAPIEN_CAPRIEN1_Pos (1) /*!< EPWM_T::CAPIEN: CAPRIEN1 Position */ 3855 #define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN1 Mask */ 3856 3857 #define EPWM_CAPIEN_CAPRIEN2_Pos (2) /*!< EPWM_T::CAPIEN: CAPRIEN2 Position */ 3858 #define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN2 Mask */ 3859 3860 #define EPWM_CAPIEN_CAPRIEN3_Pos (3) /*!< EPWM_T::CAPIEN: CAPRIEN3 Position */ 3861 #define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN3 Mask */ 3862 3863 #define EPWM_CAPIEN_CAPRIEN4_Pos (4) /*!< EPWM_T::CAPIEN: CAPRIEN4 Position */ 3864 #define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN4 Mask */ 3865 3866 #define EPWM_CAPIEN_CAPRIEN5_Pos (5) /*!< EPWM_T::CAPIEN: CAPRIEN5 Position */ 3867 #define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPRIEN5 Mask */ 3868 3869 #define EPWM_CAPIEN_CAPFIEN0_Pos (8) /*!< EPWM_T::CAPIEN: CAPFIEN0 Position */ 3870 #define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN0 Mask */ 3871 3872 #define EPWM_CAPIEN_CAPFIEN1_Pos (9) /*!< EPWM_T::CAPIEN: CAPFIEN1 Position */ 3873 #define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN1 Mask */ 3874 3875 #define EPWM_CAPIEN_CAPFIEN2_Pos (10) /*!< EPWM_T::CAPIEN: CAPFIEN2 Position */ 3876 #define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN2 Mask */ 3877 3878 #define EPWM_CAPIEN_CAPFIEN3_Pos (11) /*!< EPWM_T::CAPIEN: CAPFIEN3 Position */ 3879 #define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN3 Mask */ 3880 3881 #define EPWM_CAPIEN_CAPFIEN4_Pos (12) /*!< EPWM_T::CAPIEN: CAPFIEN4 Position */ 3882 #define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN4 Mask */ 3883 3884 #define EPWM_CAPIEN_CAPFIEN5_Pos (13) /*!< EPWM_T::CAPIEN: CAPFIEN5 Position */ 3885 #define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) /*!< EPWM_T::CAPIEN: CAPFIEN5 Mask */ 3886 3887 #define EPWM_CAPIF_CRLIF0_Pos (0) /*!< EPWM_T::CAPIF: CRLIF0 Position */ 3888 #define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) /*!< EPWM_T::CAPIF: CRLIF0 Mask */ 3889 3890 #define EPWM_CAPIF_CRLIF1_Pos (1) /*!< EPWM_T::CAPIF: CRLIF1 Position */ 3891 #define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) /*!< EPWM_T::CAPIF: CRLIF1 Mask */ 3892 3893 #define EPWM_CAPIF_CRLIF2_Pos (2) /*!< EPWM_T::CAPIF: CRLIF2 Position */ 3894 #define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) /*!< EPWM_T::CAPIF: CRLIF2 Mask */ 3895 3896 #define EPWM_CAPIF_CRLIF3_Pos (3) /*!< EPWM_T::CAPIF: CRLIF3 Position */ 3897 #define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) /*!< EPWM_T::CAPIF: CRLIF3 Mask */ 3898 3899 #define EPWM_CAPIF_CRLIF4_Pos (4) /*!< EPWM_T::CAPIF: CRLIF4 Position */ 3900 #define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) /*!< EPWM_T::CAPIF: CRLIF4 Mask */ 3901 3902 #define EPWM_CAPIF_CRLIF5_Pos (5) /*!< EPWM_T::CAPIF: CRLIF5 Position */ 3903 #define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) /*!< EPWM_T::CAPIF: CRLIF5 Mask */ 3904 3905 #define EPWM_CAPIF_CFLIF0_Pos (8) /*!< EPWM_T::CAPIF: CFLIF0 Position */ 3906 #define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) /*!< EPWM_T::CAPIF: CFLIF0 Mask */ 3907 3908 #define EPWM_CAPIF_CFLIF1_Pos (9) /*!< EPWM_T::CAPIF: CFLIF1 Position */ 3909 #define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) /*!< EPWM_T::CAPIF: CFLIF1 Mask */ 3910 3911 #define EPWM_CAPIF_CFLIF2_Pos (10) /*!< EPWM_T::CAPIF: CFLIF2 Position */ 3912 #define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) /*!< EPWM_T::CAPIF: CFLIF2 Mask */ 3913 3914 #define EPWM_CAPIF_CFLIF3_Pos (11) /*!< EPWM_T::CAPIF: CFLIF3 Position */ 3915 #define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) /*!< EPWM_T::CAPIF: CFLIF3 Mask */ 3916 3917 #define EPWM_CAPIF_CFLIF4_Pos (12) /*!< EPWM_T::CAPIF: CFLIF4 Position */ 3918 #define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) /*!< EPWM_T::CAPIF: CFLIF4 Mask */ 3919 3920 #define EPWM_CAPIF_CFLIF5_Pos (13) /*!< EPWM_T::CAPIF: CFLIF5 Position */ 3921 #define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) /*!< EPWM_T::CAPIF: CFLIF5 Mask */ 3922 3923 #define EPWM_PBUF0_PBUF_Pos (0) /*!< EPWM_T::PBUF0: PBUF Position */ 3924 #define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) /*!< EPWM_T::PBUF0: PBUF Mask */ 3925 3926 #define EPWM_PBUF1_PBUF_Pos (0) /*!< EPWM_T::PBUF1: PBUF Position */ 3927 #define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) /*!< EPWM_T::PBUF1: PBUF Mask */ 3928 3929 #define EPWM_PBUF2_PBUF_Pos (0) /*!< EPWM_T::PBUF2: PBUF Position */ 3930 #define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) /*!< EPWM_T::PBUF2: PBUF Mask */ 3931 3932 #define EPWM_PBUF3_PBUF_Pos (0) /*!< EPWM_T::PBUF3: PBUF Position */ 3933 #define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) /*!< EPWM_T::PBUF3: PBUF Mask */ 3934 3935 #define EPWM_PBUF4_PBUF_Pos (0) /*!< EPWM_T::PBUF4: PBUF Position */ 3936 #define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) /*!< EPWM_T::PBUF4: PBUF Mask */ 3937 3938 #define EPWM_PBUF5_PBUF_Pos (0) /*!< EPWM_T::PBUF5: PBUF Position */ 3939 #define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) /*!< EPWM_T::PBUF5: PBUF Mask */ 3940 3941 #define EPWM_CMPBUF0_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF0: CMPBUF Position */ 3942 #define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) /*!< EPWM_T::CMPBUF0: CMPBUF Mask */ 3943 3944 #define EPWM_CMPBUF1_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF1: CMPBUF Position */ 3945 #define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) /*!< EPWM_T::CMPBUF1: CMPBUF Mask */ 3946 3947 #define EPWM_CMPBUF2_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF2: CMPBUF Position */ 3948 #define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) /*!< EPWM_T::CMPBUF2: CMPBUF Mask */ 3949 3950 #define EPWM_CMPBUF3_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF3: CMPBUF Position */ 3951 #define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) /*!< EPWM_T::CMPBUF3: CMPBUF Mask */ 3952 3953 #define EPWM_CMPBUF4_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF4: CMPBUF Position */ 3954 #define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) /*!< EPWM_T::CMPBUF4: CMPBUF Mask */ 3955 3956 #define EPWM_CMPBUF5_CMPBUF_Pos (0) /*!< EPWM_T::CMPBUF5: CMPBUF Position */ 3957 #define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) /*!< EPWM_T::CMPBUF5: CMPBUF Mask */ 3958 3959 #define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Position */ 3960 #define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF0_1: CPSCBUF Mask */ 3961 3962 #define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Position */ 3963 #define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF2_3: CPSCBUF Mask */ 3964 3965 #define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Position */ 3966 #define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) /*!< EPWM_T::CPSCBUF4_5: CPSCBUF Mask */ 3967 3968 #define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Position */ 3969 #define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF0_1: FTCMPBUF Mask */ 3970 3971 #define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Position */ 3972 #define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF2_3: FTCMPBUF Mask */ 3973 3974 #define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Position */ 3975 #define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) /*!< EPWM_T::FTCBUF4_5: FTCMPBUF Mask */ 3976 3977 #define EPWM_FTCI_FTCMU0_Pos (0) /*!< EPWM_T::FTCI: FTCMU0 Position */ 3978 #define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) /*!< EPWM_T::FTCI: FTCMU0 Mask */ 3979 3980 #define EPWM_FTCI_FTCMU2_Pos (1) /*!< EPWM_T::FTCI: FTCMU2 Position */ 3981 #define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) /*!< EPWM_T::FTCI: FTCMU2 Mask */ 3982 3983 #define EPWM_FTCI_FTCMU4_Pos (2) /*!< EPWM_T::FTCI: FTCMU4 Position */ 3984 #define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) /*!< EPWM_T::FTCI: FTCMU4 Mask */ 3985 3986 #define EPWM_FTCI_FTCMD0_Pos (8) /*!< EPWM_T::FTCI: FTCMD0 Position */ 3987 #define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) /*!< EPWM_T::FTCI: FTCMD0 Mask */ 3988 3989 #define EPWM_FTCI_FTCMD2_Pos (9) /*!< EPWM_T::FTCI: FTCMD2 Position */ 3990 #define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) /*!< EPWM_T::FTCI: FTCMD2 Mask */ 3991 3992 #define EPWM_FTCI_FTCMD4_Pos (10) /*!< EPWM_T::FTCI: FTCMD4 Position */ 3993 #define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) /*!< EPWM_T::FTCI: FTCMD4 Mask */ 3994 3995 /**@}*/ /* EPWM_CONST */ 3996 /**@}*/ /* end of EPWM register group */ 3997 /**@}*/ /* end of REGISTER group */ 3998 3999 4000 4001 #endif /* __EPWM_REG_H__ */ 4002
