1 /**************************************************************************//** 2 * @file bpwm_reg.h 3 * @version V1.00 4 * @brief BPWM register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __BPWM_REG_H__ 10 #define __BPWM_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- Basic Pulse Width Modulation Controller -------------------------*/ 20 /** 21 @addtogroup BPWM Basic Pulse Width Modulation Controller(BPWM) 22 Memory Mapped Structure for BPWM Controller 23 @{ 24 */ 25 26 typedef struct 27 { 28 /** 29 * @var BCAPDAT_T::RCAPDAT 30 * Offset: 0x20C BPWM Rising Capture Data Register 0~5 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[15:0] |RCAPDAT |BPWM Rising Capture Data (Read Only) 35 * | | |When rising capture condition happened, the BPWM counter value will be saved in this register. 36 * @var BCAPDAT_T::FCAPDAT 37 * Offset: 0x210 BPWM Falling Capture Data Register 0~5 38 * --------------------------------------------------------------------------------------------------- 39 * |Bits |Field |Descriptions 40 * | :----: | :----: | :---- | 41 * |[15:0] |FCAPDAT |BPWM Falling Capture Data (Read Only) 42 * | | |When falling capture condition happened, the BPWM counter value will be saved in this register. 43 */ 44 __IO uint32_t RCAPDAT; /*!< [0x20C/0x214/0x21C/0x224/0x22C/0x234] BPWM Rising Capture Data Register 0~5 */ 45 __IO uint32_t FCAPDAT; /*!< [0x210/0x218/0x220/0x228/0x230/0x238] BPWM Falling Capture Data Register 0~5 */ 46 } BCAPDAT_T; 47 48 49 typedef struct 50 { 51 /** 52 * @var BPWM_T::CTL0 53 * Offset: 0x00 BPWM Control Register 0 54 * --------------------------------------------------------------------------------------------------- 55 * |Bits |Field |Descriptions 56 * | :----: | :----: | :---- | 57 * |[0] |CTRLD0 |Center Re-load 58 * | | |Each bit n controls the corresponding BPWM channel n. 59 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 60 * | | |CMPDAT will load to CMPBUF at the center point of a period 61 * |[1] |CTRLD1 |Center Re-load 62 * | | |Each bit n controls the corresponding BPWM channel n. 63 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 64 * | | |CMPDAT will load to CMPBUF at the center point of a period 65 * |[2] |CTRLD2 |Center Re-load 66 * | | |Each bit n controls the corresponding BPWM channel n. 67 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 68 * | | |CMPDAT will load to CMPBUF at the center point of a period 69 * |[3] |CTRLD3 |Center Re-load 70 * | | |Each bit n controls the corresponding BPWM channel n. 71 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 72 * | | |CMPDAT will load to CMPBUF at the center point of a period 73 * |[4] |CTRLD4 |Center Re-load 74 * | | |Each bit n controls the corresponding BPWM channel n. 75 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 76 * | | |CMPDAT will load to CMPBUF at the center point of a period 77 * |[5] |CTRLD5 |Center Re-load 78 * | | |Each bit n controls the corresponding BPWM channel n. 79 * | | |In up-down counter type, PERIOD will load to PBUF at the end point of each period 80 * | | |CMPDAT will load to CMPBUF at the center point of a period 81 * |[16] |IMMLDEN0 |Immediately Load Enable Bit(S) 82 * | | |Each bit n controls the corresponding BPWM channel n. 83 * | | |0 = PERIOD will load to PBUF at the end point of each period 84 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 85 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 86 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 87 * |[17] |IMMLDEN1 |Immediately Load Enable Bit(S) 88 * | | |Each bit n controls the corresponding BPWM channel n. 89 * | | |0 = PERIOD will load to PBUF at the end point of each period 90 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 91 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 92 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 93 * |[18] |IMMLDEN2 |Immediately Load Enable Bit(S) 94 * | | |Each bit n controls the corresponding BPWM channel n. 95 * | | |0 = PERIOD will load to PBUF at the end point of each period 96 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 97 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 98 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 99 * |[19] |IMMLDEN3 |Immediately Load Enable Bit(S) 100 * | | |Each bit n controls the corresponding BPWM channel n. 101 * | | |0 = PERIOD will load to PBUF at the end point of each period 102 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 103 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 104 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 105 * |[20] |IMMLDEN4 |Immediately Load Enable Bit(S) 106 * | | |Each bit n controls the corresponding BPWM channel n. 107 * | | |0 = PERIOD will load to PBUF at the end point of each period 108 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 109 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 110 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 111 * |[21] |IMMLDEN5 |Immediately Load Enable Bit(S) 112 * | | |Each bit n controls the corresponding BPWM channel n. 113 * | | |0 = PERIOD will load to PBUF at the end point of each period 114 * | | |CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit. 115 * | | |1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT. 116 * | | |Note: If IMMLDENn is Enabled, WINLDENn and CTRLDn will be invalid. 117 * |[30] |DBGHALT |ICE Debug Mode Counter Halt (Write Protect) 118 * | | |If counter halt is enabled, BPWM all counters will keep current value until exit ICE debug mode. 119 * | | |0 = ICE debug mode counter halt Disable. 120 * | | |1 = ICE debug mode counter halt Enable. 121 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 122 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable (Write Protect) 123 * | | |0 = ICE debug mode acknowledgement effects BPWM output. 124 * | | |BPWM pin will be forced as tri-state while ICE debug mode acknowledged. 125 * | | |1 = ICE debug mode acknowledgement Disabled. 126 * | | |BPWM pin will keep output no matter ICE debug mode acknowledged or not. 127 * | | |Note: This register is write protected. Refer to SYS_REGLCTL register. 128 * @var BPWM_T::CTL1 129 * Offset: 0x04 BPWM Control Register 1 130 * --------------------------------------------------------------------------------------------------- 131 * |Bits |Field |Descriptions 132 * | :----: | :----: | :---- | 133 * |[1:0] |CNTTYPE0 |BPWM Counter Behavior Type 0 134 * | | |Each bit n controls corresponding BPWM channel n. 135 * | | |00 = Up counter type (supports in capture mode). 136 * | | |01 = Down count type (supports in capture mode). 137 * | | |10 = Up-down counter type. 138 * | | |11 = Reserved. 139 * @var BPWM_T::CLKSRC 140 * Offset: 0x10 BPWM Clock Source Register 141 * --------------------------------------------------------------------------------------------------- 142 * |Bits |Field |Descriptions 143 * | :----: | :----: | :---- | 144 * |[2:0] |ECLKSRC0 |BPWM_CH01 External Clock Source Select 145 * | | |000 = BPWMx_CLK, x denotes 0 or 1. 146 * | | |001 = TIMER0 overflow. 147 * | | |010 = TIMER1 overflow. 148 * | | |011 = TIMER2 overflow. 149 * | | |100 = TIMER3 overflow. 150 * | | |Others = Reserved. 151 * @var BPWM_T::CLKPSC 152 * Offset: 0x14 BPWM Clock Prescale Register 153 * --------------------------------------------------------------------------------------------------- 154 * |Bits |Field |Descriptions 155 * | :----: | :----: | :---- | 156 * |[11:0] |CLKPSC |BPWM Counter Clock Prescale 157 * | | |The clock of BPWM counter is decided by clock prescaler 158 * | | |Each BPWM pair share one BPWM counter clock prescaler 159 * | | |The clock of BPWM counter is divided by (CLKPSC+ 1) 160 * @var BPWM_T::CNTEN 161 * Offset: 0x20 BPWM Counter Enable Register 162 * --------------------------------------------------------------------------------------------------- 163 * |Bits |Field |Descriptions 164 * | :----: | :----: | :---- | 165 * |[0] |CNTEN0 |BPWM Counter 0 Enable Bit 166 * | | |0 = BPWM Counter and clock prescaler stop running. 167 * | | |1 = BPWM Counter and clock prescaler start running. 168 * @var BPWM_T::CNTCLR 169 * Offset: 0x24 BPWM Clear Counter Register 170 * --------------------------------------------------------------------------------------------------- 171 * |Bits |Field |Descriptions 172 * | :----: | :----: | :---- | 173 * |[0] |CNTCLR0 |Clear BPWM Counter Control Bit 0 174 * | | |It is automatically cleared by hardware. 175 * | | |0 = No effect. 176 * | | |1 = Clear 16-bit BPWM counter to 0000H. 177 * @var BPWM_T::PERIOD 178 * Offset: 0x30 BPWM Period Register 179 * --------------------------------------------------------------------------------------------------- 180 * |Bits |Field |Descriptions 181 * | :----: | :----: | :---- | 182 * |[15:0] |PERIOD |BPWM Period Register 183 * | | |Up-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, and restarts from 0. 184 * | | |Down-Count mode: In this mode, BPWM counter counts from PERIOD to 0, and restarts from PERIOD. 185 * | | |BPWM period time = (PERIOD+1) * BPWM_CLK period. 186 * | | |Up-Down-Count mode: In this mode, BPWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again. 187 * | | |BPWM period time = 2 * PERIOD * BPWM_CLK period. 188 * @var BPWM_T::CMPDAT[6] 189 * Offset: 0x50 BPWM Comparator Register 0~5 190 * --------------------------------------------------------------------------------------------------- 191 * |Bits |Field |Descriptions 192 * | :----: | :----: | :---- | 193 * |[15:0] |CMPDAT |BPWM Comparator Register 194 * | | |CMPDAT use to compare with CNTR to generate BPWM waveform, interrupt and trigger EADC. 195 * | | |In independent mode, CMPDAT0~5 denote as 6 independent BPWM_CH0~5 compared point. 196 * @var BPWM_T::CNT 197 * Offset: 0x90 BPWM Counter Register 198 * --------------------------------------------------------------------------------------------------- 199 * |Bits |Field |Descriptions 200 * | :----: | :----: | :---- | 201 * |[15:0] |CNT |BPWM Data Register (Read Only) 202 * | | |User can monitor CNTR to know the current value in 16-bit period counter. 203 * |[16] |DIRF |BPWM Direction Indicator Flag (Read Only) 204 * | | |0 = Counter is Down count. 205 * | | |1 = Counter is UP count. 206 * @var BPWM_T::WGCTL0 207 * Offset: 0xB0 BPWM Generation Register 0 208 * --------------------------------------------------------------------------------------------------- 209 * |Bits |Field |Descriptions 210 * | :----: | :----: | :---- | 211 * |[1:0] |ZPCTL0 |BPWM Zero Point Control 212 * | | |Each bit n controls the corresponding BPWM channel n. 213 * | | |00 = Do nothing. 214 * | | |01 = BPWM zero point output Low. 215 * | | |10 = BPWM zero point output High. 216 * | | |11 = BPWM zero point output Toggle. 217 * | | |BPWM can control output level when BPWM counter count to zero. 218 * |[3:2] |ZPCTL1 |BPWM Zero Point Control 219 * | | |Each bit n controls the corresponding BPWM channel n. 220 * | | |00 = Do nothing. 221 * | | |01 = BPWM zero point output Low. 222 * | | |10 = BPWM zero point output High. 223 * | | |11 = BPWM zero point output Toggle. 224 * | | |BPWM can control output level when BPWM counter count to zero. 225 * |[5:4] |ZPCTL2 |BPWM Zero Point Control 226 * | | |Each bit n controls the corresponding BPWM channel n. 227 * | | |00 = Do nothing. 228 * | | |01 = BPWM zero point output Low. 229 * | | |10 = BPWM zero point output High. 230 * | | |11 = BPWM zero point output Toggle. 231 * | | |BPWM can control output level when BPWM counter count to zero. 232 * |[7:6] |ZPCTL3 |BPWM Zero Point Control 233 * | | |Each bit n controls the corresponding BPWM channel n. 234 * | | |00 = Do nothing. 235 * | | |01 = BPWM zero point output Low. 236 * | | |10 = BPWM zero point output High. 237 * | | |11 = BPWM zero point output Toggle. 238 * | | |BPWM can control output level when BPWM counter count to zero. 239 * |[9:8] |ZPCTL4 |BPWM Zero Point Control 240 * | | |Each bit n controls the corresponding BPWM channel n. 241 * | | |00 = Do nothing. 242 * | | |01 = BPWM zero point output Low. 243 * | | |10 = BPWM zero point output High. 244 * | | |11 = BPWM zero point output Toggle. 245 * | | |BPWM can control output level when BPWM counter count to zero. 246 * |[11:10] |ZPCTL5 |BPWM Zero Point Control 247 * | | |Each bit n controls the corresponding BPWM channel n. 248 * | | |00 = Do nothing. 249 * | | |01 = BPWM zero point output Low. 250 * | | |10 = BPWM zero point output High. 251 * | | |11 = BPWM zero point output Toggle. 252 * | | |BPWM can control output level when BPWM counter count to zero. 253 * |[17:16] |PRDPCTL0 |BPWM Period (Center) Point Control 254 * | | |Each bit n controls the corresponding BPWM channel n. 255 * | | |00 = Do nothing. 256 * | | |01 = BPWM period (center) point output Low. 257 * | | |10 = BPWM period (center) point output High. 258 * | | |11 = BPWM period (center) point output Toggle. 259 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 260 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 261 * |[19:18] |PRDPCTL1 |BPWM Period (Center) Point Control 262 * | | |Each bit n controls the corresponding BPWM channel n. 263 * | | |00 = Do nothing. 264 * | | |01 = BPWM period (center) point output Low. 265 * | | |10 = BPWM period (center) point output High. 266 * | | |11 = BPWM period (center) point output Toggle. 267 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 268 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 269 * |[21:20] |PRDPCTL2 |BPWM Period (Center) Point Control 270 * | | |Each bit n controls the corresponding BPWM channel n. 271 * | | |00 = Do nothing. 272 * | | |01 = BPWM period (center) point output Low. 273 * | | |10 = BPWM period (center) point output High. 274 * | | |11 = BPWM period (center) point output Toggle. 275 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 276 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 277 * |[23:22] |PRDPCTL3 |BPWM Period (Center) Point Control 278 * | | |Each bit n controls the corresponding BPWM channel n. 279 * | | |00 = Do nothing. 280 * | | |01 = BPWM period (center) point output Low. 281 * | | |10 = BPWM period (center) point output High. 282 * | | |11 = BPWM period (center) point output Toggle. 283 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 284 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 285 * |[25:24] |PRDPCTL4 |BPWM Period (Center) Point Control 286 * | | |Each bit n controls the corresponding BPWM channel n. 287 * | | |00 = Do nothing. 288 * | | |01 = BPWM period (center) point output Low. 289 * | | |10 = BPWM period (center) point output High. 290 * | | |11 = BPWM period (center) point output Toggle. 291 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 292 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 293 * |[27:26] |PRDPCTL5 |BPWM Period (Center) Point Control 294 * | | |Each bit n controls the corresponding BPWM channel n. 295 * | | |00 = Do nothing. 296 * | | |01 = BPWM period (center) point output Low. 297 * | | |10 = BPWM period (center) point output High. 298 * | | |11 = BPWM period (center) point output Toggle. 299 * | | |BPWM can control output level when BPWM counter count to (PERIOD+1). 300 * | | |Note: This bit is center point control when BPWM counter operating in up-down counter type. 301 * @var BPWM_T::WGCTL1 302 * Offset: 0xB4 BPWM Generation Register 1 303 * --------------------------------------------------------------------------------------------------- 304 * |Bits |Field |Descriptions 305 * | :----: | :----: | :---- | 306 * |[1:0] |CMPUCTL0 |BPWM Compare Up Point Control 307 * | | |Each bit n controls the corresponding BPWM channel n. 308 * | | |00 = Do nothing. 309 * | | |01 = BPWM compare up point output Low. 310 * | | |10 = BPWM compare up point output High. 311 * | | |11 = BPWM compare up point output Toggle. 312 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 313 * |[3:2] |CMPUCTL1 |BPWM Compare Up Point Control 314 * | | |Each bit n controls the corresponding BPWM channel n. 315 * | | |00 = Do nothing. 316 * | | |01 = BPWM compare up point output Low. 317 * | | |10 = BPWM compare up point output High. 318 * | | |11 = BPWM compare up point output Toggle. 319 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 320 * |[5:4] |CMPUCTL2 |BPWM Compare Up Point Control 321 * | | |Each bit n controls the corresponding BPWM channel n. 322 * | | |00 = Do nothing. 323 * | | |01 = BPWM compare up point output Low. 324 * | | |10 = BPWM compare up point output High. 325 * | | |11 = BPWM compare up point output Toggle. 326 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 327 * |[7:6] |CMPUCTL3 |BPWM Compare Up Point Control 328 * | | |Each bit n controls the corresponding BPWM channel n. 329 * | | |00 = Do nothing. 330 * | | |01 = BPWM compare up point output Low. 331 * | | |10 = BPWM compare up point output High. 332 * | | |11 = BPWM compare up point output Toggle. 333 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 334 * |[9:8] |CMPUCTL4 |BPWM Compare Up Point Control 335 * | | |Each bit n controls the corresponding BPWM channel n. 336 * | | |00 = Do nothing. 337 * | | |01 = BPWM compare up point output Low. 338 * | | |10 = BPWM compare up point output High. 339 * | | |11 = BPWM compare up point output Toggle. 340 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 341 * |[11:10] |CMPUCTL5 |BPWM Compare Up Point Control 342 * | | |Each bit n controls the corresponding BPWM channel n. 343 * | | |00 = Do nothing. 344 * | | |01 = BPWM compare up point output Low. 345 * | | |10 = BPWM compare up point output High. 346 * | | |11 = BPWM compare up point output Toggle. 347 * | | |BPWM can control output level when BPWM counter up count to CMPDAT. 348 * |[17:16] |CMPDCTL0 |BPWM Compare Down Point Control 349 * | | |Each bit n controls the corresponding BPWM channel n. 350 * | | |00 = Do nothing. 351 * | | |01 = BPWM compare down point output Low. 352 * | | |10 = BPWM compare down point output High. 353 * | | |11 = BPWM compare down point output Toggle. 354 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 355 * |[19:18] |CMPDCTL1 |BPWM Compare Down Point Control 356 * | | |Each bit n controls the corresponding BPWM channel n. 357 * | | |00 = Do nothing. 358 * | | |01 = BPWM compare down point output Low. 359 * | | |10 = BPWM compare down point output High. 360 * | | |11 = BPWM compare down point output Toggle. 361 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 362 * |[21:20] |CMPDCTL2 |BPWM Compare Down Point Control 363 * | | |Each bit n controls the corresponding BPWM channel n. 364 * | | |00 = Do nothing. 365 * | | |01 = BPWM compare down point output Low. 366 * | | |10 = BPWM compare down point output High. 367 * | | |11 = BPWM compare down point output Toggle. 368 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 369 * |[23:22] |CMPDCTL3 |BPWM Compare Down Point Control 370 * | | |Each bit n controls the corresponding BPWM channel n. 371 * | | |00 = Do nothing. 372 * | | |01 = BPWM compare down point output Low. 373 * | | |10 = BPWM compare down point output High. 374 * | | |11 = BPWM compare down point output Toggle. 375 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 376 * |[25:24] |CMPDCTL4 |BPWM Compare Down Point Control 377 * | | |Each bit n controls the corresponding BPWM channel n. 378 * | | |00 = Do nothing. 379 * | | |01 = BPWM compare down point output Low. 380 * | | |10 = BPWM compare down point output High. 381 * | | |11 = BPWM compare down point output Toggle. 382 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 383 * |[27:26] |CMPDCTL5 |BPWM Compare Down Point Control 384 * | | |Each bit n controls the corresponding BPWM channel n. 385 * | | |00 = Do nothing. 386 * | | |01 = BPWM compare down point output Low. 387 * | | |10 = BPWM compare down point output High. 388 * | | |11 = BPWM compare down point output Toggle. 389 * | | |BPWM can control output level when BPWM counter down count to CMPDAT. 390 * @var BPWM_T::MSKEN 391 * Offset: 0xB8 BPWM Mask Enable Register 392 * --------------------------------------------------------------------------------------------------- 393 * |Bits |Field |Descriptions 394 * | :----: | :----: | :---- | 395 * |[0] |MSKEN0 |BPWM Mask Enable Bits 396 * | | |Each bit n controls the corresponding BPWM channel n. 397 * | | |The BPWM output signal will be masked when this bit is enabled 398 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 399 * | | |0 = BPWM output signal is non-masked. 400 * | | |1 = BPWM output signal is masked and output MSKDATn data. 401 * |[1] |MSKEN1 |BPWM Mask Enable Bits 402 * | | |Each bit n controls the corresponding BPWM channel n. 403 * | | |The BPWM output signal will be masked when this bit is enabled 404 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 405 * | | |0 = BPWM output signal is non-masked. 406 * | | |1 = BPWM output signal is masked and output MSKDATn data. 407 * |[2] |MSKEN2 |BPWM Mask Enable Bits 408 * | | |Each bit n controls the corresponding BPWM channel n. 409 * | | |The BPWM output signal will be masked when this bit is enabled 410 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 411 * | | |0 = BPWM output signal is non-masked. 412 * | | |1 = BPWM output signal is masked and output MSKDATn data. 413 * |[3] |MSKEN3 |BPWM Mask Enable Bits 414 * | | |Each bit n controls the corresponding BPWM channel n. 415 * | | |The BPWM output signal will be masked when this bit is enabled 416 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 417 * | | |0 = BPWM output signal is non-masked. 418 * | | |1 = BPWM output signal is masked and output MSKDATn data. 419 * |[4] |MSKEN4 |BPWM Mask Enable Bits 420 * | | |Each bit n controls the corresponding BPWM channel n. 421 * | | |The BPWM output signal will be masked when this bit is enabled 422 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 423 * | | |0 = BPWM output signal is non-masked. 424 * | | |1 = BPWM output signal is masked and output MSKDATn data. 425 * |[5] |MSKEN5 |BPWM Mask Enable Bits 426 * | | |Each bit n controls the corresponding BPWM channel n. 427 * | | |The BPWM output signal will be masked when this bit is enabled 428 * | | |The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data. 429 * | | |0 = BPWM output signal is non-masked. 430 * | | |1 = BPWM output signal is masked and output MSKDATn data. 431 * @var BPWM_T::MSK 432 * Offset: 0xBC BPWM Mask Data Register 433 * --------------------------------------------------------------------------------------------------- 434 * |Bits |Field |Descriptions 435 * | :----: | :----: | :---- | 436 * |[0] |MSKDAT0 |BPWM Mask Data Bit 437 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 438 * | | |Each bit n controls the corresponding BPWM channel n. 439 * | | |0 = Output logic low to BPWMn. 440 * | | |1 = Output logic high to BPWMn. 441 * |[1] |MSKDAT1 |BPWM Mask Data Bit 442 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 443 * | | |Each bit n controls the corresponding BPWM channel n. 444 * | | |0 = Output logic low to BPWMn. 445 * | | |1 = Output logic high to BPWMn. 446 * |[2] |MSKDAT2 |BPWM Mask Data Bit 447 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 448 * | | |Each bit n controls the corresponding BPWM channel n. 449 * | | |0 = Output logic low to BPWMn. 450 * | | |1 = Output logic high to BPWMn. 451 * |[3] |MSKDAT3 |BPWM Mask Data Bit 452 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 453 * | | |Each bit n controls the corresponding BPWM channel n. 454 * | | |0 = Output logic low to BPWMn. 455 * | | |1 = Output logic high to BPWMn. 456 * |[4] |MSKDAT4 |BPWM Mask Data Bit 457 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 458 * | | |Each bit n controls the corresponding BPWM channel n. 459 * | | |0 = Output logic low to BPWMn. 460 * | | |1 = Output logic high to BPWMn. 461 * |[5] |MSKDAT5 |BPWM Mask Data Bit 462 * | | |This data bit control the state of BPWMn output pin, if corresponding mask function is enabled 463 * | | |Each bit n controls the corresponding BPWM channel n. 464 * | | |0 = Output logic low to BPWMn. 465 * | | |1 = Output logic high to BPWMn. 466 * @var BPWM_T::POLCTL 467 * Offset: 0xD4 BPWM Pin Polar Inverse Register 468 * --------------------------------------------------------------------------------------------------- 469 * |Bits |Field |Descriptions 470 * | :----: | :----: | :---- | 471 * |[0] |PINV0 |BPWM PIN Polar Inverse Control 472 * | | |The register controls polarity state of BPWM output 473 * | | |Each bit n controls the corresponding BPWM channel n. 474 * | | |0 = BPWM output polar inverse Disabled. 475 * | | |1 = BPWM output polar inverse Enabled. 476 * |[1] |PINV1 |BPWM PIN Polar Inverse Control 477 * | | |The register controls polarity state of BPWM output 478 * | | |Each bit n controls the corresponding BPWM channel n. 479 * | | |0 = BPWM output polar inverse Disabled. 480 * | | |1 = BPWM output polar inverse Enabled. 481 * |[2] |PINV2 |BPWM PIN Polar Inverse Control 482 * | | |The register controls polarity state of BPWM output 483 * | | |Each bit n controls the corresponding BPWM channel n. 484 * | | |0 = BPWM output polar inverse Disabled. 485 * | | |1 = BPWM output polar inverse Enabled. 486 * |[3] |PINV3 |BPWM PIN Polar Inverse Control 487 * | | |The register controls polarity state of BPWM output 488 * | | |Each bit n controls the corresponding BPWM channel n. 489 * | | |0 = BPWM output polar inverse Disabled. 490 * | | |1 = BPWM output polar inverse Enabled. 491 * |[4] |PINV4 |BPWM PIN Polar Inverse Control 492 * | | |The register controls polarity state of BPWM output 493 * | | |Each bit n controls the corresponding BPWM channel n. 494 * | | |0 = BPWM output polar inverse Disabled. 495 * | | |1 = BPWM output polar inverse Enabled. 496 * |[5] |PINV5 |BPWM PIN Polar Inverse Control 497 * | | |The register controls polarity state of BPWM output 498 * | | |Each bit n controls the corresponding BPWM channel n. 499 * | | |0 = BPWM output polar inverse Disabled. 500 * | | |1 = BPWM output polar inverse Enabled. 501 * @var BPWM_T::POEN 502 * Offset: 0xD8 BPWM Output Enable Register 503 * --------------------------------------------------------------------------------------------------- 504 * |Bits |Field |Descriptions 505 * | :----: | :----: | :---- | 506 * |[0] |POEN0 |BPWM Pin Output Enable Bits 507 * | | |Each bit n controls the corresponding BPWM channel n. 508 * | | |0 = BPWM pin at tri-state. 509 * | | |1 = BPWM pin in output mode. 510 * |[1] |POEN1 |BPWM Pin Output Enable Bits 511 * | | |Each bit n controls the corresponding BPWM channel n. 512 * | | |0 = BPWM pin at tri-state. 513 * | | |1 = BPWM pin in output mode. 514 * |[2] |POEN2 |BPWM Pin Output Enable Bits 515 * | | |Each bit n controls the corresponding BPWM channel n. 516 * | | |0 = BPWM pin at tri-state. 517 * | | |1 = BPWM pin in output mode. 518 * |[3] |POEN3 |BPWM Pin Output Enable Bits 519 * | | |Each bit n controls the corresponding BPWM channel n. 520 * | | |0 = BPWM pin at tri-state. 521 * | | |1 = BPWM pin in output mode. 522 * |[4] |POEN4 |BPWM Pin Output Enable Bits 523 * | | |Each bit n controls the corresponding BPWM channel n. 524 * | | |0 = BPWM pin at tri-state. 525 * | | |1 = BPWM pin in output mode. 526 * |[5] |POEN5 |BPWM Pin Output Enable Bits 527 * | | |Each bit n controls the corresponding BPWM channel n. 528 * | | |0 = BPWM pin at tri-state. 529 * | | |1 = BPWM pin in output mode. 530 * @var BPWM_T::INTEN 531 * Offset: 0xE0 BPWM Interrupt Enable Register 532 * --------------------------------------------------------------------------------------------------- 533 * |Bits |Field |Descriptions 534 * | :----: | :----: | :---- | 535 * |[0] |ZIEN0 |BPWM Zero Point Interrupt 0 Enable Bit 536 * | | |0 = Zero point interrupt Disabled. 537 * | | |1 = Zero point interrupt Enabled. 538 * |[8] |PIEN0 |BPWM Period Point Interrupt 0 Enable Bit 539 * | | |0 = Period point interrupt Disabled. 540 * | | |1 = Period point interrupt Enabled. 541 * | | |Note: When up-down counter type period point means center point. 542 * |[16] |CMPUIEN0 |BPWM Compare Up Count Interrupt Enable Bits 543 * | | |Each bit n controls the corresponding BPWM channel n. 544 * | | |0 = Compare up count interrupt Disabled. 545 * | | |1 = Compare up count interrupt Enabled. 546 * |[17] |CMPUIEN1 |BPWM Compare Up Count Interrupt Enable Bits 547 * | | |Each bit n controls the corresponding BPWM channel n. 548 * | | |0 = Compare up count interrupt Disabled. 549 * | | |1 = Compare up count interrupt Enabled. 550 * |[18] |CMPUIEN2 |BPWM Compare Up Count Interrupt Enable Bits 551 * | | |Each bit n controls the corresponding BPWM channel n. 552 * | | |0 = Compare up count interrupt Disabled. 553 * | | |1 = Compare up count interrupt Enabled. 554 * |[19] |CMPUIEN3 |BPWM Compare Up Count Interrupt Enable Bits 555 * | | |Each bit n controls the corresponding BPWM channel n. 556 * | | |0 = Compare up count interrupt Disabled. 557 * | | |1 = Compare up count interrupt Enabled. 558 * |[20] |CMPUIEN4 |BPWM Compare Up Count Interrupt Enable Bits 559 * | | |Each bit n controls the corresponding BPWM channel n. 560 * | | |0 = Compare up count interrupt Disabled. 561 * | | |1 = Compare up count interrupt Enabled. 562 * |[21] |CMPUIEN5 |BPWM Compare Up Count Interrupt Enable Bits 563 * | | |Each bit n controls the corresponding BPWM channel n. 564 * | | |0 = Compare up count interrupt Disabled. 565 * | | |1 = Compare up count interrupt Enabled. 566 * |[24] |CMPDIEN0 |BPWM Compare Down Count Interrupt Enable Bits 567 * | | |Each bit n controls the corresponding BPWM channel n. 568 * | | |0 = Compare down count interrupt Disabled. 569 * | | |1 = Compare down count interrupt Enabled. 570 * |[25] |CMPDIEN1 |BPWM Compare Down Count Interrupt Enable Bits 571 * | | |Each bit n controls the corresponding BPWM channel n. 572 * | | |0 = Compare down count interrupt Disabled. 573 * | | |1 = Compare down count interrupt Enabled. 574 * |[26] |CMPDIEN2 |BPWM Compare Down Count Interrupt Enable Bits 575 * | | |Each bit n controls the corresponding BPWM channel n. 576 * | | |0 = Compare down count interrupt Disabled. 577 * | | |1 = Compare down count interrupt Enabled. 578 * |[27] |CMPDIEN3 |BPWM Compare Down Count Interrupt Enable Bits 579 * | | |Each bit n controls the corresponding BPWM channel n. 580 * | | |0 = Compare down count interrupt Disabled. 581 * | | |1 = Compare down count interrupt Enabled. 582 * |[28] |CMPDIEN4 |BPWM Compare Down Count Interrupt Enable Bits 583 * | | |Each bit n controls the corresponding BPWM channel n. 584 * | | |0 = Compare down count interrupt Disabled. 585 * | | |1 = Compare down count interrupt Enabled. 586 * |[29] |CMPDIEN5 |BPWM Compare Down Count Interrupt Enable Bits 587 * | | |Each bit n controls the corresponding BPWM channel n. 588 * | | |0 = Compare down count interrupt Disabled. 589 * | | |1 = Compare down count interrupt Enabled. 590 * @var BPWM_T::INTSTS 591 * Offset: 0xE8 BPWM Interrupt Flag Register 592 * --------------------------------------------------------------------------------------------------- 593 * |Bits |Field |Descriptions 594 * | :----: | :----: | :---- | 595 * |[0] |ZIF0 |BPWM Zero Point Interrupt Flag 0 596 * | | |This bit is set by hardware when BPWM_CH0 counter reaches zero, software can write 1 to clear this bit to zero. 597 * |[8] |PIF0 |BPWM Period Point Interrupt Flag 0 598 * | | |This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0, software can write 1 to clear this bit to zero. 599 * |[16] |CMPUIF0 |BPWM Compare Up Count Interrupt Flag 600 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 601 * | | |Each bit n controls the corresponding BPWM channel n. 602 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 603 * |[17] |CMPUIF1 |BPWM Compare Up Count Interrupt Flag 604 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 605 * | | |Each bit n controls the corresponding BPWM channel n. 606 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 607 * |[18] |CMPUIF2 |BPWM Compare Up Count Interrupt Flag 608 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 609 * | | |Each bit n controls the corresponding BPWM channel n. 610 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 611 * |[19] |CMPUIF3 |BPWM Compare Up Count Interrupt Flag 612 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 613 * | | |Each bit n controls the corresponding BPWM channel n. 614 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 615 * |[20] |CMPUIF4 |BPWM Compare Up Count Interrupt Flag 616 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 617 * | | |Each bit n controls the corresponding BPWM channel n. 618 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 619 * |[21] |CMPUIF5 |BPWM Compare Up Count Interrupt Flag 620 * | | |Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it 621 * | | |Each bit n controls the corresponding BPWM channel n. 622 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection. 623 * |[24] |CMPDIF0 |BPWM Compare Down Count Interrupt Flag 624 * | | |Each bit n controls the corresponding BPWM channel n. 625 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 626 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 627 * |[25] |CMPDIF1 |BPWM Compare Down Count Interrupt Flag 628 * | | |Each bit n controls the corresponding BPWM channel n. 629 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 630 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 631 * |[26] |CMPDIF2 |BPWM Compare Down Count Interrupt Flag 632 * | | |Each bit n controls the corresponding BPWM channel n. 633 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 634 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 635 * |[27] |CMPDIF3 |BPWM Compare Down Count Interrupt Flag 636 * | | |Each bit n controls the corresponding BPWM channel n. 637 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 638 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 639 * |[28] |CMPDIF4 |BPWM Compare Down Count Interrupt Flag 640 * | | |Each bit n controls the corresponding BPWM channel n. 641 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 642 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 643 * |[29] |CMPDIF5 |BPWM Compare Down Count Interrupt Flag 644 * | | |Each bit n controls the corresponding BPWM channel n. 645 * | | |Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn, software can clear this bit by writing 1 to it. 646 * | | |Note: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection. 647 * @var BPWM_T::EADCTS0 648 * Offset: 0xF8 BPWM Trigger EADC Source Select Register 0 649 * --------------------------------------------------------------------------------------------------- 650 * |Bits |Field |Descriptions 651 * | :----: | :----: | :---- | 652 * |[3:0] |TRGSEL0 |BPWM_CH0 Trigger EADC Source Select 653 * | | |0000 = BPWM_CH0 zero point. 654 * | | |0001 = BPWM_CH0 period point. 655 * | | |0010 = BPWM_CH0 zero or period point. 656 * | | |0011 = BPWM_CH0 up-count CMPDAT point. 657 * | | |0100 = BPWM_CH0 down-count CMPDAT point. 658 * | | |0101 = Reserved. 659 * | | |0110 = Reserved. 660 * | | |0111 = Reserved. 661 * | | |1000 = BPWM_CH1 up-count CMPDAT point. 662 * | | |1001 = BPWM_CH1 down-count CMPDAT point. 663 * | | |Others reserved 664 * |[7] |TRGEN0 |BPWM_CH0 Trigger EADC Enable Bit 665 * |[11:8] |TRGSEL1 |BPWM_CH1 Trigger EADC Source Select 666 * | | |0000 = BPWM_CH0 zero point. 667 * | | |0001 = BPWM_CH0 period point. 668 * | | |0010 = BPWM_CH0 zero or period point. 669 * | | |0011 = BPWM_CH0 up-count CMPDAT point. 670 * | | |0100 = BPWM_CH0 down-count CMPDAT point. 671 * | | |0101 = Reserved. 672 * | | |0110 = Reserved. 673 * | | |0111 = Reserved. 674 * | | |1000 = BPWM_CH1 up-count CMPDAT point. 675 * | | |1001 = BPWM_CH1 down-count CMPDAT point. 676 * | | |Others reserved 677 * |[15] |TRGEN1 |BPWM_CH1 Trigger EADC Enable Bit 678 * |[19:16] |TRGSEL2 |BPWM_CH2 Trigger EADC Source Select 679 * | | |0000 = BPWM_CH2 zero point. 680 * | | |0001 = BPWM_CH2 period point. 681 * | | |0010 = BPWM_CH2 zero or period point. 682 * | | |0011 = BPWM_CH2 up-count CMPDAT point. 683 * | | |0100 = BPWM_CH2 down-count CMPDAT point. 684 * | | |0101 = Reserved. 685 * | | |0110 = Reserved. 686 * | | |0111 = Reserved. 687 * | | |1000 = BPWM_CH3 up-count CMPDAT point. 688 * | | |1001 = BPWM_CH3 down-count CMPDAT point. 689 * | | |Others reserved 690 * |[23] |TRGEN2 |BPWM_CH2 Trigger EADC Enable Bit 691 * |[27:24] |TRGSEL3 |BPWM_CH3 Trigger EADC Source Select 692 * | | |0000 = BPWM_CH2 zero point. 693 * | | |0001 = BPWM_CH2 period point. 694 * | | |0010 = BPWM_CH2 zero or period point. 695 * | | |0011 = BPWM_CH2 up-count CMPDAT point. 696 * | | |0100 = BPWM_CH2 down-count CMPDAT point. 697 * | | |0101 = Reserved. 698 * | | |0110 = Reserved. 699 * | | |0111 = Reserved. 700 * | | |1000 = BPWM_CH3 up-count CMPDAT point. 701 * | | |1001 = BPWM_CH3 down-count CMPDAT point. 702 * | | |Others reserved. 703 * |[31] |TRGEN3 |BPWM_CH3 Trigger EADC Enable Bit 704 * @var BPWM_T::EADCTS1 705 * Offset: 0xFC BPWM Trigger EADC Source Select Register 1 706 * --------------------------------------------------------------------------------------------------- 707 * |Bits |Field |Descriptions 708 * | :----: | :----: | :---- | 709 * |[3:0] |TRGSEL4 |BPWM_CH4 Trigger EADC Source Select 710 * | | |0000 = BPWM_CH4 zero point. 711 * | | |0001 = BPWM_CH4 period point. 712 * | | |0010 = BPWM_CH4 zero or period point. 713 * | | |0011 = BPWM_CH4 up-count CMPDAT point. 714 * | | |0100 = BPWM_CH4 down-count CMPDAT point. 715 * | | |0101 = Reserved. 716 * | | |0110 = Reserved. 717 * | | |0111 = Reserved. 718 * | | |1000 = BPWM_CH5 up-count CMPDAT point. 719 * | | |1001 = BPWM_CH5 down-count CMPDAT point. 720 * | | |Others reserved 721 * |[7] |TRGEN4 |BPWM_CH4 Trigger EADC Enable Bit 722 * |[11:8] |TRGSEL5 |BPWM_CH5 Trigger EADC Source Select 723 * | | |0000 = BPWM_CH4 zero point. 724 * | | |0001 = BPWM_CH4 period point. 725 * | | |0010 = BPWM_CH4 zero or period point. 726 * | | |0011 = BPWM_CH4 up-count CMPDAT point. 727 * | | |0100 = BPWM_CH4 down-count CMPDAT point. 728 * | | |0101 = Reserved. 729 * | | |0110 = Reserved. 730 * | | |0111 = Reserved. 731 * | | |1000 = BPWM_CH5 up-count CMPDAT point. 732 * | | |1001 = BPWM_CH5 down-count CMPDAT point. 733 * | | |Others reserved 734 * |[15] |TRGEN5 |BPWM_CH5 Trigger EADC Enable Bit 735 * @var BPWM_T::SSCTL 736 * Offset: 0x110 BPWM Synchronous Start Control Register 737 * --------------------------------------------------------------------------------------------------- 738 * |Bits |Field |Descriptions 739 * | :----: | :----: | :---- | 740 * |[0] |SSEN0 |BPWM Synchronous Start Function 0 Enable Bit 741 * | | |When synchronous start function is enabled, the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN). 742 * | | |0 = BPWM synchronous start function Disabled. 743 * | | |1 = BPWM synchronous start function Enabled. 744 * |[9:8] |SSRC |BPWM Synchronous Start Source Select 745 * | | |00 = Synchronous start source come from PWM0. 746 * | | |01 = Synchronous start source come from PWM1. 747 * | | |10 = Synchronous start source come from BPWM0. 748 * | | |11 = Synchronous start source come from BPWM1. 749 * @var BPWM_T::SSTRG 750 * Offset: 0x114 BPWM Synchronous Start Trigger Register 751 * --------------------------------------------------------------------------------------------------- 752 * |Bits |Field |Descriptions 753 * | :----: | :----: | :---- | 754 * |[0] |CNTSEN |BPWM Counter Synchronous Start Enable Bit(Write Only) 755 * | | |BPMW counter synchronous enable function is used to make PWM or BPWM channels start counting at the same time. 756 * | | |Writing this bit to 1 will also set the counter enable bit if correlated BPWM channel counter synchronous start function is enabled. 757 * @var BPWM_T::STATUS 758 * Offset: 0x120 BPWM Status Register 759 * --------------------------------------------------------------------------------------------------- 760 * |Bits |Field |Descriptions 761 * | :----: | :----: | :---- | 762 * |[0] |CNTMAX0 |Time-base Counter 0 Equal to 0xFFFF Latched Status 763 * | | |0 = indicates the time-base counter never reached its maximum value 0xFFFF. 764 * | | |1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit. 765 * |[16] |EADCTRG0 |EADC Start of Conversion Status 766 * | | |Each bit n controls the corresponding BPWM channel n. 767 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 768 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 769 * |[17] |EADCTRG1 |EADC Start of Conversion Status 770 * | | |Each bit n controls the corresponding BPWM channel n. 771 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 772 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 773 * |[18] |EADCTRG2 |EADC Start of Conversion Status 774 * | | |Each bit n controls the corresponding BPWM channel n. 775 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 776 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 777 * |[19] |EADCTRG3 |EADC Start of Conversion Status 778 * | | |Each bit n controls the corresponding BPWM channel n. 779 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 780 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 781 * |[20] |EADCTRG4 |EADC Start of Conversion Status 782 * | | |Each bit n controls the corresponding BPWM channel n. 783 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 784 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 785 * |[21] |EADCTRG5 |EADC Start of Conversion Status 786 * | | |Each bit n controls the corresponding BPWM channel n. 787 * | | |0 = Indicates no EADC start of conversion trigger event has occurred. 788 * | | |1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit. 789 * @var BPWM_T::CAPINEN 790 * Offset: 0x200 BPWM Capture Input Enable Register 791 * --------------------------------------------------------------------------------------------------- 792 * |Bits |Field |Descriptions 793 * | :----: | :----: | :---- | 794 * |[0] |CAPINEN0 |Capture Input Enable Bits 795 * | | |Each bit n controls the corresponding BPWM channel n. 796 * | | |0 = BPWM Channel capture input path Disabled 797 * | | |The input of BPWM channel capture function is always regarded as 0. 798 * | | |1 = BPWM Channel capture input path Enabled 799 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 800 * |[1] |CAPINEN1 |Capture Input Enable Bits 801 * | | |Each bit n controls the corresponding BPWM channel n. 802 * | | |0 = BPWM Channel capture input path Disabled 803 * | | |The input of BPWM channel capture function is always regarded as 0. 804 * | | |1 = BPWM Channel capture input path Enabled 805 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 806 * |[2] |CAPINEN2 |Capture Input Enable Bits 807 * | | |Each bit n controls the corresponding BPWM channel n. 808 * | | |0 = BPWM Channel capture input path Disabled 809 * | | |The input of BPWM channel capture function is always regarded as 0. 810 * | | |1 = BPWM Channel capture input path Enabled 811 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 812 * |[3] |CAPINEN3 |Capture Input Enable Bits 813 * | | |Each bit n controls the corresponding BPWM channel n. 814 * | | |0 = BPWM Channel capture input path Disabled 815 * | | |The input of BPWM channel capture function is always regarded as 0. 816 * | | |1 = BPWM Channel capture input path Enabled 817 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 818 * |[4] |CAPINEN4 |Capture Input Enable Bits 819 * | | |Each bit n controls the corresponding BPWM channel n. 820 * | | |0 = BPWM Channel capture input path Disabled 821 * | | |The input of BPWM channel capture function is always regarded as 0. 822 * | | |1 = BPWM Channel capture input path Enabled 823 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 824 * |[5] |CAPINEN5 |Capture Input Enable Bits 825 * | | |Each bit n controls the corresponding BPWM channel n. 826 * | | |0 = BPWM Channel capture input path Disabled 827 * | | |The input of BPWM channel capture function is always regarded as 0. 828 * | | |1 = BPWM Channel capture input path Enabled 829 * | | |The input of BPWM channel capture function comes from correlative multifunction pin. 830 * @var BPWM_T::CAPCTL 831 * Offset: 0x204 BPWM Capture Control Register 832 * --------------------------------------------------------------------------------------------------- 833 * |Bits |Field |Descriptions 834 * | :----: | :----: | :---- | 835 * |[0] |CAPEN0 |Capture Function Enable Bits 836 * | | |Each bit n controls the corresponding BPWM channel n. 837 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 838 * | | |1 = Capture function Enabled 839 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 840 * |[1] |CAPEN1 |Capture Function Enable Bits 841 * | | |Each bit n controls the corresponding BPWM channel n. 842 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 843 * | | |1 = Capture function Enabled 844 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 845 * |[2] |CAPEN2 |Capture Function Enable Bits 846 * | | |Each bit n controls the corresponding BPWM channel n. 847 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 848 * | | |1 = Capture function Enabled 849 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 850 * |[3] |CAPEN3 |Capture Function Enable Bits 851 * | | |Each bit n controls the corresponding BPWM channel n. 852 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 853 * | | |1 = Capture function Enabled 854 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 855 * |[4] |CAPEN4 |Capture Function Enable Bits 856 * | | |Each bit n controls the corresponding BPWM channel n. 857 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 858 * | | |1 = Capture function Enabled 859 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 860 * |[5] |CAPEN5 |Capture Function Enable Bits 861 * | | |Each bit n controls the corresponding BPWM channel n. 862 * | | |0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated. 863 * | | |1 = Capture function Enabled 864 * | | |Capture latched the BPWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch). 865 * |[8] |CAPINV0 |Capture Inverter Enable Bits 866 * | | |Each bit n controls the corresponding BPWM channel n. 867 * | | |0 = Capture source inverter Disabled. 868 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 869 * |[9] |CAPINV1 |Capture Inverter Enable Bits 870 * | | |Each bit n controls the corresponding BPWM channel n. 871 * | | |0 = Capture source inverter Disabled. 872 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 873 * |[10] |CAPINV2 |Capture Inverter Enable Bits 874 * | | |Each bit n controls the corresponding BPWM channel n. 875 * | | |0 = Capture source inverter Disabled. 876 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 877 * |[11] |CAPINV3 |Capture Inverter Enable Bits 878 * | | |Each bit n controls the corresponding BPWM channel n. 879 * | | |0 = Capture source inverter Disabled. 880 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 881 * |[12] |CAPINV4 |Capture Inverter Enable Bits 882 * | | |Each bit n controls the corresponding BPWM channel n. 883 * | | |0 = Capture source inverter Disabled. 884 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 885 * |[13] |CAPINV5 |Capture Inverter Enable Bits 886 * | | |Each bit n controls the corresponding BPWM channel n. 887 * | | |0 = Capture source inverter Disabled. 888 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO. 889 * |[16] |RCRLDEN0 |Rising Capture Reload Enable Bits 890 * | | |Each bit n controls the corresponding BPWM channel n. 891 * | | |0 = Rising capture reload counter Disabled. 892 * | | |1 = Rising capture reload counter Enabled. 893 * |[17] |RCRLDEN1 |Rising Capture Reload Enable Bits 894 * | | |Each bit n controls the corresponding BPWM channel n. 895 * | | |0 = Rising capture reload counter Disabled. 896 * | | |1 = Rising capture reload counter Enabled. 897 * |[18] |RCRLDEN2 |Rising Capture Reload Enable Bits 898 * | | |Each bit n controls the corresponding BPWM channel n. 899 * | | |0 = Rising capture reload counter Disabled. 900 * | | |1 = Rising capture reload counter Enabled. 901 * |[19] |RCRLDEN3 |Rising Capture Reload Enable Bits 902 * | | |Each bit n controls the corresponding BPWM channel n. 903 * | | |0 = Rising capture reload counter Disabled. 904 * | | |1 = Rising capture reload counter Enabled. 905 * |[20] |RCRLDEN4 |Rising Capture Reload Enable Bits 906 * | | |Each bit n controls the corresponding BPWM channel n. 907 * | | |0 = Rising capture reload counter Disabled. 908 * | | |1 = Rising capture reload counter Enabled. 909 * |[21] |RCRLDEN5 |Rising Capture Reload Enable Bits 910 * | | |Each bit n controls the corresponding BPWM channel n. 911 * | | |0 = Rising capture reload counter Disabled. 912 * | | |1 = Rising capture reload counter Enabled. 913 * |[24] |FCRLDEN0 |Falling Capture Reload Enable Bits 914 * | | |Each bit n controls the corresponding BPWM channel n. 915 * | | |0 = Falling capture reload counter Disabled. 916 * | | |1 = Falling capture reload counter Enabled. 917 * |[25] |FCRLDEN1 |Falling Capture Reload Enable Bits 918 * | | |Each bit n controls the corresponding BPWM channel n. 919 * | | |0 = Falling capture reload counter Disabled. 920 * | | |1 = Falling capture reload counter Enabled. 921 * |[26] |FCRLDEN2 |Falling Capture Reload Enable Bits 922 * | | |Each bit n controls the corresponding BPWM channel n. 923 * | | |0 = Falling capture reload counter Disabled. 924 * | | |1 = Falling capture reload counter Enabled. 925 * |[27] |FCRLDEN3 |Falling Capture Reload Enable Bits 926 * | | |Each bit n controls the corresponding BPWM channel n. 927 * | | |0 = Falling capture reload counter Disabled. 928 * | | |1 = Falling capture reload counter Enabled. 929 * |[28] |FCRLDEN4 |Falling Capture Reload Enable Bits 930 * | | |Each bit n controls the corresponding BPWM channel n. 931 * | | |0 = Falling capture reload counter Disabled. 932 * | | |1 = Falling capture reload counter Enabled. 933 * |[29] |FCRLDEN5 |Falling Capture Reload Enable Bits 934 * | | |Each bit n controls the corresponding BPWM channel n. 935 * | | |0 = Falling capture reload counter Disabled. 936 * | | |1 = Falling capture reload counter Enabled. 937 * @var BPWM_T::CAPSTS 938 * Offset: 0x208 BPWM Capture Status Register 939 * --------------------------------------------------------------------------------------------------- 940 * |Bits |Field |Descriptions 941 * | :----: | :----: | :---- | 942 * |[0] |CRIFOV0 |Capture Rising Interrupt Flag Overrun Status (Read Only) 943 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 944 * | | |Each bit n controls the corresponding BPWM channel n. 945 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 946 * |[1] |CRIFOV1 |Capture Rising Interrupt Flag Overrun Status (Read Only) 947 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 948 * | | |Each bit n controls the corresponding BPWM channel n. 949 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 950 * |[2] |CRIFOV2 |Capture Rising Interrupt Flag Overrun Status (Read Only) 951 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 952 * | | |Each bit n controls the corresponding BPWM channel n. 953 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 954 * |[3] |CRIFOV3 |Capture Rising Interrupt Flag Overrun Status (Read Only) 955 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 956 * | | |Each bit n controls the corresponding BPWM channel n. 957 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 958 * |[4] |CRIFOV4 |Capture Rising Interrupt Flag Overrun Status (Read Only) 959 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 960 * | | |Each bit n controls the corresponding BPWM channel n. 961 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 962 * |[5] |CRIFOV5 |Capture Rising Interrupt Flag Overrun Status (Read Only) 963 * | | |This flag indicates if rising latch happened when the corresponding CAPRIF is 1 964 * | | |Each bit n controls the corresponding BPWM channel n. 965 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPRIF. 966 * |[8] |CFIFOV0 |Capture Falling Interrupt Flag Overrun Status (Read Only) 967 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 968 * | | |Each bit n controls the corresponding BPWM channel n. 969 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 970 * |[9] |CFIFOV1 |Capture Falling Interrupt Flag Overrun Status (Read Only) 971 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 972 * | | |Each bit n controls the corresponding BPWM channel n. 973 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 974 * |[10] |CFIFOV2 |Capture Falling Interrupt Flag Overrun Status (Read Only) 975 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 976 * | | |Each bit n controls the corresponding BPWM channel n. 977 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 978 * |[11] |CFIFOV3 |Capture Falling Interrupt Flag Overrun Status (Read Only) 979 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 980 * | | |Each bit n controls the corresponding BPWM channel n. 981 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 982 * |[12] |CFIFOV4 |Capture Falling Interrupt Flag Overrun Status (Read Only) 983 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 984 * | | |Each bit n controls the corresponding BPWM channel n. 985 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 986 * |[13] |CFIFOV5 |Capture Falling Interrupt Flag Overrun Status (Read Only) 987 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 988 * | | |Each bit n controls the corresponding BPWM channel n. 989 * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. 990 * @var BPWM_T::CAPIEN 991 * Offset: 0x250 BPWM Capture Interrupt Enable Register 992 * --------------------------------------------------------------------------------------------------- 993 * |Bits |Field |Descriptions 994 * | :----: | :----: | :---- | 995 * |[5:0] |CAPRIENn |BPWM Capture Rising Latch Interrupt Enable Bits 996 * | | |Each bit n controls the corresponding BPWM channel n. 997 * | | |0 = Capture rising edge latch interrupt Disabled. 998 * | | |1 = Capture rising edge latch interrupt Enabled. 999 * |[13:8] |CAPFIENn |BPWM Capture Falling Latch Interrupt Enable Bits 1000 * | | |Each bit n controls the corresponding BPWM channel n. 1001 * | | |0 = Capture falling edge latch interrupt Disabled. 1002 * | | |1 = Capture falling edge latch interrupt Enabled. 1003 * @var BPWM_T::CAPIF 1004 * Offset: 0x254 BPWM Capture Interrupt Flag Register 1005 * --------------------------------------------------------------------------------------------------- 1006 * |Bits |Field |Descriptions 1007 * | :----: | :----: | :---- | 1008 * |[0] |CAPRIF0 |BPWM Capture Rising Latch Interrupt Flag 1009 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1010 * | | |0 = No capture rising latch condition happened. 1011 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1012 * |[1] |CAPRIF1 |BPWM Capture Rising Latch Interrupt Flag 1013 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1014 * | | |0 = No capture rising latch condition happened. 1015 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1016 * |[2] |CAPRIF2 |BPWM Capture Rising Latch Interrupt Flag 1017 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1018 * | | |0 = No capture rising latch condition happened. 1019 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1020 * |[3] |CAPRIF3 |BPWM Capture Rising Latch Interrupt Flag 1021 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1022 * | | |0 = No capture rising latch condition happened. 1023 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1024 * |[4] |CAPRIF4 |BPWM Capture Rising Latch Interrupt Flag 1025 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1026 * | | |0 = No capture rising latch condition happened. 1027 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1028 * |[5] |CAPRIF5 |BPWM Capture Rising Latch Interrupt Flag 1029 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1030 * | | |0 = No capture rising latch condition happened. 1031 * | | |1 = Capture rising latch condition happened, this flag will be set to high. 1032 * |[8] |CAPFIF0 |BPWM Capture Falling Latch Interrupt Flag 1033 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1034 * | | |0 = No capture falling latch condition happened. 1035 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1036 * |[9] |CAPFIF1 |BPWM Capture Falling Latch Interrupt Flag 1037 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1038 * | | |0 = No capture falling latch condition happened. 1039 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1040 * |[10] |CAPFIF2 |BPWM Capture Falling Latch Interrupt Flag 1041 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1042 * | | |0 = No capture falling latch condition happened. 1043 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1044 * |[11] |CAPFIF3 |BPWM Capture Falling Latch Interrupt Flag 1045 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1046 * | | |0 = No capture falling latch condition happened. 1047 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1048 * |[12] |CAPFIF4 |BPWM Capture Falling Latch Interrupt Flag 1049 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1050 * | | |0 = No capture falling latch condition happened. 1051 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1052 * |[13] |CAPFIF5 |BPWM Capture Falling Latch Interrupt Flag 1053 * | | |This bit is writing 1 to clear. Each bit n controls the corresponding BPWM channel n. 1054 * | | |0 = No capture falling latch condition happened. 1055 * | | |1 = Capture falling latch condition happened, this flag will be set to high. 1056 * @var BPWM_T::PBUF 1057 * Offset: 0x304 BPWM PERIOD Buffer 1058 * --------------------------------------------------------------------------------------------------- 1059 * |Bits |Field |Descriptions 1060 * | :----: | :----: | :---- | 1061 * |[15:0] |PBUF |BPWM Period Buffer (Read Only) 1062 * | | |Used as PERIOD active register. 1063 * @var BPWM_T::CMPBUF[6] 1064 * Offset: 0x31C BPWM CMPDAT 0~5 Buffer 1065 * --------------------------------------------------------------------------------------------------- 1066 * |Bits |Field |Descriptions 1067 * | :----: | :----: | :---- | 1068 * |[15:0] |CMPBUF |BPWM Comparator Buffer (Read Only) 1069 * | | |Used as CMP active register. 1070 */ 1071 __IO uint32_t CTL0; /*!< [0x0000] BPWM Control Register 0 */ 1072 __IO uint32_t CTL1; /*!< [0x0004] BPWM Control Register 1 */ 1073 __I uint32_t RESERVED0[2]; 1074 __IO uint32_t CLKSRC; /*!< [0x0010] BPWM Clock Source Register */ 1075 __IO uint32_t CLKPSC; /*!< [0x0014] BPWM Clock Prescale Register */ 1076 __I uint32_t RESERVED1[2]; 1077 __IO uint32_t CNTEN; /*!< [0x0020] BPWM Counter Enable Register */ 1078 __IO uint32_t CNTCLR; /*!< [0x0024] BPWM Clear Counter Register */ 1079 __I uint32_t RESERVED2[2]; 1080 __IO uint32_t PERIOD; /*!< [0x0030] BPWM Period Register */ 1081 __I uint32_t RESERVED3[7]; 1082 __IO uint32_t CMPDAT[6]; /*!< [0x0050~0x0064] BPWM Comparator Register 0~5 */ 1083 __I uint32_t RESERVED4[10]; 1084 __I uint32_t CNT; /*!< [0x0090] BPWM Counter Register */ 1085 __I uint32_t RESERVED5[7]; 1086 __IO uint32_t WGCTL0; /*!< [0x00b0] BPWM Generation Register 0 */ 1087 __IO uint32_t WGCTL1; /*!< [0x00b4] BPWM Generation Register 1 */ 1088 __IO uint32_t MSKEN; /*!< [0x00b8] BPWM Mask Enable Register */ 1089 __IO uint32_t MSK; /*!< [0x00bc] BPWM Mask Data Register */ 1090 __I uint32_t RESERVED6[5]; 1091 __IO uint32_t POLCTL; /*!< [0x00d4] BPWM Pin Polar Inverse Register */ 1092 __IO uint32_t POEN; /*!< [0x00d8] BPWM Output Enable Register */ 1093 __I uint32_t RESERVED7[1]; 1094 __IO uint32_t INTEN; /*!< [0x00e0] BPWM Interrupt Enable Register */ 1095 __I uint32_t RESERVED8[1]; 1096 __IO uint32_t INTSTS; /*!< [0x00e8] BPWM Interrupt Flag Register */ 1097 __I uint32_t RESERVED9[3]; 1098 __IO uint32_t EADCTS0; /*!< [0x00f8] BPWM Trigger EADC Source Select Register 0 */ 1099 __IO uint32_t EADCTS1; /*!< [0x00fc] BPWM Trigger EADC Source Select Register 1 */ 1100 __I uint32_t RESERVED10[4]; 1101 __IO uint32_t SSCTL; /*!< [0x0110] BPWM Synchronous Start Control Register */ 1102 __O uint32_t SSTRG; /*!< [0x0114] BPWM Synchronous Start Trigger Register */ 1103 __I uint32_t RESERVED11[2]; 1104 __IO uint32_t STATUS; /*!< [0x0120] BPWM Status Register */ 1105 __I uint32_t RESERVED12[55]; 1106 __IO uint32_t CAPINEN; /*!< [0x0200] BPWM Capture Input Enable Register */ 1107 __IO uint32_t CAPCTL; /*!< [0x0204] BPWM Capture Control Register */ 1108 __I uint32_t CAPSTS; /*!< [0x0208] BPWM Capture Status Register */ 1109 BCAPDAT_T CAPDAT[6]; /*!< [0x020c~0x0238] BPWM Rising and Falling Capture Data Register 0~5 */ 1110 __I uint32_t RESERVED13[5]; 1111 __IO uint32_t CAPIEN; /*!< [0x0250] BPWM Capture Interrupt Enable Register */ 1112 __IO uint32_t CAPIF; /*!< [0x0254] BPWM Capture Interrupt Flag Register */ 1113 __I uint32_t RESERVED14[43]; 1114 __I uint32_t PBUF; /*!< [0x0304] BPWM PERIOD Buffer */ 1115 __I uint32_t RESERVED15[5]; 1116 __I uint32_t CMPBUF[6]; /*!< [0x031c~0x0330] BPWM CMPDAT 0~5 Buffer */ 1117 1118 } BPWM_T; 1119 1120 /** 1121 @addtogroup BPWM_CONST BPWM Bit Field Definition 1122 Constant Definitions for BPWM Controller 1123 @{ 1124 */ 1125 1126 #define BPWM_CTL0_CTRLD0_Pos (0) /*!< BPWM_T::CTL0: CTRLD0 Position */ 1127 #define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM_T::CTL0: CTRLD0 Mask */ 1128 1129 #define BPWM_CTL0_CTRLD1_Pos (1) /*!< BPWM_T::CTL0: CTRLD1 Position */ 1130 #define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) /*!< BPWM_T::CTL0: CTRLD1 Mask */ 1131 1132 #define BPWM_CTL0_CTRLD2_Pos (2) /*!< BPWM_T::CTL0: CTRLD2 Position */ 1133 #define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) /*!< BPWM_T::CTL0: CTRLD2 Mask */ 1134 1135 #define BPWM_CTL0_CTRLD3_Pos (3) /*!< BPWM_T::CTL0: CTRLD3 Position */ 1136 #define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) /*!< BPWM_T::CTL0: CTRLD3 Mask */ 1137 1138 #define BPWM_CTL0_CTRLD4_Pos (4) /*!< BPWM_T::CTL0: CTRLD4 Position */ 1139 #define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) /*!< BPWM_T::CTL0: CTRLD4 Mask */ 1140 1141 #define BPWM_CTL0_CTRLD5_Pos (5) /*!< BPWM_T::CTL0: CTRLD5 Position */ 1142 #define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) /*!< BPWM_T::CTL0: CTRLD5 Mask */ 1143 1144 #define BPWM_CTL0_IMMLDEN0_Pos (16) /*!< BPWM_T::CTL0: IMMLDEN0 Position */ 1145 #define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM_T::CTL0: IMMLDEN0 Mask */ 1146 1147 #define BPWM_CTL0_IMMLDEN1_Pos (17) /*!< BPWM_T::CTL0: IMMLDEN1 Position */ 1148 #define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) /*!< BPWM_T::CTL0: IMMLDEN1 Mask */ 1149 1150 #define BPWM_CTL0_IMMLDEN2_Pos (18) /*!< BPWM_T::CTL0: IMMLDEN2 Position */ 1151 #define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) /*!< BPWM_T::CTL0: IMMLDEN2 Mask */ 1152 1153 #define BPWM_CTL0_IMMLDEN3_Pos (19) /*!< BPWM_T::CTL0: IMMLDEN3 Position */ 1154 #define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) /*!< BPWM_T::CTL0: IMMLDEN3 Mask */ 1155 1156 #define BPWM_CTL0_IMMLDEN4_Pos (20) /*!< BPWM_T::CTL0: IMMLDEN4 Position */ 1157 #define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) /*!< BPWM_T::CTL0: IMMLDEN4 Mask */ 1158 1159 #define BPWM_CTL0_IMMLDEN5_Pos (21) /*!< BPWM_T::CTL0: IMMLDEN5 Position */ 1160 #define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) /*!< BPWM_T::CTL0: IMMLDEN5 Mask */ 1161 1162 #define BPWM_CTL0_DBGHALT_Pos (30) /*!< BPWM_T::CTL0: DBGHALT Position */ 1163 #define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) /*!< BPWM_T::CTL0: DBGHALT Mask */ 1164 1165 #define BPWM_CTL0_DBGTRIOFF_Pos (31) /*!< BPWM_T::CTL0: DBGTRIOFF Position */ 1166 #define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) /*!< BPWM_T::CTL0: DBGTRIOFF Mask */ 1167 1168 #define BPWM_CTL1_CNTTYPE0_Pos (0) /*!< BPWM_T::CTL1: CNTTYPE0 Position */ 1169 #define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) /*!< BPWM_T::CTL1: CNTTYPE0 Mask */ 1170 1171 #define BPWM_CLKSRC_ECLKSRC0_Pos (0) /*!< BPWM_T::CLKSRC: ECLKSRC0 Position */ 1172 #define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) /*!< BPWM_T::CLKSRC: ECLKSRC0 Mask */ 1173 1174 #define BPWM_CLKPSC_CLKPSC_Pos (0) /*!< BPWM_T::CLKPSC: CLKPSC Position */ 1175 #define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) /*!< BPWM_T::CLKPSC: CLKPSC Mask */ 1176 1177 #define BPWM_CNTEN_CNTEN0_Pos (0) /*!< BPWM_T::CNTEN: CNTEN0 Position */ 1178 #define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) /*!< BPWM_T::CNTEN: CNTEN0 Mask */ 1179 1180 #define BPWM_CNTCLR_CNTCLR0_Pos (0) /*!< BPWM_T::CNTCLR: CNTCLR0 Position */ 1181 #define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) /*!< BPWM_T::CNTCLR: CNTCLR0 Mask */ 1182 1183 #define BPWM_PERIOD_PERIOD_Pos (0) /*!< BPWM_T::PERIOD: PERIOD Position */ 1184 #define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) /*!< BPWM_T::PERIOD: PERIOD Mask */ 1185 1186 #define BPWM_CMPDAT0_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT0: CMPDAT Position */ 1187 #define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) /*!< BPWM_T::CMPDAT0: CMPDAT Mask */ 1188 1189 #define BPWM_CMPDAT1_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT1: CMPDAT Position */ 1190 #define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) /*!< BPWM_T::CMPDAT1: CMPDAT Mask */ 1191 1192 #define BPWM_CMPDAT2_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT2: CMPDAT Position */ 1193 #define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) /*!< BPWM_T::CMPDAT2: CMPDAT Mask */ 1194 1195 #define BPWM_CMPDAT3_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT3: CMPDAT Position */ 1196 #define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) /*!< BPWM_T::CMPDAT3: CMPDAT Mask */ 1197 1198 #define BPWM_CMPDAT4_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT4: CMPDAT Position */ 1199 #define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) /*!< BPWM_T::CMPDAT4: CMPDAT Mask */ 1200 1201 #define BPWM_CMPDAT5_CMPDAT_Pos (0) /*!< BPWM_T::CMPDAT5: CMPDAT Position */ 1202 #define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) /*!< BPWM_T::CMPDAT5: CMPDAT Mask */ 1203 1204 #define BPWM_CNT_CNT_Pos (0) /*!< BPWM_T::CNT: CNT Position */ 1205 #define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) /*!< BPWM_T::CNT: CNT Mask */ 1206 1207 #define BPWM_CNT_DIRF_Pos (16) /*!< BPWM_T::CNT: DIRF Position */ 1208 #define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) /*!< BPWM_T::CNT: DIRF Mask */ 1209 1210 #define BPWM_WGCTL0_ZPCTL0_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTL0 Position */ 1211 #define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) /*!< BPWM_T::WGCTL0: ZPCTL0 Mask */ 1212 1213 #define BPWM_WGCTL0_ZPCTL1_Pos (2) /*!< BPWM_T::WGCTL0: ZPCTL1 Position */ 1214 #define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) /*!< BPWM_T::WGCTL0: ZPCTL1 Mask */ 1215 1216 #define BPWM_WGCTL0_ZPCTL2_Pos (4) /*!< BPWM_T::WGCTL0: ZPCTL2 Position */ 1217 #define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) /*!< BPWM_T::WGCTL0: ZPCTL2 Mask */ 1218 1219 #define BPWM_WGCTL0_ZPCTL3_Pos (6) /*!< BPWM_T::WGCTL0: ZPCTL3 Position */ 1220 #define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) /*!< BPWM_T::WGCTL0: ZPCTL3 Mask */ 1221 1222 #define BPWM_WGCTL0_ZPCTL4_Pos (8) /*!< BPWM_T::WGCTL0: ZPCTL4 Position */ 1223 #define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) /*!< BPWM_T::WGCTL0: ZPCTL4 Mask */ 1224 1225 #define BPWM_WGCTL0_ZPCTL5_Pos (10) /*!< BPWM_T::WGCTL0: ZPCTL5 Position */ 1226 #define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) /*!< BPWM_T::WGCTL0: ZPCTL5 Mask */ 1227 1228 #define BPWM_WGCTL0_ZPCTLn_Pos (0) /*!< BPWM_T::WGCTL0: ZPCTLn Position */ 1229 #define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) /*!< BPWM_T::WGCTL0: ZPCTLn Mask */ 1230 1231 #define BPWM_WGCTL0_PRDPCTL0_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTL0 Position */ 1232 #define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL0 Mask */ 1233 1234 #define BPWM_WGCTL0_PRDPCTL1_Pos (18) /*!< BPWM_T::WGCTL0: PRDPCTL1 Position */ 1235 #define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL1 Mask */ 1236 1237 #define BPWM_WGCTL0_PRDPCTL2_Pos (20) /*!< BPWM_T::WGCTL0: PRDPCTL2 Position */ 1238 #define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL2 Mask */ 1239 1240 #define BPWM_WGCTL0_PRDPCTL3_Pos (22) /*!< BPWM_T::WGCTL0: PRDPCTL3 Position */ 1241 #define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL3 Mask */ 1242 1243 #define BPWM_WGCTL0_PRDPCTL4_Pos (24) /*!< BPWM_T::WGCTL0: PRDPCTL4 Position */ 1244 #define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL4 Mask */ 1245 1246 #define BPWM_WGCTL0_PRDPCTL5_Pos (26) /*!< BPWM_T::WGCTL0: PRDPCTL5 Position */ 1247 #define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) /*!< BPWM_T::WGCTL0: PRDPCTL5 Mask */ 1248 1249 #define BPWM_WGCTL0_PRDPCTLn_Pos (16) /*!< BPWM_T::WGCTL0: PRDPCTLn Position */ 1250 #define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) /*!< BPWM_T::WGCTL0: PRDPCTLn Mask */ 1251 1252 #define BPWM_WGCTL1_CMPUCTL0_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTL0 Position */ 1253 #define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL0 Mask */ 1254 1255 #define BPWM_WGCTL1_CMPUCTL1_Pos (2) /*!< BPWM_T::WGCTL1: CMPUCTL1 Position */ 1256 #define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL1 Mask */ 1257 1258 #define BPWM_WGCTL1_CMPUCTL2_Pos (4) /*!< BPWM_T::WGCTL1: CMPUCTL2 Position */ 1259 #define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL2 Mask */ 1260 1261 #define BPWM_WGCTL1_CMPUCTL3_Pos (6) /*!< BPWM_T::WGCTL1: CMPUCTL3 Position */ 1262 #define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL3 Mask */ 1263 1264 #define BPWM_WGCTL1_CMPUCTL4_Pos (8) /*!< BPWM_T::WGCTL1: CMPUCTL4 Position */ 1265 #define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL4 Mask */ 1266 1267 #define BPWM_WGCTL1_CMPUCTL5_Pos (10) /*!< BPWM_T::WGCTL1: CMPUCTL5 Position */ 1268 #define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPUCTL5 Mask */ 1269 1270 #define BPWM_WGCTL1_CMPUCTLn_Pos (0) /*!< BPWM_T::WGCTL1: CMPUCTLn Position */ 1271 #define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPUCTLn Mask */ 1272 1273 #define BPWM_WGCTL1_CMPDCTL0_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTL0 Position */ 1274 #define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL0 Mask */ 1275 1276 #define BPWM_WGCTL1_CMPDCTL1_Pos (18) /*!< BPWM_T::WGCTL1: CMPDCTL1 Position */ 1277 #define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL1 Mask */ 1278 1279 #define BPWM_WGCTL1_CMPDCTL2_Pos (20) /*!< BPWM_T::WGCTL1: CMPDCTL2 Position */ 1280 #define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL2 Mask */ 1281 1282 #define BPWM_WGCTL1_CMPDCTL3_Pos (22) /*!< BPWM_T::WGCTL1: CMPDCTL3 Position */ 1283 #define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL3 Mask */ 1284 1285 #define BPWM_WGCTL1_CMPDCTL4_Pos (24) /*!< BPWM_T::WGCTL1: CMPDCTL4 Position */ 1286 #define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL4 Mask */ 1287 1288 #define BPWM_WGCTL1_CMPDCTL5_Pos (26) /*!< BPWM_T::WGCTL1: CMPDCTL5 Position */ 1289 #define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) /*!< BPWM_T::WGCTL1: CMPDCTL5 Mask */ 1290 1291 #define BPWM_WGCTL1_CMPDCTLn_Pos (16) /*!< BPWM_T::WGCTL1: CMPDCTLn Position */ 1292 #define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) /*!< BPWM_T::WGCTL1: CMPDCTLn Mask */ 1293 1294 #define BPWM_MSKEN_MSKEN0_Pos (0) /*!< BPWM_T::MSKEN: MSKEN0 Position */ 1295 #define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) /*!< BPWM_T::MSKEN: MSKEN0 Mask */ 1296 1297 #define BPWM_MSKEN_MSKEN1_Pos (1) /*!< BPWM_T::MSKEN: MSKEN1 Position */ 1298 #define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) /*!< BPWM_T::MSKEN: MSKEN1 Mask */ 1299 1300 #define BPWM_MSKEN_MSKEN2_Pos (2) /*!< BPWM_T::MSKEN: MSKEN2 Position */ 1301 #define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) /*!< BPWM_T::MSKEN: MSKEN2 Mask */ 1302 1303 #define BPWM_MSKEN_MSKEN3_Pos (3) /*!< BPWM_T::MSKEN: MSKEN3 Position */ 1304 #define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) /*!< BPWM_T::MSKEN: MSKEN3 Mask */ 1305 1306 #define BPWM_MSKEN_MSKEN4_Pos (4) /*!< BPWM_T::MSKEN: MSKEN4 Position */ 1307 #define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) /*!< BPWM_T::MSKEN: MSKEN4 Mask */ 1308 1309 #define BPWM_MSKEN_MSKEN5_Pos (5) /*!< BPWM_T::MSKEN: MSKEN5 Position */ 1310 #define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) /*!< BPWM_T::MSKEN: MSKEN5 Mask */ 1311 1312 #define BPWM_MSKEN_MSKENn_Pos (0) /*!< BPWM_T::MSKEN: MSKENn Position */ 1313 #define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) /*!< BPWM_T::MSKEN: MSKENn Mask */ 1314 1315 #define BPWM_MSK_MSKDAT0_Pos (0) /*!< BPWM_T::MSK: MSKDAT0 Position */ 1316 #define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) /*!< BPWM_T::MSK: MSKDAT0 Mask */ 1317 1318 #define BPWM_MSK_MSKDAT1_Pos (1) /*!< BPWM_T::MSK: MSKDAT1 Position */ 1319 #define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) /*!< BPWM_T::MSK: MSKDAT1 Mask */ 1320 1321 #define BPWM_MSK_MSKDAT2_Pos (2) /*!< BPWM_T::MSK: MSKDAT2 Position */ 1322 #define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) /*!< BPWM_T::MSK: MSKDAT2 Mask */ 1323 1324 #define BPWM_MSK_MSKDAT3_Pos (3) /*!< BPWM_T::MSK: MSKDAT3 Position */ 1325 #define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) /*!< BPWM_T::MSK: MSKDAT3 Mask */ 1326 1327 #define BPWM_MSK_MSKDAT4_Pos (4) /*!< BPWM_T::MSK: MSKDAT4 Position */ 1328 #define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) /*!< BPWM_T::MSK: MSKDAT4 Mask */ 1329 1330 #define BPWM_MSK_MSKDAT5_Pos (5) /*!< BPWM_T::MSK: MSKDAT5 Position */ 1331 #define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) /*!< BPWM_T::MSK: MSKDAT5 Mask */ 1332 1333 #define BPWM_MSK_MSKDATn_Pos (0) /*!< BPWM_T::MSK: MSKDATn Position */ 1334 #define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) /*!< BPWM_T::MSK: MSKDATn Mask */ 1335 1336 #define BPWM_POLCTL_PINV0_Pos (0) /*!< BPWM_T::POLCTL: PINV0 Position */ 1337 #define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) /*!< BPWM_T::POLCTL: PINV0 Mask */ 1338 1339 #define BPWM_POLCTL_PINV1_Pos (1) /*!< BPWM_T::POLCTL: PINV1 Position */ 1340 #define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) /*!< BPWM_T::POLCTL: PINV1 Mask */ 1341 1342 #define BPWM_POLCTL_PINV2_Pos (2) /*!< BPWM_T::POLCTL: PINV2 Position */ 1343 #define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) /*!< BPWM_T::POLCTL: PINV2 Mask */ 1344 1345 #define BPWM_POLCTL_PINV3_Pos (3) /*!< BPWM_T::POLCTL: PINV3 Position */ 1346 #define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) /*!< BPWM_T::POLCTL: PINV3 Mask */ 1347 1348 #define BPWM_POLCTL_PINV4_Pos (4) /*!< BPWM_T::POLCTL: PINV4 Position */ 1349 #define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) /*!< BPWM_T::POLCTL: PINV4 Mask */ 1350 1351 #define BPWM_POLCTL_PINV5_Pos (5) /*!< BPWM_T::POLCTL: PINV5 Position */ 1352 #define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) /*!< BPWM_T::POLCTL: PINV5 Mask */ 1353 1354 #define BPWM_POLCTL_PINVn_Pos (0) /*!< BPWM_T::POLCTL: PINVn Position */ 1355 #define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) /*!< BPWM_T::POLCTL: PINVn Mask */ 1356 1357 #define BPWM_POEN_POEN0_Pos (0) /*!< BPWM_T::POEN: POEN0 Position */ 1358 #define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) /*!< BPWM_T::POEN: POEN0 Mask */ 1359 1360 #define BPWM_POEN_POEN1_Pos (1) /*!< BPWM_T::POEN: POEN1 Position */ 1361 #define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) /*!< BPWM_T::POEN: POEN1 Mask */ 1362 1363 #define BPWM_POEN_POEN2_Pos (2) /*!< BPWM_T::POEN: POEN2 Position */ 1364 #define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) /*!< BPWM_T::POEN: POEN2 Mask */ 1365 1366 #define BPWM_POEN_POEN3_Pos (3) /*!< BPWM_T::POEN: POEN3 Position */ 1367 #define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) /*!< BPWM_T::POEN: POEN3 Mask */ 1368 1369 #define BPWM_POEN_POEN4_Pos (4) /*!< BPWM_T::POEN: POEN4 Position */ 1370 #define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) /*!< BPWM_T::POEN: POEN4 Mask */ 1371 1372 #define BPWM_POEN_POEN5_Pos (5) /*!< BPWM_T::POEN: POEN5 Position */ 1373 #define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) /*!< BPWM_T::POEN: POEN5 Mask */ 1374 1375 #define BPWM_POEN_POENn_Pos (0) /*!< BPWM_T::POEN: POENn Position */ 1376 #define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) /*!< BPWM_T::POEN: POENn Mask */ 1377 1378 #define BPWM_INTEN_ZIEN0_Pos (0) /*!< BPWM_T::INTEN: ZIEN0 Position */ 1379 #define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) /*!< BPWM_T::INTEN: ZIEN0 Mask */ 1380 1381 #define BPWM_INTEN_PIEN0_Pos (8) /*!< BPWM_T::INTEN: PIEN0 Position */ 1382 #define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) /*!< BPWM_T::INTEN: PIEN0 Mask */ 1383 1384 #define BPWM_INTEN_CMPUIEN0_Pos (16) /*!< BPWM_T::INTEN: CMPUIEN0 Position */ 1385 #define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM_T::INTEN: CMPUIEN0 Mask */ 1386 1387 #define BPWM_INTEN_CMPUIEN1_Pos (17) /*!< BPWM_T::INTEN: CMPUIEN1 Position */ 1388 #define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) /*!< BPWM_T::INTEN: CMPUIEN1 Mask */ 1389 1390 #define BPWM_INTEN_CMPUIEN2_Pos (18) /*!< BPWM_T::INTEN: CMPUIEN2 Position */ 1391 #define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) /*!< BPWM_T::INTEN: CMPUIEN2 Mask */ 1392 1393 #define BPWM_INTEN_CMPUIEN3_Pos (19) /*!< BPWM_T::INTEN: CMPUIEN3 Position */ 1394 #define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) /*!< BPWM_T::INTEN: CMPUIEN3 Mask */ 1395 1396 #define BPWM_INTEN_CMPUIEN4_Pos (20) /*!< BPWM_T::INTEN: CMPUIEN4 Position */ 1397 #define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) /*!< BPWM_T::INTEN: CMPUIEN4 Mask */ 1398 1399 #define BPWM_INTEN_CMPUIEN5_Pos (21) /*!< BPWM_T::INTEN: CMPUIEN5 Position */ 1400 #define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) /*!< BPWM_T::INTEN: CMPUIEN5 Mask */ 1401 1402 #define BPWM_INTEN_CMPUIENn_Pos (16) /*!< BPWM_T::INTEN: CMPUIENn Position */ 1403 #define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM_T::INTEN: CMPUIENn Mask */ 1404 1405 #define BPWM_INTEN_CMPDIEN0_Pos (24) /*!< BPWM_T::INTEN: CMPDIEN0 Position */ 1406 #define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM_T::INTEN: CMPDIEN0 Mask */ 1407 1408 #define BPWM_INTEN_CMPDIEN1_Pos (25) /*!< BPWM_T::INTEN: CMPDIEN1 Position */ 1409 #define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) /*!< BPWM_T::INTEN: CMPDIEN1 Mask */ 1410 1411 #define BPWM_INTEN_CMPDIEN2_Pos (26) /*!< BPWM_T::INTEN: CMPDIEN2 Position */ 1412 #define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) /*!< BPWM_T::INTEN: CMPDIEN2 Mask */ 1413 1414 #define BPWM_INTEN_CMPDIEN3_Pos (27) /*!< BPWM_T::INTEN: CMPDIEN3 Position */ 1415 #define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) /*!< BPWM_T::INTEN: CMPDIEN3 Mask */ 1416 1417 #define BPWM_INTEN_CMPDIEN4_Pos (28) /*!< BPWM_T::INTEN: CMPDIEN4 Position */ 1418 #define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) /*!< BPWM_T::INTEN: CMPDIEN4 Mask */ 1419 1420 #define BPWM_INTEN_CMPDIEN5_Pos (29) /*!< BPWM_T::INTEN: CMPDIEN5 Position */ 1421 #define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) /*!< BPWM_T::INTEN: CMPDIEN5 Mask */ 1422 1423 #define BPWM_INTEN_CMPDIENn_Pos (24) /*!< BPWM_T::INTEN: CMPDIENn Position */ 1424 #define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM_T::INTEN: CMPDIENn Mask */ 1425 1426 #define BPWM_INTSTS_ZIF0_Pos (0) /*!< BPWM_T::INTSTS: ZIF0 Position */ 1427 #define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) /*!< BPWM_T::INTSTS: ZIF0 Mask */ 1428 1429 #define BPWM_INTSTS_PIF0_Pos (8) /*!< BPWM_T::INTSTS: PIF0 Position */ 1430 #define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) /*!< BPWM_T::INTSTS: PIF0 Mask */ 1431 1432 #define BPWM_INTSTS_CMPUIF0_Pos (16) /*!< BPWM_T::INTSTS: CMPUIF0 Position */ 1433 #define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) /*!< BPWM_T::INTSTS: CMPUIF0 Mask */ 1434 1435 #define BPWM_INTSTS_CMPUIF1_Pos (17) /*!< BPWM_T::INTSTS: CMPUIF1 Position */ 1436 #define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) /*!< BPWM_T::INTSTS: CMPUIF1 Mask */ 1437 1438 #define BPWM_INTSTS_CMPUIF2_Pos (18) /*!< BPWM_T::INTSTS: CMPUIF2 Position */ 1439 #define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) /*!< BPWM_T::INTSTS: CMPUIF2 Mask */ 1440 1441 #define BPWM_INTSTS_CMPUIF3_Pos (19) /*!< BPWM_T::INTSTS: CMPUIF3 Position */ 1442 #define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) /*!< BPWM_T::INTSTS: CMPUIF3 Mask */ 1443 1444 #define BPWM_INTSTS_CMPUIF4_Pos (20) /*!< BPWM_T::INTSTS: CMPUIF4 Position */ 1445 #define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) /*!< BPWM_T::INTSTS: CMPUIF4 Mask */ 1446 1447 #define BPWM_INTSTS_CMPUIF5_Pos (21) /*!< BPWM_T::INTSTS: CMPUIF5 Position */ 1448 #define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) /*!< BPWM_T::INTSTS: CMPUIF5 Mask */ 1449 1450 #define BPWM_INTSTS_CMPUIFn_Pos (16) /*!< BPWM_T::INTSTS: CMPUIFn Position */ 1451 #define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) /*!< BPWM_T::INTSTS: CMPUIFn Mask */ 1452 1453 #define BPWM_INTSTS_CMPDIF0_Pos (24) /*!< BPWM_T::INTSTS: CMPDIF0 Position */ 1454 #define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) /*!< BPWM_T::INTSTS: CMPDIF0 Mask */ 1455 1456 #define BPWM_INTSTS_CMPDIF1_Pos (25) /*!< BPWM_T::INTSTS: CMPDIF1 Position */ 1457 #define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) /*!< BPWM_T::INTSTS: CMPDIF1 Mask */ 1458 1459 #define BPWM_INTSTS_CMPDIF2_Pos (26) /*!< BPWM_T::INTSTS: CMPDIF2 Position */ 1460 #define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) /*!< BPWM_T::INTSTS: CMPDIF2 Mask */ 1461 1462 #define BPWM_INTSTS_CMPDIF3_Pos (27) /*!< BPWM_T::INTSTS: CMPDIF3 Position */ 1463 #define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) /*!< BPWM_T::INTSTS: CMPDIF3 Mask */ 1464 1465 #define BPWM_INTSTS_CMPDIF4_Pos (28) /*!< BPWM_T::INTSTS: CMPDIF4 Position */ 1466 #define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) /*!< BPWM_T::INTSTS: CMPDIF4 Mask */ 1467 1468 #define BPWM_INTSTS_CMPDIF5_Pos (29) /*!< BPWM_T::INTSTS: CMPDIF5 Position */ 1469 #define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) /*!< BPWM_T::INTSTS: CMPDIF5 Mask */ 1470 1471 #define BPWM_INTSTS_CMPDIFn_Pos (24) /*!< BPWM_T::INTSTS: CMPDIFn Position */ 1472 #define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) /*!< BPWM_T::INTSTS: CMPDIFn Mask */ 1473 1474 #define BPWM_EADCTS0_TRGSEL0_Pos (0) /*!< BPWM_T::EADCTS0: TRGSEL0 Position */ 1475 #define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) /*!< BPWM_T::EADCTS0: TRGSEL0 Mask */ 1476 1477 #define BPWM_EADCTS0_TRGEN0_Pos (7) /*!< BPWM_T::EADCTS0: TRGEN0 Position */ 1478 #define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) /*!< BPWM_T::EADCTS0: TRGEN0 Mask */ 1479 1480 #define BPWM_EADCTS0_TRGSEL1_Pos (8) /*!< BPWM_T::EADCTS0: TRGSEL1 Position */ 1481 #define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) /*!< BPWM_T::EADCTS0: TRGSEL1 Mask */ 1482 1483 #define BPWM_EADCTS0_TRGEN1_Pos (15) /*!< BPWM_T::EADCTS0: TRGEN1 Position */ 1484 #define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) /*!< BPWM_T::EADCTS0: TRGEN1 Mask */ 1485 1486 #define BPWM_EADCTS0_TRGSEL2_Pos (16) /*!< BPWM_T::EADCTS0: TRGSEL2 Position */ 1487 #define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) /*!< BPWM_T::EADCTS0: TRGSEL2 Mask */ 1488 1489 #define BPWM_EADCTS0_TRGEN2_Pos (23) /*!< BPWM_T::EADCTS0: TRGEN2 Position */ 1490 #define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) /*!< BPWM_T::EADCTS0: TRGEN2 Mask */ 1491 1492 #define BPWM_EADCTS0_TRGSEL3_Pos (24) /*!< BPWM_T::EADCTS0: TRGSEL3 Position */ 1493 #define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) /*!< BPWM_T::EADCTS0: TRGSEL3 Mask */ 1494 1495 #define BPWM_EADCTS0_TRGEN3_Pos (31) /*!< BPWM_T::EADCTS0: TRGEN3 Position */ 1496 #define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) /*!< BPWM_T::EADCTS0: TRGEN3 Mask */ 1497 1498 #define BPWM_EADCTS1_TRGSEL4_Pos (0) /*!< BPWM_T::EADCTS1: TRGSEL4 Position */ 1499 #define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) /*!< BPWM_T::EADCTS1: TRGSEL4 Mask */ 1500 1501 #define BPWM_EADCTS1_TRGEN4_Pos (7) /*!< BPWM_T::EADCTS1: TRGEN4 Position */ 1502 #define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) /*!< BPWM_T::EADCTS1: TRGEN4 Mask */ 1503 1504 #define BPWM_EADCTS1_TRGSEL5_Pos (8) /*!< BPWM_T::EADCTS1: TRGSEL5 Position */ 1505 #define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) /*!< BPWM_T::EADCTS1: TRGSEL5 Mask */ 1506 1507 #define BPWM_EADCTS1_TRGEN5_Pos (15) /*!< BPWM_T::EADCTS1: TRGEN5 Position */ 1508 #define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) /*!< BPWM_T::EADCTS1: TRGEN5 Mask */ 1509 1510 #define BPWM_SSCTL_SSEN0_Pos (0) /*!< BPWM_T::SSCTL: SSEN0 Position */ 1511 #define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) /*!< BPWM_T::SSCTL: SSEN0 Mask */ 1512 1513 #define BPWM_SSCTL_SSRC_Pos (8) /*!< BPWM_T::SSCTL: SSRC Position */ 1514 #define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) /*!< BPWM_T::SSCTL: SSRC Mask */ 1515 1516 #define BPWM_SSTRG_CNTSEN_Pos (0) /*!< BPWM_T::SSTRG: CNTSEN Position */ 1517 #define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) /*!< BPWM_T::SSTRG: CNTSEN Mask */ 1518 1519 #define BPWM_STATUS_CNTMAX0_Pos (0) /*!< BPWM_T::STATUS: CNTMAX0 Position */ 1520 #define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) /*!< BPWM_T::STATUS: CNTMAX0 Mask */ 1521 1522 #define BPWM_STATUS_EADCTRG0_Pos (16) /*!< BPWM_T::STATUS: EADCTRG0 Position */ 1523 #define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) /*!< BPWM_T::STATUS: EADCTRG0 Mask */ 1524 1525 #define BPWM_STATUS_EADCTRG1_Pos (17) /*!< BPWM_T::STATUS: EADCTRG1 Position */ 1526 #define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) /*!< BPWM_T::STATUS: EADCTRG1 Mask */ 1527 1528 #define BPWM_STATUS_EADCTRG2_Pos (18) /*!< BPWM_T::STATUS: EADCTRG2 Position */ 1529 #define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) /*!< BPWM_T::STATUS: EADCTRG2 Mask */ 1530 1531 #define BPWM_STATUS_EADCTRG3_Pos (19) /*!< BPWM_T::STATUS: EADCTRG3 Position */ 1532 #define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) /*!< BPWM_T::STATUS: EADCTRG3 Mask */ 1533 1534 #define BPWM_STATUS_EADCTRG4_Pos (20) /*!< BPWM_T::STATUS: EADCTRG4 Position */ 1535 #define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) /*!< BPWM_T::STATUS: EADCTRG4 Mask */ 1536 1537 #define BPWM_STATUS_EADCTRG5_Pos (21) /*!< BPWM_T::STATUS: EADCTRG5 Position */ 1538 #define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) /*!< BPWM_T::STATUS: EADCTRG5 Mask */ 1539 1540 #define BPWM_STATUS_EADCTRGn_Pos (16) /*!< BPWM_T::STATUS: EADCTRGn Position */ 1541 #define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) /*!< BPWM_T::STATUS: EADCTRGn Mask */ 1542 1543 #define BPWM_CAPINEN_CAPINEN0_Pos (0) /*!< BPWM_T::CAPINEN: CAPINEN0 Position */ 1544 #define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) /*!< BPWM_T::CAPINEN: CAPINEN0 Mask */ 1545 1546 #define BPWM_CAPINEN_CAPINEN1_Pos (1) /*!< BPWM_T::CAPINEN: CAPINEN1 Position */ 1547 #define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) /*!< BPWM_T::CAPINEN: CAPINEN1 Mask */ 1548 1549 #define BPWM_CAPINEN_CAPINEN2_Pos (2) /*!< BPWM_T::CAPINEN: CAPINEN2 Position */ 1550 #define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) /*!< BPWM_T::CAPINEN: CAPINEN2 Mask */ 1551 1552 #define BPWM_CAPINEN_CAPINEN3_Pos (3) /*!< BPWM_T::CAPINEN: CAPINEN3 Position */ 1553 #define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) /*!< BPWM_T::CAPINEN: CAPINEN3 Mask */ 1554 1555 #define BPWM_CAPINEN_CAPINEN4_Pos (4) /*!< BPWM_T::CAPINEN: CAPINEN4 Position */ 1556 #define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) /*!< BPWM_T::CAPINEN: CAPINEN4 Mask */ 1557 1558 #define BPWM_CAPINEN_CAPINEN5_Pos (5) /*!< BPWM_T::CAPINEN: CAPINEN5 Position */ 1559 #define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) /*!< BPWM_T::CAPINEN: CAPINEN5 Mask */ 1560 1561 #define BPWM_CAPINEN_CAPINENn_Pos (0) /*!< BPWM_T::CAPINEN: CAPINENn Position */ 1562 #define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) /*!< BPWM_T::CAPINEN: CAPINENn Mask */ 1563 1564 #define BPWM_CAPCTL_CAPEN0_Pos (0) /*!< BPWM_T::CAPCTL: CAPEN0 Position */ 1565 #define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) /*!< BPWM_T::CAPCTL: CAPEN0 Mask */ 1566 1567 #define BPWM_CAPCTL_CAPEN1_Pos (1) /*!< BPWM_T::CAPCTL: CAPEN1 Position */ 1568 #define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) /*!< BPWM_T::CAPCTL: CAPEN1 Mask */ 1569 1570 #define BPWM_CAPCTL_CAPEN2_Pos (2) /*!< BPWM_T::CAPCTL: CAPEN2 Position */ 1571 #define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) /*!< BPWM_T::CAPCTL: CAPEN2 Mask */ 1572 1573 #define BPWM_CAPCTL_CAPEN3_Pos (3) /*!< BPWM_T::CAPCTL: CAPEN3 Position */ 1574 #define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) /*!< BPWM_T::CAPCTL: CAPEN3 Mask */ 1575 1576 #define BPWM_CAPCTL_CAPEN4_Pos (4) /*!< BPWM_T::CAPCTL: CAPEN4 Position */ 1577 #define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) /*!< BPWM_T::CAPCTL: CAPEN4 Mask */ 1578 1579 #define BPWM_CAPCTL_CAPEN5_Pos (5) /*!< BPWM_T::CAPCTL: CAPEN5 Position */ 1580 #define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) /*!< BPWM_T::CAPCTL: CAPEN5 Mask */ 1581 1582 #define BPWM_CAPCTL_CAPENn_Pos (0) /*!< BPWM_T::CAPCTL: CAPENn Position */ 1583 #define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) /*!< BPWM_T::CAPCTL: CAPENn Mask */ 1584 1585 #define BPWM_CAPCTL_CAPINV0_Pos (8) /*!< BPWM_T::CAPCTL: CAPINV0 Position */ 1586 #define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) /*!< BPWM_T::CAPCTL: CAPINV0 Mask */ 1587 1588 #define BPWM_CAPCTL_CAPINV1_Pos (9) /*!< BPWM_T::CAPCTL: CAPINV1 Position */ 1589 #define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) /*!< BPWM_T::CAPCTL: CAPINV1 Mask */ 1590 1591 #define BPWM_CAPCTL_CAPINV2_Pos (10) /*!< BPWM_T::CAPCTL: CAPINV2 Position */ 1592 #define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) /*!< BPWM_T::CAPCTL: CAPINV2 Mask */ 1593 1594 #define BPWM_CAPCTL_CAPINV3_Pos (11) /*!< BPWM_T::CAPCTL: CAPINV3 Position */ 1595 #define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) /*!< BPWM_T::CAPCTL: CAPINV3 Mask */ 1596 1597 #define BPWM_CAPCTL_CAPINV4_Pos (12) /*!< BPWM_T::CAPCTL: CAPINV4 Position */ 1598 #define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) /*!< BPWM_T::CAPCTL: CAPINV4 Mask */ 1599 1600 #define BPWM_CAPCTL_CAPINV5_Pos (13) /*!< BPWM_T::CAPCTL: CAPINV5 Position */ 1601 #define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) /*!< BPWM_T::CAPCTL: CAPINV5 Mask */ 1602 1603 #define BPWM_CAPCTL_CAPINVn_Pos (8) /*!< BPWM_T::CAPCTL: CAPINVn Position */ 1604 #define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) /*!< BPWM_T::CAPCTL: CAPINVn Mask */ 1605 1606 #define BPWM_CAPCTL_RCRLDEN0_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDEN0 Position */ 1607 #define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN0 Mask */ 1608 1609 #define BPWM_CAPCTL_RCRLDEN1_Pos (17) /*!< BPWM_T::CAPCTL: RCRLDEN1 Position */ 1610 #define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN1 Mask */ 1611 1612 #define BPWM_CAPCTL_RCRLDEN2_Pos (18) /*!< BPWM_T::CAPCTL: RCRLDEN2 Position */ 1613 #define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN2 Mask */ 1614 1615 #define BPWM_CAPCTL_RCRLDEN3_Pos (19) /*!< BPWM_T::CAPCTL: RCRLDEN3 Position */ 1616 #define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN3 Mask */ 1617 1618 #define BPWM_CAPCTL_RCRLDEN4_Pos (20) /*!< BPWM_T::CAPCTL: RCRLDEN4 Position */ 1619 #define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN4 Mask */ 1620 1621 #define BPWM_CAPCTL_RCRLDEN5_Pos (21) /*!< BPWM_T::CAPCTL: RCRLDEN5 Position */ 1622 #define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: RCRLDEN5 Mask */ 1623 1624 #define BPWM_CAPCTL_RCRLDENn_Pos (16) /*!< BPWM_T::CAPCTL: RCRLDENn Position */ 1625 #define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) /*!< BPWM_T::CAPCTL: RCRLDENn Mask */ 1626 1627 #define BPWM_CAPCTL_FCRLDEN0_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDEN0 Position */ 1628 #define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN0 Mask */ 1629 1630 #define BPWM_CAPCTL_FCRLDEN1_Pos (25) /*!< BPWM_T::CAPCTL: FCRLDEN1 Position */ 1631 #define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN1 Mask */ 1632 1633 #define BPWM_CAPCTL_FCRLDEN2_Pos (26) /*!< BPWM_T::CAPCTL: FCRLDEN2 Position */ 1634 #define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN2 Mask */ 1635 1636 #define BPWM_CAPCTL_FCRLDEN3_Pos (27) /*!< BPWM_T::CAPCTL: FCRLDEN3 Position */ 1637 #define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN3 Mask */ 1638 1639 #define BPWM_CAPCTL_FCRLDEN4_Pos (28) /*!< BPWM_T::CAPCTL: FCRLDEN4 Position */ 1640 #define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN4 Mask */ 1641 1642 #define BPWM_CAPCTL_FCRLDEN5_Pos (29) /*!< BPWM_T::CAPCTL: FCRLDEN5 Position */ 1643 #define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) /*!< BPWM_T::CAPCTL: FCRLDEN5 Mask */ 1644 1645 #define BPWM_CAPCTL_FCRLDENn_Pos (24) /*!< BPWM_T::CAPCTL: FCRLDENn Position */ 1646 #define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) /*!< BPWM_T::CAPCTL: FCRLDENn Mask */ 1647 1648 #define BPWM_CAPSTS_CRIFOV0_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOV0 Position */ 1649 #define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) /*!< BPWM_T::CAPSTS: CRIFOV0 Mask */ 1650 1651 #define BPWM_CAPSTS_CRIFOV1_Pos (1) /*!< BPWM_T::CAPSTS: CRIFOV1 Position */ 1652 #define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) /*!< BPWM_T::CAPSTS: CRIFOV1 Mask */ 1653 1654 #define BPWM_CAPSTS_CRIFOV2_Pos (2) /*!< BPWM_T::CAPSTS: CRIFOV2 Position */ 1655 #define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) /*!< BPWM_T::CAPSTS: CRIFOV2 Mask */ 1656 1657 #define BPWM_CAPSTS_CRIFOV3_Pos (3) /*!< BPWM_T::CAPSTS: CRIFOV3 Position */ 1658 #define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) /*!< BPWM_T::CAPSTS: CRIFOV3 Mask */ 1659 1660 #define BPWM_CAPSTS_CRIFOV4_Pos (4) /*!< BPWM_T::CAPSTS: CRIFOV4 Position */ 1661 #define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) /*!< BPWM_T::CAPSTS: CRIFOV4 Mask */ 1662 1663 #define BPWM_CAPSTS_CRIFOV5_Pos (5) /*!< BPWM_T::CAPSTS: CRIFOV5 Position */ 1664 #define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) /*!< BPWM_T::CAPSTS: CRIFOV5 Mask */ 1665 1666 #define BPWM_CAPSTS_CRIFOVn_Pos (0) /*!< BPWM_T::CAPSTS: CRIFOVn Position */ 1667 #define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) /*!< BPWM_T::CAPSTS: CRIFOVn Mask */ 1668 1669 #define BPWM_CAPSTS_CFIFOV0_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOV0 Position */ 1670 #define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) /*!< BPWM_T::CAPSTS: CFIFOV0 Mask */ 1671 1672 #define BPWM_CAPSTS_CFIFOV1_Pos (9) /*!< BPWM_T::CAPSTS: CFIFOV1 Position */ 1673 #define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) /*!< BPWM_T::CAPSTS: CFIFOV1 Mask */ 1674 1675 #define BPWM_CAPSTS_CFIFOV2_Pos (10) /*!< BPWM_T::CAPSTS: CFIFOV2 Position */ 1676 #define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) /*!< BPWM_T::CAPSTS: CFIFOV2 Mask */ 1677 1678 #define BPWM_CAPSTS_CFIFOV3_Pos (11) /*!< BPWM_T::CAPSTS: CFIFOV3 Position */ 1679 #define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) /*!< BPWM_T::CAPSTS: CFIFOV3 Mask */ 1680 1681 #define BPWM_CAPSTS_CFIFOV4_Pos (12) /*!< BPWM_T::CAPSTS: CFIFOV4 Position */ 1682 #define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) /*!< BPWM_T::CAPSTS: CFIFOV4 Mask */ 1683 1684 #define BPWM_CAPSTS_CFIFOV5_Pos (13) /*!< BPWM_T::CAPSTS: CFIFOV5 Position */ 1685 #define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) /*!< BPWM_T::CAPSTS: CFIFOV5 Mask */ 1686 1687 #define BPWM_CAPSTS_CFIFOVn_Pos (8) /*!< BPWM_T::CAPSTS: CFIFOVn Position */ 1688 #define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) /*!< BPWM_T::CAPSTS: CFIFOVn Mask */ 1689 1690 #define BPWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT0: RCAPDAT Position */ 1691 #define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT0: RCAPDAT Mask */ 1692 1693 #define BPWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT0: FCAPDAT Position */ 1694 #define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT0: FCAPDAT Mask */ 1695 1696 #define BPWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT1: RCAPDAT Position */ 1697 #define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT1: RCAPDAT Mask */ 1698 1699 #define BPWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT1: FCAPDAT Position */ 1700 #define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT1: FCAPDAT Mask */ 1701 1702 #define BPWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT2: RCAPDAT Position */ 1703 #define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT2: RCAPDAT Mask */ 1704 1705 #define BPWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT2: FCAPDAT Position */ 1706 #define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT2: FCAPDAT Mask */ 1707 1708 #define BPWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT3: RCAPDAT Position */ 1709 #define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT3: RCAPDAT Mask */ 1710 1711 #define BPWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT3: FCAPDAT Position */ 1712 #define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT3: FCAPDAT Mask */ 1713 1714 #define BPWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT4: RCAPDAT Position */ 1715 #define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT4: RCAPDAT Mask */ 1716 1717 #define BPWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT4: FCAPDAT Position */ 1718 #define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT4: FCAPDAT Mask */ 1719 1720 #define BPWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< BPWM_T::RCAPDAT5: RCAPDAT Position */ 1721 #define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) /*!< BPWM_T::RCAPDAT5: RCAPDAT Mask */ 1722 1723 #define BPWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< BPWM_T::FCAPDAT5: FCAPDAT Position */ 1724 #define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) /*!< BPWM_T::FCAPDAT5: FCAPDAT Mask */ 1725 1726 #define BPWM_CAPIEN_CAPRIENn_Pos (0) /*!< BPWM_T::CAPIEN: CAPRIENn Position */ 1727 #define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) /*!< BPWM_T::CAPIEN: CAPRIENn Mask */ 1728 1729 #define BPWM_CAPIEN_CAPFIENn_Pos (8) /*!< BPWM_T::CAPIEN: CAPFIENn Position */ 1730 #define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) /*!< BPWM_T::CAPIEN: CAPFIENn Mask */ 1731 1732 #define BPWM_CAPIF_CAPRIF0_Pos (0) /*!< BPWM_T::CAPIF: CAPRIF0 Position */ 1733 #define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) /*!< BPWM_T::CAPIF: CAPRIF0 Mask */ 1734 1735 #define BPWM_CAPIF_CAPRIF1_Pos (1) /*!< BPWM_T::CAPIF: CAPRIF1 Position */ 1736 #define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) /*!< BPWM_T::CAPIF: CAPRIF1 Mask */ 1737 1738 #define BPWM_CAPIF_CAPRIF2_Pos (2) /*!< BPWM_T::CAPIF: CAPRIF2 Position */ 1739 #define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) /*!< BPWM_T::CAPIF: CAPRIF2 Mask */ 1740 1741 #define BPWM_CAPIF_CAPRIF3_Pos (3) /*!< BPWM_T::CAPIF: CAPRIF3 Position */ 1742 #define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) /*!< BPWM_T::CAPIF: CAPRIF3 Mask */ 1743 1744 #define BPWM_CAPIF_CAPRIF4_Pos (4) /*!< BPWM_T::CAPIF: CAPRIF4 Position */ 1745 #define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) /*!< BPWM_T::CAPIF: CAPRIF4 Mask */ 1746 1747 #define BPWM_CAPIF_CAPRIF5_Pos (5) /*!< BPWM_T::CAPIF: CAPRIF5 Position */ 1748 #define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) /*!< BPWM_T::CAPIF: CAPRIF5 Mask */ 1749 1750 #define BPWM_CAPIF_CAPRIFn_Pos (0) /*!< BPWM_T::CAPIF: CAPRIFn Position */ 1751 #define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) /*!< BPWM_T::CAPIF: CAPRIFn Mask */ 1752 1753 #define BPWM_CAPIF_CAPFIF0_Pos (8) /*!< BPWM_T::CAPIF: CAPFIF0 Position */ 1754 #define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) /*!< BPWM_T::CAPIF: CAPFIF0 Mask */ 1755 1756 #define BPWM_CAPIF_CAPFIF1_Pos (9) /*!< BPWM_T::CAPIF: CAPFIF1 Position */ 1757 #define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) /*!< BPWM_T::CAPIF: CAPFIF1 Mask */ 1758 1759 #define BPWM_CAPIF_CAPFIF2_Pos (10) /*!< BPWM_T::CAPIF: CAPFIF2 Position */ 1760 #define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) /*!< BPWM_T::CAPIF: CAPFIF2 Mask */ 1761 1762 #define BPWM_CAPIF_CAPFIF3_Pos (11) /*!< BPWM_T::CAPIF: CAPFIF3 Position */ 1763 #define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) /*!< BPWM_T::CAPIF: CAPFIF3 Mask */ 1764 1765 #define BPWM_CAPIF_CAPFIF4_Pos (12) /*!< BPWM_T::CAPIF: CAPFIF4 Position */ 1766 #define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) /*!< BPWM_T::CAPIF: CAPFIF4 Mask */ 1767 1768 #define BPWM_CAPIF_CAPFIF5_Pos (13) /*!< BPWM_T::CAPIF: CAPFIF5 Position */ 1769 #define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) /*!< BPWM_T::CAPIF: CAPFIF5 Mask */ 1770 1771 #define BPWM_CAPIF_CAPFIFn_Pos (8) /*!< BPWM_T::CAPIF: CAPFIFn Position */ 1772 #define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) /*!< BPWM_T::CAPIF: CAPFIFn Mask */ 1773 1774 #define BPWM_PBUF_PBUF_Pos (0) /*!< BPWM_T::PBUF: PBUF Position */ 1775 #define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) /*!< BPWM_T::PBUF: PBUF Mask */ 1776 1777 #define BPWM_CMPBUF0_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF0: CMPBUF Position */ 1778 #define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) /*!< BPWM_T::CMPBUF0: CMPBUF Mask */ 1779 1780 #define BPWM_CMPBUF1_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF1: CMPBUF Position */ 1781 #define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) /*!< BPWM_T::CMPBUF1: CMPBUF Mask */ 1782 1783 #define BPWM_CMPBUF2_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF2: CMPBUF Position */ 1784 #define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) /*!< BPWM_T::CMPBUF2: CMPBUF Mask */ 1785 1786 #define BPWM_CMPBUF3_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF3: CMPBUF Position */ 1787 #define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) /*!< BPWM_T::CMPBUF3: CMPBUF Mask */ 1788 1789 #define BPWM_CMPBUF4_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF4: CMPBUF Position */ 1790 #define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) /*!< BPWM_T::CMPBUF4: CMPBUF Mask */ 1791 1792 #define BPWM_CMPBUF5_CMPBUF_Pos (0) /*!< BPWM_T::CMPBUF5: CMPBUF Position */ 1793 #define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) /*!< BPWM_T::CMPBUF5: CMPBUF Mask */ 1794 1795 /**@}*/ /* BPWM_CONST */ 1796 /**@}*/ /* end of BPWM register group */ 1797 /**@}*/ /* end of REGISTER group */ 1798 1799 1800 #endif /* __BPWM_REG_H__ */ 1801
