| /trusted-firmware-m-3.6.0/platform/ext/target/nxp/common/Native_Driver/drivers/ |
| D | fsl_common_arm.h | 499 static inline status_t EnableIRQ(IRQn_Type interrupt) in EnableIRQ() argument
503 if (NotAvail_IRQn == interrupt) in EnableIRQ()
509 else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) in EnableIRQ()
518 GIC_EnableIRQ(interrupt); in EnableIRQ()
520 NVIC_EnableIRQ(interrupt); in EnableIRQ()
543 static inline status_t DisableIRQ(IRQn_Type interrupt) in DisableIRQ() argument
547 if (NotAvail_IRQn == interrupt) in DisableIRQ()
553 else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) in DisableIRQ()
562 GIC_DisableIRQ(interrupt); in DisableIRQ()
564 NVIC_DisableIRQ(interrupt); in DisableIRQ()
[all …]
|
| D | fsl_common_arm.c | 84 void EnableDeepSleepIRQ(IRQn_Type interrupt) in EnableDeepSleepIRQ() argument
86 uint32_t intNumber = (uint32_t)interrupt; in EnableDeepSleepIRQ()
97 (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ in EnableDeepSleepIRQ()
100 void DisableDeepSleepIRQ(IRQn_Type interrupt) in DisableDeepSleepIRQ() argument
102 uint32_t intNumber = (uint32_t)interrupt; in DisableDeepSleepIRQ()
104 (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ in DisableDeepSleepIRQ()
|
| /trusted-firmware-m-3.6.0/docs/integration_guide/ |
| D | tfm_secure_irq_integration_guide.rst | 9 This document describes how to enable an interrupt in TF-M. The target audiences
20 TF-M supports the two interrupt handling model defined by FF-M:
24 In this model, the interrupt handling is carried out immediately when the
25 interrupt exception happens.
27 The interrupt handling can optionally set an interrupt signal for the Secure
32 In this model, the interrupt handling is deferred after the interrupt
36 The FLIH supports handling an interrupt in a bounded time, but very limited APIs
49 Please refer to chapter 6.2 of FF-M v1.1 [1]_ for more details on the interrupt
56 To enable an interrupt, you need to do the following:
58 - Binding the interrupt to a Secure Partition.
[all …]
|
| D | index.rst | 123 be possible for any non-secure interrupt to preempt a higher-priority secure
124 interrupt.
130 run after handling a secure interrupt that pre-empted the NSPE. On systems
|
| D | tfm_fpu_support.rst | 37 tests on Musca-S1, secure thread fails to trigger secure interrupt. FPU test
|
| /trusted-firmware-m-3.6.0/docs/design_docs/software/ |
| D | tfm_cooperative_scheduling_rules.rst | 23 2. Efficient interrupt handling by SPE as well as NSPE
30 a. NSPE interrupt handling implementation should be independent
44 - A NSPE interrupt take control into NSPE from SPE
45 - A SPE interrupt takes control into SPE from NSPE
87 2. **The SPE interrupt handler is allowed to trigger a SPE context switch**
90 If the SPE context targeted by the interrupt is not same as current SPE context,
98 b. If SP1 was pre-empted by a NSPE interrupt, and subsequent NSPE execution is
104 c. If SP1 was pre-empted by a NSPE interrupt, and subsequent NSPE execution is
110 the SP1 context, if a SPE interrupt preempts the currently running NSPE context,
150 interrupt bringing back the execution into SPE.
[all …]
|
| D | hardware_abstraction_layer.rst | 58 - **Interrupt API**: Provides the interrupt functions.
111 platform, interrupt, devices, etc.
592 The SPM HAL interrupt APIs are intended for operations on Interrupt Controllers
595 APIs for control registers of interrupt sources are not in the scope of this set
614 This API enables an interrupt from the Interrupt Controller of the platform.
618 - ``irq_num`` - the interrupt to be enabled with a number
624 - ``TFM_HAL_ERROR_GENERIC`` - failed to enable the interrupt.
625 - ``TFM_HAL_SUCCESS`` - the interrupt is successfully enabled.
638 This API disables an interrupt from the Interrupt Controller of the platform.
642 - ``irq_num`` - the interrupt to be disabled with a number
[all …]
|
| /trusted-firmware-m-3.6.0/docs/security/security_advisories/ |
| D | stack_seal_vulnerability.rst | 30 Non-Secure interrupt handling (EXC_RETURN), the hardware pops the secure return
57 non-secure interrupt or a non-secure callback invocation, the non-secure
78 As described in the white paper, de-privileged interrupt handling is
80 interrupt handling and does not allow non-secure interrupt to pre-empt the
81 secure interrupt handling. But if the de-privileged handler makes a
86 part of de-privileged interrupt handling mitigates this vulnerability.
88 The interrupt handling in IPC model uses PSA signal to signal the partition
89 and does not use de-privileged interrupt handling mechanism. The PSA signal
91 during interrupt handling in IPC model, there is no additional threat caused
100 interrupt handling) cannot be influenced by the Non Secure world. To mitigate
[all …]
|
| /trusted-firmware-m-3.6.0/platform/ext/target/cypress/psoc64/Device/Source/armclang/ |
| D | startup_psoc64_ns.s | 81 … DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
82 … DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
83 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
113 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
217 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
218 DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
219 DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
220 DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
221 DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
222 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
[all …]
|
| /trusted-firmware-m-3.6.0/platform/ext/target/cypress/psoc64/Device/Source/iar/ |
| D | startup_psoc64_ns.s | 87 … DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt
88 … DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt
89 DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt
119 DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt
223 DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt
224 DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt
225 DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt
226 DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt
227 DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt
228 DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt
[all …]
|
| /trusted-firmware-m-3.6.0/docs/design_docs/dual-cpu/ |
| D | communication_prototype_between_nspe_and_spe_in_dual_core_systems.rst | 65 3. Inter-Processor Communication interrupt handler and mailbox handling in TF-M
155 1. Platform specific Inter-Processor Communication interrupt handler is
156 triggered after the mailbox event is asserted by NSPE. The interrupt handler
169 - `Inter-Processor Communication interrupt handler`_ discusses the
170 Inter-Processor Communication interrupt handler
177 Inter-Processor Communication interrupt handler
181 interrupt handler to deal with the Inter-Processor Communication interrupt
183 The platform specific interrupt handler shall complete the interrupt
184 operations, such as interrupt EOI or acknowledge.
186 The interrupt handler shall call ``spm_handle_interrupt()`` to notify SPM of
[all …]
|
| D | mailbox_design_on_dual_core_system.rst | 198 #. Platform specific Inter-Processor Communication interrupt for mailbox is
199 asserted in SPE. The interrupt handler activates SPE mailbox to process the
252 In SPE, the Inter-Processor Communication interrupt handler should deal with the
255 Communication interrupt handler.
257 NSPE can implement an interrupt handler or a polling of notification status to
297 therefore it must not be called in interrupt service routine.
341 NS mailbox interrupt handler.
371 Communication interrupts. The interrupt handler invokes
450 Platform specific Inter-Processor Communication interrupt handler in SPE should
451 call ``spm_handle_interrupt()`` to notify SPM of the interrupt. SPM will then
[all …]
|
| D | mailbox_ns_agent_update.rst | 24 interrupt handling was not ready. Hence a customized solution
27 - Perform customized operations on SPM internal data in a deferred interrupt
37 - Can use FF-M compliant interrupt mechanism and APIs.
|
| D | booting_a_dual_core_system.rst | 69 interrupt-driven.
|
| /trusted-firmware-m-3.6.0/secure_fw/spm/ |
| D | Kconfig.comp | 25 bool "Run the scheduler after a secure interrupt pre-empts the NSPE"
|
| D | CMakeLists.txt | 62 $<$<OR:$<BOOL:${CONFIG_TFM_FLIH_API}>,$<BOOL:${CONFIG_TFM_SLIH_API}>>:core/interrupt.c>
|
| /trusted-firmware-m-3.6.0/docs/platform/arm/mps3/corstone300/ |
| D | README.rst | 17 interrupt number and an example NPU setup as non-secure, unprivileged.
36 interrupt number and an example NPU setup as non-secure, unprivileged.
45 interrupt number and an example NPU setup as non-secure, unprivileged.
54 interrupt number and an example NPU setup as non-secure, unprivileged.
|
| /trusted-firmware-m-3.6.0/docs/platform/arm/mps3/corstone310/ |
| D | README.rst | 18 interrupt number and an example NPU setup as non-secure, unprivileged.
37 interrupt number and an example NPU setup as non-secure, unprivileged.
47 interrupt number and an example NPU setup as non-secure, unprivileged.
|
| /trusted-firmware-m-3.6.0/docs/releases/ |
| D | 1.4.0.rst | 89 * - | NS interrupt masking prevents from executing PSA calls.
|
| /trusted-firmware-m-3.6.0/platform/ext/target/arm/musca_s1/ |
| D | CMakeLists.txt | 90 # To configure S and NS timer in S side for FP interrupt test
|
| /trusted-firmware-m-3.6.0/docs/security/threat_models/ |
| D | generic_threat_model.rst | 983 | | switches back to Non-secure state on Secure interrupt |
988 | | Secure interrupt return. |
997 | | into secure stack during secure interrupt entry. |
998 | | After secure interrupt handling completes, TF-M unstacks |
1000 | | in R4~R11 before secure interrupt return. |
1004 | | not banked, such as R0~R3 and R12, during secure interrupt |
1041 | | de-privilege an interrupt, it is possible for Non-secure |
|
| /trusted-firmware-m-3.6.0/platform/ext/target/arm/mps3/corstone310/common/ |
| D | common.cmake | 189 # To configure S and NS timer in S side for FP interrupt test
|
| /trusted-firmware-m-3.6.0/docs/platform/arm/rss/ |
| D | rss_comms.rst | 15 polling the MHU or waiting for interrupt). The messages are defined as packed C
|
| /trusted-firmware-m-3.6.0/platform/ext/target/arm/mps3/corstone300/common/ |
| D | common.cmake | 191 # To configure S and NS timer in S side for FP interrupt test
|
| /trusted-firmware-m-3.6.0/docs/design_docs/services/ |
| D | secure_partition_manager.rst | 170 - `Background` state, such as the arrival of secure interrupt or unexpected
517 interrupt handler can preempt an ongoing interrupt execution.
614 - An interrupt triggered scheduling during PendSV execution lead to another
|
