1 /**************************************************************************//** 2 * @file scu_reg.h 3 * @version V1.00 4 * @brief SCU register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SCU_REG_H__ 10 #define __SCU_REG_H__ 11 12 /******************************************************************************/ 13 /* Device Specific Peripheral registers structures */ 14 /******************************************************************************/ 15 16 /** @addtogroup REGISTER Control Register 17 18 @{ 19 20 */ 21 22 23 /*---------------------- Booting Flag -------------------------*/ 24 /** 25 @addtogroup BTF Booting Flag 26 Memory Mapped Structure for BTF Controller 27 @{ 28 */ 29 30 typedef struct 31 { 32 33 34 /** 35 * @var BTF_T::BTF 36 * Offset: 0x00 Booting Flag Register 37 * --------------------------------------------------------------------------------------------------- 38 * |Bits |Field |Descriptions 39 * | :----: | :----: | :---- | 40 * |[0] |BL2 |BL2 Flag 41 * | | |Indicating the CPU is running at BL2 42 */ 43 __IO uint32_t BTF; /*!< [0x0000] Booting Flag Register */ 44 45 } BTF_T; 46 47 /** 48 @addtogroup BTF_CONST BTF Bit Field Definition 49 Constant Definitions for BTF Controller 50 @{ 51 */ 52 53 #define BTF_BTF_BL2_Pos (0) /*!< BTF_T::BTF: BL2 Position */ 54 #define BTF_BTF_BL2_Msk (0x1ul << BTF_BTF_BL2_Pos) /*!< BTF_T::BTF: BL2 Mask */ 55 56 /**@}*/ /* BTF_CONST */ 57 /**@}*/ /* end of BTF register group */ 58 59 60 /*---------------------- Debug Protection Mechanism -------------------------*/ 61 /** 62 @addtogroup DPM Debug Protection Mechanism(DPM) 63 Memory Mapped Structure for DPM Controller 64 @{ 65 */ 66 67 typedef struct 68 { 69 70 71 /** 72 * @var DPM_T::CTL 73 * Offset: 0x00 Secure DPM Control Register 74 * --------------------------------------------------------------------------------------------------- 75 * |Bits |Field |Descriptions 76 * | :----: | :----: | :---- | 77 * |[0] |DBGDIS |Set Secure DPM Debug Disable Bit 78 * | | |When this bit is read as zero, it can be write to one to configure the Secure DPM DBGDIS bit (DBGDISS). 79 * | | |When write: 80 * | | |0 = No operation. 81 * | | |1 = Trigger the process to set DBGDISS configuration bit. 82 * | | |Note: This bit can be set to 1 but cannot be cleared to 0. 83 * |[1] |LOCK |Set Secure DPM Debug Lock Bit 84 * | | |When this bit is read as zero, it can be write to one to configure the Secure DPM LOCK bit (LOCKS). 85 * | | |When write: 86 * | | |0 = No operation. 87 * | | |1 = Trigger the process to set LOCKS configuration bit. 88 * | | |Note: This bit can be set to 1 but cannot be cleared to 0. 89 * |[2] |PWCMP |Secure DPM Password Compare Bit 90 * | | |Set to enter the process of compare Secure DPM password. 91 * | | |0 = No operation. 92 * | | |1 = Compare Secure DPM password. 93 * | | |Note: This bit will be cleared after the comparison process is finished. 94 * |[3] |PWUPD |Secure DPM Password Update Bit 95 * | | |Set to enter the process of updating Secure DPM password. 96 * | | |0 = No operation. 97 * | | |1 = Update Secure DPM password. 98 * | | |Note 1: This bit should be set with PWCMP equal to 0. 99 * | | |Note 2: This bit will be cleared after the update process is finished. 100 * |[8] |INTEN |DPM Interrupt Enable Bit 101 * | | |0 = DPM interrupt function Enabled. 102 * | | |1 = DPM interrupt function Disabled. 103 * |[12] |DACCWDIS |Secure DPM Debug Write Access Disable Bit 104 * | | |This bit disables the writability of external debugger to Secure DPM registers for debug authentication. 105 * | | |0 = External debugger can write Secure DPM registers. 106 * | | |1 = External debugger cannot write Secure DPM registers. 107 * |[13] |DACCDIS |Debug Access Disable Bit 108 * | | |This bit disables the accessibility of external debugger to all DPM registers. 109 * | | |0 = External debugger can read/write DPM registers. 110 * | | |1 = External debugger cannot read/write DPM registers. 111 * |[31:24] |WVCODE |Write Verify Code and Read Verify Code 112 * | |RVCODE |Read operation: 113 * | | |0xA5 = The read access for DPM_CTL is correct. 114 * | | |Others = The read access for DPM_CTL is incorrect. 115 * | | |Write operation: 116 * | | |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_CTL. 117 * | | |Others = Invalid write verify code. 118 * @var DPM_T::STS 119 * Offset: 0x04 Secure DPM Status Register 120 * --------------------------------------------------------------------------------------------------- 121 * |Bits |Field |Descriptions 122 * | :----: | :----: | :---- | 123 * |[0] |BUSY |DPM Busy Flag (Read Only) 124 * | | |This bit indicates the DPM is busy. 125 * | | |0 = DPM is not busy and writing to any register is accepted. 126 * | | |1 = DPM is busy and other bits in DPM_STS register are not valid and writing to any register is ignored. 127 * |[1] |INT |DPM Interrupt Flag (Read Only) 128 * | | |This bit indicates the interrupt is triggered. 129 * | | |0 = Interrupt is not enabled or no password comparison flag is set. 130 * | | |1 = Interrupt is enabled and PWCERR flag in either DPM_STS or DPM_NSSTS register is not cleared. 131 * | | |Note: This bit is cleared automatically when PWCERR flag in both DPM_STS and DPM_NSSTS are zero. 132 * |[4] |PWCERR |Secure DPM Password Compared Error Flag 133 * | | |This bit indicates the result of Secure DPM password comparison. 134 * | | |When read: 135 * | | |0 = The result of Secure DPM password is correct. 136 * | | |1 = The result of Seucre DPM password is incorrect. 137 * | | |Note: This flag is write-one-clear. 138 * |[5] |PWUOK |Secure DPM Password Updated Flag 139 * | | |This bit indicates Secure DPM password has been updated successfully. 140 * | | |When read: 141 * | | |0 = No successful updating process has happened. 142 * | | |1 = There is at least one successful updating process since last clearing of this bit. 143 * | | |Note: This flag is write-one-clear. 144 * |[6] |PWFMAX |Secure DPM Password Fail Times Maximum Reached Flag (Read Only) 145 * | | |This bit indicates if the fail times of comparing Secure DPM password reached max times. 146 * | | |0 = Max time has not reached and Secure DPM password comparison can be triggered. 147 * | | |1 = Max time reached and Secure DPM password comparison cannot be processed anymore. 148 * |[10:8] |PWUCNT |Secure DPM Password Updated Times (Read Only) 149 * | | |This bit indicates how many times of secure password has been updated. 150 * | | |The max value is 7. If PWUCNT reached the max value, Secure DPM password cannot be updated anymore. 151 * |[16] |DBGDIS |Secure Debug Disable Flag (Read Only) 152 * | | |This bit indicates the current value of Secure DPM DBGDIS bit (DBGDISS). 153 * | | |{PWOK, LOCK, DBGDIS} bits define the current state of DPM. 154 * | | |x00 = DEFAULT state. 155 * | | |x1x = LOCKED state. 156 * | | |001 = CLOSE state. 157 * | | |101 = OPEN state. 158 * | | |Others = Unknown. 159 * |[17] |LOCK |Secure Debug Lock Flag (Read Only) 160 * | | |This bit indicates the current value of Secure DPM LOCK bit (LOCKS). 161 * |[18] |PWOK |Secure Password OK Flag (Read Only) 162 * | | |This bit indicates the Secure DPM password has been checked and is correct. 163 * | | |0 = The Secure DPM password has not been checked pass, yet. 164 * | | |1 = The Secure DPM password has been checked pass since last cold reset. 165 * @var DPM_T::SPW 166 * Offset: 0x10 Secure DPM Password 0 167 * --------------------------------------------------------------------------------------------------- 168 * |Bits |Field |Descriptions 169 * | :----: | :----: | :---- | 170 * |[31:0] |PW |Password 171 * | | |Write password[31:0] to this register to update or compare Secure DPM password. 172 * | | |It is write-only and always read as 0xFFFFFFFF. 173 * Offset: 0x14 Secure DPM Password 1 174 * --------------------------------------------------------------------------------------------------- 175 * |Bits |Field |Descriptions 176 * | :----: | :----: | :---- | 177 * |[31:0] |PW |Password 178 * | | |Write password[63:32] to this register to update or compare Secure DPM password 179 * | | |It is write-only and always read as 0xFFFFFFFF. 180 * Offset: 0x18 Secure DPM Password 2 181 * --------------------------------------------------------------------------------------------------- 182 * |Bits |Field |Descriptions 183 * | :----: | :----: | :---- | 184 * |[31:0] |PW |Password 185 * | | |Write password[95:64] to this register to update or compare Secure DPM password. 186 * | | |It is write-only and always read as 0xFFFFFFFF. 187 * Offset: 0x1C Secure DPM Password 3 188 * --------------------------------------------------------------------------------------------------- 189 * |Bits |Field |Descriptions 190 * | :----: | :----: | :---- | 191 * |[31:0] |PW |Password 192 * | | |Write password[127:96] to this register to update or compare Secure DPM password. 193 * | | |It is write-only and always read as 0xFFFFFFFF. 194 * @var DPM_T::NSCTL 195 * Offset: 0x50 Non-secure DPM Control Register 196 * --------------------------------------------------------------------------------------------------- 197 * |Bits |Field |Descriptions 198 * | :----: | :----: | :---- | 199 * |[0] |DBGDIS |Set Non-secure DPM Debug Disable Bit 200 * | | |When this bit is read as zero, it can be write to one to configure the Non-secure DPM DBGDIS bit (DBGDISNS). 201 * | | |When write: 202 * | | |0 = No operation. 203 * | | |1 = Trigger the process to set DBGDISNS configuration bit. 204 * | | |Note: This bit can be set to 1 but cannot be cleared to 0. 205 * |[1] |LOCK |Set Non-secure DPM Debug Lock Bit 206 * | | |When this bit is read as zero, it can be write to one to configure the Non-secure DPM LOCK bit (LOCKNS). 207 * | | |When write: 208 * | | |0 = No operation. 209 * | | |1 = Trigger the process to set LOCKNS configuration bit. 210 * | | |Note: This bit can be set to 1 but cannot be cleared to 0. 211 * |[2] |PWCMP |Non-secure DPM Password Compare Bit 212 * | | |Set to enter the process of compare Non-secure DPM password. 213 * | | |0 = No operation. 214 * | | |1 = Compare Non-secure DPM password. 215 * | | |Note: This bit will be cleared after the comparison process is finished. 216 * |[3] |PWUPD |Non-secure DPM Password Update Bit 217 * | | |Set to enter the process of updating Non-secure DPM password. 218 * | | |0 = No operation. 219 * | | |1 = Update Non-secure DPM password. 220 * | | |Note 1: This bit should be set with PWCMP equal to 0. 221 * | | |Note 2: This bit will be cleared after the update process is finished. 222 * |[12] |DACCWDIS |Debug Write Access Disable Bit 223 * | | |This bit disables the writability of external debugger to Non-secure DPM registers for debug authentication. 224 * | | |0 = External debugger can write Non-secure DPM registers. 225 * | | |1 = External debugger cannot write Non-secure DPM registers. 226 * |[31:24] |WVCODE |Write Verify Code and Read Verify Code 227 * | |RVCODE |Read operation: 228 * | | |0xA5 = The read access for DPM_NSCTL is correct. 229 * | | |Others = The read access for DPM_NSCTL is incorrect. 230 * | | |Write operation: 231 * | | |0x5A = The write verify code, 0x5A, is needed to do a valid write to DPM_NSCTL. 232 * | | |Others = Invalid write verify code. 233 * @var DPM_T::NSSTS 234 * Offset: 0x54 Non-secure DPM Status Register 235 * --------------------------------------------------------------------------------------------------- 236 * |Bits |Field |Descriptions 237 * | :----: | :----: | :---- | 238 * |[0] |BUSY |DPM Busy Flag (Read Only) 239 * | | |This bit indicates the DPM is busy. 240 * | | |0 = DPM is not busy and writing to any register is accepted. 241 * | | |1 = DPM is busy and other bits in DPM_NSSTS register are not valid and writing to any register is ignored. 242 * |[4] |PWCERR |Non-secure DPM Password Compared Error Flag 243 * | | |This bit indicates the result of Non-secure DPM password comparison. 244 * | | |0 = The result of Non-secure DPM password is correct. 245 * | | |1 = The result of Non-seucre DPM password is incorrect. 246 * | | |Note: This flag is write-one-clear. 247 * |[5] |PWUOK |Non-secure DPM Password Updated Flag 248 * | | |This bit indicates Non-secure DPM password has been updated correctly. 249 * | | |When read: 250 * | | |0 = No successful updating process has happened. 251 * | | |1 = There is at least one successful updating process since last clearing of this bit. 252 * | | |Note: This flag is write-one-clear. 253 * |[6] |PWFMAX |Non-secure DPM Password Fail Times Maximum Reached Flag (Read Only) 254 * | | |This bit indicates if the fail times of comparing Non-secure DPM password reached max times. 255 * | | |0 = Max time has not reached and Non-secure DPM password comparison can be triggered. 256 * | | |1 = Max time reached and Non-secure DPM password comparison cannot be processed anymore. 257 * |[10:8] |PWUCNT |Non-secure DPM Password Updated Times (Read Only) 258 * | | |This bit indicates how many times of non-secure password has been updated. 259 * | | |The max value is 7. If PWUCNT reached the max value, Non-secure DPM password cannot be updated anymore. 260 * |[16] |DBGDIS |Non-secure Debug Disable Flag (Read Only) 261 * | | |This bit indicates the current value of of Non-secure DPM DBGDIS bit (DBGDISNS). 262 * | | |{PWOK, LOCK, DBGDIS} bits define the current state of DPM. 263 * | | |x00 = DEFAULT state. 264 * | | |x1x = LOCKED state. 265 * | | |001 = CLOSE state. 266 * | | |101 = OPEN state. 267 * | | |Others = Unknown. 268 * |[17] |LOCK |Non-secure Debug Lock Flag (Read Only) 269 * | | |This bit indicates the current value of Non-secure DPM DBGDIS bit (LOCKNS). 270 * |[18] |PWOK |Non-secure Password OK Flag (Read Only) 271 * | | |This bit indicates the Non-secure DPM password has been checked and is correct. 272 * | | |0 = The Non-secure DPM password has not been checked pass, yet. 273 * | | |1 = The Non-secure DPM password has been checked pass since last cold reset. 274 * @var DPM_T::NSPW 275 * Offset: 0x60 Non-secure DPM Password 0 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[31:0] |PW |Password 280 * | | |Write password[31:0] to this register to update or compare Non-secure DPM password. 281 * | | |It is write-only and always read as 0xFFFFFFFF. 282 * Offset: 0x64 Non-secure DPM Password 1 283 * --------------------------------------------------------------------------------------------------- 284 * |Bits |Field |Descriptions 285 * | :----: | :----: | :---- | 286 * |[31:0] |PW |Password 287 * | | |Write password[63:32] to this register to update or compare Non-secure DPM password. 288 * | | |It is write-only and always read as 0xFFFFFFFF. 289 * Offset: 0x68 Non-secure DPM Password 2 290 * --------------------------------------------------------------------------------------------------- 291 * |Bits |Field |Descriptions 292 * | :----: | :----: | :---- | 293 * |[31:0] |PW |Password 294 * | | |Write password[95:64] to this register to update or compare Non-secure DPM password. 295 * | | |It is write-only and always read as 0xFFFFFFFF. 296 * Offset: 0x6C Non-secure DPM Password 3 297 * --------------------------------------------------------------------------------------------------- 298 * |Bits |Field |Descriptions 299 * | :----: | :----: | :---- | 300 * |[31:0] |PW |Password 301 * | | |Write password[127:96] to this register to update or compare Non-secure DPM password. 302 * | | |It is write-only and always read as 0xFFFFFFFF. 303 */ 304 __IO uint32_t CTL; /*!< [0x0000] Secure DPM Control Register */ 305 __IO uint32_t STS; /*!< [0x0004] Secure DPM Status Register */ 306 __I uint32_t RESERVE0[2]; 307 __O uint32_t SPW[4]; /*!< [0x0010/0x0014/0x0018/0x001c] Secure DPM Password 0/1/2/3 */ 308 __I uint32_t RESERVE1[12]; 309 __IO uint32_t NSCTL; /*!< [0x0050] Non-secure DPM Control Register */ 310 __IO uint32_t NSSTS; /*!< [0x0054] Non-secure DPM Status Register */ 311 __I uint32_t RESERVE2[2]; 312 __O uint32_t NSPW[4]; /*!< [0x00600/0x0064/0x0068/0x006c] Non-secure DPM Password 0/1/2/3 */ 313 314 315 } DPM_T; 316 317 /** 318 @addtogroup DPM_CONST DPM Bit Field Definition 319 Constant Definitions for DPM Controller 320 @{ 321 */ 322 323 #define DPM_CTL_DBGDIS_Pos (0) /*!< DPM_T::CTL: DBGDIS Position */ 324 #define DPM_CTL_DBGDIS_Msk (0x1ul << DPM_CTL_DBGDIS_Pos) /*!< DPM_T::CTL: DBGDIS Mask */ 325 326 #define DPM_CTL_LOCK_Pos (1) /*!< DPM_T::CTL: LOCK Position */ 327 #define DPM_CTL_LOCK_Msk (0x1ul << DPM_CTL_LOCK_Pos) /*!< DPM_T::CTL: LOCK Mask */ 328 329 #define DPM_CTL_PWCMP_Pos (2) /*!< DPM_T::CTL: PWCMP Position */ 330 #define DPM_CTL_PWCMP_Msk (0x1ul << DPM_CTL_PWCMP_Pos) /*!< DPM_T::CTL: PWCMP Mask */ 331 332 #define DPM_CTL_PWUPD_Pos (3) /*!< DPM_T::CTL: PWUPD Position */ 333 #define DPM_CTL_PWUPD_Msk (0x1ul << DPM_CTL_PWUPD_Pos) /*!< DPM_T::CTL: PWUPD Mask */ 334 335 #define DPM_CTL_INTEN_Pos (8) /*!< DPM_T::CTL: INTEN Position */ 336 #define DPM_CTL_INTEN_Msk (0x1ul << DPM_CTL_INTEN_Pos) /*!< DPM_T::CTL: INTEN Mask */ 337 338 #define DPM_CTL_DACCWDIS_Pos (12) /*!< DPM_T::CTL: DACCWDIS Position */ 339 #define DPM_CTL_DACCWDIS_Msk (0x1ul << DPM_CTL_DACCWDIS_Pos) /*!< DPM_T::CTL: DACCWDIS Mask */ 340 341 #define DPM_CTL_DACCDIS_Pos (13) /*!< DPM_T::CTL: DACCDIS Position */ 342 #define DPM_CTL_DACCDIS_Msk (0x1ul << DPM_CTL_DACCDIS_Pos) /*!< DPM_T::CTL: DACCDIS Mask */ 343 344 #define DPM_CTL_WVCODE_Pos (24) /*!< DPM_T::CTL: WVCODE Position */ 345 #define DPM_CTL_WVCODE_Msk (0xfful << DPM_CTL_WVCODE_Pos) /*!< DPM_T::CTL: WVCODE Mask */ 346 347 #define DPM_CTL_RVCODE_Pos (24) /*!< DPM_T::CTL: RVCODE Position */ 348 #define DPM_CTL_RVCODE_Msk (0xfful << DPM_CTL_RVCODE_Pos) /*!< DPM_T::CTL: RVCODE Mask */ 349 350 #define DPM_STS_BUSY_Pos (0) /*!< DPM_T::STS: BUSY Position */ 351 #define DPM_STS_BUSY_Msk (0x1ul << DPM_STS_BUSY_Pos) /*!< DPM_T::STS: BUSY Mask */ 352 353 #define DPM_STS_INT_Pos (1) /*!< DPM_T::STS: INT Position */ 354 #define DPM_STS_INT_Msk (0x1ul << DPM_STS_INT_Pos) /*!< DPM_T::STS: INT Mask */ 355 356 #define DPM_STS_PWCERR_Pos (4) /*!< DPM_T::STS: PWCERR Position */ 357 #define DPM_STS_PWCERR_Msk (0x1ul << DPM_STS_PWCERR_Pos) /*!< DPM_T::STS: PWCERR Mask */ 358 359 #define DPM_STS_PWUOK_Pos (5) /*!< DPM_T::STS: PWUOK Position */ 360 #define DPM_STS_PWUOK_Msk (0x1ul << DPM_STS_PWUOK_Pos) /*!< DPM_T::STS: PWUOK Mask */ 361 362 #define DPM_STS_PWFMAX_Pos (6) /*!< DPM_T::STS: PWFMAX Position */ 363 #define DPM_STS_PWFMAX_Msk (0x1ul << DPM_STS_PWFMAX_Pos) /*!< DPM_T::STS: PWFMAX Mask */ 364 365 #define DPM_STS_PWUCNT_Pos (8) /*!< DPM_T::STS: PWUCNT Position */ 366 #define DPM_STS_PWUCNT_Msk (0x7ul << DPM_STS_PWUCNT_Pos) /*!< DPM_T::STS: PWUCNT Mask */ 367 368 #define DPM_STS_DBGDIS_Pos (16) /*!< DPM_T::STS: DBGDIS Position */ 369 #define DPM_STS_DBGDIS_Msk (0x1ul << DPM_STS_DBGDIS_Pos) /*!< DPM_T::STS: DBGDIS Mask */ 370 371 #define DPM_STS_LOCK_Pos (17) /*!< DPM_T::STS: LOCK Position */ 372 #define DPM_STS_LOCK_Msk (0x1ul << DPM_STS_LOCK_Pos) /*!< DPM_T::STS: LOCK Mask */ 373 374 #define DPM_STS_PWOK_Pos (18) /*!< DPM_T::STS: PWOK Position */ 375 #define DPM_STS_PWOK_Msk (0x1ul << DPM_STS_PWOK_Pos) /*!< DPM_T::STS: PWOK Mask */ 376 377 #define DPM_SPW0_PW_Pos (0) /*!< DPM_T::SPW0: PW Position */ 378 #define DPM_SPW0_PW_Msk (0xfffffffful << DPM_SPW0_PW_Pos) /*!< DPM_T::SPW0: PW Mask */ 379 380 #define DPM_SPW1_PW_Pos (0) /*!< DPM_T::SPW1: PW Position */ 381 #define DPM_SPW1_PW_Msk (0xfffffffful << DPM_SPW1_PW_Pos) /*!< DPM_T::SPW1: PW Mask */ 382 383 #define DPM_SPW2_PW_Pos (0) /*!< DPM_T::SPW2: PW Position */ 384 #define DPM_SPW2_PW_Msk (0xfffffffful << DPM_SPW2_PW_Pos) /*!< DPM_T::SPW2: PW Mask */ 385 386 #define DPM_SPW3_PW_Pos (0) /*!< DPM_T::SPW3: PW Position */ 387 #define DPM_SPW3_PW_Msk (0xfffffffful << DPM_SPW3_PW_Pos) /*!< DPM_T::SPW3: PW Mask */ 388 389 #define DPM_NSCTL_DBGDIS_Pos (0) /*!< DPM_T::NSCTL: DBGDIS Position */ 390 #define DPM_NSCTL_DBGDIS_Msk (0x1ul << DPM_NSCTL_DBGDIS_Pos) /*!< DPM_T::NSCTL: DBGDIS Mask */ 391 392 #define DPM_NSCTL_LOCK_Pos (1) /*!< DPM_T::NSCTL: LOCK Position */ 393 #define DPM_NSCTL_LOCK_Msk (0x1ul << DPM_NSCTL_LOCK_Pos) /*!< DPM_T::NSCTL: LOCK Mask */ 394 395 #define DPM_NSCTL_PWCMP_Pos (2) /*!< DPM_T::NSCTL: PWCMP Position */ 396 #define DPM_NSCTL_PWCMP_Msk (0x1ul << DPM_NSCTL_PWCMP_Pos) /*!< DPM_T::NSCTL: PWCMP Mask */ 397 398 #define DPM_NSCTL_PWUPD_Pos (3) /*!< DPM_T::NSCTL: PWUPD Position */ 399 #define DPM_NSCTL_PWUPD_Msk (0x1ul << DPM_NSCTL_PWUPD_Pos) /*!< DPM_T::NSCTL: PWUPD Mask */ 400 401 #define DPM_NSCTL_DACCWDIS_Pos (12) /*!< DPM_T::NSCTL: DACCWDIS Position */ 402 #define DPM_NSCTL_DACCWDIS_Msk (0x1ul << DPM_NSCTL_DACCWDIS_Pos) /*!< DPM_T::NSCTL: DACCWDIS Mask */ 403 404 #define DPM_NSCTL_WVCODE_Pos (24) /*!< DPM_T::NSCTL: WVCODE Position */ 405 #define DPM_NSCTL_WVCODE_Msk (0xfful << DPM_NSCTL_WVCODE_Pos) /*!< DPM_T::NSCTL: WVCODE Mask */ 406 407 #define DPM_NSCTL_RVCODE_Pos (24) /*!< DPM_T::NSCTL: RVCODE Position */ 408 #define DPM_NSCTL_RVCODE_Msk (0xfful << DPM_NSCTL_RVCODE_Pos) /*!< DPM_T::NSCTL: RVCODE Mask */ 409 410 #define DPM_NSSTS_BUSY_Pos (0) /*!< DPM_T::NSSTS: BUSY Position */ 411 #define DPM_NSSTS_BUSY_Msk (0x1ul << DPM_NSSTS_BUSY_Pos) /*!< DPM_T::NSSTS: BUSY Mask */ 412 413 #define DPM_NSSTS_PWCERR_Pos (4) /*!< DPM_T::NSSTS: PWCERR Position */ 414 #define DPM_NSSTS_PWCERR_Msk (0x1ul << DPM_NSSTS_PWCERR_Pos) /*!< DPM_T::NSSTS: PWCERR Mask */ 415 416 #define DPM_NSSTS_PWUOK_Pos (5) /*!< DPM_T::NSSTS: PWUOK Position */ 417 #define DPM_NSSTS_PWUOK_Msk (0x1ul << DPM_NSSTS_PWUOK_Pos) /*!< DPM_T::NSSTS: PWUOK Mask */ 418 419 #define DPM_NSSTS_PWFMAX_Pos (6) /*!< DPM_T::NSSTS: PWFMAX Position */ 420 #define DPM_NSSTS_PWFMAX_Msk (0x1ul << DPM_NSSTS_PWFMAX_Pos) /*!< DPM_T::NSSTS: PWFMAX Mask */ 421 422 #define DPM_NSSTS_PWUCNT_Pos (8) /*!< DPM_T::NSSTS: PWUCNT Position */ 423 #define DPM_NSSTS_PWUCNT_Msk (0x7ul << DPM_NSSTS_PWUCNT_Pos) /*!< DPM_T::NSSTS: PWUCNT Mask */ 424 425 #define DPM_NSSTS_DBGDIS_Pos (16) /*!< DPM_T::NSSTS: DBGDIS Position */ 426 #define DPM_NSSTS_DBGDIS_Msk (0x1ul << DPM_NSSTS_DBGDIS_Pos) /*!< DPM_T::NSSTS: DBGDIS Mask */ 427 428 #define DPM_NSSTS_LOCK_Pos (17) /*!< DPM_T::NSSTS: LOCK Position */ 429 #define DPM_NSSTS_LOCK_Msk (0x1ul << DPM_NSSTS_LOCK_Pos) /*!< DPM_T::NSSTS: LOCK Mask */ 430 431 #define DPM_NSSTS_PWOK_Pos (18) /*!< DPM_T::NSSTS: PWOK Position */ 432 #define DPM_NSSTS_PWOK_Msk (0x1ul << DPM_NSSTS_PWOK_Pos) /*!< DPM_T::NSSTS: PWOK Mask */ 433 434 #define DPM_NSPW0_PW_Pos (0) /*!< DPM_T::NSPW0: PW Position */ 435 #define DPM_NSPW0_PW_Msk (0xfffffffful << DPM_NSPW0_PW_Pos) /*!< DPM_T::NSPW0: PW Mask */ 436 437 #define DPM_NSPW1_PW_Pos (0) /*!< DPM_T::NSPW1: PW Position */ 438 #define DPM_NSPW1_PW_Msk (0xfffffffful << DPM_NSPW1_PW_Pos) /*!< DPM_T::NSPW1: PW Mask */ 439 440 #define DPM_NSPW2_PW_Pos (0) /*!< DPM_T::NSPW2: PW Position */ 441 #define DPM_NSPW2_PW_Msk (0xfffffffful << DPM_NSPW2_PW_Pos) /*!< DPM_T::NSPW2: PW Mask */ 442 443 #define DPM_NSPW3_PW_Pos (0) /*!< DPM_T::NSPW3: PW Position */ 444 #define DPM_NSPW3_PW_Msk (0xfffffffful << DPM_NSPW3_PW_Pos) /*!< DPM_T::NSPW3: PW Mask */ 445 446 447 /**@}*/ /* DPM_CONST */ 448 /**@}*/ /* end of DPM register group */ 449 450 451 452 /*---------------------- Firmware Version Counter -------------------------*/ 453 /** 454 @addtogroup FVC Firmware Version Counter(FVC) 455 Memory Mapped Structure for FVC Controller 456 @{ */ 457 458 typedef struct 459 { 460 461 462 /** 463 * @var FVC_T::CTL 464 * Offset: 0x00 FVC Control Register 465 * --------------------------------------------------------------------------------------------------- 466 * |Bits |Field |Descriptions 467 * | :----: | :----: | :---- | 468 * |[0] |INIT |FVC Init Bit 469 * | | |Set to 1 to enable FVC 470 * | | |This bit is writable when FVC is at Reset state. 471 * | | |Note: After set to 1, this bit is cleared to 0 automatically when FVC is back to Reset state. 472 * |[1] |MONOEN |Monotonic Enable Bit 473 * | | |Set to 1 to enable the monotonic mechanism of FVC. 474 * | | |Note: This bit can be set to1 but cannot be cleared to 0. 475 * |[31:16] |WVCODE |Verification Code 476 * | | |When written, this field must be 0x7710 477 * @var FVC_T::STS 478 * Offset: 0x04 FVC Status Register 479 * --------------------------------------------------------------------------------------------------- 480 * |Bits |Field |Descriptions 481 * | :----: | :----: | :---- | 482 * |[0] |BUSY |FVC Busy Bit 483 * | | |Indicates the FVC is at busy state. 484 * |[1] |RDY |FVC Ready Bit 485 * | | |Indicates the FVC is ready after the initial process. 486 * @var FVC_T::NVC0 487 * Offset: 0x10 Non-volatile Version Counter Control Register0 BL2 Firmware 488 * --------------------------------------------------------------------------------------------------- 489 * |Bits |Field |Descriptions 490 * | :----: | :----: | :---- | 491 * |[15:0] |FWVER |Firmware Version 492 * | | |Read: Indicates the current firmware version of FVC0. 493 * | | |Write: Updates the firmware version of FVC0. 494 * | | |The maximum value of this field is 63. 495 * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash 496 * |[31:16] |WVCODE |Verification Code 497 * | | |When written, this field must be the current firmware version number 498 * @var FVC_T::NVC1 499 * Offset: 0x14 Non-volatile Version Counter Control Register1 BL32 Firmware 500 * --------------------------------------------------------------------------------------------------- 501 * |Bits |Field |Descriptions 502 * | :----: | :----: | :---- | 503 * |[15:0] |FWVER |Firmware Version 504 * | | |Read: Indicates the current firmware version of NVC1. 505 * | | |Write: Updates the firmware version of NVC1. 506 * | | |The maximum value of this field is 63. 507 * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash 508 * |[31:16] |WVCODE |Verification Code 509 * | | |When written, this field must be the current firmware version number 510 * @var FVC_T::NVC4 511 * Offset: 0x20 Non-volatile Version Counter Control Register4 BL33 Firmware 512 * --------------------------------------------------------------------------------------------------- 513 * |Bits |Field |Descriptions 514 * | :----: | :----: | :---- | 515 * |[15:0] |FWVER |Firmware Version 516 * | | |Read: Indicates the current firmware version of NVC4. 517 * | | |Write: Updates the firmware version of NVC4. 518 * | | |The maximum value of this field is 255. 519 * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash 520 * |[31:16] |WVCODE |Verification Code 521 * | | |When written, this field must be the current firmware version number 522 * @var FVC_T::NVC5 523 * Offset: 0x24 Non-volatile Version Counter Control Register5 User-defined Firmware 524 * --------------------------------------------------------------------------------------------------- 525 * |Bits |Field |Descriptions 526 * | :----: | :----: | :---- | 527 * |[15:0] |FWVER |Firmware Version 528 * | | |Read: Indicates the current firmware version of NVC5. 529 * | | |Write: Updates the firmware version of NVC5. 530 * | | |The maximum value of this field is 255. 531 * | | |Indicating number of 1 in Fuse OTP or number of 0 in Flash 532 * |[31:16] |WVCODE |Verification Code 533 * | | |When written, this field must be the current firmware version number 534 */ 535 __IO uint32_t CTL; /*!< [0x0000] FVC Control Register */ 536 __I uint32_t STS; /*!< [0x0004] FVC Status Register */ 537 __I uint32_t RESERVE0[2]; 538 __IO uint32_t NVC[6]; /*!< [0x0010-0x24] Non-volatile Version Counter Control Register Firmware. NVC[2], NVC[3] is reserved */ 539 } FVC_T; 540 541 /** 542 @addtogroup FVC_CONST FVC Bit Field Definition 543 Constant Definitions for FVC Controller 544 @{ */ 545 546 #define FVC_CTL_INIT_Pos (0) /*!< FVC_T::CTL: INIT Position */ 547 #define FVC_CTL_INIT_Msk (0x1ul << FVC_CTL_INIT_Pos) /*!< FVC_T::CTL: INIT Mask */ 548 549 #define FVC_CTL_MONOEN_Pos (1) /*!< FVC_T::CTL: MONOEN Position */ 550 #define FVC_CTL_MONOEN_Msk (0x1ul << FVC_CTL_MONOEN_Pos) /*!< FVC_T::CTL: MONOEN Mask */ 551 552 #define FVC_CTL_WVCODE_Pos (16) /*!< FVC_T::CTL: WVCODE Position */ 553 #define FVC_CTL_WVCODE_Msk (0xfffful << FVC_CTL_WVCODE_Pos) /*!< FVC_T::CTL: WVCODE Mask */ 554 555 #define FVC_STS_BUSY_Pos (0) /*!< FVC_T::STS: BUSY Position */ 556 #define FVC_STS_BUSY_Msk (0x1ul << FVC_STS_BUSY_Pos) /*!< FVC_T::STS: BUSY Mask */ 557 558 #define FVC_STS_RDY_Pos (1) /*!< FVC_T::STS: RDY Position */ 559 #define FVC_STS_RDY_Msk (0x1ul << FVC_STS_RDY_Pos) /*!< FVC_T::STS: RDY Mask */ 560 561 #define FVC_NVC_FWVER_Pos (0) /*!< FVC_T::NVC: FWVER Position */ 562 #define FVC_NVC_FWVER_Msk (0xfffful << FVC_NVC_FWVER_Pos) /*!< FVC_T::NVC: FWVER Mask */ 563 564 /**@}*/ /* FVC_CONST */ 565 /**@}*/ /* end of FVC register group */ 566 567 568 /*---------------------- Product Life-cycle Manager -------------------------*/ 569 /** 570 @addtogroup PLM Product Life-cycle Manager(PLM) 571 Memory Mapped Structure for PLM Controller 572 @{ 573 */ 574 575 typedef struct 576 { 577 578 579 /** 580 * @var PLM_T::CTL 581 * Offset: 0x00 Product Life-cycle Control Register 582 * --------------------------------------------------------------------------------------------------- 583 * |Bits |Field |Descriptions 584 * | :----: | :----: | :---- | 585 * |[2:0] |STAGE |Life-cycle Stage Update Bits 586 * | | |Bits to update PLM stage. All bits can be set to one but cannot be cleared to zero. 587 * | | |001 = progress to OEM stage. 588 * | | |011 = progress to Deployed stage. 589 * | | |111 = progress to RMA stage. 590 * | | |Other value will be ignored. 591 * |[31:16] |WVCODE |Write Verify Code 592 * | | |The code is 0x475A for a valid write to this register. 593 * @var PLM_T::STS 594 * Offset: 0x04 Product Life-cycle Status Register 595 * --------------------------------------------------------------------------------------------------- 596 * |Bits |Field |Descriptions 597 * | :----: | :----: | :---- | 598 * |[2:0] |STAGE |Life-cycle Stage (Read Only) 599 * | | |Indicates the current stage of PLM. 600 * | | |000 = Vendor Stage. 601 * | | |001 = OEM Stage. 602 * | | |011 = Deployed Stage. 603 * | | |111 = RMA Stage. 604 * | | |Others = ERROR Stage. 605 * |[8] |DIRTY |DIRTY Bit (Read Only) 606 * | | |Indicate the life-cycle stage has been progressed after last cold-reset 607 * | | |Value of STAGE bits is not Current stage of PLM 608 * | | |It needs a cold reset to make it work. 609 */ 610 __IO uint32_t CTL; /*!< [0x0000] Product Life-cycle Control Register */ 611 __I uint32_t STS; /*!< [0x0004] Product Life-cycle Status Register */ 612 613 } PLM_T; 614 615 /** 616 @addtogroup PLM_CONST PLM Bit Field Definition 617 Constant Definitions for PLM Controller 618 @{ 619 */ 620 621 #define PLM_CTL_STAGE_Pos (0) /*!< PLM_T::CTL: STAGE Position */ 622 #define PLM_CTL_STAGE_Msk (0x7ul << PLM_CTL_STAGE_Pos) /*!< PLM_T::CTL: STAGE Mask */ 623 624 #define PLM_CTL_WVCODE_Pos (16) /*!< PLM_T::CTL: WVCODE Position */ 625 #define PLM_CTL_WVCODE_Msk (0xfffful << PLM_CTL_WVCODE_Pos) /*!< PLM_T::CTL: WVCODE Mask */ 626 627 #define PLM_STS_STAGE_Pos (0) /*!< PLM_T::STS: STAGE Position */ 628 #define PLM_STS_STAGE_Msk (0x7ul << PLM_STS_STAGE_Pos) /*!< PLM_T::STS: STAGE Mask */ 629 630 #define PLM_STS_DIRTY_Pos (8) /*!< PLM_T::STS: DIRTY Position */ 631 #define PLM_STS_DIRTY_Msk (0x1ul << PLM_STS_DIRTY_Pos) /*!< PLM_T::STS: DIRTY Mask */ 632 633 /**@}*/ /* PLM_CONST */ 634 /**@}*/ /* end of PLM register group */ 635 636 637 /*---------------------- Secure configuration Unit -------------------------*/ 638 /** 639 @addtogroup SCU Secure configuration Unit(SCU) 640 Memory Mapped Structure for SCU Controller 641 @{ 642 */ 643 644 typedef struct 645 { 646 647 648 /** 649 * @var SCU_T::PNSSET 650 * Offset: 0x00 Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF) 651 * --------------------------------------------------------------------------------------------------- 652 * |Bits |Field |Descriptions 653 * | :----: | :----: | :---- | 654 * |[9] |USBH |Set USBH to Non-secure State 655 * | | |Write 1 to set USBH to non-secure state. Write 0 has no effect. 656 * | | |0 = USBH is a secure module (default). 657 * | | |1 = USBH is a non-secure module. 658 * |[13] |SDH0 |Set SDH0 to Non-secure State 659 * | | |Write 1 to set SDH0 to non-secure state. Write 0 has no effect. 660 * | | |0 = SDH0 is a secure module (default). 661 * | | |1 = SDH0 is a non-secure module. 662 * |[16] |EBI |Set EBI to Non-secure State 663 * | | |Write 1 to set EBI to non-secure state. Write 0 has no effect. 664 * | | |0 = EBI is a secure module (default). 665 * | | |1 = EBI is a non-secure module. 666 * |[24] |PDMA1 |Set PDMA1 to Non-secure State 667 * | | |Write 1 to set PDMA1 to non-secure state. Write 0 has no effect. 668 * | | |0 = PDMA1 is a secure module (default). 669 * | | |1 = PDMA1 is a non-secure module. 670 * Offset: 0x04 Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF) 671 * --------------------------------------------------------------------------------------------------- 672 * |Bits |Field |Descriptions 673 * | :----: | :----: | :---- | 674 * |[17] |CRC |Set CRC to Non-secure State 675 * | | |Write 1 to set CRC to non-secure state. Write 0 has no effect. 676 * | | |0 = CRC is a secure module (default). 677 * | | |1 = CRC is a non-secure module. 678 * |[18] |CRPT |Set CRPT to Non-secure State 679 * | | |0 = CRPT is a secure module (default). 680 * | | |1 = CRPT is a non-secure module. 681 * Offset: 0x08 Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF) 682 * --------------------------------------------------------------------------------------------------- 683 * |Bits |Field |Descriptions 684 * | :----: | :----: | :---- | 685 * |[2] |EWDT |Set EWDT to Non-secure State 686 * | | |Write 1 to set EWDT to non-secure state. Write 0 has no effect. 687 * | | |0 = EWDT is a secure module (default). 688 * | | |1 = EWDT is a non-secure module. 689 * |[3] |EADC |Set EADC to Non-secure State 690 * | | |Write 1 to set EADC to non-secure state. Write 0 has no effect. 691 * | | |0 = EADC is a secure module (default). 692 * | | |1 = EADC is a non-secure module. 693 * |[5] |ACMP01 |Set ACMP01 to Non-secure State 694 * | | |Write 1 to set ACMP0, ACMP1 to non-secure state. Write 0 has no effect. 695 * | | |0 = ACMP0, ACMP1 are secure modules (default). 696 * | | |1 = ACMP0, ACMP1 are non-secure modules. 697 * |[7] |DAC |Set DAC to Non-secure State 698 * | | |Write 1 to set DAC to non-secure state. Write 0 has no effect. 699 * | | |0 = DAC is a secure module (default). 700 * | | |1 = DAC is a non-secure module. 701 * |[8] |I2S0 |Set I2S0 to Non-secure State 702 * | | |Write 1 to set I2S0 to non-secure state. Write 0 has no effect. 703 * | | |0 = I2S0 is a secure module (default). 704 * | | |1 = I2S0 is a non-secure module. 705 * |[13] |OTG |Set OTG to Non-secure State 706 * | | |Write 1 to set OTG to non-secure state. Write 0 has no effect. 707 * | | |0 = OTG is a secure module (default). 708 * | | |1 = OTG is a non-secure module. 709 * |[17] |TMR23 |Set TMR23 to Non-secure State 710 * | | |Write 1 to set TMR23 to non-secure state. Write 0 has no effect. 711 * | | |0 = TMR23 is a secure module (default). 712 * | | |1 = TMR23 is a non-secure module. 713 * |[24] |EPWM0 |Set EPWM0 to Non-secure State 714 * | | |Write 1 to set EPWM0 to non-secure state. Write 0 has no effect. 715 * | | |0 = EPWM0 is a secure module (default). 716 * | | |1 = EPWM0 is a non-secure module. 717 * |[25] |EPWM1 |Set EPWM1 to Non-secure State 718 * | | |Write 1 to set EPWM1 to non-secure state. Write 0 has no effect. 719 * | | |0 = EPWM1 is a secure module (default). 720 * | | |1 = EPWM1 is a non-secure module. 721 * |[26] |BPWM0 |Set BPWM0 to Non-secure State 722 * | | |Write 1 to set BPWM0 to non-secure state. Write 0 has no effect. 723 * | | |0 = BPWM0 is a secure module (default). 724 * | | |1 = BPWM0 is a non-secure module. 725 * |[27] |BPWM1 |Set BPWM1 to Non-secure State 726 * | | |Write 1 to set BPWM1 to non-secure state. Write 0 has no effect. 727 * | | |0 = BPWM1 is a secure module (default). 728 * | | |1 = BPWM1 is a non-secure module. 729 * Offset: 0x0C Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF) 730 * --------------------------------------------------------------------------------------------------- 731 * |Bits |Field |Descriptions 732 * | :----: | :----: | :---- | 733 * |[0] |QSPI0 |Set QSPI0 to Non-secure State 734 * | | |Write 1 to set QSPI0 to non-secure state. Write 0 has no effect. 735 * | | |0 = QSPI0 is a secure module (default). 736 * | | |1 = QSPI0 is a non-secure module. 737 * |[1] |SPI0 |Set SPI0 to Non-secure State 738 * | | |Write 1 to set SPI0 to non-secure state. Write 0 has no effect. 739 * | | |0 = SPI0 is a secure module (default). 740 * | | |1 = SPI0 is a non-secure module. 741 * |[2] |SPI1 |Set SPI1 to Non-secure State 742 * | | |Write 1 to set SPI1 to non-secure state. Write 0 has no effect. 743 * | | |0 = SPI1 is a secure module (default). 744 * | | |1 = SPI1 is a non-secure module. 745 * |[3] |SPI2 |Set SPI2 to Non-secure State 746 * | | |Write 1 to set SPI2 to non-secure state. Write 0 has no effect. 747 * | | |0 = SPI2 is a secure module (default). 748 * | | |1 = SPI2 is a non-secure module. 749 * |[4] |SPI3 |Set SPI3 to Non-secure State 750 * | | |Write 1 to set SPI3 to non-secure state. Write 0 has no effect. 751 * | | |0 = SPI3 is a secure module (default). 752 * | | |1 = SPI3 is a non-secure module. 753 * |[16] |UART0 |Set UART0 to Non-secure State 754 * | | |Write 1 to set UART0 to non-secure state. Write 0 has no effect. 755 * | | |0 = UART0 is a secure module (default). 756 * | | |1 = UART0 is a non-secure module. 757 * |[17] |UART1 |Set UART1 to Non-secure State 758 * | | |Write 1 to set UART1 to non-secure state. Write 0 has no effect. 759 * | | |0 = UART1 is a secure module (default). 760 * | | |1 = UART1 is a non-secure module. 761 * |[18] |UART2 |Set UART2 to Non-secure State 762 * | | |Write 1 to set UART2 to non-secure state. Write 0 has no effect. 763 * | | |0 = UART2 is a secure module (default). 764 * | | |1 = UART2 is a non-secure module. 765 * |[19] |UART3 |Set UART3 to Non-secure State 766 * | | |Write 1 to set UART3 to non-secure state. Write 0 has no effect. 767 * | | |0 = UART3 is a secure module (default). 768 * | | |1 = UART3 is a non-secure module. 769 * |[20] |UART4 |Set UART4 to Non-secure State 770 * | | |Write 1 to set UART4 to non-secure state. Write 0 has no effect. 771 * | | |0 = UART4 is a secure module (default). 772 * | | |1 = UART4 is a non-secure module. 773 * |[21] |UART5 |Set UART5 to Non-secure State 774 * | | |Write 1 to set UART5 to non-secure state. Write 0 has no effect. 775 * | | |0 = UART5 is a secure module (default). 776 * | | |1 = UART5 is a non-secure module. 777 * Offset: 0x10 Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF) 778 * --------------------------------------------------------------------------------------------------- 779 * |Bits |Field |Descriptions 780 * | :----: | :----: | :---- | 781 * |[0] |I2C0 |Set I2C0 to Non-secure State 782 * | | |Write 1 to set I2C0 to non-secure state. Write 0 has no effect. 783 * | | |0 = I2C0 is a secure module (default). 784 * | | |1 = I2C0 is a non-secure module. 785 * |[1] |I2C1 |Set I2C1 to Non-secure State 786 * | | |Write 1 to set I2C1 to non-secure state. Write 0 has no effect. 787 * | | |0 = I2C1 is a secure module (default). 788 * | | |1 = I2C1 is a non-secure module. 789 * |[2] |I2C2 |Set I2C2 to Non-secure State 790 * | | |Write 1 to set I2C2 to non-secure state. Write 0 has no effect. 791 * | | |0 = I2C2 is a secure module (default). 792 * | | |1 = I2C2 is a non-secure module. 793 * |[16] |SC0 |Set SC0 to Non-secure State 794 * | | |Write 1 to set SC0 to non-secure state. Write 0 has no effect. 795 * | | |0 = SC0 is a secure module (default). 796 * | | |1 = SC0 is a non-secure module. 797 * |[17] |SC1 |Set SC1 to Non-secure State 798 * | | |Write 1 to set SC1 to non-secure state. Write 0 has no effect. 799 * | | |0 = SC1 is a secure module (default). 800 * | | |1 = SC1 is a non-secure module. 801 * |[18] |SC2 |Set SC2 to Non-secure State 802 * | | |Write 1 to set SC2 to non-secure state. Write 0 has no effect. 803 * | | |0 = SC2 is a secure module (default). 804 * | | |1 = SC2 is a non-secure module. 805 * Offset: 0x14 Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF) 806 * --------------------------------------------------------------------------------------------------- 807 * |Bits |Field |Descriptions 808 * | :----: | :----: | :---- | 809 * |[0] |CAN0 |Set CAN0 to Non-secure State 810 * | | |Write 1 to set CAN0 to non-secure state. Write 0 has no effect. 811 * | | |0 = CAN0 is a secure module (default). 812 * | | |1 = CAN0 is a non-secure module. 813 * |[16] |QEI0 |Set QEI0 to Non-secure State 814 * | | |Write 1 to set QEI0 to non-secure state. Write 0 has no effect. 815 * | | |0 = QEI0 is a secure module (default). 816 * | | |1 = QEI0 is a non-secure module. 817 * |[17] |QEI1 |Set QEI1 to Non-secure State 818 * | | |Write 1 to set QEI1 to non-secure state. Write 0 has no effect. 819 * | | |0 = QEI1 is a secure module (default). 820 * | | |1 = QEI1 is a non-secure module. 821 * |[20] |ECAP0 |Set ECAP0 to Non-secure State 822 * | | |Write 1 to set ECAP0 to non-secure state. Write 0 has no effect. 823 * | | |0 = ECAP0 is a secure module (default). 824 * | | |1 = ECAP0 is a non-secure module. 825 * |[21] |ECAP1 |Set ECAP1 to Non-secure State 826 * | | |Write 1 to set ECAP1 to non-secure state. Write 0 has no effect. 827 * | | |0 = ECAP1 is a secure module (default). 828 * | | |1 = ECAP1 is a non-secure module. 829 * |[25] |TRNG |Set TRNG to Non-secure State 830 * | | |Write 1 to set TRNG to non-secure state. Write 0 has no effect. 831 * | | |0 = TRNG is a secure module (default). 832 * | | |1 = TRNG is a non-secure module. 833 * |[27] |LCD |Set LCD to Non-secure State 834 * | | |Write 1 to set LCD to non-secure state. Write 0 has no effect. 835 * | | |0 = LCD is a secure module (default). 836 * | | |1 = LCD is a non-secure module. 837 * Offset: 0x18 Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF) 838 * --------------------------------------------------------------------------------------------------- 839 * |Bits |Field |Descriptions 840 * | :----: | :----: | :---- | 841 * |[0] |USBD |Set USBD to Non-secure State 842 * | | |Write 1 to set USBD to non-secure state. Write 0 has no effect. 843 * | | |0 = USBD is a secure module (default). 844 * | | |1 = USBD is a non-secure module. 845 * |[16] |USCI0 |Set USCI0 to Non-secure State 846 * | | |Write 1 to set USCI0 to non-secure state. Write 0 has no effect. 847 * | | |0 = USCI0 is a secure module (default). 848 * | | |1 = USCI0 is a non-secure module. 849 * |[17] |USCI1 |Set USCI1 to Non-secure State 850 * | | |Write 1 to set USCI1 to non-secure state. Write 0 has no effect. 851 * | | |0 = USCI1 is a secure module (default). 852 * | | |1 = USCI1 is a non-secure module. 853 * @var SCU_T::IONSSET 854 * Offset: 0x20 IO Non-secure Attribution Set Register 855 * --------------------------------------------------------------------------------------------------- 856 * |Bits |Field |Descriptions 857 * | :----: | :----: | :---- | 858 * |[0] |PA |Set GPIO Port a to Non-scecure State 859 * | | |Write 1 to set PA to non-secure state. Write 0 has no effect. 860 * | | |0 = GPIO port A is secure (default). 861 * | | |1 = GPIO port A is non-secure. 862 * |[1] |PB |Set GPIO Port B to Non-scecure State 863 * | | |Write 1 to set PB to non-secure state. Write 0 has no effect. 864 * | | |0 = GPIO port B is secure (default). 865 * | | |1 = GPIO port B is non-secure. 866 * |[2] |PC |Set GPIO Port C to Non-scecure State 867 * | | |Write 1 to set PC to non-secure state. Write 0 has no effect. 868 * | | |0 = GPIO port C is secure (default). 869 * | | |1 = GPIO port C is non-secure. 870 * |[3] |PD |Set GPIO Port D to Non-scecure State 871 * | | |Write 1 to set PD to non-secure state. Write 0 has no effect. 872 * | | |0 = GPIO port D is secure (default). 873 * | | |1 = GPIO port D is non-secure. 874 * |[4] |PE |Set GPIO Port E to Non-scecure State 875 * | | |Write 1 to set PE to non-secure state. Write 0 has no effect. 876 * | | |0 = GPIO port E is secure (default). 877 * | | |1 = GPIO port E is non-secure. 878 * |[5] |PF |Set GPIO Port F to Non-scecure State 879 * | | |Write 1 to set PF to non-secure state. Write 0 has no effect. 880 * | | |0 = GPIO port F is secure (default). 881 * | | |1 = GPIO port F is non-secure. 882 * |[6] |PG |Set GPIO Port G to Non-scecure State 883 * | | |Write 1 to set PG to non-secure state. Write 0 has no effect. 884 * | | |0 = GPIO port G is secure (default). 885 * | | |1 = GPIO port G is non-secure. 886 * |[7] |PH |Set GPIO Port H to Non-scecure State 887 * | | |Write 1 to set PH to non-secure state. Write 0 has no effect. 888 * | | |0 = GPIO port H is secure (default). 889 * | | |1 = GPIO port H is non-secure. 890 * @var SCU_T::SRAMNSSET 891 * Offset: 0x24 SRAM Non-secure Attribution Set Register 892 * --------------------------------------------------------------------------------------------------- 893 * |Bits |Field |Descriptions 894 * | :----: | :----: | :---- | 895 * |[11:0] |SECn |Set SRAM Section n to Non-scecure State 896 * | | |Write 1 to set SRAM section n to non-secure state. Write 0 is ignored. 897 * | | |0 = SRAM Section n is secure (default). 898 * | | |1 = SRAM Section n is non-secure. 899 * | | |Size per section is 16 Kbytes. 900 * | | |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 901 * | | |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1 902 * @var SCU_T::FNSADDR 903 * Offset: 0x28 Flash Non-secure Boundary Address Register 904 * --------------------------------------------------------------------------------------------------- 905 * |Bits |Field |Descriptions 906 * | :----: | :----: | :---- | 907 * |[31:0] |FNSADDR |Flash Non-secure Boundary Address 908 * | | |Indicate the base address of Non-secure region set in user configuration 909 * | | |Refer to FMC section for more details. 910 * @var SCU_T::SVIOIEN 911 * Offset: 0x2C Security Violation Interrupt Enable Register 912 * --------------------------------------------------------------------------------------------------- 913 * |Bits |Field |Descriptions 914 * | :----: | :----: | :---- | 915 * |[0] |APB0IEN |APB0 Security Violation Interrupt Enable Bit 916 * | | |0 = Interrupt triggered from security violation of APB0 Disabled. 917 * | | |1 = Interrupt triggered from security violation of APB0 Enabled. 918 * |[1] |APB1IEN |APB1 Security Violation Interrupt Enable Bit 919 * | | |0 = Interrupt triggered from security violation of APB1 Disabled. 920 * | | |1 = Interrupt triggered from security violation of APB1 Enabled. 921 * |[4] |GPIOIEN |GPIO Security Violation Interrupt Enable Bit 922 * | | |0 = Interrupt triggered from security violation of GPIO Disabled. 923 * | | |1 = Interrupt triggered from security violation of GPIO Enabled. 924 * |[5] |EBIIEN |EBI Security Violation Interrupt Enable Bit 925 * | | |0 = Interrupt triggered from security violation of EBI Disabled. 926 * | | |1 = Interrupt triggered from security violation of EBI Enabled. 927 * |[6] |USBHIEN |USBH Security Violation Interrupt Enable Bit 928 * | | |0 = Interrupt triggered from security violation of USB host Disabled. 929 * | | |1 = Interrupt triggered from security violation of USB host Enabled. 930 * |[7] |CRCIEN |CRC Security Violation Interrupt Enable Bit 931 * | | |0 = Interrupt triggered from security violation of CRC Disabled. 932 * | | |1 = Interrupt triggered from security violation of CRC Enabled. 933 * |[8] |SDH0IEN |SDH0 Security Violation Interrupt Enable Bit 934 * | | |0 = Interrupt triggered from security violation of SD host 0 Disabled. 935 * | | |1 = Interrupt triggered from security violation of SD host 0 Enabled. 936 * |[10] |PDMA0IEN |PDMA0 Security Violation Interrupt Enable Bit 937 * | | |0 = Interrupt triggered from security violation of PDMA0 Disabled. 938 * | | |1 = Interrupt triggered from security violation of PDMA0 Enabled. 939 * |[11] |PDMA1IEN |PDMA1 Security Violation Interrupt Enable Bit 940 * | | |0 = Interrupt triggered from security violation of PDMA1 Disabled. 941 * | | |1 = Interrupt triggered from security violation of PDMA1 Enabled. 942 * |[12] |SRAM0IEN |SRAM Bank 0 Security Violation Interrupt Enable Bit 943 * | | |0 = Interrupt triggered from security violation of SRAM bank0 Disabled. 944 * | | |1 = Interrupt triggered from security violation of SRAM bank0 Enabled. 945 * |[13] |SRAM1IEN |SRAM Bank 1 Security Violation Interrupt Enable Bit 946 * | | |0 = Interrupt triggered from security violation of SRAM bank1 Disabled. 947 * | | |1 = Interrupt triggered from security violation of SRAM bank1 Enabled. 948 * |[14] |FMCIEN |FMC Security Violation Interrupt Enable Bit 949 * | | |0 = Interrupt triggered from security violation of FMC Disabled. 950 * | | |1 = Interrupt triggered from security violation of FMC Enabled. 951 * |[15] |FLASHIEN |FLASH Security Violation Interrupt Enable Bit 952 * | | |0 = Interrupt triggered from security violation of Flash data Disabled. 953 * | | |1 = Interrupt triggered from security violation of Flash data Enabled. 954 * |[16] |SCUIEN |SCU Security Violation Interrupt Enable Bit 955 * | | |0 = Interrupt triggered from security violation of SCU Disabled. 956 * | | |1 = Interrupt triggered from security violation of SCU Enabled. 957 * |[17] |SYSIEN |SYS Security Violation Interrupt Enable Bit 958 * | | |0 = Interrupt triggered from security violation of system manager Disabled. 959 * | | |1 = Interrupt triggered from security violation of system manager Enabled. 960 * |[18] |CRPTIEN |CRPT Security Violation Interrupt Enable Bit 961 * | | |0 = Interrupt triggered from security violation of crypto Disabled. 962 * | | |1 = Interrupt triggered from security violation of crypto Enabled. 963 * |[19] |KSIEN |KS Security Violation Interrupt Enable Bit 964 * | | |0 = Interrupt triggered from security violation of keystore Disabled. 965 * | | |1 = Interrupt triggered from security violation of keystore Enabled. 966 * @var SCU_T::SVINTSTS 967 * Offset: 0x30 Security Violation Interrupt Status Register 968 * --------------------------------------------------------------------------------------------------- 969 * |Bits |Field |Descriptions 970 * | :----: | :----: | :---- | 971 * |[0] |APB0IF |APB0 Security Violation Interrupt Status 972 * | | |0 = No APB0 violation interrupt event. 973 * | | |1 = There is APB0 violation interrupt event. 974 * | | |Note: Write 1 to clear the interrupt flag. 975 * |[1] |APB1IF |APB1 Security Violation Interrupt Status 976 * | | |0 = No APB1 violation interrupt event. 977 * | | |1 = There is APB1 violation interrupt event. 978 * | | |Note: Write 1 to clear the interrupt flag. 979 * |[4] |GPIOIF |GPIO Security Violation Interrupt Status 980 * | | |0 = No GPIO violation interrupt event. 981 * | | |1 = There is GPIO violation interrupt event. 982 * | | |Note: Write 1 to clear the interrupt flag. 983 * |[5] |EBIIF |EBI Security Violation Interrupt Status 984 * | | |0 = No EBI violation interrupt event. 985 * | | |1 = There is EBI violation interrupt event. 986 * | | |Note: Write 1 to clear the interrupt flag. 987 * |[6] |USBHIF |USBH Security Violation Interrupt Status 988 * | | |0 = No USBH violation interrupt event. 989 * | | |1 = There is USBH violation interrupt event. 990 * | | |Note: Write 1 to clear the interrupt flag. 991 * |[7] |CRCIF |CRC Security Violation Interrupt Status 992 * | | |0 = No CRC violation interrupt event. 993 * | | |1 = There is CRC violation interrupt event. 994 * | | |Note: Write 1 to clear the interrupt flag. 995 * |[8] |SDH0IF |SDH0 Security Violation Interrupt Status 996 * | | |0 = No SDH0 violation interrupt event. 997 * | | |1 = There is SDH0 violation interrupt event. 998 * | | |Note: Write 1 to clear the interrupt flag. 999 * |[10] |PDMA0IF |PDMA0 Security Violation Interrupt Status 1000 * | | |0 = No PDMA0 violation interrupt event. 1001 * | | |1 = There is PDMA0 violation interrupt event. 1002 * | | |Note: Write 1 to clear the interrupt flag. 1003 * |[11] |PDMA1IF |PDMA1 Security Violation Interrupt Status 1004 * | | |0 = No PDMA1 violation interrupt event. 1005 * | | |1 = There is PDMA1 violation interrupt event. 1006 * | | |Note: Write 1 to clear the interrupt flag. 1007 * |[12] |SRAM0IF |SRAM0 Security Violation Interrupt Status 1008 * | | |0 = No SRAM0 violation interrupt event. 1009 * | | |1 = There is SRAM0 violation interrupt event. 1010 * | | |Note: Write 1 to clear the interrupt flag. 1011 * |[13] |SRAM1IF |SRAM Bank 1 Security Violation Interrupt Status 1012 * | | |0 = No SRAM1 violation interrupt event. 1013 * | | |1 = There is SRAM1 violation interrupt event. 1014 * | | |Note: Write 1 to clear the interrupt flag. 1015 * |[14] |FMCIF |FMC Security Violation Interrupt Status 1016 * | | |0 = No FMC violation interrupt event. 1017 * | | |1 = There is FMC violation interrupt event. 1018 * | | |Note: Write 1 to clear the interrupt flag. 1019 * |[15] |FLASHIF |FLASH Security Violation Interrupt Status 1020 * | | |0 = No FLASH violation interrupt event. 1021 * | | |1 = There is FLASH violation interrupt event. 1022 * | | |Note: Write 1 to clear the interrupt flag. 1023 * |[16] |SCUIF |SCU Security Violation Interrupt Status 1024 * | | |0 = No SCU violation interrupt event. 1025 * | | |1 = There is SCU violation interrupt event. 1026 * | | |Note: Write 1 to clear the interrupt flag. 1027 * |[17] |SYSIF |SYS Security Violation Interrupt Status 1028 * | | |0 = No SYS violation interrupt event. 1029 * | | |1 = There is SYS violation interrupt event. 1030 * | | |Note: Write 1 to clear the interrupt flag. 1031 * |[18] |CRPTIF |CRPT Security Violation Interrupt Status 1032 * | | |0 = No CRPT violation interrupt event. 1033 * | | |1 = There is CRPT violation interrupt event. 1034 * | | |Note: Write 1 to clear the interrupt flag. 1035 * |[19] |KSIF |KS Security Violation Interrupt Status 1036 * | | |0 = No KS violation interrupt event. 1037 * | | |1 = There is KS violation interrupt event. 1038 * | | |Note: Write 1 to clear the interrupt flag. 1039 * @var SCU_T::APB0VSRC 1040 * Offset: 0x34 APB0 Security Policy Violation Source 1041 * --------------------------------------------------------------------------------------------------- 1042 * |Bits |Field |Descriptions 1043 * | :----: | :----: | :---- | 1044 * |[3:0] |MASTER |Master Violating Security Policy 1045 * | | |Indicate which master invokes the security violation. 1046 * | | |0x0 = core processor. 1047 * | | |0x3 = PDMA0. 1048 * | | |0x4 = SDH0. 1049 * | | |0x5 = CRYPTO. 1050 * | | |0x6 = USH. 1051 * | | |0xB = PDMA1. 1052 * | | |Others is undefined. 1053 * @var SCU_T::APB0VA 1054 * Offset: 0x38 APB0 Violation Address 1055 * --------------------------------------------------------------------------------------------------- 1056 * |Bits |Field |Descriptions 1057 * | :----: | :----: | :---- | 1058 * |[31:0] |VIOADDR |Violation Address 1059 * | | |Indicate the target address of the access, which invokes the security violation. 1060 * @var SCU_T::APB1VSRC 1061 * Offset: 0x3C APB1 Security Policy Violation Source 1062 * --------------------------------------------------------------------------------------------------- 1063 * |Bits |Field |Descriptions 1064 * | :----: | :----: | :---- | 1065 * |[3:0] |MASTER |Master Violating Security Policy 1066 * | | |Indicate which master invokes the security violation. 1067 * | | |0x0 = core processor. 1068 * | | |0x3 = PDMA0. 1069 * | | |0x4 = SDH0. 1070 * | | |0x5 = CRYPTO. 1071 * | | |0x6 = USH. 1072 * | | |0xB = PDMA1. 1073 * | | |Others is undefined. 1074 * @var SCU_T::APB1VA 1075 * Offset: 0x40 APB1 Violation Address 1076 * --------------------------------------------------------------------------------------------------- 1077 * |Bits |Field |Descriptions 1078 * | :----: | :----: | :---- | 1079 * |[31:0] |VIOADDR |Violation Address 1080 * | | |Indicate the target address of the access, which invokes the security violation. 1081 * @var SCU_T::GPIOVSRC 1082 * Offset: 0x44 GPIO Security Policy Violation Source 1083 * --------------------------------------------------------------------------------------------------- 1084 * |Bits |Field |Descriptions 1085 * | :----: | :----: | :---- | 1086 * |[3:0] |MASTER |Master Violating Security Policy 1087 * | | |Indicate which master invokes the security violation. 1088 * | | |0x0 = core processor. 1089 * | | |0x3 = PDMA0. 1090 * | | |0x4 = SDH0. 1091 * | | |0x5 = CRYPTO. 1092 * | | |0x6 = USH. 1093 * | | |0xB = PDMA1. 1094 * | | |Others is undefined. 1095 * @var SCU_T::GPIOVA 1096 * Offset: 0x48 GPIO Violation Address 1097 * --------------------------------------------------------------------------------------------------- 1098 * |Bits |Field |Descriptions 1099 * | :----: | :----: | :---- | 1100 * |[31:0] |VIOADDR |Violation Address 1101 * | | |Indicate the target address of the access, which invokes the security violation. 1102 * @var SCU_T::EBIVSRC 1103 * Offset: 0x4C EBI Security Policy Violation Source 1104 * --------------------------------------------------------------------------------------------------- 1105 * |Bits |Field |Descriptions 1106 * | :----: | :----: | :---- | 1107 * |[3:0] |MASTER |Master Violating Security Policy 1108 * | | |Indicate which master invokes the security violation. 1109 * | | |0x0 = core processor. 1110 * | | |0x3 = PDMA0. 1111 * | | |0x4 = SDH0. 1112 * | | |0x5 = CRYPTO. 1113 * | | |0x6 = USH. 1114 * | | |0xB = PDMA1. 1115 * | | |Others is undefined. 1116 * @var SCU_T::EBIVA 1117 * Offset: 0x50 EBI Violation Address 1118 * --------------------------------------------------------------------------------------------------- 1119 * |Bits |Field |Descriptions 1120 * | :----: | :----: | :---- | 1121 * |[31:0] |VIOADDR |Violation Address 1122 * | | |Indicate the target address of the access, which invokes the security violation. 1123 * @var SCU_T::USBHVSRC 1124 * Offset: 0x54 USBH Security Policy Violation Source 1125 * --------------------------------------------------------------------------------------------------- 1126 * |Bits |Field |Descriptions 1127 * | :----: | :----: | :---- | 1128 * |[3:0] |MASTER |Master Violating Security Policy 1129 * | | |Indicate which master invokes the security violation. 1130 * | | |0x0 = core processor. 1131 * | | |0x3 = PDMA0. 1132 * | | |0x4 = SDH0. 1133 * | | |0x5 = CRYPTO. 1134 * | | |0x6 = USH. 1135 * | | |0xB = PDMA1. 1136 * | | |Others is undefined. 1137 * @var SCU_T::USBHVA 1138 * Offset: 0x58 USBH Violation Address 1139 * --------------------------------------------------------------------------------------------------- 1140 * |Bits |Field |Descriptions 1141 * | :----: | :----: | :---- | 1142 * |[31:0] |VIOADDR |Violation Address 1143 * | | |Indicate the target address of the access, which invokes the security violation. 1144 * @var SCU_T::CRCVSRC 1145 * Offset: 0x5C CRC Security Policy Violation Source 1146 * --------------------------------------------------------------------------------------------------- 1147 * |Bits |Field |Descriptions 1148 * | :----: | :----: | :---- | 1149 * |[3:0] |MASTER |Master Violating Security Policy 1150 * | | |Indicate which master invokes the security violation. 1151 * | | |0x0 = core processor. 1152 * | | |0x3 = PDMA0. 1153 * | | |0x4 = SDH0. 1154 * | | |0x5 = CRYPTO. 1155 * | | |0x6 = USH. 1156 * | | |0xB = PDMA1. 1157 * | | |Others is undefined. 1158 * @var SCU_T::CRCVA 1159 * Offset: 0x60 CRC Violation Address 1160 * --------------------------------------------------------------------------------------------------- 1161 * |Bits |Field |Descriptions 1162 * | :----: | :----: | :---- | 1163 * |[31:0] |VIOADDR |Violation Address 1164 * | | |Indicate the target address of the access, which invokes the security violation. 1165 * @var SCU_T::SD0VSRC 1166 * Offset: 0x64 SDH0 Security Policy Violation Source 1167 * --------------------------------------------------------------------------------------------------- 1168 * |Bits |Field |Descriptions 1169 * | :----: | :----: | :---- | 1170 * |[3:0] |MASTER |Master Violating Security Policy 1171 * | | |Indicate which master invokes the security violation. 1172 * | | |0x0 = core processor. 1173 * | | |0x3 = PDMA0. 1174 * | | |0x4 = SDH0. 1175 * | | |0x5 = CRYPTO. 1176 * | | |0x6 = USH. 1177 * | | |0xB = PDMA1. 1178 * | | |Others is undefined. 1179 * @var SCU_T::SD0VA 1180 * Offset: 0x68 SDH0 Violation Address 1181 * --------------------------------------------------------------------------------------------------- 1182 * |Bits |Field |Descriptions 1183 * | :----: | :----: | :---- | 1184 * |[31:0] |VIOADDR |Violation Address 1185 * | | |Indicate the target address of the access, which invokes the security violation. 1186 * @var SCU_T::PDMA0VSRC 1187 * Offset: 0x74 PDMA0 Security Policy Violation Source 1188 * --------------------------------------------------------------------------------------------------- 1189 * |Bits |Field |Descriptions 1190 * | :----: | :----: | :---- | 1191 * |[3:0] |MASTER |Master Violating Security Policy 1192 * | | |Indicate which master invokes the security violation. 1193 * | | |0x0 = core processor. 1194 * | | |0x3 = PDMA0. 1195 * | | |0x4 = SDH0. 1196 * | | |0x5 = CRYPTO. 1197 * | | |0x6 = USH. 1198 * | | |0xB = PDMA1. 1199 * | | |Others is undefined. 1200 * @var SCU_T::PDMA0VA 1201 * Offset: 0x78 PDMA0 Violation Address 1202 * --------------------------------------------------------------------------------------------------- 1203 * |Bits |Field |Descriptions 1204 * | :----: | :----: | :---- | 1205 * |[31:0] |VIOADDR |Violation Address 1206 * | | |Indicate the target address of the access, which invokes the security violation. 1207 * @var SCU_T::PDMA1VSRC 1208 * Offset: 0x7C PDMA1 Security Policy Violation Source 1209 * --------------------------------------------------------------------------------------------------- 1210 * |Bits |Field |Descriptions 1211 * | :----: | :----: | :---- | 1212 * |[3:0] |MASTER |Master Violating Security Policy 1213 * | | |Indicate which master invokes the security violation. 1214 * | | |0x0 = core processor. 1215 * | | |0x3 = PDMA0. 1216 * | | |0x4 = SDH0. 1217 * | | |0x5 = CRYPTO. 1218 * | | |0x6 = USH. 1219 * | | |0xB = PDMA1. 1220 * | | |Others is undefined. 1221 * @var SCU_T::PDMA1VA 1222 * Offset: 0x80 PDMA1 Violation Address 1223 * --------------------------------------------------------------------------------------------------- 1224 * |Bits |Field |Descriptions 1225 * | :----: | :----: | :---- | 1226 * |[31:0] |VIOADDR |Violation Address 1227 * | | |Indicate the target address of the access, which invokes the security violation. 1228 * @var SCU_T::SRAM0VSRC 1229 * Offset: 0x84 SRAM0 Security Policy Violation Source 1230 * --------------------------------------------------------------------------------------------------- 1231 * |Bits |Field |Descriptions 1232 * | :----: | :----: | :---- | 1233 * |[3:0] |MASTER |Master Violating Security Policy 1234 * | | |Indicate which master invokes the security violation. 1235 * | | |0x0 = core processor. 1236 * | | |0x3 = PDMA0. 1237 * | | |0x4 = SDH0. 1238 * | | |0x5 = CRYPTO. 1239 * | | |0x6 = USH. 1240 * | | |0xB = PDMA1. 1241 * | | |Others is undefined. 1242 * @var SCU_T::SRAM0VA 1243 * Offset: 0x88 SRAM0 Violation Address 1244 * --------------------------------------------------------------------------------------------------- 1245 * |Bits |Field |Descriptions 1246 * | :----: | :----: | :---- | 1247 * |[31:0] |VIOADDR |Violation Address 1248 * | | |Indicate the target address of the access, which invokes the security violation. 1249 * @var SCU_T::SRAM1VSRC 1250 * Offset: 0x8C SRAM1 Security Policy Violation Source 1251 * --------------------------------------------------------------------------------------------------- 1252 * |Bits |Field |Descriptions 1253 * | :----: | :----: | :---- | 1254 * |[3:0] |MASTER |Master Violating Security Policy 1255 * | | |Indicate which master invokes the security violation. 1256 * | | |0x0 = core processor. 1257 * | | |0x3 = PDMA0. 1258 * | | |0x4 = SDH0. 1259 * | | |0x5 = CRYPTO. 1260 * | | |0x6 = USH. 1261 * | | |0xB = PDMA1. 1262 * | | |Others is undefined. 1263 * @var SCU_T::SRAM1VA 1264 * Offset: 0x90 SRAM1 Violation Address 1265 * --------------------------------------------------------------------------------------------------- 1266 * |Bits |Field |Descriptions 1267 * | :----: | :----: | :---- | 1268 * |[31:0] |VIOADDR |Violation Address 1269 * | | |Indicate the target address of the access, which invokes the security violation. 1270 * @var SCU_T::FMCVSRC 1271 * Offset: 0x94 FMC Security Policy Violation Source 1272 * --------------------------------------------------------------------------------------------------- 1273 * |Bits |Field |Descriptions 1274 * | :----: | :----: | :---- | 1275 * |[3:0] |MASTER |Master Violating Security Policy 1276 * | | |Indicate which master invokes the security violation. 1277 * | | |0x0 = core processor. 1278 * | | |0x3 = PDMA0. 1279 * | | |0x4 = SDH0. 1280 * | | |0x5 = CRYPTO. 1281 * | | |0x6 = USH. 1282 * | | |0xB = PDMA1. 1283 * | | |Others is undefined. 1284 * @var SCU_T::FMCVA 1285 * Offset: 0x98 FMC Violation Address 1286 * --------------------------------------------------------------------------------------------------- 1287 * |Bits |Field |Descriptions 1288 * | :----: | :----: | :---- | 1289 * |[31:0] |VIOADDR |Violation Address 1290 * | | |Indicate the target address of the access, which invokes the security violation. 1291 * @var SCU_T::FLASHVSRC 1292 * Offset: 0x9C Flash Security Policy Violation Source 1293 * --------------------------------------------------------------------------------------------------- 1294 * |Bits |Field |Descriptions 1295 * | :----: | :----: | :---- | 1296 * |[3:0] |MASTER |Master Violating Security Policy 1297 * | | |Indicate which master invokes the security violation. 1298 * | | |0x0 = core processor. 1299 * | | |0x3 = PDMA0. 1300 * | | |0x4 = SDH0. 1301 * | | |0x5 = CRYPTO. 1302 * | | |0x6 = USH. 1303 * | | |0xB = PDMA1. 1304 * | | |Others is undefined. 1305 * @var SCU_T::FLASHVA 1306 * Offset: 0xA0 Flash Violation Address 1307 * --------------------------------------------------------------------------------------------------- 1308 * |Bits |Field |Descriptions 1309 * | :----: | :----: | :---- | 1310 * |[31:0] |VIOADDR |Violation Address 1311 * | | |Indicate the target address of the access, which invokes the security violation. 1312 * @var SCU_T::SCUVSRC 1313 * Offset: 0xA4 SCU Security Policy Violation Source 1314 * --------------------------------------------------------------------------------------------------- 1315 * |Bits |Field |Descriptions 1316 * | :----: | :----: | :---- | 1317 * |[3:0] |MASTER |Master Violating Security Policy 1318 * | | |Indicate which master invokes the security violation. 1319 * | | |0x0 = core processor. 1320 * | | |0x3 = PDMA0. 1321 * | | |0x4 = SDH0. 1322 * | | |0x5 = CRYPTO. 1323 * | | |0x6 = USH. 1324 * | | |0xB = PDMA1. 1325 * | | |Others is undefined. 1326 * @var SCU_T::SCUVA 1327 * Offset: 0xA8 SCU Violation Address 1328 * --------------------------------------------------------------------------------------------------- 1329 * |Bits |Field |Descriptions 1330 * | :----: | :----: | :---- | 1331 * |[31:0] |VIOADDR |Violation Address 1332 * | | |Indicate the target address of the access, which invokes the security violation. 1333 * @var SCU_T::SYSVSRC 1334 * Offset: 0xAC System(GMISC) Security Policy Violation Source 1335 * --------------------------------------------------------------------------------------------------- 1336 * |Bits |Field |Descriptions 1337 * | :----: | :----: | :---- | 1338 * |[3:0] |MASTER |Master Violating Security Policy 1339 * | | |Indicate which master invokes the security violation. 1340 * | | |0x0 = core processor. 1341 * | | |0x3 = PDMA0. 1342 * | | |0x4 = SDH0. 1343 * | | |0x5 = CRYPTO. 1344 * | | |0x6 = USH. 1345 * | | |0xB = PDMA1. 1346 * | | |Others is undefined. 1347 * @var SCU_T::SYSVA 1348 * Offset: 0xB0 System(GMISC) Violation Address 1349 * --------------------------------------------------------------------------------------------------- 1350 * |Bits |Field |Descriptions 1351 * | :----: | :----: | :---- | 1352 * |[31:0] |VIOADDR |Violation Address 1353 * | | |Indicate the target address of the access, which invokes the security violation. 1354 * @var SCU_T::CRPTVSRC 1355 * Offset: 0xB4 Crypto Security Policy Violation Source 1356 * --------------------------------------------------------------------------------------------------- 1357 * |Bits |Field |Descriptions 1358 * | :----: | :----: | :---- | 1359 * |[3:0] |MASTER |Master Violating Security Policy 1360 * | | |Indicate which master invokes the security violation. 1361 * | | |0x0 = core processor. 1362 * | | |0x3 = PDMA0. 1363 * | | |0x4 = SDH0. 1364 * | | |0x5 = CRYPTO. 1365 * | | |0x6 = USH. 1366 * | | |0xB = PDMA1. 1367 * | | |Others is undefined. 1368 * @var SCU_T::CRPTVA 1369 * Offset: 0xB8 Crypto Violation Address 1370 * --------------------------------------------------------------------------------------------------- 1371 * |Bits |Field |Descriptions 1372 * | :----: | :----: | :---- | 1373 * |[31:0] |VIOADDR |Violation Address 1374 * | | |Indicate the target address of the access, which invokes the security violation. 1375 * @var SCU_T::KSVSRC 1376 * Offset: 0xBC KS Security Policy Violation Source 1377 * --------------------------------------------------------------------------------------------------- 1378 * |Bits |Field |Descriptions 1379 * | :----: | :----: | :---- | 1380 * |[3:0] |MASTER |Master Violating Security Policy 1381 * | | |Indicate which master invokes the security violation. 1382 * | | |0x0 = core processor. 1383 * | | |0x3 = PDMA0. 1384 * | | |0x4 = SDH0. 1385 * | | |0x5 = CRYPTO. 1386 * | | |0x6 = USH. 1387 * | | |0xB = PDMA1. 1388 * | | |Others is undefined. 1389 * @var SCU_T::KSVA 1390 * Offset: 0xC0 KS Violation Address 1391 * --------------------------------------------------------------------------------------------------- 1392 * |Bits |Field |Descriptions 1393 * | :----: | :----: | :---- | 1394 * |[31:0] |VIOADDR |Violation Address 1395 * | | |Indicate the target address of the access, which invokes the security violation. 1396 * @var SCU_T::SRAM2VSRC 1397 * Offset: 0xC4 SRAM2 Security Policy Violation Source 1398 * --------------------------------------------------------------------------------------------------- 1399 * |Bits |Field |Descriptions 1400 * | :----: | :----: | :---- | 1401 * |[3:0] |MASTER |Master Violating Security Policy 1402 * | | |Indicate which master invokes the security violation. 1403 * | | |0x0 = core processor. 1404 * | | |0x3 = PDMA0. 1405 * | | |0x4 = SDH0. 1406 * | | |0x5 = CRYPTO. 1407 * | | |0x6 = USH. 1408 * | | |0xB = PDMA1. 1409 * | | |Others is undefined. 1410 * @var SCU_T::SRAM2VA 1411 * Offset: 0xC8 SRAM2 Violation Address 1412 * --------------------------------------------------------------------------------------------------- 1413 * |Bits |Field |Descriptions 1414 * | :----: | :----: | :---- | 1415 * |[31:0] |VIOADDR |Violation Address 1416 * | | |Indicate the target address of the access, which invokes the security violation. 1417 * @var SCU_T::SINFAEN 1418 * Offset: 0xF0 Shared Information Access Enable Register 1419 * --------------------------------------------------------------------------------------------------- 1420 * |Bits |Field |Descriptions 1421 * | :----: | :----: | :---- | 1422 * |[0] |SCUSIAEN |SCU Shared Information Access Enable Bit 1423 * | | |0 = Non-secure CPU access SCU Shared information Disabled. 1424 * | | |1 = Non-secure CPU access SCU Shared information Enabled. 1425 * |[1] |SYSSIAEN |SYS Shared Information Access Enable Bit 1426 * | | |0 = Non-secure CPU access SYS Shared information Disabled. 1427 * | | |1 = Non-secure CPU access SYS Shared information Enabled. 1428 * | | |Note:Include clock information. 1429 * |[2] |FMCSIAEN |FMC Shared Information Access Enable Bit 1430 * | | |0 = Non-secure CPU access FMC Shared information Disabled. 1431 * | | |1 = Non-secure CPU access FMC Shared information Enabled. 1432 * @var SCU_T::PNPSET 1433 * Offset: 0x100 Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x4001_FFFF) 1434 * --------------------------------------------------------------------------------------------------- 1435 * |Bits |Field |Descriptions 1436 * | :----: | :----: | :---- | 1437 * |[0] |SYS |Set SYS to Non-privileged State 1438 * | | |0 = SYS is a privileged module (default). 1439 * | | |1 = SYS is a non-privileged module. 1440 * |[8] |PDMA0 |Set PDMA0 to Non-privileged State 1441 * | | |0 = PDMA0 is a privileged module (default). 1442 * | | |1 = PDMA0 is a non-privileged module. 1443 * |[9] |USBH |Set USBH to Non-privileged State 1444 * | | |0 = USBH is a privileged module (default). 1445 * | | |1 = USBH is a non-privileged module. 1446 * |[12] |FMC |Set FMC to Non-privileged State 1447 * | | |0 = FMC is a privileged module (default). 1448 * | | |1 = FMC is a non-privileged module. 1449 * |[13] |SDH0 |Set SDH0 to Non-privileged State 1450 * | | |0 = SDH0 is a privileged module (default). 1451 * | | |1 = SDH0 is a non-privileged module. 1452 * |[16] |EBI |Set EBI to Non-privileged State 1453 * | | |0 = EBI is a privileged module (default). 1454 * | | |1 = EBI is a non-privileged module. 1455 * |[24] |PDMA1 |Set PDMA1 to Non-privileged State 1456 * | | |0 = PDMA1 is a privileged module (default). 1457 * | | |1 = PDMA1 is a non-privileged module. 1458 * Offset: 0x104 Peripheral Non-privileged Attribution Set Register1 (0x4002_0000~0x4003_FFFF) 1459 * --------------------------------------------------------------------------------------------------- 1460 * |Bits |Field |Descriptions 1461 * | :----: | :----: | :---- | 1462 * |[15] |SCU |Set SCU to Non-privileged State 1463 * | | |0 = SCU is a privileged module (default). 1464 * | | |1 = SCU is a non-privileged module. 1465 * |[17] |CRC |Set CRC to Non-privileged State 1466 * | | |0 = CRC is a privileged module (default). 1467 * | | |1 = CRC is a non-privileged module. 1468 * |[18] |CRPT |Set CRPT to Non-privileged State 1469 * | | |0 = CRPT is a privileged module (default). 1470 * | | |1 = CRPT is a non-privileged module. 1471 * |[21] |KS |Set KS to Non-privileged State 1472 * | | |0 = KS is a privileged module (default). 1473 * | | |1 = KS is a non-privileged module. 1474 * Offset: 0x108 Peripheral Non-privileged Attribution Set Register2 (0x4004_0000~0x4005_FFFF) 1475 * --------------------------------------------------------------------------------------------------- 1476 * |Bits |Field |Descriptions 1477 * | :----: | :----: | :---- | 1478 * |[0] |WDT |Set WDT to Non-privileged State 1479 * | | |0 = WDT is a privileged module (default). 1480 * | | |1 = WDT is a non-privileged module. 1481 * |[1] |RTC |Set RTC to Non-privileged State 1482 * | | |0 = RTC is a privileged module (default). 1483 * | | |1 = RTC is a non-privileged module. 1484 * |[2] |EWDT |Set EWDT to Non-privileged State 1485 * | | |0 = EWDT is a privileged module (default). 1486 * | | |1 = EWDT is a non-privileged module. 1487 * |[3] |EADC |Set EADC to Non-privileged State 1488 * | | |0 = EADC is a privileged module (default). 1489 * | | |1 = EADC is a non-privileged module. 1490 * |[5] |ACMP01 |Set ACMP01 to Non-privileged State 1491 * | | |0 = ACMP0, ACMP1 are privileged modules (default). 1492 * | | |1 = ACMP0, ACMP1 are non-privileged modules. 1493 * |[7] |DAC |Set DAC to Non-privileged State 1494 * | | |0 = DAC is a privileged module (default). 1495 * | | |1 = DAC is a non-privileged module. 1496 * |[8] |I2S0 |Set I2S0 to Non-privileged State 1497 * | | |0 = I2S0 is a privileged module (default). 1498 * | | |1 = I2S0 is a non-privileged module. 1499 * |[13] |OTG |Set OTG to Non-privileged State 1500 * | | |0 = OTG is a privileged module (default). 1501 * | | |1 = OTG is a non-privileged module. 1502 * |[16:14] |TMR01 |Set TMR01 to Non-privileged State 1503 * | | |0 = TMR01 is a privileged module (default). 1504 * | | |1 = TMR01 is a non-privileged module. 1505 * |[17] |TMR23 |Set TMR23 to Non-privileged State 1506 * | | |0 = TMR23 is a privileged module (default). 1507 * | | |1 = TMR23 is a non-privileged module. 1508 * |[24] |EPWM0 |Set EPWM0 to Non-privileged State 1509 * | | |0 = EPWM0 is a privileged module (default). 1510 * | | |1 = EPWM0 is a non-privileged module. 1511 * |[25] |EPWM1 |Set EPWM1 to Non-privileged State 1512 * | | |0 = EPWM1 is a privileged module (default). 1513 * | | |1 = EPWM1 is a non-privileged module. 1514 * |[26] |BPWM0 |Set BPWM0 to Non-privileged State 1515 * | | |0 = BPWM0 is a privileged module (default). 1516 * | | |1 = BPWM0 is a non-privileged module. 1517 * |[27] |BPWM1 |Set BPWM1 to Non-privileged State 1518 * | | |0 = BPWM1 is a privileged module (default). 1519 * | | |1 = BPWM1 is a non-privileged module. 1520 * Offset: 0x10C Peripheral Non-privileged Attribution Set Register3 (0x4006_0000~0x4007_FFFF) 1521 * --------------------------------------------------------------------------------------------------- 1522 * |Bits |Field |Descriptions 1523 * | :----: | :----: | :---- | 1524 * |[0] |QSPI0 |Set QSPI0 to Non-privileged State 1525 * | | |0 = QSPI0 is a privileged module (default). 1526 * | | |1 = QSPI0 is a non-privileged module. 1527 * |[1] |SPI0 |Set SPI0 to Non-privileged State 1528 * | | |0 = SPI0 is a privileged module (default). 1529 * | | |1 = SPI0 is a non-privileged module. 1530 * |[2] |SPI1 |Set SPI1 to Non-privileged State 1531 * | | |0 = SPI1 is a privileged module (default). 1532 * | | |1 = SPI1 is a non-privileged module. 1533 * |[3] |SPI2 |Set SPI2 to Non-privileged State 1534 * | | |0 = SPI2 is a privileged module (default). 1535 * | | |1 = SPI2 is a non-privileged module. 1536 * |[4] |SPI3 |Set SPI3 to Non-privileged State 1537 * | | |0 = SPI3 is a privileged module (default). 1538 * | | |1 = SPI3 is a non-privileged module. 1539 * |[16] |UART0 |Set UART0 to Non-privileged State 1540 * | | |0 = UART0 is a privileged module (default). 1541 * | | |1 = UART0 is a non-privileged module. 1542 * |[17] |UART1 |Set UART1 to Non-privileged State 1543 * | | |0 = UART1 is a privileged module (default). 1544 * | | |1 = UART1 is a non-privileged module. 1545 * |[18] |UART2 |Set UART2 to Non-privileged State 1546 * | | |0 = UART2 is a privileged module (default). 1547 * | | |1 = UART2 is a non-privileged module. 1548 * |[19] |UART3 |Set UART3 to Non-privileged State 1549 * | | |0 = UART3 is a privileged module (default). 1550 * | | |1 = UART3 is a non-privileged module. 1551 * |[20] |UART4 |Set UART4 to Non-privileged State 1552 * | | |0 = UART4 is a privileged module (default). 1553 * | | |1 = UART4 is a non-privileged module. 1554 * |[21] |UART5 |Set UART5 to Non-privileged State 1555 * | | |0 = UART5 is a privileged module (default). 1556 * | | |1 = UART5 is a non-privileged module. 1557 * Offset: 0x110 Peripheral Non-privileged Attribution Set Register4 (0x4008_0000~0x4009_FFFF) 1558 * --------------------------------------------------------------------------------------------------- 1559 * |Bits |Field |Descriptions 1560 * | :----: | :----: | :---- | 1561 * |[0] |I2C0 |Set I2C0 to Non-privileged State 1562 * | | |0 = I2C0 is a privileged module (default). 1563 * | | |1 = I2C0 is a non-privileged module. 1564 * |[1] |I2C1 |Set I2C1 to Non-privileged State 1565 * | | |0 = I2C1 is a privileged module (default). 1566 * | | |1 = I2C1 is a non-privileged module. 1567 * |[2] |I2C2 |Set I2C2 to Non-privileged State 1568 * | | |0 = I2C2 is a privileged module (default). 1569 * | | |1 = I2C2 is a non-privileged module. 1570 * |[16] |SC0 |Set SC0 to Non-privileged State 1571 * | | |0 = SC0 is a privileged module (default). 1572 * | | |1 = SC0 is a non-privileged module. 1573 * |[17] |SC1 |Set SC1 to Non-privileged State 1574 * | | |0 = SC1 is a privileged module (default). 1575 * | | |1 = SC1 is a non-privileged module. 1576 * |[18] |SC2 |Set SC2 to Non-privileged State 1577 * | | |0 = SC2 is a privileged module (default). 1578 * | | |1 = SC2 is a non-privileged module. 1579 * Offset: 0x114 Peripheral Non-privileged Attribution Set Register5 (0x400A_0000~0x400B_FFFF) 1580 * --------------------------------------------------------------------------------------------------- 1581 * |Bits |Field |Descriptions 1582 * | :----: | :----: | :---- | 1583 * |[0] |CAN0 |Set CAN0 to Non-privileged State 1584 * | | |0 = CAN0 is a privileged module (default). 1585 * | | |1 = CAN0 is a non-privileged module. 1586 * |[16] |QEI0 |Set QEI0 to Non-privileged State 1587 * | | |0 = QEI0 is a privileged module (default). 1588 * | | |1 = QEI0 is a non-privileged module. 1589 * |[17] |QEI1 |Set QEI1 to Non-privileged State 1590 * | | |0 = QEI1 is a privileged module (default). 1591 * | | |1 = QEI1 is a non-privileged module. 1592 * |[20] |ECAP0 |Set ECAP0 to Non-privileged State 1593 * | | |0 = ECAP0 is a privileged module (default). 1594 * | | |1 = ECAP0 is a non-privileged module. 1595 * |[21] |ECAP1 |Set ECAP1 to Non-privileged State 1596 * | | |0 = ECAP1 is a privileged module (default). 1597 * | | |1 = ECAP1 is a non-privileged module. 1598 * |[25] |TRNG |Set TRNG to Non-privileged State 1599 * | | |0 = TRNG is a privileged module (default). 1600 * | | |1 = TRNG is a non-privileged module. 1601 * |[27] |LCD |Set LCD to Non-privileged State 1602 * | | |0 = LCD is a privileged module (default). 1603 * | | |1 = LCD is a non-privileged module. 1604 * |[29] |TAMPER |Set TAMPER to Non-privileged State 1605 * | | |0 = TAMPER is a privileged module (default). 1606 * | | |1 = TAMPER is a non-privileged module. 1607 * Offset: 0x118 Peripheral Non-privileged Attribution Set Register6 (0x400C_0000~0x400D_FFFF) 1608 * --------------------------------------------------------------------------------------------------- 1609 * |Bits |Field |Descriptions 1610 * | :----: | :----: | :---- | 1611 * |[0] |USBD |Set USBD to Non-privileged State 1612 * | | |0 = USBD is a privileged module (default). 1613 * | | |1 = USBD is a non-privileged module. 1614 * |[16] |USCI0 |Set USCI0 to Non-privileged State 1615 * | | |0 = USCI0 is a privileged module (default). 1616 * | | |1 = USCI0 is a non-privileged module. 1617 * |[17] |USCI1 |Set USCI1 to Non-privileged State 1618 * | | |0 = USCI1 is a privileged module (default). 1619 * | | |1 = USCI1 is a non-privileged module. 1620 * @var SCU_T::IONPSET 1621 * Offset: 0x120 IO Non-privileged Attribution Set Register 1622 * --------------------------------------------------------------------------------------------------- 1623 * |Bits |Field |Descriptions 1624 * | :----: | :----: | :---- | 1625 * |[0] |PA |Set GPIO Port a to Non-privileged State 1626 * | | |0 = GPIO port A is privileged (default). 1627 * | | |1 = GPIO port A is non-privileged. 1628 * |[1] |PB |Set GPIO Port B to Non-privileged State 1629 * | | |0 = GPIO port B is privileged (default). 1630 * | | |1 = GPIO port B is non-privileged. 1631 * |[2] |PC |Set GPIO Port C to Non-privileged State 1632 * | | |0 = GPIO port C is privileged (default). 1633 * | | |1 = GPIO port C is non-privileged. 1634 * |[3] |PD |Set GPIO Port D to Non-privileged State 1635 * | | |0 = GPIO port D is privileged (default). 1636 * | | |1 = GPIO port D is non-privileged. 1637 * |[4] |PE |Set GPIO Port E to Nonj-privileged State 1638 * | | |0 = GPIO port E is privileged (default). 1639 * | | |1 = GPIO port E is non-privileged. 1640 * |[5] |PF |Set GPIO Port F to Non-privileged State 1641 * | | |0 = GPIO port F is privileged (default). 1642 * | | |1 = GPIO port F is non-privileged. 1643 * |[6] |PG |Set GPIO Port G to Non-privileged State 1644 * | | |0 = GPIO port G is privileged (default). 1645 * | | |1 = GPIO port G is non-privileged. 1646 * |[7] |PH |Set GPIO Port H to Non-privileged State 1647 * | | |0 = GPIO port H is privileged (default). 1648 * | | |1 = GPIO port H is non-privileged. 1649 * @var SCU_T::SRAMNPSET 1650 * Offset: 0x124 SRAM Non-privileged Attribution Set Register 1651 * --------------------------------------------------------------------------------------------------- 1652 * |Bits |Field |Descriptions 1653 * | :----: | :----: | :---- | 1654 * |[19:0] |SECn |Set SRAM Section n to Non-privileged State 1655 * | | |0 = SRAM Section n is privileged (default). 1656 * | | |1 = SRAM Section n is non-privileged. 1657 * | | |Size per section is 16 Kbytes. 1658 * | | |Secure SRAM section n is 0x2000_0000+0x4000*n to 0x2000_0000+0x4000*(n+1)-0x1 1659 * | | |Non-secure SRAM section n is 0x3000_0000+0x4000*n to 0x3000_0000+0x4000*(n+1)-0x1 1660 * @var SCU_T::MEMNPSET 1661 * Offset: 0x128 Other Memory Non-privileged Attribution Set Register 1662 * --------------------------------------------------------------------------------------------------- 1663 * |Bits |Field |Descriptions 1664 * | :----: | :----: | :---- | 1665 * |[0] |FLASH |Set Flash to Non-privileged State 1666 * | | |Set the privileged state of memory ranging from 0x0000_0000 to 0x1FFF_FFFF. 1667 * | | |0 = Flash is setting to privileged (default). 1668 * | | |1 = Flash is setting to non-privileged. 1669 * |[1] |EXTMEM |Set External Memory (EBI Memory) to Non-privileged State 1670 * | | |Set the privileged state of memory ranging from 0x6000_0000 to 0x7FFF_FFFF. 1671 * | | |0 = External Memory is setting to privileged (default). 1672 * | | |1 = External Memory is setting to non-privileged. 1673 * @var SCU_T::PVIOIEN 1674 * Offset: 0x12C Privileged Violation Interrupt Enable Register 1675 * --------------------------------------------------------------------------------------------------- 1676 * |Bits |Field |Descriptions 1677 * | :----: | :----: | :---- | 1678 * |[0] |APB0IEN |APB0 Privileged Violation Interrupt Enable Bit 1679 * | | |0 = Interrupt triggered from privileged violation of APB0 Disabled. 1680 * | | |1 = Interrupt triggered from privileged violation of APB0 Enabled. 1681 * |[1] |APB1IEN |APB1 Privileged Violation Interrupt Enable Bit 1682 * | | |0 = Interrupt triggered from privileged violation of APB1 Disabled. 1683 * | | |1 = Interrupt triggered from privileged violation of APB1 Enabled. 1684 * |[4] |GPIOIEN |GPIO Privileged Violation Interrupt Enable Bit 1685 * | | |0 = Interrupt triggered from privileged violation of GPIO Disabled. 1686 * | | |1 = Interrupt triggered from privileged violation of GPIO Enabled. 1687 * |[5] |EBIIEN |EBI Privileged Violation Interrupt Enable Bit 1688 * | | |0 = Interrupt triggered from privileged violation of EBI Disabled. 1689 * | | |1 = Interrupt triggered from privileged violation of EBI Enabled. 1690 * |[6] |USBHIEN |USBH Privileged Violation Interrupt Enable Bit 1691 * | | |0 = Interrupt triggered from privileged violation of USB host Disabled. 1692 * | | |1 = Interrupt triggered from privileged violation of USB host Enabled. 1693 * |[7] |CRCIEN |CRC Privileged Violation Interrupt Enable Bit 1694 * | | |0 = Interrupt triggered from privileged violation of CRC Disabled. 1695 * | | |1 = Interrupt triggered from privileged violation of CRC Enabled. 1696 * |[8] |SDH0IEN |SDH0 Privileged Violation Interrupt Enable Bit 1697 * | | |0 = Interrupt triggered from privileged violation of SD host 0 Disabled. 1698 * | | |1 = Interrupt triggered from privileged violation of SD host 0 Enabled. 1699 * |[10] |PDMA0IEN |PDMA0 Privileged Violation Interrupt Enable Bit 1700 * | | |0 = Interrupt triggered from privileged violation of PDMA0 Disabled. 1701 * | | |1 = Interrupt triggered from privileged violation of PDMA0 Enabled. 1702 * |[11] |PDMA1IEN |PDMA1 Privileged Violation Interrupt Enable Bit 1703 * | | |0 = Interrupt triggered from privileged violation of PDMA1 Disabled. 1704 * | | |1 = Interrupt triggered from privileged violation of PDMA1 Enabled. 1705 * |[12] |SRAM0IEN |SRAM Bank 0 Privileged Violation Interrupt Enable Bit 1706 * | | |0 = Interrupt triggered from privileged violation of SRAM bank0 Disabled. 1707 * | | |1 = Interrupt triggered from privileged violation of SRAM bank0 Enabled. 1708 * |[13] |SRAM1IEN |SRAM Bank 1 Privileged Violation Interrupt Enable Bit 1709 * | | |0 = Interrupt triggered from privileged violation of SRAM bank1 Disabled. 1710 * | | |1 = Interrupt triggered from privileged violation of SRAM bank1 Enabled. 1711 * |[14] |FMCIEN |FMC Privileged Violation Interrupt Enable Bit 1712 * | | |0 = Interrupt triggered from privileged violation of FMC Disabled. 1713 * | | |1 = Interrupt triggered from privileged violation of FMC Enabled. 1714 * |[15] |FLASHIEN |FLASH Privileged Violation Interrupt Enable Bit 1715 * | | |0 = Interrupt triggered from privileged violation of Flash data Disabled. 1716 * | | |1 = Interrupt triggered from privileged violation of Flash data Enabled. 1717 * |[16] |SCUIEN |SCU Privileged Violation Interrupt Enable Bit 1718 * | | |0 = Interrupt triggered from privileged violation of SCU Disabled. 1719 * | | |1 = Interrupt triggered from privileged violation of SCU Enabled. 1720 * |[17] |SYSIEN |SYS Privileged Violation Interrupt Enable Bit 1721 * | | |0 = Interrupt triggered from privileged violation of system manager Disabled. 1722 * | | |1 = Interrupt triggered from privileged violation of system manager Enabled. 1723 * |[18] |CRPTIEN |CRPT Privileged Violation Interrupt Enable Bit 1724 * | | |0 = Interrupt triggered from privileged violation of crypto Disabled. 1725 * | | |1 = Interrupt triggered from privileged violation of crypto Enabled. 1726 * |[19] |KSIEN |KS Privileged Violation Interrupt Enale Bit 1727 * | | |0 = Interrupt triggered from privileged violation of keystore Disabled. 1728 * | | |1 = Interrupt triggered from privileged violation of keystore Enabled. 1729 * @var SCU_T::PVINTSTS 1730 * Offset: 0x130 Privileged Violation Interrupt Status Register 1731 * --------------------------------------------------------------------------------------------------- 1732 * |Bits |Field |Descriptions 1733 * | :----: | :----: | :---- | 1734 * |[0] |APB0IF |APB0 Privileged Violation Interrupt Status 1735 * | | |0 = No APB0 violation interrupt event. 1736 * | | |1 = There is APB0 violation interrupt event. 1737 * | | |Note: Write 1 to clear the interrupt flag. 1738 * |[1] |APB1IF |APB1 Privileged Violation Interrupt Status 1739 * | | |0 = No APB1 violation interrupt event. 1740 * | | |1 = There is APB1 violation interrupt event. 1741 * | | |Note: Write 1 to clear the interrupt flag. 1742 * |[4] |GPIOIF |GPIO Privileged Violation Interrupt Status 1743 * | | |0 = No GPIO violation interrupt event. 1744 * | | |1 = There is GPIO violation interrupt event. 1745 * | | |Note: Write 1 to clear the interrupt flag. 1746 * |[5] |EBIIF |EBI Privileged Violation Interrupt Status 1747 * | | |0 = No EBI violation interrupt event. 1748 * | | |1 = There is EBI violation interrupt event. 1749 * | | |Note: Write 1 to clear the interrupt flag. 1750 * |[6] |USBHIF |USBH Privileged Violation Interrupt Status 1751 * | | |0 = No USBH violation interrupt event. 1752 * | | |1 = There is USBH violation interrupt event. 1753 * | | |Note: Write 1 to clear the interrupt flag. 1754 * |[7] |CRCIF |CRC Privileged Violation Interrupt Status 1755 * | | |0 = No CRC violation interrupt event. 1756 * | | |1 = There is CRC violation interrupt event. 1757 * | | |Note: Write 1 to clear the interrupt flag. 1758 * |[8] |SDH0IF |SDH0 Privileged Violation Interrupt Status 1759 * | | |0 = No SDH0 violation interrupt event. 1760 * | | |1 = There is SDH0 violation interrupt event. 1761 * | | |Note: Write 1 to clear the interrupt flag. 1762 * |[10] |PDMA0IF |PDMA0 Privileged Violation Interrupt Status 1763 * | | |0 = No PDMA0 violation interrupt event. 1764 * | | |1 = There is PDMA0 violation interrupt event. 1765 * | | |Note: Write 1 to clear the interrupt flag. 1766 * |[11] |PDMA1IF |PDMA1 Privileged Violation Interrupt Status 1767 * | | |0 = No PDMA1 violation interrupt event. 1768 * | | |1 = There is PDMA1 violation interrupt event. 1769 * | | |Note: Write 1 to clear the interrupt flag. 1770 * |[12] |SRAM0IF |SRAM0 Privileged Violation Interrupt Status 1771 * | | |0 = No SRAM0 violation interrupt event. 1772 * | | |1 = There is SRAM0 violation interrupt event. 1773 * | | |Note: Write 1 to clear the interrupt flag. 1774 * |[13] |SRAM1IF |SRAM Bank 1 Privileged Violation Interrupt Status 1775 * | | |0 = No SRAM1 violation interrupt event. 1776 * | | |1 = There is SRAM1 violation interrupt event. 1777 * | | |Note: Write 1 to clear the interrupt flag. 1778 * |[14] |FMCIF |FMC Privileged Violation Interrupt Status 1779 * | | |0 = No FMC violation interrupt event. 1780 * | | |1 = There is FMC violation interrupt event. 1781 * | | |Note: Write 1 to clear the interrupt flag. 1782 * |[15] |FLASHIF |FLASH Privileged Violation Interrupt Status 1783 * | | |0 = No FLASH violation interrupt event. 1784 * | | |1 = There is FLASH violation interrupt event. 1785 * | | |Note: Write 1 to clear the interrupt flag. 1786 * |[16] |SCUIF |SCU Privileged Violation Interrupt Status 1787 * | | |0 = No SCU violation interrupt event. 1788 * | | |1 = There is SCU violation interrupt event. 1789 * | | |Note: Write 1 to clear the interrupt flag. 1790 * |[17] |SYSIF |SYS Privileged Violation Interrupt Status 1791 * | | |0 = No SYS violation interrupt event. 1792 * | | |1 = There is SYS violation interrupt event. 1793 * | | |Note: Write 1 to clear the interrupt flag. 1794 * |[18] |CRPTIF |CRPT Privileged Violation Interrupt Status 1795 * | | |0 = No CRPT violation interrupt event. 1796 * | | |1 = There is CRPT violation interrupt event. 1797 * | | |Note: Write 1 to clear the interrupt flag. 1798 * |[19] |KSIF |KS Privileged Violation Interrupt Status 1799 * | | |0 = No KS violation interrupt event. 1800 * | | |1 = There is KS violation interrupt event. 1801 * | | |Note: Write 1 to clear the interrupt flag. 1802 * @var SCU_T::NSMCTL 1803 * Offset: 0x200 Non-secure State Monitor Control Register 1804 * --------------------------------------------------------------------------------------------------- 1805 * |Bits |Field |Descriptions 1806 * | :----: | :----: | :---- | 1807 * |[7:0] |PRESCALE |Pre-scale Value of Non-secure State Monitor Counter 1808 * | | |0 = Counter Disabled. 1809 * | | |Others = Counter Enabled and the counter clock source = HCLK/PRESCALE. 1810 * |[8] |NSMIEN |Non-secure State Monitor Interrupt Enable Bit 1811 * | | |0 = Non-secure state monitor interrupt Disabled. 1812 * | | |1 = Non-secure state monitor interrupt Enabled. 1813 * |[9] |AUTORLD |Auto Reload Non-secure State Monitor Counter When CURRNS Changing to 1 1814 * | | |0 = Disable clearing non-secure state monitor counter automtically (default). 1815 * | | |1 = Enable clearing non-secure state monitor counter automatically when the core processor changes from secure state to non-secure state 1816 * | | |(i.e.when CURRNS chagned from 0 to 1). 1817 * |[10] |TMRMOD |Non-secure Monitor Mode Enable Bit 1818 * | | |0 = Monitor mode. The counter will count down when the core processor is in non-secure state. (default) 1819 * | | |1 = Free-counting mode 1820 * | | |The counter will keep counting no mater the core processor is in secure or non-secure state. 1821 * |[12] |IDLEON |Monitor Counter Keep Counting When the Chip Is in Idle Mode Enable Bit 1822 * | | |0 = The counter will be halted when the chip is in idle mode. 1823 * | | |1 = The counter will keep counting when the chip is in idle mode. (default) 1824 * | | |Note: In monitor mode, the counter is always halted when the core processor is in secure state. 1825 * |[13] |DBGON |Monitor Counter Keep Counting When the Chip Is in Debug Mode Enable Bit 1826 * | | |0 = The counter will be halted when the core processor is halted by ICE. (default) 1827 * | | |1 = The counter will keep counting when the core processor is halted by ICE. 1828 * @var SCU_T::NSMLOAD 1829 * Offset: 0x204 Non-secure State Monitor Reload Value Register 1830 * --------------------------------------------------------------------------------------------------- 1831 * |Bits |Field |Descriptions 1832 * | :----: | :----: | :---- | 1833 * |[23:0] |RELOAD |Reload Value for Non-secure State Monitor Counter 1834 * | | |The RELOAD value will be reloaded to the counter whenever the counter counts down to 0. 1835 * @var SCU_T::NSMVAL 1836 * Offset: 0x208 Non-secure State Monitor Counter Value Register 1837 * --------------------------------------------------------------------------------------------------- 1838 * |Bits |Field |Descriptions 1839 * | :----: | :----: | :---- | 1840 * |[23:0] |VALUE |Counter Value of Non-secure State Monitor Counter 1841 * | | |Current value of non-secure state monitor counter 1842 * | | |This is down counter and counts down only when CURRNS = 1 1843 * | | |When counting down to 0, VALUE will automatically be reloaded from NSMLOAD register. 1844 * | | |A write of any value clears the VALUE to 0 and also clears NSMIF. 1845 * @var SCU_T::NSMSTS 1846 * Offset: 0x20C Non-secure State Monitor Status Register 1847 * --------------------------------------------------------------------------------------------------- 1848 * |Bits |Field |Descriptions 1849 * | :----: | :----: | :---- | 1850 * |[0] |CURRNS |Current Core Processor Secure/Non-secure State (Read Only) 1851 * | | |0 = Core processor is in secure state. 1852 * | | |1 = Core processor is in non-secure state. 1853 * | | |Note: This bit can be used to monitor the current secure/non-secure state of the core processor, even if the non-secure state monitor counter is disabled. 1854 * |[1] |NSMIF |Non-secure State Monitor Interrupt Flag 1855 * | | |0 = Counter doesnu2019t count down to 0 since the last NSMIF has been cleared. 1856 * | | |1 = Counter counts down to 0. 1857 * | | |Note: This bit is cleared by writing 1. 1858 * @var SCU_T::BBE 1859 * Offset: 0x300 Block Bus Error Register 1860 * --------------------------------------------------------------------------------------------------- 1861 * |Bits |Field |Descriptions 1862 * | :----: | :----: | :---- | 1863 * |[0] |BBEEN |Block Bus-error Enable Bit 1864 * | | |0 = Disable Blocking Bus Error to the core processor. 1865 * | | |1 = Enable Blocking Bus Error to the core processor. 1866 * | | |This bit is double write-protected, WRVERY and SYS_REGLCTL register. 1867 * |[31:8] |WVERY |Write Verify Code 1868 * | | |In order to write BBEEN bit, the code should be set as 0x59475A. 1869 * | | |When read access, the return value of this field is always 0. 1870 * @var SCU_T::IDAUANS 1871 * Offset: 0x304 IDAU All Non-secure Set Register 1872 * --------------------------------------------------------------------------------------------------- 1873 * |Bits |Field |Descriptions 1874 * | :----: | :----: | :---- | 1875 * |[0] |IDAUANSEN |IDAU All Non-secure Enable Bit 1876 * | | |0 = Disable IDAU sets all region Non-secure. 1877 * | | |1 = Enable IDAU sets all region Non-secure. 1878 * | | |This bit is double write-protected, WRVERY and SYS_REGLCTL register. 1879 * |[31:8] |WVERY |Write Verify Code 1880 * | | |In order to write BBEEN bit, the code should be set as 0x59475A. 1881 * | | |When read access, the return value of this field is always 0. 1882 * @var SCU_T::VERSION 1883 * Offset: 0xFFC SCU RTL Design Version Register 1884 * --------------------------------------------------------------------------------------------------- 1885 * |Bits |Field |Descriptions 1886 * | :----: | :----: | :---- | 1887 * |[15:0] |MINOR |SCU RTL Design Minor Version 1888 * | | |Minor version number is dependent on ECO version control. 1889 * |[23:16] |SUB |SCU RTL Design Sub Version Number 1890 * | | |Major version number is correlated to product line. 1891 * |[31:24] |MAJOR |SCU RTL Design Major Version Number 1892 * | | |Major version number is correlated to product line. 1893 */ 1894 __IO uint32_t PNSSET[7]; /*!< [0x0000:0x0018] Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */ 1895 __I uint32_t RESERVE0[2]; 1896 __IO uint32_t SRAMNSSET; /*!< [0x0024] SRAM Non-secure Attribution Set Register */ 1897 __I uint32_t FNSADDR; /*!< [0x0028] Flash Non-secure Boundary Address Register */ 1898 __IO uint32_t SVIOIEN; /*!< [0x002c] Security Violation Interrupt Enable Register */ 1899 __IO uint32_t SVINTSTS; /*!< [0x0030] Security Violation Interrupt Status Register */ 1900 __I uint32_t APB0VSRC; /*!< [0x0034] APB0 Security Policy Violation Source */ 1901 __I uint32_t APB0VA; /*!< [0x0038] APB0 Violation Address */ 1902 __I uint32_t APB1VSRC; /*!< [0x003c] APB1 Security Policy Violation Source */ 1903 __I uint32_t APB1VA; /*!< [0x0040] APB1 Violation Address */ 1904 __I uint32_t GPIOVSRC; /*!< [0x0044] GPIO Security Policy Violation Source */ 1905 __I uint32_t GPIOVA; /*!< [0x0048] GPIO Violation Address */ 1906 __I uint32_t EBIVSRC; /*!< [0x004c] EBI Security Policy Violation Source */ 1907 __I uint32_t EBIVA; /*!< [0x0050] EBI Violation Address */ 1908 __I uint32_t USBHVSRC; /*!< [0x0054] USBH Security Policy Violation Source */ 1909 __I uint32_t USBHVA; /*!< [0x0058] USBH Violation Address */ 1910 __I uint32_t CRCVSRC; /*!< [0x005c] CRC Security Policy Violation Source */ 1911 __I uint32_t CRCVA; /*!< [0x0060] CRC Violation Address */ 1912 __I uint32_t SD0VSRC; /*!< [0x0064] SDH0 Security Policy Violation Source */ 1913 __I uint32_t SD0VA; /*!< [0x0068] SDH0 Violation Address */ 1914 __I uint32_t RESERVE1[2]; 1915 __I uint32_t PDMA0VSRC; /*!< [0x0074] PDMA0 Security Policy Violation Source */ 1916 __I uint32_t PDMA0VA; /*!< [0x0078] PDMA0 Violation Address */ 1917 __I uint32_t PDMA1VSRC; /*!< [0x007c] PDMA1 Security Policy Violation Source */ 1918 __I uint32_t PDMA1VA; /*!< [0x0080] PDMA1 Violation Address */ 1919 __I uint32_t SRAM0VSRC; /*!< [0x0084] SRAM0 Security Policy Violation Source */ 1920 __I uint32_t SRAM0VA; /*!< [0x0088] SRAM0 Violation Address */ 1921 __I uint32_t SRAM1VSRC; /*!< [0x008c] SRAM1 Security Policy Violation Source */ 1922 __I uint32_t SRAM1VA; /*!< [0x0090] SRAM1 Violation Address */ 1923 __I uint32_t FMCVSRC; /*!< [0x0094] FMC Security Policy Violation Source */ 1924 __I uint32_t FMCVA; /*!< [0x0098] FMC Violation Address */ 1925 __I uint32_t FLASHVSRC; /*!< [0x009c] Flash Security Policy Violation Source */ 1926 __I uint32_t FLASHVA; /*!< [0x00a0] Flash Violation Address */ 1927 __I uint32_t SCUVSRC; /*!< [0x00a4] SCU Security Policy Violation Source */ 1928 __I uint32_t SCUVA; /*!< [0x00a8] SCU Violation Address */ 1929 __I uint32_t SYSVSRC; /*!< [0x00ac] System(GMISC) Security Policy Violation Source */ 1930 __I uint32_t SYSVA; /*!< [0x00b0] System(GMISC) Violation Address */ 1931 __I uint32_t CRPTVSRC; /*!< [0x00b4] Crypto Security Policy Violation Source */ 1932 __I uint32_t CRPTVA; /*!< [0x00b8] Crypto Violation Address */ 1933 __I uint32_t KSVSRC; /*!< [0x00bc] KS Security Policy Violation Source */ 1934 __I uint32_t KSVA; /*!< [0x00c0] KS Violation Address */ 1935 __I uint32_t SRAM2VSRC; /*!< [0x00c4] SRAM2 Security Policy Violation Source */ 1936 __I uint32_t SRAM2VA; /*!< [0x00c8] SRAM2 Violation Address */ 1937 __I uint32_t RESERVE2[9]; 1938 __IO uint32_t SINFAEN; /*!< [0x00f0] Shared Information Access Enable Register */ 1939 __I uint32_t RESERVE3[3]; 1940 __IO uint32_t PNPSET[7]; /*!< [0x0100:0x0118] Peripheral Non-privileged Attribution Set Register0 (0x4000_0000~0x400D_FFFF) */ 1941 __I uint32_t RESERVE4[1]; 1942 __IO uint32_t IONPSET; /*!< [0x0120] IO Non-privileged Attribution Set Register */ 1943 __IO uint32_t SRAMNPSET; /*!< [0x0124] SRAM Non-privileged Attribution Set Register */ 1944 __IO uint32_t MEMNPSET; /*!< [0x0128] Other Memory Non-privileged Attribution Set Register */ 1945 __IO uint32_t PVIOIEN; /*!< [0x012c] Privileged Violation Interrupt Enable Register */ 1946 __IO uint32_t PVINTSTS; /*!< [0x0130] Privileged Violation Interrupt Status Register */ 1947 __I uint32_t RESERVE5[3]; 1948 __IO uint32_t IONSSET[8]; /*!< [0x0140:0x015C] IO Non-secure Attribution Set Register */ 1949 __I uint32_t RESERVE6[40]; 1950 __IO uint32_t NSMCTL; /*!< [0x0200] Non-secure State Monitor Control Register */ 1951 __IO uint32_t NSMLOAD; /*!< [0x0204] Non-secure State Monitor Reload Value Register */ 1952 __IO uint32_t NSMVAL; /*!< [0x0208] Non-secure State Monitor Counter Value Register */ 1953 __IO uint32_t NSMSTS; /*!< [0x020c] Non-secure State Monitor Status Register */ 1954 __I uint32_t RESERVE7[60]; 1955 __IO uint32_t BBE; /*!< [0x0300] Block Bus Error Register */ 1956 __IO uint32_t IDAUANS; /*!< [0x0304] IDAU All Non-secure Set Register */ 1957 __I uint32_t RESERVE8[829]; 1958 __I uint32_t VERSION; /*!< [0x0ffc] SCU RTL Design Version Register */ 1959 1960 } SCU_T; 1961 1962 /** 1963 @addtogroup SCU_CONST SCU Bit Field Definition 1964 Constant Definitions for SCU Controller 1965 @{ 1966 */ 1967 1968 #define SCU_PNSSET0_USBH_Pos (9) /*!< SCU_T::PNSSET0: USBH Position */ 1969 #define SCU_PNSSET0_USBH_Msk (0x1ul << SCU_PNSSET0_USBH_Pos) /*!< SCU_T::PNSSET0: USBH Mask */ 1970 1971 #define SCU_PNSSET0_SDH0_Pos (13) /*!< SCU_T::PNSSET0: SDH0 Position */ 1972 #define SCU_PNSSET0_SDH0_Msk (0x1ul << SCU_PNSSET0_SDH0_Pos) /*!< SCU_T::PNSSET0: SDH0 Mask */ 1973 1974 #define SCU_PNSSET0_EBI_Pos (16) /*!< SCU_T::PNSSET0: EBI Position */ 1975 #define SCU_PNSSET0_EBI_Msk (0x1ul << SCU_PNSSET0_EBI_Pos) /*!< SCU_T::PNSSET0: EBI Mask */ 1976 1977 #define SCU_PNSSET0_PDMA1_Pos (24) /*!< SCU_T::PNSSET0: PDMA1 Position */ 1978 #define SCU_PNSSET0_PDMA1_Msk (0x1ul << SCU_PNSSET0_PDMA1_Pos) /*!< SCU_T::PNSSET0: PDMA1 Mask */ 1979 1980 #define SCU_PNSSET1_CRC_Pos (17) /*!< SCU_T::PNSSET1: CRC Position */ 1981 #define SCU_PNSSET1_CRC_Msk (0x1ul << SCU_PNSSET1_CRC_Pos) /*!< SCU_T::PNSSET1: CRC Mask */ 1982 1983 #define SCU_PNSSET1_CRPT_Pos (18) /*!< SCU_T::PNSSET1: CRPT Position */ 1984 #define SCU_PNSSET1_CRPT_Msk (0x1ul << SCU_PNSSET1_CRPT_Pos) /*!< SCU_T::PNSSET1: CRPT Mask */ 1985 1986 #define SCU_PNSSET2_EWDT_Pos (2) /*!< SCU_T::PNSSET2: EWDT Position */ 1987 #define SCU_PNSSET2_EWDT_Msk (0x1ul << SCU_PNSSET2_EWDT_Pos) /*!< SCU_T::PNSSET2: EWDT Mask */ 1988 1989 #define SCU_PNSSET2_EADC_Pos (3) /*!< SCU_T::PNSSET2: EADC Position */ 1990 #define SCU_PNSSET2_EADC_Msk (0x1ul << SCU_PNSSET2_EADC_Pos) /*!< SCU_T::PNSSET2: EADC Mask */ 1991 1992 #define SCU_PNSSET2_ACMP01_Pos (5) /*!< SCU_T::PNSSET2: ACMP01 Position */ 1993 #define SCU_PNSSET2_ACMP01_Msk (0x1ul << SCU_PNSSET2_ACMP01_Pos) /*!< SCU_T::PNSSET2: ACMP01 Mask */ 1994 1995 #define SCU_PNSSET2_DAC_Pos (7) /*!< SCU_T::PNSSET2: DAC Position */ 1996 #define SCU_PNSSET2_DAC_Msk (0x1ul << SCU_PNSSET2_DAC_Pos) /*!< SCU_T::PNSSET2: DAC Mask */ 1997 1998 #define SCU_PNSSET2_I2S0_Pos (8) /*!< SCU_T::PNSSET2: I2S0 Position */ 1999 #define SCU_PNSSET2_I2S0_Msk (0x1ul << SCU_PNSSET2_I2S0_Pos) /*!< SCU_T::PNSSET2: I2S0 Mask */ 2000 2001 #define SCU_PNSSET2_OTG_Pos (13) /*!< SCU_T::PNSSET2: OTG Position */ 2002 #define SCU_PNSSET2_OTG_Msk (0x1ul << SCU_PNSSET2_OTG_Pos) /*!< SCU_T::PNSSET2: OTG Mask */ 2003 2004 #define SCU_PNSSET2_TMR23_Pos (17) /*!< SCU_T::PNSSET2: TMR23 Position */ 2005 #define SCU_PNSSET2_TMR23_Msk (0x1ul << SCU_PNSSET2_TMR23_Pos) /*!< SCU_T::PNSSET2: TMR23 Mask */ 2006 2007 #define SCU_PNSSET2_EPWM0_Pos (24) /*!< SCU_T::PNSSET2: EPWM0 Position */ 2008 #define SCU_PNSSET2_EPWM0_Msk (0x1ul << SCU_PNSSET2_EPWM0_Pos) /*!< SCU_T::PNSSET2: EPWM0 Mask */ 2009 2010 #define SCU_PNSSET2_EPWM1_Pos (25) /*!< SCU_T::PNSSET2: EPWM1 Position */ 2011 #define SCU_PNSSET2_EPWM1_Msk (0x1ul << SCU_PNSSET2_EPWM1_Pos) /*!< SCU_T::PNSSET2: EPWM1 Mask */ 2012 2013 #define SCU_PNSSET2_BPWM0_Pos (26) /*!< SCU_T::PNSSET2: BPWM0 Position */ 2014 #define SCU_PNSSET2_BPWM0_Msk (0x1ul << SCU_PNSSET2_BPWM0_Pos) /*!< SCU_T::PNSSET2: BPWM0 Mask */ 2015 2016 #define SCU_PNSSET2_BPWM1_Pos (27) /*!< SCU_T::PNSSET2: BPWM1 Position */ 2017 #define SCU_PNSSET2_BPWM1_Msk (0x1ul << SCU_PNSSET2_BPWM1_Pos) /*!< SCU_T::PNSSET2: BPWM1 Mask */ 2018 2019 #define SCU_PNSSET3_QSPI0_Pos (0) /*!< SCU_T::PNSSET3: QSPI0 Position */ 2020 #define SCU_PNSSET3_QSPI0_Msk (0x1ul << SCU_PNSSET3_QSPI0_Pos) /*!< SCU_T::PNSSET3: QSPI0 Mask */ 2021 2022 #define SCU_PNSSET3_SPI0_Pos (1) /*!< SCU_T::PNSSET3: SPI0 Position */ 2023 #define SCU_PNSSET3_SPI0_Msk (0x1ul << SCU_PNSSET3_SPI0_Pos) /*!< SCU_T::PNSSET3: SPI0 Mask */ 2024 2025 #define SCU_PNSSET3_SPI1_Pos (2) /*!< SCU_T::PNSSET3: SPI1 Position */ 2026 #define SCU_PNSSET3_SPI1_Msk (0x1ul << SCU_PNSSET3_SPI1_Pos) /*!< SCU_T::PNSSET3: SPI1 Mask */ 2027 2028 #define SCU_PNSSET3_SPI2_Pos (3) /*!< SCU_T::PNSSET3: SPI2 Position */ 2029 #define SCU_PNSSET3_SPI2_Msk (0x1ul << SCU_PNSSET3_SPI2_Pos) /*!< SCU_T::PNSSET3: SPI2 Mask */ 2030 2031 #define SCU_PNSSET3_SPI3_Pos (4) /*!< SCU_T::PNSSET3: SPI3 Position */ 2032 #define SCU_PNSSET3_SPI3_Msk (0x1ul << SCU_PNSSET3_SPI3_Pos) /*!< SCU_T::PNSSET3: SPI3 Mask */ 2033 2034 #define SCU_PNSSET3_UART0_Pos (16) /*!< SCU_T::PNSSET3: UART0 Position */ 2035 #define SCU_PNSSET3_UART0_Msk (0x1ul << SCU_PNSSET3_UART0_Pos) /*!< SCU_T::PNSSET3: UART0 Mask */ 2036 2037 #define SCU_PNSSET3_UART1_Pos (17) /*!< SCU_T::PNSSET3: UART1 Position */ 2038 #define SCU_PNSSET3_UART1_Msk (0x1ul << SCU_PNSSET3_UART1_Pos) /*!< SCU_T::PNSSET3: UART1 Mask */ 2039 2040 #define SCU_PNSSET3_UART2_Pos (18) /*!< SCU_T::PNSSET3: UART2 Position */ 2041 #define SCU_PNSSET3_UART2_Msk (0x1ul << SCU_PNSSET3_UART2_Pos) /*!< SCU_T::PNSSET3: UART2 Mask */ 2042 2043 #define SCU_PNSSET3_UART3_Pos (19) /*!< SCU_T::PNSSET3: UART3 Position */ 2044 #define SCU_PNSSET3_UART3_Msk (0x1ul << SCU_PNSSET3_UART3_Pos) /*!< SCU_T::PNSSET3: UART3 Mask */ 2045 2046 #define SCU_PNSSET3_UART4_Pos (20) /*!< SCU_T::PNSSET3: UART4 Position */ 2047 #define SCU_PNSSET3_UART4_Msk (0x1ul << SCU_PNSSET3_UART4_Pos) /*!< SCU_T::PNSSET3: UART4 Mask */ 2048 2049 #define SCU_PNSSET3_UART5_Pos (21) /*!< SCU_T::PNSSET3: UART5 Position */ 2050 #define SCU_PNSSET3_UART5_Msk (0x1ul << SCU_PNSSET3_UART5_Pos) /*!< SCU_T::PNSSET3: UART5 Mask */ 2051 2052 #define SCU_PNSSET4_I2C0_Pos (0) /*!< SCU_T::PNSSET4: I2C0 Position */ 2053 #define SCU_PNSSET4_I2C0_Msk (0x1ul << SCU_PNSSET4_I2C0_Pos) /*!< SCU_T::PNSSET4: I2C0 Mask */ 2054 2055 #define SCU_PNSSET4_I2C1_Pos (1) /*!< SCU_T::PNSSET4: I2C1 Position */ 2056 #define SCU_PNSSET4_I2C1_Msk (0x1ul << SCU_PNSSET4_I2C1_Pos) /*!< SCU_T::PNSSET4: I2C1 Mask */ 2057 2058 #define SCU_PNSSET4_I2C2_Pos (2) /*!< SCU_T::PNSSET4: I2C2 Position */ 2059 #define SCU_PNSSET4_I2C2_Msk (0x1ul << SCU_PNSSET4_I2C2_Pos) /*!< SCU_T::PNSSET4: I2C2 Mask */ 2060 2061 #define SCU_PNSSET4_SC0_Pos (16) /*!< SCU_T::PNSSET4: SC0 Position */ 2062 #define SCU_PNSSET4_SC0_Msk (0x1ul << SCU_PNSSET4_SC0_Pos) /*!< SCU_T::PNSSET4: SC0 Mask */ 2063 2064 #define SCU_PNSSET4_SC1_Pos (17) /*!< SCU_T::PNSSET4: SC1 Position */ 2065 #define SCU_PNSSET4_SC1_Msk (0x1ul << SCU_PNSSET4_SC1_Pos) /*!< SCU_T::PNSSET4: SC1 Mask */ 2066 2067 #define SCU_PNSSET4_SC2_Pos (18) /*!< SCU_T::PNSSET4: SC2 Position */ 2068 #define SCU_PNSSET4_SC2_Msk (0x1ul << SCU_PNSSET4_SC2_Pos) /*!< SCU_T::PNSSET4: SC2 Mask */ 2069 2070 #define SCU_PNSSET5_CAN0_Pos (0) /*!< SCU_T::PNSSET5: CAN0 Position */ 2071 #define SCU_PNSSET5_CAN0_Msk (0x1ul << SCU_PNSSET5_CAN0_Pos) /*!< SCU_T::PNSSET5: CAN0 Mask */ 2072 2073 #define SCU_PNSSET5_QEI0_Pos (16) /*!< SCU_T::PNSSET5: QEI0 Position */ 2074 #define SCU_PNSSET5_QEI0_Msk (0x1ul << SCU_PNSSET5_QEI0_Pos) /*!< SCU_T::PNSSET5: QEI0 Mask */ 2075 2076 #define SCU_PNSSET5_QEI1_Pos (17) /*!< SCU_T::PNSSET5: QEI1 Position */ 2077 #define SCU_PNSSET5_QEI1_Msk (0x1ul << SCU_PNSSET5_QEI1_Pos) /*!< SCU_T::PNSSET5: QEI1 Mask */ 2078 2079 #define SCU_PNSSET5_ECAP0_Pos (20) /*!< SCU_T::PNSSET5: ECAP0 Position */ 2080 #define SCU_PNSSET5_ECAP0_Msk (0x1ul << SCU_PNSSET5_ECAP0_Pos) /*!< SCU_T::PNSSET5: ECAP0 Mask */ 2081 2082 #define SCU_PNSSET5_ECAP1_Pos (21) /*!< SCU_T::PNSSET5: ECAP1 Position */ 2083 #define SCU_PNSSET5_ECAP1_Msk (0x1ul << SCU_PNSSET5_ECAP1_Pos) /*!< SCU_T::PNSSET5: ECAP1 Mask */ 2084 2085 #define SCU_PNSSET5_TRNG_Pos (25) /*!< SCU_T::PNSSET5: TRNG Position */ 2086 #define SCU_PNSSET5_TRNG_Msk (0x1ul << SCU_PNSSET5_TRNG_Pos) /*!< SCU_T::PNSSET5: TRNG Mask */ 2087 2088 #define SCU_PNSSET5_LCD_Pos (27) /*!< SCU_T::PNSSET5: LCD Position */ 2089 #define SCU_PNSSET5_LCD_Msk (0x1ul << SCU_PNSSET5_LCD_Pos) /*!< SCU_T::PNSSET5: LCD Mask */ 2090 2091 #define SCU_PNSSET6_USBD_Pos (0) /*!< SCU_T::PNSSET6: USBD Position */ 2092 #define SCU_PNSSET6_USBD_Msk (0x1ul << SCU_PNSSET6_USBD_Pos) /*!< SCU_T::PNSSET6: USBD Mask */ 2093 2094 #define SCU_PNSSET6_USCI0_Pos (16) /*!< SCU_T::PNSSET6: USCI0 Position */ 2095 #define SCU_PNSSET6_USCI0_Msk (0x1ul << SCU_PNSSET6_USCI0_Pos) /*!< SCU_T::PNSSET6: USCI0 Mask */ 2096 2097 #define SCU_PNSSET6_USCI1_Pos (17) /*!< SCU_T::PNSSET6: USCI1 Position */ 2098 #define SCU_PNSSET6_USCI1_Msk (0x1ul << SCU_PNSSET6_USCI1_Pos) /*!< SCU_T::PNSSET6: USCI1 Mask */ 2099 2100 #define SCU_IONSSET_PA_Pos (0) /*!< SCU_T::IONSSET: PA Position */ 2101 #define SCU_IONSSET_PA_Msk (0x1ul << SCU_IONSSET_PA_Pos) /*!< SCU_T::IONSSET: PA Mask */ 2102 2103 #define SCU_IONSSET_PB_Pos (1) /*!< SCU_T::IONSSET: PB Position */ 2104 #define SCU_IONSSET_PB_Msk (0x1ul << SCU_IONSSET_PB_Pos) /*!< SCU_T::IONSSET: PB Mask */ 2105 2106 #define SCU_IONSSET_PC_Pos (2) /*!< SCU_T::IONSSET: PC Position */ 2107 #define SCU_IONSSET_PC_Msk (0x1ul << SCU_IONSSET_PC_Pos) /*!< SCU_T::IONSSET: PC Mask */ 2108 2109 #define SCU_IONSSET_PD_Pos (3) /*!< SCU_T::IONSSET: PD Position */ 2110 #define SCU_IONSSET_PD_Msk (0x1ul << SCU_IONSSET_PD_Pos) /*!< SCU_T::IONSSET: PD Mask */ 2111 2112 #define SCU_IONSSET_PE_Pos (4) /*!< SCU_T::IONSSET: PE Position */ 2113 #define SCU_IONSSET_PE_Msk (0x1ul << SCU_IONSSET_PE_Pos) /*!< SCU_T::IONSSET: PE Mask */ 2114 2115 #define SCU_IONSSET_PF_Pos (5) /*!< SCU_T::IONSSET: PF Position */ 2116 #define SCU_IONSSET_PF_Msk (0x1ul << SCU_IONSSET_PF_Pos) /*!< SCU_T::IONSSET: PF Mask */ 2117 2118 #define SCU_IONSSET_PG_Pos (6) /*!< SCU_T::IONSSET: PG Position */ 2119 #define SCU_IONSSET_PG_Msk (0x1ul << SCU_IONSSET_PG_Pos) /*!< SCU_T::IONSSET: PG Mask */ 2120 2121 #define SCU_IONSSET_PH_Pos (7) /*!< SCU_T::IONSSET: PH Position */ 2122 #define SCU_IONSSET_PH_Msk (0x1ul << SCU_IONSSET_PH_Pos) /*!< SCU_T::IONSSET: PH Mask */ 2123 2124 #define SCU_SRAMNSSET_SECn_Pos (0) /*!< SCU_T::SRAMNSSET: SECn Position */ 2125 #define SCU_SRAMNSSET_SECn_Msk (0xffful << SCU_SRAMNSSET_SECn_Pos) /*!< SCU_T::SRAMNSSET: SECn Mask */ 2126 2127 #define SCU_FNSADDR_FNSADDR_Pos (0) /*!< SCU_T::FNSADDR: FNSADDR Position */ 2128 #define SCU_FNSADDR_FNSADDR_Msk (0xfffffffful << SCU_FNSADDR_FNSADDR_Pos) /*!< SCU_T::FNSADDR: FNSADDR Mask */ 2129 2130 #define SCU_SVIOIEN_APB0IEN_Pos (0) /*!< SCU_T::SVIOIEN: APB0IEN Position */ 2131 #define SCU_SVIOIEN_APB0IEN_Msk (0x1ul << SCU_SVIOIEN_APB0IEN_Pos) /*!< SCU_T::SVIOIEN: APB0IEN Mask */ 2132 2133 #define SCU_SVIOIEN_APB1IEN_Pos (1) /*!< SCU_T::SVIOIEN: APB1IEN Position */ 2134 #define SCU_SVIOIEN_APB1IEN_Msk (0x1ul << SCU_SVIOIEN_APB1IEN_Pos) /*!< SCU_T::SVIOIEN: APB1IEN Mask */ 2135 2136 #define SCU_SVIOIEN_GPIOIEN_Pos (4) /*!< SCU_T::SVIOIEN: GPIOIEN Position */ 2137 #define SCU_SVIOIEN_GPIOIEN_Msk (0x1ul << SCU_SVIOIEN_GPIOIEN_Pos) /*!< SCU_T::SVIOIEN: GPIOIEN Mask */ 2138 2139 #define SCU_SVIOIEN_EBIIEN_Pos (5) /*!< SCU_T::SVIOIEN: EBIIEN Position */ 2140 #define SCU_SVIOIEN_EBIIEN_Msk (0x1ul << SCU_SVIOIEN_EBIIEN_Pos) /*!< SCU_T::SVIOIEN: EBIIEN Mask */ 2141 2142 #define SCU_SVIOIEN_USBHIEN_Pos (6) /*!< SCU_T::SVIOIEN: USBHIEN Position */ 2143 #define SCU_SVIOIEN_USBHIEN_Msk (0x1ul << SCU_SVIOIEN_USBHIEN_Pos) /*!< SCU_T::SVIOIEN: USBHIEN Mask */ 2144 2145 #define SCU_SVIOIEN_CRCIEN_Pos (7) /*!< SCU_T::SVIOIEN: CRCIEN Position */ 2146 #define SCU_SVIOIEN_CRCIEN_Msk (0x1ul << SCU_SVIOIEN_CRCIEN_Pos) /*!< SCU_T::SVIOIEN: CRCIEN Mask */ 2147 2148 #define SCU_SVIOIEN_SDH0IEN_Pos (8) /*!< SCU_T::SVIOIEN: SDH0IEN Position */ 2149 #define SCU_SVIOIEN_SDH0IEN_Msk (0x1ul << SCU_SVIOIEN_SDH0IEN_Pos) /*!< SCU_T::SVIOIEN: SDH0IEN Mask */ 2150 2151 #define SCU_SVIOIEN_PDMA0IEN_Pos (10) /*!< SCU_T::SVIOIEN: PDMA0IEN Position */ 2152 #define SCU_SVIOIEN_PDMA0IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA0IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA0IEN Mask */ 2153 2154 #define SCU_SVIOIEN_PDMA1IEN_Pos (11) /*!< SCU_T::SVIOIEN: PDMA1IEN Position */ 2155 #define SCU_SVIOIEN_PDMA1IEN_Msk (0x1ul << SCU_SVIOIEN_PDMA1IEN_Pos) /*!< SCU_T::SVIOIEN: PDMA1IEN Mask */ 2156 2157 #define SCU_SVIOIEN_SRAM0IEN_Pos (12) /*!< SCU_T::SVIOIEN: SRAM0IEN Position */ 2158 #define SCU_SVIOIEN_SRAM0IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM0IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM0IEN Mask */ 2159 2160 #define SCU_SVIOIEN_SRAM1IEN_Pos (13) /*!< SCU_T::SVIOIEN: SRAM1IEN Position */ 2161 #define SCU_SVIOIEN_SRAM1IEN_Msk (0x1ul << SCU_SVIOIEN_SRAM1IEN_Pos) /*!< SCU_T::SVIOIEN: SRAM1IEN Mask */ 2162 2163 #define SCU_SVIOIEN_FMCIEN_Pos (14) /*!< SCU_T::SVIOIEN: FMCIEN Position */ 2164 #define SCU_SVIOIEN_FMCIEN_Msk (0x1ul << SCU_SVIOIEN_FMCIEN_Pos) /*!< SCU_T::SVIOIEN: FMCIEN Mask */ 2165 2166 #define SCU_SVIOIEN_FLASHIEN_Pos (15) /*!< SCU_T::SVIOIEN: FLASHIEN Position */ 2167 #define SCU_SVIOIEN_FLASHIEN_Msk (0x1ul << SCU_SVIOIEN_FLASHIEN_Pos) /*!< SCU_T::SVIOIEN: FLASHIEN Mask */ 2168 2169 #define SCU_SVIOIEN_SCUIEN_Pos (16) /*!< SCU_T::SVIOIEN: SCUIEN Position */ 2170 #define SCU_SVIOIEN_SCUIEN_Msk (0x1ul << SCU_SVIOIEN_SCUIEN_Pos) /*!< SCU_T::SVIOIEN: SCUIEN Mask */ 2171 2172 #define SCU_SVIOIEN_SYSIEN_Pos (17) /*!< SCU_T::SVIOIEN: SYSIEN Position */ 2173 #define SCU_SVIOIEN_SYSIEN_Msk (0x1ul << SCU_SVIOIEN_SYSIEN_Pos) /*!< SCU_T::SVIOIEN: SYSIEN Mask */ 2174 2175 #define SCU_SVIOIEN_CRPTIEN_Pos (18) /*!< SCU_T::SVIOIEN: CRPTIEN Position */ 2176 #define SCU_SVIOIEN_CRPTIEN_Msk (0x1ul << SCU_SVIOIEN_CRPTIEN_Pos) /*!< SCU_T::SVIOIEN: CRPTIEN Mask */ 2177 2178 #define SCU_SVIOIEN_KSIEN_Pos (19) /*!< SCU_T::SVIOIEN: KSIEN Position */ 2179 #define SCU_SVIOIEN_KSIEN_Msk (0x1ul << SCU_SVIOIEN_KSIEN_Pos) /*!< SCU_T::SVIOIEN: KSIEN Mask */ 2180 2181 #define SCU_SVINTSTS_APB0IF_Pos (0) /*!< SCU_T::SVINTSTS: APB0IF Position */ 2182 #define SCU_SVINTSTS_APB0IF_Msk (0x1ul << SCU_SVINTSTS_APB0IF_Pos) /*!< SCU_T::SVINTSTS: APB0IF Mask */ 2183 2184 #define SCU_SVINTSTS_APB1IF_Pos (1) /*!< SCU_T::SVINTSTS: APB1IF Position */ 2185 #define SCU_SVINTSTS_APB1IF_Msk (0x1ul << SCU_SVINTSTS_APB1IF_Pos) /*!< SCU_T::SVINTSTS: APB1IF Mask */ 2186 2187 #define SCU_SVINTSTS_GPIOIF_Pos (4) /*!< SCU_T::SVINTSTS: GPIOIF Position */ 2188 #define SCU_SVINTSTS_GPIOIF_Msk (0x1ul << SCU_SVINTSTS_GPIOIF_Pos) /*!< SCU_T::SVINTSTS: GPIOIF Mask */ 2189 2190 #define SCU_SVINTSTS_EBIIF_Pos (5) /*!< SCU_T::SVINTSTS: EBIIF Position */ 2191 #define SCU_SVINTSTS_EBIIF_Msk (0x1ul << SCU_SVINTSTS_EBIIF_Pos) /*!< SCU_T::SVINTSTS: EBIIF Mask */ 2192 2193 #define SCU_SVINTSTS_USBHIF_Pos (6) /*!< SCU_T::SVINTSTS: USBHIF Position */ 2194 #define SCU_SVINTSTS_USBHIF_Msk (0x1ul << SCU_SVINTSTS_USBHIF_Pos) /*!< SCU_T::SVINTSTS: USBHIF Mask */ 2195 2196 #define SCU_SVINTSTS_CRCIF_Pos (7) /*!< SCU_T::SVINTSTS: CRCIF Position */ 2197 #define SCU_SVINTSTS_CRCIF_Msk (0x1ul << SCU_SVINTSTS_CRCIF_Pos) /*!< SCU_T::SVINTSTS: CRCIF Mask */ 2198 2199 #define SCU_SVINTSTS_SDH0IF_Pos (8) /*!< SCU_T::SVINTSTS: SDH0IF Position */ 2200 #define SCU_SVINTSTS_SDH0IF_Msk (0x1ul << SCU_SVINTSTS_SDH0IF_Pos) /*!< SCU_T::SVINTSTS: SDH0IF Mask */ 2201 2202 #define SCU_SVINTSTS_PDMA0IF_Pos (10) /*!< SCU_T::SVINTSTS: PDMA0IF Position */ 2203 #define SCU_SVINTSTS_PDMA0IF_Msk (0x1ul << SCU_SVINTSTS_PDMA0IF_Pos) /*!< SCU_T::SVINTSTS: PDMA0IF Mask */ 2204 2205 #define SCU_SVINTSTS_PDMA1IF_Pos (11) /*!< SCU_T::SVINTSTS: PDMA1IF Position */ 2206 #define SCU_SVINTSTS_PDMA1IF_Msk (0x1ul << SCU_SVINTSTS_PDMA1IF_Pos) /*!< SCU_T::SVINTSTS: PDMA1IF Mask */ 2207 2208 #define SCU_SVINTSTS_SRAM0IF_Pos (12) /*!< SCU_T::SVINTSTS: SRAM0IF Position */ 2209 #define SCU_SVINTSTS_SRAM0IF_Msk (0x1ul << SCU_SVINTSTS_SRAM0IF_Pos) /*!< SCU_T::SVINTSTS: SRAM0IF Mask */ 2210 2211 #define SCU_SVINTSTS_SRAM1IF_Pos (13) /*!< SCU_T::SVINTSTS: SRAM1IF Position */ 2212 #define SCU_SVINTSTS_SRAM1IF_Msk (0x1ul << SCU_SVINTSTS_SRAM1IF_Pos) /*!< SCU_T::SVINTSTS: SRAM1IF Mask */ 2213 2214 #define SCU_SVINTSTS_FMCIF_Pos (14) /*!< SCU_T::SVINTSTS: FMCIF Position */ 2215 #define SCU_SVINTSTS_FMCIF_Msk (0x1ul << SCU_SVINTSTS_FMCIF_Pos) /*!< SCU_T::SVINTSTS: FMCIF Mask */ 2216 2217 #define SCU_SVINTSTS_FLASHIF_Pos (15) /*!< SCU_T::SVINTSTS: FLASHIF Position */ 2218 #define SCU_SVINTSTS_FLASHIF_Msk (0x1ul << SCU_SVINTSTS_FLASHIF_Pos) /*!< SCU_T::SVINTSTS: FLASHIF Mask */ 2219 2220 #define SCU_SVINTSTS_SCUIF_Pos (16) /*!< SCU_T::SVINTSTS: SCUIF Position */ 2221 #define SCU_SVINTSTS_SCUIF_Msk (0x1ul << SCU_SVINTSTS_SCUIF_Pos) /*!< SCU_T::SVINTSTS: SCUIF Mask */ 2222 2223 #define SCU_SVINTSTS_SYSIF_Pos (17) /*!< SCU_T::SVINTSTS: SYSIF Position */ 2224 #define SCU_SVINTSTS_SYSIF_Msk (0x1ul << SCU_SVINTSTS_SYSIF_Pos) /*!< SCU_T::SVINTSTS: SYSIF Mask */ 2225 2226 #define SCU_SVINTSTS_CRPTIF_Pos (18) /*!< SCU_T::SVINTSTS: CRPTIF Position */ 2227 #define SCU_SVINTSTS_CRPTIF_Msk (0x1ul << SCU_SVINTSTS_CRPTIF_Pos) /*!< SCU_T::SVINTSTS: CRPTIF Mask */ 2228 2229 #define SCU_SVINTSTS_KSIF_Pos (19) /*!< SCU_T::SVINTSTS: KSIF Position */ 2230 #define SCU_SVINTSTS_KSIF_Msk (0x1ul << SCU_SVINTSTS_KSIF_Pos) /*!< SCU_T::SVINTSTS: KSIF Mask */ 2231 2232 #define SCU_APB0VSRC_MASTER_Pos (0) /*!< SCU_T::APB0VSRC: MASTER Position */ 2233 #define SCU_APB0VSRC_MASTER_Msk (0xful << SCU_APB0VSRC_MASTER_Pos) /*!< SCU_T::APB0VSRC: MASTER Mask */ 2234 2235 #define SCU_APB0VA_VIOADDR_Pos (0) /*!< SCU_T::APB0VA: VIOADDR Position */ 2236 #define SCU_APB0VA_VIOADDR_Msk (0xfffffffful << SCU_APB0VA_VIOADDR_Pos) /*!< SCU_T::APB0VA: VIOADDR Mask */ 2237 2238 #define SCU_APB1VSRC_MASTER_Pos (0) /*!< SCU_T::APB1VSRC: MASTER Position */ 2239 #define SCU_APB1VSRC_MASTER_Msk (0xful << SCU_APB1VSRC_MASTER_Pos) /*!< SCU_T::APB1VSRC: MASTER Mask */ 2240 2241 #define SCU_APB1VA_VIOADDR_Pos (0) /*!< SCU_T::APB1VA: VIOADDR Position */ 2242 #define SCU_APB1VA_VIOADDR_Msk (0xfffffffful << SCU_APB1VA_VIOADDR_Pos) /*!< SCU_T::APB1VA: VIOADDR Mask */ 2243 2244 #define SCU_GPIOVSRC_MASTER_Pos (0) /*!< SCU_T::GPIOVSRC: MASTER Position */ 2245 #define SCU_GPIOVSRC_MASTER_Msk (0xful << SCU_GPIOVSRC_MASTER_Pos) /*!< SCU_T::GPIOVSRC: MASTER Mask */ 2246 2247 #define SCU_GPIOVA_VIOADDR_Pos (0) /*!< SCU_T::GPIOVA: VIOADDR Position */ 2248 #define SCU_GPIOVA_VIOADDR_Msk (0xfffffffful << SCU_GPIOVA_VIOADDR_Pos) /*!< SCU_T::GPIOVA: VIOADDR Mask */ 2249 2250 #define SCU_EBIVSRC_MASTER_Pos (0) /*!< SCU_T::EBIVSRC: MASTER Position */ 2251 #define SCU_EBIVSRC_MASTER_Msk (0xful << SCU_EBIVSRC_MASTER_Pos) /*!< SCU_T::EBIVSRC: MASTER Mask */ 2252 2253 #define SCU_EBIVA_VIOADDR_Pos (0) /*!< SCU_T::EBIVA: VIOADDR Position */ 2254 #define SCU_EBIVA_VIOADDR_Msk (0xfffffffful << SCU_EBIVA_VIOADDR_Pos) /*!< SCU_T::EBIVA: VIOADDR Mask */ 2255 2256 #define SCU_USBHVSRC_MASTER_Pos (0) /*!< SCU_T::USBHVSRC: MASTER Position */ 2257 #define SCU_USBHVSRC_MASTER_Msk (0xful << SCU_USBHVSRC_MASTER_Pos) /*!< SCU_T::USBHVSRC: MASTER Mask */ 2258 2259 #define SCU_USBHVA_VIOADDR_Pos (0) /*!< SCU_T::USBHVA: VIOADDR Position */ 2260 #define SCU_USBHVA_VIOADDR_Msk (0xfffffffful << SCU_USBHVA_VIOADDR_Pos) /*!< SCU_T::USBHVA: VIOADDR Mask */ 2261 2262 #define SCU_CRCVSRC_MASTER_Pos (0) /*!< SCU_T::CRCVSRC: MASTER Position */ 2263 #define SCU_CRCVSRC_MASTER_Msk (0xful << SCU_CRCVSRC_MASTER_Pos) /*!< SCU_T::CRCVSRC: MASTER Mask */ 2264 2265 #define SCU_CRCVA_VIOADDR_Pos (0) /*!< SCU_T::CRCVA: VIOADDR Position */ 2266 #define SCU_CRCVA_VIOADDR_Msk (0xfffffffful << SCU_CRCVA_VIOADDR_Pos) /*!< SCU_T::CRCVA: VIOADDR Mask */ 2267 2268 #define SCU_SD0VSRC_MASTER_Pos (0) /*!< SCU_T::SD0VSRC: MASTER Position */ 2269 #define SCU_SD0VSRC_MASTER_Msk (0xful << SCU_SD0VSRC_MASTER_Pos) /*!< SCU_T::SD0VSRC: MASTER Mask */ 2270 2271 #define SCU_SD0VA_VIOADDR_Pos (0) /*!< SCU_T::SD0VA: VIOADDR Position */ 2272 #define SCU_SD0VA_VIOADDR_Msk (0xfffffffful << SCU_SD0VA_VIOADDR_Pos) /*!< SCU_T::SD0VA: VIOADDR Mask */ 2273 2274 #define SCU_PDMA0VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA0VSRC: MASTER Position */ 2275 #define SCU_PDMA0VSRC_MASTER_Msk (0xful << SCU_PDMA0VSRC_MASTER_Pos) /*!< SCU_T::PDMA0VSRC: MASTER Mask */ 2276 2277 #define SCU_PDMA0VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA0VA: VIOADDR Position */ 2278 #define SCU_PDMA0VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA0VA_VIOADDR_Pos) /*!< SCU_T::PDMA0VA: VIOADDR Mask */ 2279 2280 #define SCU_PDMA1VSRC_MASTER_Pos (0) /*!< SCU_T::PDMA1VSRC: MASTER Position */ 2281 #define SCU_PDMA1VSRC_MASTER_Msk (0xful << SCU_PDMA1VSRC_MASTER_Pos) /*!< SCU_T::PDMA1VSRC: MASTER Mask */ 2282 2283 #define SCU_PDMA1VA_VIOADDR_Pos (0) /*!< SCU_T::PDMA1VA: VIOADDR Position */ 2284 #define SCU_PDMA1VA_VIOADDR_Msk (0xfffffffful << SCU_PDMA1VA_VIOADDR_Pos) /*!< SCU_T::PDMA1VA: VIOADDR Mask */ 2285 2286 #define SCU_SRAM0VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM0VSRC: MASTER Position */ 2287 #define SCU_SRAM0VSRC_MASTER_Msk (0xful << SCU_SRAM0VSRC_MASTER_Pos) /*!< SCU_T::SRAM0VSRC: MASTER Mask */ 2288 2289 #define SCU_SRAM0VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM0VA: VIOADDR Position */ 2290 #define SCU_SRAM0VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM0VA_VIOADDR_Pos) /*!< SCU_T::SRAM0VA: VIOADDR Mask */ 2291 2292 #define SCU_SRAM1VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM1VSRC: MASTER Position */ 2293 #define SCU_SRAM1VSRC_MASTER_Msk (0xful << SCU_SRAM1VSRC_MASTER_Pos) /*!< SCU_T::SRAM1VSRC: MASTER Mask */ 2294 2295 #define SCU_SRAM1VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM1VA: VIOADDR Position */ 2296 #define SCU_SRAM1VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM1VA_VIOADDR_Pos) /*!< SCU_T::SRAM1VA: VIOADDR Mask */ 2297 2298 #define SCU_FMCVSRC_MASTER_Pos (0) /*!< SCU_T::FMCVSRC: MASTER Position */ 2299 #define SCU_FMCVSRC_MASTER_Msk (0xful << SCU_FMCVSRC_MASTER_Pos) /*!< SCU_T::FMCVSRC: MASTER Mask */ 2300 2301 #define SCU_FMCVA_VIOADDR_Pos (0) /*!< SCU_T::FMCVA: VIOADDR Position */ 2302 #define SCU_FMCVA_VIOADDR_Msk (0xfffffffful << SCU_FMCVA_VIOADDR_Pos) /*!< SCU_T::FMCVA: VIOADDR Mask */ 2303 2304 #define SCU_FLASHVSRC_MASTER_Pos (0) /*!< SCU_T::FLASHVSRC: MASTER Position */ 2305 #define SCU_FLASHVSRC_MASTER_Msk (0xful << SCU_FLASHVSRC_MASTER_Pos) /*!< SCU_T::FLASHVSRC: MASTER Mask */ 2306 2307 #define SCU_FLASHVA_VIOADDR_Pos (0) /*!< SCU_T::FLASHVA: VIOADDR Position */ 2308 #define SCU_FLASHVA_VIOADDR_Msk (0xfffffffful << SCU_FLASHVA_VIOADDR_Pos) /*!< SCU_T::FLASHVA: VIOADDR Mask */ 2309 2310 #define SCU_SCUVSRC_MASTER_Pos (0) /*!< SCU_T::SCUVSRC: MASTER Position */ 2311 #define SCU_SCUVSRC_MASTER_Msk (0xful << SCU_SCUVSRC_MASTER_Pos) /*!< SCU_T::SCUVSRC: MASTER Mask */ 2312 2313 #define SCU_SCUVA_VIOADDR_Pos (0) /*!< SCU_T::SCUVA: VIOADDR Position */ 2314 #define SCU_SCUVA_VIOADDR_Msk (0xfffffffful << SCU_SCUVA_VIOADDR_Pos) /*!< SCU_T::SCUVA: VIOADDR Mask */ 2315 2316 #define SCU_SYSVSRC_MASTER_Pos (0) /*!< SCU_T::SYSVSRC: MASTER Position */ 2317 #define SCU_SYSVSRC_MASTER_Msk (0xful << SCU_SYSVSRC_MASTER_Pos) /*!< SCU_T::SYSVSRC: MASTER Mask */ 2318 2319 #define SCU_SYSVA_VIOADDR_Pos (0) /*!< SCU_T::SYSVA: VIOADDR Position */ 2320 #define SCU_SYSVA_VIOADDR_Msk (0xfffffffful << SCU_SYSVA_VIOADDR_Pos) /*!< SCU_T::SYSVA: VIOADDR Mask */ 2321 2322 #define SCU_CRPTVSRC_MASTER_Pos (0) /*!< SCU_T::CRPTVSRC: MASTER Position */ 2323 #define SCU_CRPTVSRC_MASTER_Msk (0xful << SCU_CRPTVSRC_MASTER_Pos) /*!< SCU_T::CRPTVSRC: MASTER Mask */ 2324 2325 #define SCU_CRPTVA_VIOADDR_Pos (0) /*!< SCU_T::CRPTVA: VIOADDR Position */ 2326 #define SCU_CRPTVA_VIOADDR_Msk (0xfffffffful << SCU_CRPTVA_VIOADDR_Pos) /*!< SCU_T::CRPTVA: VIOADDR Mask */ 2327 2328 #define SCU_KSVSRC_MASTER_Pos (0) /*!< SCU_T::KSVSRC: MASTER Position */ 2329 #define SCU_KSVSRC_MASTER_Msk (0xful << SCU_KSVSRC_MASTER_Pos) /*!< SCU_T::KSVSRC: MASTER Mask */ 2330 2331 #define SCU_KSVA_VIOADDR_Pos (0) /*!< SCU_T::KSVA: VIOADDR Position */ 2332 #define SCU_KSVA_VIOADDR_Msk (0xfffffffful << SCU_KSVA_VIOADDR_Pos) /*!< SCU_T::KSVA: VIOADDR Mask */ 2333 2334 #define SCU_SRAM2VSRC_MASTER_Pos (0) /*!< SCU_T::SRAM2VSRC: MASTER Position */ 2335 #define SCU_SRAM2VSRC_MASTER_Msk (0xful << SCU_SRAM2VSRC_MASTER_Pos) /*!< SCU_T::SRAM2VSRC: MASTER Mask */ 2336 2337 #define SCU_SRAM2VA_VIOADDR_Pos (0) /*!< SCU_T::SRAM2VA: VIOADDR Position */ 2338 #define SCU_SRAM2VA_VIOADDR_Msk (0xfffffffful << SCU_SRAM2VA_VIOADDR_Pos) /*!< SCU_T::SRAM2VA: VIOADDR Mask */ 2339 2340 #define SCU_SINFAEN_SCUSIAEN_Pos (0) /*!< SCU_T::SINFAEN: SCUSIAEN Position */ 2341 #define SCU_SINFAEN_SCUSIAEN_Msk (0x1ul << SCU_SINFAEN_SCUSIAEN_Pos) /*!< SCU_T::SINFAEN: SCUSIAEN Mask */ 2342 2343 #define SCU_SINFAEN_SYSSIAEN_Pos (1) /*!< SCU_T::SINFAEN: SYSSIAEN Position */ 2344 #define SCU_SINFAEN_SYSSIAEN_Msk (0x1ul << SCU_SINFAEN_SYSSIAEN_Pos) /*!< SCU_T::SINFAEN: SYSSIAEN Mask */ 2345 2346 #define SCU_SINFAEN_FMCSIAEN_Pos (2) /*!< SCU_T::SINFAEN: FMCSIAEN Position */ 2347 #define SCU_SINFAEN_FMCSIAEN_Msk (0x1ul << SCU_SINFAEN_FMCSIAEN_Pos) /*!< SCU_T::SINFAEN: FMCSIAEN Mask */ 2348 2349 #define SCU_PNPSET0_SYS_Pos (0) /*!< SCU_T::PNPSET0: SYS Position */ 2350 #define SCU_PNPSET0_SYS_Msk (0x1ul << SCU_PNPSET0_SYS_Pos) /*!< SCU_T::PNPSET0: SYS Mask */ 2351 2352 #define SCU_PNPSET0_PDMA0_Pos (8) /*!< SCU_T::PNPSET0: PDMA0 Position */ 2353 #define SCU_PNPSET0_PDMA0_Msk (0x1ul << SCU_PNPSET0_PDMA0_Pos) /*!< SCU_T::PNPSET0: PDMA0 Mask */ 2354 2355 #define SCU_PNPSET0_USBH_Pos (9) /*!< SCU_T::PNPSET0: USBH Position */ 2356 #define SCU_PNPSET0_USBH_Msk (0x1ul << SCU_PNPSET0_USBH_Pos) /*!< SCU_T::PNPSET0: USBH Mask */ 2357 2358 #define SCU_PNPSET0_FMC_Pos (12) /*!< SCU_T::PNPSET0: FMC Position */ 2359 #define SCU_PNPSET0_FMC_Msk (0x1ul << SCU_PNPSET0_FMC_Pos) /*!< SCU_T::PNPSET0: FMC Mask */ 2360 2361 #define SCU_PNPSET0_SDH0_Pos (13) /*!< SCU_T::PNPSET0: SDH0 Position */ 2362 #define SCU_PNPSET0_SDH0_Msk (0x1ul << SCU_PNPSET0_SDH0_Pos) /*!< SCU_T::PNPSET0: SDH0 Mask */ 2363 2364 #define SCU_PNPSET0_EBI_Pos (16) /*!< SCU_T::PNPSET0: EBI Position */ 2365 #define SCU_PNPSET0_EBI_Msk (0x1ul << SCU_PNPSET0_EBI_Pos) /*!< SCU_T::PNPSET0: EBI Mask */ 2366 2367 #define SCU_PNPSET0_PDMA1_Pos (24) /*!< SCU_T::PNPSET0: PDMA1 Position */ 2368 #define SCU_PNPSET0_PDMA1_Msk (0x1ul << SCU_PNPSET0_PDMA1_Pos) /*!< SCU_T::PNPSET0: PDMA1 Mask */ 2369 2370 #define SCU_PNPSET1_SCU_Pos (15) /*!< SCU_T::PNPSET1: SCU Position */ 2371 #define SCU_PNPSET1_SCU_Msk (0x1ul << SCU_PNPSET1_SCU_Pos) /*!< SCU_T::PNPSET1: SCU Mask */ 2372 2373 #define SCU_PNPSET1_CRC_Pos (17) /*!< SCU_T::PNPSET1: CRC Position */ 2374 #define SCU_PNPSET1_CRC_Msk (0x1ul << SCU_PNPSET1_CRC_Pos) /*!< SCU_T::PNPSET1: CRC Mask */ 2375 2376 #define SCU_PNPSET1_CRPT_Pos (18) /*!< SCU_T::PNPSET1: CRPT Position */ 2377 #define SCU_PNPSET1_CRPT_Msk (0x1ul << SCU_PNPSET1_CRPT_Pos) /*!< SCU_T::PNPSET1: CRPT Mask */ 2378 2379 #define SCU_PNPSET1_KS_Pos (21) /*!< SCU_T::PNPSET1: KS Position */ 2380 #define SCU_PNPSET1_KS_Msk (0x1ul << SCU_PNPSET1_KS_Pos) /*!< SCU_T::PNPSET1: KS Mask */ 2381 2382 #define SCU_PNPSET2_WDT_Pos (0) /*!< SCU_T::PNPSET2: WDT Position */ 2383 #define SCU_PNPSET2_WDT_Msk (0x1ul << SCU_PNPSET2_WDT_Pos) /*!< SCU_T::PNPSET2: WDT Mask */ 2384 2385 #define SCU_PNPSET2_RTC_Pos (1) /*!< SCU_T::PNPSET2: RTC Position */ 2386 #define SCU_PNPSET2_RTC_Msk (0x1ul << SCU_PNPSET2_RTC_Pos) /*!< SCU_T::PNPSET2: RTC Mask */ 2387 2388 #define SCU_PNPSET2_EWDT_Pos (2) /*!< SCU_T::PNPSET2: EWDT Position */ 2389 #define SCU_PNPSET2_EWDT_Msk (0x1ul << SCU_PNPSET2_EWDT_Pos) /*!< SCU_T::PNPSET2: EWDT Mask */ 2390 2391 #define SCU_PNPSET2_EADC_Pos (3) /*!< SCU_T::PNPSET2: EADC Position */ 2392 #define SCU_PNPSET2_EADC_Msk (0x1ul << SCU_PNPSET2_EADC_Pos) /*!< SCU_T::PNPSET2: EADC Mask */ 2393 2394 #define SCU_PNPSET2_ACMP01_Pos (5) /*!< SCU_T::PNPSET2: ACMP01 Position */ 2395 #define SCU_PNPSET2_ACMP01_Msk (0x1ul << SCU_PNPSET2_ACMP01_Pos) /*!< SCU_T::PNPSET2: ACMP01 Mask */ 2396 2397 #define SCU_PNPSET2_DAC_Pos (7) /*!< SCU_T::PNPSET2: DAC Position */ 2398 #define SCU_PNPSET2_DAC_Msk (0x1ul << SCU_PNPSET2_DAC_Pos) /*!< SCU_T::PNPSET2: DAC Mask */ 2399 2400 #define SCU_PNPSET2_I2S0_Pos (8) /*!< SCU_T::PNPSET2: I2S0 Position */ 2401 #define SCU_PNPSET2_I2S0_Msk (0x1ul << SCU_PNPSET2_I2S0_Pos) /*!< SCU_T::PNPSET2: I2S0 Mask */ 2402 2403 #define SCU_PNPSET2_OTG_Pos (13) /*!< SCU_T::PNPSET2: OTG Position */ 2404 #define SCU_PNPSET2_OTG_Msk (0x1ul << SCU_PNPSET2_OTG_Pos) /*!< SCU_T::PNPSET2: OTG Mask */ 2405 2406 #define SCU_PNPSET2_TMR01_Pos (14) /*!< SCU_T::PNPSET2: TMR01 Position */ 2407 #define SCU_PNPSET2_TMR01_Msk (0x7ul << SCU_PNPSET2_TMR01_Pos) /*!< SCU_T::PNPSET2: TMR01 Mask */ 2408 2409 #define SCU_PNPSET2_TMR23_Pos (17) /*!< SCU_T::PNPSET2: TMR23 Position */ 2410 #define SCU_PNPSET2_TMR23_Msk (0x1ul << SCU_PNPSET2_TMR23_Pos) /*!< SCU_T::PNPSET2: TMR23 Mask */ 2411 2412 #define SCU_PNPSET2_EPWM0_Pos (24) /*!< SCU_T::PNPSET2: EPWM0 Position */ 2413 #define SCU_PNPSET2_EPWM0_Msk (0x1ul << SCU_PNPSET2_EPWM0_Pos) /*!< SCU_T::PNPSET2: EPWM0 Mask */ 2414 2415 #define SCU_PNPSET2_EPWM1_Pos (25) /*!< SCU_T::PNPSET2: EPWM1 Position */ 2416 #define SCU_PNPSET2_EPWM1_Msk (0x1ul << SCU_PNPSET2_EPWM1_Pos) /*!< SCU_T::PNPSET2: EPWM1 Mask */ 2417 2418 #define SCU_PNPSET2_BPWM0_Pos (26) /*!< SCU_T::PNPSET2: BPWM0 Position */ 2419 #define SCU_PNPSET2_BPWM0_Msk (0x1ul << SCU_PNPSET2_BPWM0_Pos) /*!< SCU_T::PNPSET2: BPWM0 Mask */ 2420 2421 #define SCU_PNPSET2_BPWM1_Pos (27) /*!< SCU_T::PNPSET2: BPWM1 Position */ 2422 #define SCU_PNPSET2_BPWM1_Msk (0x1ul << SCU_PNPSET2_BPWM1_Pos) /*!< SCU_T::PNPSET2: BPWM1 Mask */ 2423 2424 #define SCU_PNPSET3_QSPI0_Pos (0) /*!< SCU_T::PNPSET3: QSPI0 Position */ 2425 #define SCU_PNPSET3_QSPI0_Msk (0x1ul << SCU_PNPSET3_QSPI0_Pos) /*!< SCU_T::PNPSET3: QSPI0 Mask */ 2426 2427 #define SCU_PNPSET3_SPI0_Pos (1) /*!< SCU_T::PNPSET3: SPI0 Position */ 2428 #define SCU_PNPSET3_SPI0_Msk (0x1ul << SCU_PNPSET3_SPI0_Pos) /*!< SCU_T::PNPSET3: SPI0 Mask */ 2429 2430 #define SCU_PNPSET3_SPI1_Pos (2) /*!< SCU_T::PNPSET3: SPI1 Position */ 2431 #define SCU_PNPSET3_SPI1_Msk (0x1ul << SCU_PNPSET3_SPI1_Pos) /*!< SCU_T::PNPSET3: SPI1 Mask */ 2432 2433 #define SCU_PNPSET3_SPI2_Pos (3) /*!< SCU_T::PNPSET3: SPI2 Position */ 2434 #define SCU_PNPSET3_SPI2_Msk (0x1ul << SCU_PNPSET3_SPI2_Pos) /*!< SCU_T::PNPSET3: SPI2 Mask */ 2435 2436 #define SCU_PNPSET3_SPI3_Pos (4) /*!< SCU_T::PNPSET3: SPI3 Position */ 2437 #define SCU_PNPSET3_SPI3_Msk (0x1ul << SCU_PNPSET3_SPI3_Pos) /*!< SCU_T::PNPSET3: SPI3 Mask */ 2438 2439 #define SCU_PNPSET3_UART0_Pos (16) /*!< SCU_T::PNPSET3: UART0 Position */ 2440 #define SCU_PNPSET3_UART0_Msk (0x1ul << SCU_PNPSET3_UART0_Pos) /*!< SCU_T::PNPSET3: UART0 Mask */ 2441 2442 #define SCU_PNPSET3_UART1_Pos (17) /*!< SCU_T::PNPSET3: UART1 Position */ 2443 #define SCU_PNPSET3_UART1_Msk (0x1ul << SCU_PNPSET3_UART1_Pos) /*!< SCU_T::PNPSET3: UART1 Mask */ 2444 2445 #define SCU_PNPSET3_UART2_Pos (18) /*!< SCU_T::PNPSET3: UART2 Position */ 2446 #define SCU_PNPSET3_UART2_Msk (0x1ul << SCU_PNPSET3_UART2_Pos) /*!< SCU_T::PNPSET3: UART2 Mask */ 2447 2448 #define SCU_PNPSET3_UART3_Pos (19) /*!< SCU_T::PNPSET3: UART3 Position */ 2449 #define SCU_PNPSET3_UART3_Msk (0x1ul << SCU_PNPSET3_UART3_Pos) /*!< SCU_T::PNPSET3: UART3 Mask */ 2450 2451 #define SCU_PNPSET3_UART4_Pos (20) /*!< SCU_T::PNPSET3: UART4 Position */ 2452 #define SCU_PNPSET3_UART4_Msk (0x1ul << SCU_PNPSET3_UART4_Pos) /*!< SCU_T::PNPSET3: UART4 Mask */ 2453 2454 #define SCU_PNPSET3_UART5_Pos (21) /*!< SCU_T::PNPSET3: UART5 Position */ 2455 #define SCU_PNPSET3_UART5_Msk (0x1ul << SCU_PNPSET3_UART5_Pos) /*!< SCU_T::PNPSET3: UART5 Mask */ 2456 2457 #define SCU_PNPSET4_I2C0_Pos (0) /*!< SCU_T::PNPSET4: I2C0 Position */ 2458 #define SCU_PNPSET4_I2C0_Msk (0x1ul << SCU_PNPSET4_I2C0_Pos) /*!< SCU_T::PNPSET4: I2C0 Mask */ 2459 2460 #define SCU_PNPSET4_I2C1_Pos (1) /*!< SCU_T::PNPSET4: I2C1 Position */ 2461 #define SCU_PNPSET4_I2C1_Msk (0x1ul << SCU_PNPSET4_I2C1_Pos) /*!< SCU_T::PNPSET4: I2C1 Mask */ 2462 2463 #define SCU_PNPSET4_I2C2_Pos (2) /*!< SCU_T::PNPSET4: I2C2 Position */ 2464 #define SCU_PNPSET4_I2C2_Msk (0x1ul << SCU_PNPSET4_I2C2_Pos) /*!< SCU_T::PNPSET4: I2C2 Mask */ 2465 2466 #define SCU_PNPSET4_SC0_Pos (16) /*!< SCU_T::PNPSET4: SC0 Position */ 2467 #define SCU_PNPSET4_SC0_Msk (0x1ul << SCU_PNPSET4_SC0_Pos) /*!< SCU_T::PNPSET4: SC0 Mask */ 2468 2469 #define SCU_PNPSET4_SC1_Pos (17) /*!< SCU_T::PNPSET4: SC1 Position */ 2470 #define SCU_PNPSET4_SC1_Msk (0x1ul << SCU_PNPSET4_SC1_Pos) /*!< SCU_T::PNPSET4: SC1 Mask */ 2471 2472 #define SCU_PNPSET4_SC2_Pos (18) /*!< SCU_T::PNPSET4: SC2 Position */ 2473 #define SCU_PNPSET4_SC2_Msk (0x1ul << SCU_PNPSET4_SC2_Pos) /*!< SCU_T::PNPSET4: SC2 Mask */ 2474 2475 #define SCU_PNPSET5_CAN0_Pos (0) /*!< SCU_T::PNPSET5: CAN0 Position */ 2476 #define SCU_PNPSET5_CAN0_Msk (0x1ul << SCU_PNPSET5_CAN0_Pos) /*!< SCU_T::PNPSET5: CAN0 Mask */ 2477 2478 #define SCU_PNPSET5_QEI0_Pos (16) /*!< SCU_T::PNPSET5: QEI0 Position */ 2479 #define SCU_PNPSET5_QEI0_Msk (0x1ul << SCU_PNPSET5_QEI0_Pos) /*!< SCU_T::PNPSET5: QEI0 Mask */ 2480 2481 #define SCU_PNPSET5_QEI1_Pos (17) /*!< SCU_T::PNPSET5: QEI1 Position */ 2482 #define SCU_PNPSET5_QEI1_Msk (0x1ul << SCU_PNPSET5_QEI1_Pos) /*!< SCU_T::PNPSET5: QEI1 Mask */ 2483 2484 #define SCU_PNPSET5_ECAP0_Pos (20) /*!< SCU_T::PNPSET5: ECAP0 Position */ 2485 #define SCU_PNPSET5_ECAP0_Msk (0x1ul << SCU_PNPSET5_ECAP0_Pos) /*!< SCU_T::PNPSET5: ECAP0 Mask */ 2486 2487 #define SCU_PNPSET5_ECAP1_Pos (21) /*!< SCU_T::PNPSET5: ECAP1 Position */ 2488 #define SCU_PNPSET5_ECAP1_Msk (0x1ul << SCU_PNPSET5_ECAP1_Pos) /*!< SCU_T::PNPSET5: ECAP1 Mask */ 2489 2490 #define SCU_PNPSET5_TRNG_Pos (25) /*!< SCU_T::PNPSET5: TRNG Position */ 2491 #define SCU_PNPSET5_TRNG_Msk (0x1ul << SCU_PNPSET5_TRNG_Pos) /*!< SCU_T::PNPSET5: TRNG Mask */ 2492 2493 #define SCU_PNPSET5_LCD_Pos (27) /*!< SCU_T::PNPSET5: LCD Position */ 2494 #define SCU_PNPSET5_LCD_Msk (0x1ul << SCU_PNPSET5_LCD_Pos) /*!< SCU_T::PNPSET5: LCD Mask */ 2495 2496 #define SCU_PNPSET5_TAMPER_Pos (29) /*!< SCU_T::PNPSET5: TAMPER Position */ 2497 #define SCU_PNPSET5_TAMPER_Msk (0x1ul << SCU_PNPSET5_TAMPER_Pos) /*!< SCU_T::PNPSET5: TAMPER Mask */ 2498 2499 #define SCU_PNPSET6_USBD_Pos (0) /*!< SCU_T::PNPSET6: USBD Position */ 2500 #define SCU_PNPSET6_USBD_Msk (0x1ul << SCU_PNPSET6_USBD_Pos) /*!< SCU_T::PNPSET6: USBD Mask */ 2501 2502 #define SCU_PNPSET6_USCI0_Pos (16) /*!< SCU_T::PNPSET6: USCI0 Position */ 2503 #define SCU_PNPSET6_USCI0_Msk (0x1ul << SCU_PNPSET6_USCI0_Pos) /*!< SCU_T::PNPSET6: USCI0 Mask */ 2504 2505 #define SCU_PNPSET6_USCI1_Pos (17) /*!< SCU_T::PNPSET6: USCI1 Position */ 2506 #define SCU_PNPSET6_USCI1_Msk (0x1ul << SCU_PNPSET6_USCI1_Pos) /*!< SCU_T::PNPSET6: USCI1 Mask */ 2507 2508 #define SCU_IONPSET_PA_Pos (0) /*!< SCU_T::IONPSET: PA Position */ 2509 #define SCU_IONPSET_PA_Msk (0x1ul << SCU_IONPSET_PA_Pos) /*!< SCU_T::IONPSET: PA Mask */ 2510 2511 #define SCU_IONPSET_PB_Pos (1) /*!< SCU_T::IONPSET: PB Position */ 2512 #define SCU_IONPSET_PB_Msk (0x1ul << SCU_IONPSET_PB_Pos) /*!< SCU_T::IONPSET: PB Mask */ 2513 2514 #define SCU_IONPSET_PC_Pos (2) /*!< SCU_T::IONPSET: PC Position */ 2515 #define SCU_IONPSET_PC_Msk (0x1ul << SCU_IONPSET_PC_Pos) /*!< SCU_T::IONPSET: PC Mask */ 2516 2517 #define SCU_IONPSET_PD_Pos (3) /*!< SCU_T::IONPSET: PD Position */ 2518 #define SCU_IONPSET_PD_Msk (0x1ul << SCU_IONPSET_PD_Pos) /*!< SCU_T::IONPSET: PD Mask */ 2519 2520 #define SCU_IONPSET_PE_Pos (4) /*!< SCU_T::IONPSET: PE Position */ 2521 #define SCU_IONPSET_PE_Msk (0x1ul << SCU_IONPSET_PE_Pos) /*!< SCU_T::IONPSET: PE Mask */ 2522 2523 #define SCU_IONPSET_PF_Pos (5) /*!< SCU_T::IONPSET: PF Position */ 2524 #define SCU_IONPSET_PF_Msk (0x1ul << SCU_IONPSET_PF_Pos) /*!< SCU_T::IONPSET: PF Mask */ 2525 2526 #define SCU_IONPSET_PG_Pos (6) /*!< SCU_T::IONPSET: PG Position */ 2527 #define SCU_IONPSET_PG_Msk (0x1ul << SCU_IONPSET_PG_Pos) /*!< SCU_T::IONPSET: PG Mask */ 2528 2529 #define SCU_IONPSET_PH_Pos (7) /*!< SCU_T::IONPSET: PH Position */ 2530 #define SCU_IONPSET_PH_Msk (0x1ul << SCU_IONPSET_PH_Pos) /*!< SCU_T::IONPSET: PH Mask */ 2531 2532 #define SCU_SRAMNPSET_SECn_Pos (0) /*!< SCU_T::SRAMNPSET: SECn Position */ 2533 #define SCU_SRAMNPSET_SECn_Msk (0xffffful << SCU_SRAMNPSET_SECn_Pos) /*!< SCU_T::SRAMNPSET: SECn Mask */ 2534 2535 #define SCU_MEMNPSET_FLASH_Pos (0) /*!< SCU_T::MEMNPSET: FLASH Position */ 2536 #define SCU_MEMNPSET_FLASH_Msk (0x1ul << SCU_MEMNPSET_FLASH_Pos) /*!< SCU_T::MEMNPSET: FLASH Mask */ 2537 2538 #define SCU_MEMNPSET_EXTMEM_Pos (1) /*!< SCU_T::MEMNPSET: EXTMEM Position */ 2539 #define SCU_MEMNPSET_EXTMEM_Msk (0x1ul << SCU_MEMNPSET_EXTMEM_Pos) /*!< SCU_T::MEMNPSET: EXTMEM Mask */ 2540 2541 #define SCU_PVIOIEN_APB0IEN_Pos (0) /*!< SCU_T::PVIOIEN: APB0IEN Position */ 2542 #define SCU_PVIOIEN_APB0IEN_Msk (0x1ul << SCU_PVIOIEN_APB0IEN_Pos) /*!< SCU_T::PVIOIEN: APB0IEN Mask */ 2543 2544 #define SCU_PVIOIEN_APB1IEN_Pos (1) /*!< SCU_T::PVIOIEN: APB1IEN Position */ 2545 #define SCU_PVIOIEN_APB1IEN_Msk (0x1ul << SCU_PVIOIEN_APB1IEN_Pos) /*!< SCU_T::PVIOIEN: APB1IEN Mask */ 2546 2547 #define SCU_PVIOIEN_GPIOIEN_Pos (4) /*!< SCU_T::PVIOIEN: GPIOIEN Position */ 2548 #define SCU_PVIOIEN_GPIOIEN_Msk (0x1ul << SCU_PVIOIEN_GPIOIEN_Pos) /*!< SCU_T::PVIOIEN: GPIOIEN Mask */ 2549 2550 #define SCU_PVIOIEN_EBIIEN_Pos (5) /*!< SCU_T::PVIOIEN: EBIIEN Position */ 2551 #define SCU_PVIOIEN_EBIIEN_Msk (0x1ul << SCU_PVIOIEN_EBIIEN_Pos) /*!< SCU_T::PVIOIEN: EBIIEN Mask */ 2552 2553 #define SCU_PVIOIEN_USBHIEN_Pos (6) /*!< SCU_T::PVIOIEN: USBHIEN Position */ 2554 #define SCU_PVIOIEN_USBHIEN_Msk (0x1ul << SCU_PVIOIEN_USBHIEN_Pos) /*!< SCU_T::PVIOIEN: USBHIEN Mask */ 2555 2556 #define SCU_PVIOIEN_CRCIEN_Pos (7) /*!< SCU_T::PVIOIEN: CRCIEN Position */ 2557 #define SCU_PVIOIEN_CRCIEN_Msk (0x1ul << SCU_PVIOIEN_CRCIEN_Pos) /*!< SCU_T::PVIOIEN: CRCIEN Mask */ 2558 2559 #define SCU_PVIOIEN_SDH0IEN_Pos (8) /*!< SCU_T::PVIOIEN: SDH0IEN Position */ 2560 #define SCU_PVIOIEN_SDH0IEN_Msk (0x1ul << SCU_PVIOIEN_SDH0IEN_Pos) /*!< SCU_T::PVIOIEN: SDH0IEN Mask */ 2561 2562 #define SCU_PVIOIEN_PDMA0IEN_Pos (10) /*!< SCU_T::PVIOIEN: PDMA0IEN Position */ 2563 #define SCU_PVIOIEN_PDMA0IEN_Msk (0x1ul << SCU_PVIOIEN_PDMA0IEN_Pos) /*!< SCU_T::PVIOIEN: PDMA0IEN Mask */ 2564 2565 #define SCU_PVIOIEN_PDMA1IEN_Pos (11) /*!< SCU_T::PVIOIEN: PDMA1IEN Position */ 2566 #define SCU_PVIOIEN_PDMA1IEN_Msk (0x1ul << SCU_PVIOIEN_PDMA1IEN_Pos) /*!< SCU_T::PVIOIEN: PDMA1IEN Mask */ 2567 2568 #define SCU_PVIOIEN_SRAM0IEN_Pos (12) /*!< SCU_T::PVIOIEN: SRAM0IEN Position */ 2569 #define SCU_PVIOIEN_SRAM0IEN_Msk (0x1ul << SCU_PVIOIEN_SRAM0IEN_Pos) /*!< SCU_T::PVIOIEN: SRAM0IEN Mask */ 2570 2571 #define SCU_PVIOIEN_SRAM1IEN_Pos (13) /*!< SCU_T::PVIOIEN: SRAM1IEN Position */ 2572 #define SCU_PVIOIEN_SRAM1IEN_Msk (0x1ul << SCU_PVIOIEN_SRAM1IEN_Pos) /*!< SCU_T::PVIOIEN: SRAM1IEN Mask */ 2573 2574 #define SCU_PVIOIEN_FMCIEN_Pos (14) /*!< SCU_T::PVIOIEN: FMCIEN Position */ 2575 #define SCU_PVIOIEN_FMCIEN_Msk (0x1ul << SCU_PVIOIEN_FMCIEN_Pos) /*!< SCU_T::PVIOIEN: FMCIEN Mask */ 2576 2577 #define SCU_PVIOIEN_FLASHIEN_Pos (15) /*!< SCU_T::PVIOIEN: FLASHIEN Position */ 2578 #define SCU_PVIOIEN_FLASHIEN_Msk (0x1ul << SCU_PVIOIEN_FLASHIEN_Pos) /*!< SCU_T::PVIOIEN: FLASHIEN Mask */ 2579 2580 #define SCU_PVIOIEN_SCUIEN_Pos (16) /*!< SCU_T::PVIOIEN: SCUIEN Position */ 2581 #define SCU_PVIOIEN_SCUIEN_Msk (0x1ul << SCU_PVIOIEN_SCUIEN_Pos) /*!< SCU_T::PVIOIEN: SCUIEN Mask */ 2582 2583 #define SCU_PVIOIEN_SYSIEN_Pos (17) /*!< SCU_T::PVIOIEN: SYSIEN Position */ 2584 #define SCU_PVIOIEN_SYSIEN_Msk (0x1ul << SCU_PVIOIEN_SYSIEN_Pos) /*!< SCU_T::PVIOIEN: SYSIEN Mask */ 2585 2586 #define SCU_PVIOIEN_CRPTIEN_Pos (18) /*!< SCU_T::PVIOIEN: CRPTIEN Position */ 2587 #define SCU_PVIOIEN_CRPTIEN_Msk (0x1ul << SCU_PVIOIEN_CRPTIEN_Pos) /*!< SCU_T::PVIOIEN: CRPTIEN Mask */ 2588 2589 #define SCU_PVIOIEN_KSIEN_Pos (19) /*!< SCU_T::PVIOIEN: KSIEN Position */ 2590 #define SCU_PVIOIEN_KSIEN_Msk (0x1ul << SCU_PVIOIEN_KSIEN_Pos) /*!< SCU_T::PVIOIEN: KSIEN Mask */ 2591 2592 #define SCU_PVINTSTS_APB0IF_Pos (0) /*!< SCU_T::PVINTSTS: APB0IF Position */ 2593 #define SCU_PVINTSTS_APB0IF_Msk (0x1ul << SCU_PVINTSTS_APB0IF_Pos) /*!< SCU_T::PVINTSTS: APB0IF Mask */ 2594 2595 #define SCU_PVINTSTS_APB1IF_Pos (1) /*!< SCU_T::PVINTSTS: APB1IF Position */ 2596 #define SCU_PVINTSTS_APB1IF_Msk (0x1ul << SCU_PVINTSTS_APB1IF_Pos) /*!< SCU_T::PVINTSTS: APB1IF Mask */ 2597 2598 #define SCU_PVINTSTS_GPIOIF_Pos (4) /*!< SCU_T::PVINTSTS: GPIOIF Position */ 2599 #define SCU_PVINTSTS_GPIOIF_Msk (0x1ul << SCU_PVINTSTS_GPIOIF_Pos) /*!< SCU_T::PVINTSTS: GPIOIF Mask */ 2600 2601 #define SCU_PVINTSTS_EBIIF_Pos (5) /*!< SCU_T::PVINTSTS: EBIIF Position */ 2602 #define SCU_PVINTSTS_EBIIF_Msk (0x1ul << SCU_PVINTSTS_EBIIF_Pos) /*!< SCU_T::PVINTSTS: EBIIF Mask */ 2603 2604 #define SCU_PVINTSTS_USBHIF_Pos (6) /*!< SCU_T::PVINTSTS: USBHIF Position */ 2605 #define SCU_PVINTSTS_USBHIF_Msk (0x1ul << SCU_PVINTSTS_USBHIF_Pos) /*!< SCU_T::PVINTSTS: USBHIF Mask */ 2606 2607 #define SCU_PVINTSTS_CRCIF_Pos (7) /*!< SCU_T::PVINTSTS: CRCIF Position */ 2608 #define SCU_PVINTSTS_CRCIF_Msk (0x1ul << SCU_PVINTSTS_CRCIF_Pos) /*!< SCU_T::PVINTSTS: CRCIF Mask */ 2609 2610 #define SCU_PVINTSTS_SDH0IF_Pos (8) /*!< SCU_T::PVINTSTS: SDH0IF Position */ 2611 #define SCU_PVINTSTS_SDH0IF_Msk (0x1ul << SCU_PVINTSTS_SDH0IF_Pos) /*!< SCU_T::PVINTSTS: SDH0IF Mask */ 2612 2613 #define SCU_PVINTSTS_PDMA0IF_Pos (10) /*!< SCU_T::PVINTSTS: PDMA0IF Position */ 2614 #define SCU_PVINTSTS_PDMA0IF_Msk (0x1ul << SCU_PVINTSTS_PDMA0IF_Pos) /*!< SCU_T::PVINTSTS: PDMA0IF Mask */ 2615 2616 #define SCU_PVINTSTS_PDMA1IF_Pos (11) /*!< SCU_T::PVINTSTS: PDMA1IF Position */ 2617 #define SCU_PVINTSTS_PDMA1IF_Msk (0x1ul << SCU_PVINTSTS_PDMA1IF_Pos) /*!< SCU_T::PVINTSTS: PDMA1IF Mask */ 2618 2619 #define SCU_PVINTSTS_SRAM0IF_Pos (12) /*!< SCU_T::PVINTSTS: SRAM0IF Position */ 2620 #define SCU_PVINTSTS_SRAM0IF_Msk (0x1ul << SCU_PVINTSTS_SRAM0IF_Pos) /*!< SCU_T::PVINTSTS: SRAM0IF Mask */ 2621 2622 #define SCU_PVINTSTS_SRAM1IF_Pos (13) /*!< SCU_T::PVINTSTS: SRAM1IF Position */ 2623 #define SCU_PVINTSTS_SRAM1IF_Msk (0x1ul << SCU_PVINTSTS_SRAM1IF_Pos) /*!< SCU_T::PVINTSTS: SRAM1IF Mask */ 2624 2625 #define SCU_PVINTSTS_FMCIF_Pos (14) /*!< SCU_T::PVINTSTS: FMCIF Position */ 2626 #define SCU_PVINTSTS_FMCIF_Msk (0x1ul << SCU_PVINTSTS_FMCIF_Pos) /*!< SCU_T::PVINTSTS: FMCIF Mask */ 2627 2628 #define SCU_PVINTSTS_FLASHIF_Pos (15) /*!< SCU_T::PVINTSTS: FLASHIF Position */ 2629 #define SCU_PVINTSTS_FLASHIF_Msk (0x1ul << SCU_PVINTSTS_FLASHIF_Pos) /*!< SCU_T::PVINTSTS: FLASHIF Mask */ 2630 2631 #define SCU_PVINTSTS_SCUIF_Pos (16) /*!< SCU_T::PVINTSTS: SCUIF Position */ 2632 #define SCU_PVINTSTS_SCUIF_Msk (0x1ul << SCU_PVINTSTS_SCUIF_Pos) /*!< SCU_T::PVINTSTS: SCUIF Mask */ 2633 2634 #define SCU_PVINTSTS_SYSIF_Pos (17) /*!< SCU_T::PVINTSTS: SYSIF Position */ 2635 #define SCU_PVINTSTS_SYSIF_Msk (0x1ul << SCU_PVINTSTS_SYSIF_Pos) /*!< SCU_T::PVINTSTS: SYSIF Mask */ 2636 2637 #define SCU_PVINTSTS_CRPTIF_Pos (18) /*!< SCU_T::PVINTSTS: CRPTIF Position */ 2638 #define SCU_PVINTSTS_CRPTIF_Msk (0x1ul << SCU_PVINTSTS_CRPTIF_Pos) /*!< SCU_T::PVINTSTS: CRPTIF Mask */ 2639 2640 #define SCU_PVINTSTS_KSIF_Pos (19) /*!< SCU_T::PVINTSTS: KSIF Position */ 2641 #define SCU_PVINTSTS_KSIF_Msk (0x1ul << SCU_PVINTSTS_KSIF_Pos) /*!< SCU_T::PVINTSTS: KSIF Mask */ 2642 2643 #define SCU_NSMCTL_PRESCALE_Pos (0) /*!< SCU_T::NSMCTL: PRESCALE Position */ 2644 #define SCU_NSMCTL_PRESCALE_Msk (0xfful << SCU_NSMCTL_PRESCALE_Pos) /*!< SCU_T::NSMCTL: PRESCALE Mask */ 2645 2646 #define SCU_NSMCTL_NSMIEN_Pos (8) /*!< SCU_T::NSMCTL: NSMIEN Position */ 2647 #define SCU_NSMCTL_NSMIEN_Msk (0x1ul << SCU_NSMCTL_NSMIEN_Pos) /*!< SCU_T::NSMCTL: NSMIEN Mask */ 2648 2649 #define SCU_NSMCTL_AUTORLD_Pos (9) /*!< SCU_T::NSMCTL: AUTORLD Position */ 2650 #define SCU_NSMCTL_AUTORLD_Msk (0x1ul << SCU_NSMCTL_AUTORLD_Pos) /*!< SCU_T::NSMCTL: AUTORLD Mask */ 2651 2652 #define SCU_NSMCTL_TMRMOD_Pos (10) /*!< SCU_T::NSMCTL: TMRMOD Position */ 2653 #define SCU_NSMCTL_TMRMOD_Msk (0x1ul << SCU_NSMCTL_TMRMOD_Pos) /*!< SCU_T::NSMCTL: TMRMOD Mask */ 2654 2655 #define SCU_NSMCTL_IDLEON_Pos (12) /*!< SCU_T::NSMCTL: IDLEON Position */ 2656 #define SCU_NSMCTL_IDLEON_Msk (0x1ul << SCU_NSMCTL_IDLEON_Pos) /*!< SCU_T::NSMCTL: IDLEON Mask */ 2657 2658 #define SCU_NSMCTL_DBGON_Pos (13) /*!< SCU_T::NSMCTL: DBGON Position */ 2659 #define SCU_NSMCTL_DBGON_Msk (0x1ul << SCU_NSMCTL_DBGON_Pos) /*!< SCU_T::NSMCTL: DBGON Mask */ 2660 2661 #define SCU_NSMLOAD_RELOAD_Pos (0) /*!< SCU_T::NSMLOAD: RELOAD Position */ 2662 #define SCU_NSMLOAD_RELOAD_Msk (0xfffffful << SCU_NSMLOAD_RELOAD_Pos) /*!< SCU_T::NSMLOAD: RELOAD Mask */ 2663 2664 #define SCU_NSMVAL_VALUE_Pos (0) /*!< SCU_T::NSMVAL: VALUE Position */ 2665 #define SCU_NSMVAL_VALUE_Msk (0xfffffful << SCU_NSMVAL_VALUE_Pos) /*!< SCU_T::NSMVAL: VALUE Mask */ 2666 2667 #define SCU_NSMSTS_CURRNS_Pos (0) /*!< SCU_T::NSMSTS: CURRNS Position */ 2668 #define SCU_NSMSTS_CURRNS_Msk (0x1ul << SCU_NSMSTS_CURRNS_Pos) /*!< SCU_T::NSMSTS: CURRNS Mask */ 2669 2670 #define SCU_NSMSTS_NSMIF_Pos (1) /*!< SCU_T::NSMSTS: NSMIF Position */ 2671 #define SCU_NSMSTS_NSMIF_Msk (0x1ul << SCU_NSMSTS_NSMIF_Pos) /*!< SCU_T::NSMSTS: NSMIF Mask */ 2672 2673 #define SCU_BBE_BBEEN_Pos (0) /*!< SCU_T::BBE: BBEEN Position */ 2674 #define SCU_BBE_BBEEN_Msk (0x1ul << SCU_BBE_BBEEN_Pos) /*!< SCU_T::BBE: BBEEN Mask */ 2675 2676 #define SCU_BBE_WVERY_Pos (8) /*!< SCU_T::BBE: WVERY Position */ 2677 #define SCU_BBE_WVERY_Msk (0xfffffful << SCU_BBE_WVERY_Pos) /*!< SCU_T::BBE: WVERY Mask */ 2678 2679 #define SCU_IDAUANS_IDAUANSEN_Pos (0) /*!< SCU_T::IDAUANS: IDAUANSEN Position */ 2680 #define SCU_IDAUANS_IDAUANSEN_Msk (0x1ul << SCU_IDAUANS_IDAUANSEN_Pos) /*!< SCU_T::IDAUANS: IDAUANSEN Mask */ 2681 2682 #define SCU_IDAUANS_WVERY_Pos (8) /*!< SCU_T::IDAUANS: WVERY Position */ 2683 #define SCU_IDAUANS_WVERY_Msk (0xfffffful << SCU_IDAUANS_WVERY_Pos) /*!< SCU_T::IDAUANS: WVERY Mask */ 2684 2685 #define SCU_VERSION_MINOR_Pos (0) /*!< SCU_T::VERSION: MINOR Position */ 2686 #define SCU_VERSION_MINOR_Msk (0xfffful << SCU_VERSION_MINOR_Pos) /*!< SCU_T::VERSION: MINOR Mask */ 2687 2688 #define SCU_VERSION_SUB_Pos (16) /*!< SCU_T::VERSION: SUB Position */ 2689 #define SCU_VERSION_SUB_Msk (0xfful << SCU_VERSION_SUB_Pos) /*!< SCU_T::VERSION: SUB Mask */ 2690 2691 #define SCU_VERSION_MAJOR_Pos (24) /*!< SCU_T::VERSION: MAJOR Position */ 2692 #define SCU_VERSION_MAJOR_Msk (0xfful << SCU_VERSION_MAJOR_Pos) /*!< SCU_T::VERSION: MAJOR Mask */ 2693 2694 /**@}*/ /* SCU_CONST */ 2695 /**@}*/ /* end of SCU register group */ 2696 2697 2698 /**@}*/ /* end of REGISTER group */ 2699 #endif /* __SCU_REG_H__ */ 2700
