1 /**************************************************************************//** 2 * @file ui2c_reg.h 3 * @version V1.00 4 * @brief UI2C register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __UI2C_REG_H__ 10 #define __UI2C_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- I2C Mode of USCI Controller -------------------------*/ 19 /** 20 @addtogroup UI2C I2C Mode of USCI Controller(UI2C) 21 Memory Mapped Structure for UI2C Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var UI2C_T::CTL 31 * Offset: 0x00 USCI Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[2:0] |FUNMODE |Function Mode 36 * | | |This bit field selects the protocol for this USCI controller 37 * | | |Selecting a protocol that is not available or a reserved combination disables the USCI 38 * | | |When switching between two protocols, the USCI has to be disabled before selecting a new protocol 39 * | | |Simultaneously, the USCI will be reset when user write 000 to FUNMODE. 40 * | | |000 = The USCI is disabled. All protocol related state machines are set to idle state. 41 * | | |001 = The SPI protocol is selected. 42 * | | |010 = The UART protocol is selected. 43 * | | |100 = The I2C protocol is selected. 44 * | | |Note: Other bit combinations are reserved. 45 * @var UI2C_T::BRGEN 46 * Offset: 0x08 USCI Baud Rate Generator Register 47 * --------------------------------------------------------------------------------------------------- 48 * |Bits |Field |Descriptions 49 * | :----: | :----: | :---- | 50 * |[0] |RCLKSEL |Reference Clock Source Selection 51 * | | |This bit selects the source signal of reference clock (fREF_CLK). 52 * | | |0 = Peripheral device clock fPCLK. 53 * | | |1 = Reserved. 54 * |[1] |PTCLKSEL |Protocol Clock Source Selection 55 * | | |This bit selects the source signal of protocol clock (fPROT_CLK). 56 * | | |0 = Reference clock fREF_CLK. 57 * | | |1 = fREF_CLK2 (its frequency is half of fREF_CLK). 58 * |[3:2] |SPCLKSEL |Sample Clock Source Selection 59 * | | |This bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor. 60 * | | |00 = fSAMP_CLK = fDIV_CLK. 61 * | | |01 = fSAMP_CLK = fPROT_CLK. 62 * | | |10 = fSAMP_CLK = fSCLK. 63 * | | |11 = fSAMP_CLK = fREF_CLK. 64 * |[4] |TMCNTEN |Time Measurement Counter Enable Bit 65 * | | |This bit enables the 10-bit timing measurement counter. 66 * | | |0 = Time measurement counter is Disabled. 67 * | | |1 = Time measurement counter is Enabled. 68 * |[5] |TMCNTSRC |Time Measurement Counter Clock Source Selection 69 * | | |0 = Time measurement counter with fPROT_CLK. 70 * | | |1 = Time measurement counter with fDIV_CLK. 71 * |[9:8] |PDSCNT |Pre-divider for Sample Counter 72 * | | |This bit field defines the divide ratio of the clock division from sample clock fSAMP_CLK 73 * | | |The divided frequency fPDS_CNT = fSAMP_CLK / (PDSCNT+1). 74 * |[14:10] |DSCNT |Denominator for Sample Counter 75 * | | |This bit field defines the divide ratio of the sample clock fSAMP_CLK. 76 * | | |The divided frequency fDS_CNT = fPDS_CNT / (DSCNT+1). 77 * | | |Note: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value 78 * |[25:16] |CLKDIV |Clock Divider 79 * | | |This bit field defines the ratio between the protocol clock frequency fPROT_CLK and the clock divider frequency fDIV_CLK (fDIV_CLK = fPROT_CLK / (CLKDIV+1) ). 80 * | | |Note: In UART function, it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UI2C_PROTCTL[6])) is enabled 81 * | | |The revised value is the average bit time between bit 5 and bit 6 82 * | | |The user can use revised CLKDIV and new BRDETITV (UI2C_PROTCTL[24:16]) to calculate the precise baud rate. 83 * @var UI2C_T::LINECTL 84 * Offset: 0x2C USCI Line Control Register 85 * --------------------------------------------------------------------------------------------------- 86 * |Bits |Field |Descriptions 87 * | :----: | :----: | :---- | 88 * |[0] |LSB |LSB First Transmission Selection 89 * | | |0 = The MSB, which bit of transmit/receive data buffer depends on the setting of DWIDTH, is transmitted/received first. 90 * | | |1 = The LSB, the bit 0 of data buffer, will be transmitted/received first. 91 * |[11:8] |DWIDTH |Word Length of Transmission 92 * | | |This bit field defines the data word length (amount of bits) for reception and transmission 93 * | | |The data word is always right-aligned in the data buffer 94 * | | |USCI support word length from 4 to 16 bits. 95 * | | |0x0: The data word contains 16 bits located at bit positions [15:0]. 96 * | | |0x1: Reserved. 97 * | | |0x2: Reserved. 98 * | | |0x3: Reserved. 99 * | | |0x4: The data word contains 4 bits located at bit positions [3:0]. 100 * | | |0x5: The data word contains 5 bits located at bit positions [4:0]. 101 * | | |... 102 * | | |0xF: The data word contains 15 bits located at bit positions [14:0]. 103 * | | |Note: In UART protocol, the length can be configured as 6~13 bits. 104 * @var UI2C_T::TXDAT 105 * Offset: 0x30 USCI Transmit Data Register 106 * --------------------------------------------------------------------------------------------------- 107 * |Bits |Field |Descriptions 108 * | :----: | :----: | :---- | 109 * |[15:0] |TXDAT |Transmit Data 110 * | | |Software can use this bit field to write 16-bit transmit data for transmission. 111 * @var UI2C_T::RXDAT 112 * Offset: 0x34 USCI Receive Data Register 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[15:0] |RXDAT |Received Data 117 * | | |This bit field monitors the received data which stored in receive data buffer. 118 * | | |Note 1: In I2C protocol, RXDAT[12:8] indicate the different transmission conditions which defined in I2C. 119 * | | |Note 2: In UART protocol, RXDAT[15:13] indicate the same frame status of BREAK, FRMERR and PARITYERR (UI2C_PROTSTS[7:5]). 120 * @var UI2C_T::DEVADDR0 121 * Offset: 0x44 USCI Device Address Register 0 122 * --------------------------------------------------------------------------------------------------- 123 * |Bits |Field |Descriptions 124 * | :----: | :----: | :---- | 125 * |[9:0] |DEVADDR |Device Address 126 * | | |In I2C protocol, this bit field contains the programmed slave address 127 * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit 128 * | | |Then the second address byte is also compared to DEVADDR[7:0]. 129 * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. 130 * @var UI2C_T::DEVADDR1 131 * Offset: 0x48 USCI Device Address Register 1 132 * --------------------------------------------------------------------------------------------------- 133 * |Bits |Field |Descriptions 134 * | :----: | :----: | :---- | 135 * |[9:0] |DEVADDR |Device Address 136 * | | |In I2C protocol, this bit field contains the programmed slave address 137 * | | |If the first received address byte are 1111 0AAXB, the AA bits are compared to the bits DEVADDR[9:8] to check for address match, where the X is R/W bit 138 * | | |Then the second address byte is also compared to DEVADDR[7:0]. 139 * | | |Note: The DEVADDR [9:7] must be set 3'b000 when I2C operating in 7-bit address mode. 140 * @var UI2C_T::ADDRMSK0 141 * Offset: 0x4C USCI Device Address Mask Register 0 142 * --------------------------------------------------------------------------------------------------- 143 * |Bits |Field |Descriptions 144 * | :----: | :----: | :---- | 145 * |[9:0] |ADDRMSK |USCI Device Address Mask 146 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 147 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 148 * | | |USCI support multiple address recognition with two address mask register 149 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 150 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 151 * | | |Note: The wake-up function can not set address mask. 152 * @var UI2C_T::ADDRMSK1 153 * Offset: 0x50 USCI Device Address Mask Register 1 154 * --------------------------------------------------------------------------------------------------- 155 * |Bits |Field |Descriptions 156 * | :----: | :----: | :---- | 157 * |[9:0] |ADDRMSK |USCI Device Address Mask 158 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.). 159 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.). 160 * | | |USCI support multiple address recognition with two address mask register 161 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care 162 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register. 163 * | | |Note: The wake-up function can not set address mask. 164 * @var UI2C_T::WKCTL 165 * Offset: 0x54 USCI Wake-up Control Register 166 * --------------------------------------------------------------------------------------------------- 167 * |Bits |Field |Descriptions 168 * | :----: | :----: | :---- | 169 * |[0] |WKEN |Wake-up Enable Bit 170 * | | |0 = Wake-up function Disabled. 171 * | | |1 = Wake-up function Enabled. 172 * |[1] |WKADDREN |Wake-up Address Match Enable Bit 173 * | | |0 = The chip is woken up according data toggle. 174 * | | |1 = The chip is woken up according address match. 175 * @var UI2C_T::WKSTS 176 * Offset: 0x58 USCI Wake-up Status Register 177 * --------------------------------------------------------------------------------------------------- 178 * |Bits |Field |Descriptions 179 * | :----: | :----: | :---- | 180 * |[0] |WKF |Wake-up Flag 181 * | | |When chip is woken up from Power-down mode, this bit is set to 1 182 * | | |Software can write 1 to clear this bit. 183 * @var UI2C_T::PROTCTL 184 * Offset: 0x5C USCI Protocol Control Register 185 * --------------------------------------------------------------------------------------------------- 186 * |Bits |Field |Descriptions 187 * | :----: | :----: | :---- | 188 * |[0] |GCFUNC |General Call Function 189 * | | |0 = General Call Function Disabled. 190 * | | |1 = General Call Function Enabled. 191 * |[1] |AA |Assert Acknowledge Control 192 * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter 193 * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line. 194 * |[2] |STO |I2C STOP Control 195 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically 196 * | | |In a slave mode, setting STO resets I2C hardware to the defined not addressed slave mode when bus error (UI2C_PROTSTS.ERRIF = 1). 197 * |[3] |STA |I2C START Control 198 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free. 199 * |[4] |ADDR10EN |Address 10-bit Function Enable Bit 200 * | | |0 = Address match 10 bit function is disabled. 201 * | | |1 = Address match 10 bit function is enabled. 202 * |[5] |PTRG |I2C Protocol Trigger (Write Only) 203 * | | |When a new state is present in the UI2C_PROTSTS register, if the related interrupt enable bits are set, the I2C interrupt is requested 204 * | | |It must write one by software to this bit after the related interrupt flags are set to 1 and the I2C protocol function will go ahead until the STOP is active or the PROTEN is disabled. 205 * | | |0 = I2C's stretch disabled and the I2C protocol function will go ahead. 206 * | | |1 = I2C's stretch active. 207 * |[8] |SCLOUTEN |SCL Output Enable Bit 208 * | | |This bit enables monitor pulling SCL to low 209 * | | |This monitor will pull SCL to low until it has had time to respond to an I2C interrupt. 210 * | | |0 = SCL output will be forced high due to open drain mechanism. 211 * | | |1 = I2C module may act as a slave peripheral just like in normal operation, the I2C holds the clock line low until it has had time to clear I2C interrupt. 212 * |[9] |MONEN |Monitor Mode Enable Bit 213 * | | |This bit enables monitor mode 214 * | | |In monitor mode the SDA output will be put in high impedance mode 215 * | | |This prevents the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. 216 * | | |0 = The monitor mode is disabled. 217 * | | |1 = The monitor mode is enabled. 218 * | | |Note: Depending on the state of the SCLOUTEN bit, the SCL output may be also forced high, preventing the module from having control over the I2C clock line. 219 * |[25:16] |TOCNT |Time-out Clock Cycle 220 * | | |This bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear 221 * | | |The time-out is enable when TOCNT bigger than 0. 222 * | | |Note: The TMCNTSRC (UI2C_BRGEN [5]) must be set zero on I2C mode. 223 * |[31] |PROTEN |I2C Protocol Enable Bit 224 * | | |0 = I2C Protocol disable. 225 * | | |1 = I2C Protocol enable. 226 * @var UI2C_T::PROTIEN 227 * Offset: 0x60 USCI Protocol Interrupt Enable Register 228 * --------------------------------------------------------------------------------------------------- 229 * |Bits |Field |Descriptions 230 * | :----: | :----: | :---- | 231 * |[0] |TOIEN |Time-out Interrupt Enable Control 232 * | | |In I2C protocol, this bit enables the interrupt generation in case of a time-out event. 233 * | | |0 = The time-out interrupt is disabled. 234 * | | |1 = The time-out interrupt is enabled. 235 * |[1] |STARIEN |Start Condition Received Interrupt Enable Control 236 * | | |This bit enables the generation of a protocol interrupt if a start condition is detected. 237 * | | |0 = The start condition interrupt is disabled. 238 * | | |1 = The start condition interrupt is enabled. 239 * |[2] |STORIEN |Stop Condition Received Interrupt Enable Control 240 * | | |This bit enables the generation of a protocol interrupt if a stop condition is detected. 241 * | | |0 = The stop condition interrupt is disabled. 242 * | | |1 = The stop condition interrupt is enabled. 243 * |[3] |NACKIEN |Non - Acknowledge Interrupt Enable Control 244 * | | |This bit enables the generation of a protocol interrupt if a non - acknowledge is detected by a master. 245 * | | |0 = The non - acknowledge interrupt is disabled. 246 * | | |1 = The non - acknowledge interrupt is enabled. 247 * |[4] |ARBLOIEN |Arbitration Lost Interrupt Enable Control 248 * | | |This bit enables the generation of a protocol interrupt if an arbitration lost event is detected. 249 * | | |0 = The arbitration lost interrupt is disabled. 250 * | | |1 = The arbitration lost interrupt is enabled. 251 * |[5] |ERRIEN |Error Interrupt Enable Control 252 * | | |This bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERR (UI2C_PROTSTS [16])). 253 * | | |0 = The error interrupt is disabled. 254 * | | |1 = The error interrupt is enabled. 255 * |[6] |ACKIEN |Acknowledge Interrupt Enable Control 256 * | | |This bit enables the generation of a protocol interrupt if an acknowledge is detected by a master. 257 * | | |0 = The acknowledge interrupt is disabled. 258 * | | |1 = The acknowledge interrupt is enabled. 259 * @var UI2C_T::PROTSTS 260 * Offset: 0x64 USCI Protocol Status Register 261 * --------------------------------------------------------------------------------------------------- 262 * |Bits |Field |Descriptions 263 * | :----: | :----: | :---- | 264 * |[5] |TOIF |Time-out Interrupt Flag 265 * | | |0 = A time-out interrupt status has not occurred. 266 * | | |1 = A time-out interrupt status has occurred. 267 * | | |Note: It is cleared by software writing one into this bit 268 * |[6] |ONBUSY |On Bus Busy 269 * | | |Indicates that a communication is in progress on the bus 270 * | | |It is set by hardware when a START condition is detected 271 * | | |It is cleared by hardware when a STOP condition is detected 272 * | | |0 = The bus is IDLE (both SCLK and SDA High). 273 * | | |1 = The bus is busy. 274 * |[8] |STARIF |Start Condition Received Interrupt Flag 275 * | | |This bit indicates that a start condition or repeated start condition has been detected on master mode 276 * | | |However, this bit also indicates that a repeated start condition has been detected on slave mode. 277 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STARIEN = 1. 278 * | | |0 = A start condition has not yet been detected. 279 * | | |1 = A start condition has been detected. 280 * | | |It is cleared by software writing one into this bit 281 * |[9] |STORIF |Stop Condition Received Interrupt Flag 282 * | | |This bit indicates that a stop condition has been detected on the I2C bus lines 283 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.STORIEN = 1. 284 * | | |0 = A stop condition has not yet been detected. 285 * | | |1 = A stop condition has been detected. 286 * | | |It is cleared by software writing one into this bit 287 * | | |Note: This bit is set when slave RX mode. 288 * |[10] |NACKIF |Non - Acknowledge Received Interrupt Flag 289 * | | |This bit indicates that a non - acknowledge has been received in master mode 290 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.NACKIEN = 1. 291 * | | |0 = A non - acknowledge has not been received. 292 * | | |1 = A non - acknowledge has been received. 293 * | | |It is cleared by software writing one into this bit 294 * |[11] |ARBLOIF |Arbitration Lost Interrupt Flag 295 * | | |This bit indicates that an arbitration has been lost 296 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ARBLOIEN = 1. 297 * | | |0 = An arbitration has not been lost. 298 * | | |1 = An arbitration has been lost. 299 * | | |It is cleared by software writing one into this bit 300 * |[12] |ERRIF |Error Interrupt Flag 301 * | | |This bit indicates that a Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame 302 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit 303 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ERRIEN = 1. 304 * | | |0 = An I2C error has not been detected. 305 * | | |1 = An I2C error has been detected. 306 * | | |It is cleared by software writing one into this bit 307 * | | |Note: This bit is set when slave mode, user must write one into STO register to the defined not addressed slave mode. 308 * |[13] |ACKIF |Acknowledge Received Interrupt Flag 309 * | | |This bit indicates that an acknowledge has been received in master mode 310 * | | |A protocol interrupt can be generated if UI2C_PROTCTL.ACKIEN = 1. 311 * | | |0 = An acknowledge has not been received. 312 * | | |1 = An acknowledge has been received. 313 * | | |It is cleared by software writing one into this bit 314 * |[14] |SLASEL |Slave Select Status 315 * | | |This bit indicates that this device has been selected as slave. 316 * | | |0 = The device is not selected as slave. 317 * | | |1 = The device is selected as slave. 318 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 319 * |[15] |SLAREAD |Slave Read Request Status 320 * | | |This bit indicates that a slave read request has been detected. 321 * | | |0 = A slave R/W bit is 1 has not been detected. 322 * | | |1 = A slave R/W bit is 1 has been detected. 323 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware. 324 * |[16] |WKAKDONE |Wakeup Address Frame Acknowledge Bit Done 325 * | | |0 = The ACK bit cycle of address match frame isn't done. 326 * | | |1 = The ACK bit cycle of address match frame is done in power-down. 327 * | | |Note: This bit can't release when WKUPIF is set. 328 * |[17] |WRSTSWK |Read/Write Status Bit in Address Wakeup Frame 329 * | | |0 = Write command be record on the address match wakeup frame. 330 * | | |1 = Read command be record on the address match wakeup frame. 331 * |[18] |BUSHANG |Bus Hang-up 332 * | | |This bit indicates bus hang-up status 333 * | | |There is 4-bit counter count when SCL hold high and refer fSAMP_CLK 334 * | | |The hang-up counter will count to overflow and set this bit when SDA is low 335 * | | |The counter will be reset by falling edge of SCL signal. 336 * | | |0 = The bus is normal status for transmission. 337 * | | |1 = The bus is hang-up status for transmission. 338 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 339 * |[19] |ERRARBLO |Error Arbitration Lost 340 * | | |This bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor 341 * | | |The I2C can send start condition when ERRARBLO is set 342 * | | |Thus this bit doesn't be cared on slave mode. 343 * | | |0 = The bus is normal status for transmission. 344 * | | |1 = The bus is error arbitration lost status for transmission. 345 * | | |Note: This bit has no interrupt signal, and it will be cleared automatically by hardware when a START condition is present. 346 * @var UI2C_T::ADMAT 347 * Offset: 0x88 I2C Slave Match Address Register 348 * --------------------------------------------------------------------------------------------------- 349 * |Bits |Field |Descriptions 350 * | :----: | :----: | :---- | 351 * |[0] |ADMAT0 |USCI Address 0 Match Status Register 352 * | | |When address 0 is matched, hardware will inform which address used 353 * | | |This bit will set to 1, and software can write 1 to clear this bit. 354 * |[1] |ADMAT1 |USCI Address 1 Match Status Register 355 * | | |When address 1 is matched, hardware will inform which address used 356 * | | |This bit will set to 1, and software can write 1 to clear this bit. 357 * @var UI2C_T::TMCTL 358 * Offset: 0x8C I2C Timing Configure Control Register 359 * --------------------------------------------------------------------------------------------------- 360 * |Bits |Field |Descriptions 361 * | :----: | :----: | :---- | 362 * |[8:0] |STCTL |Setup Time Configure Control Register 363 * | | |This field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode.. 364 * | | |The delay setup time is numbers of peripheral clock = STCTL x fPCLK. 365 * |[24:16] |HTCTL |Hold Time Configure Control Register 366 * | | |This field is used to generate the delay timing between SCL falling edge SDA edge in 367 * | | |transmission mode. 368 * | | |The delay hold time is numbers of peripheral clock = HTCTL x fPCLK. 369 */ 370 __IO uint32_t CTL; /*!< [0x0000] USCI Control Register */ 371 __I uint32_t RESERVE0[1]; 372 __IO uint32_t BRGEN; /*!< [0x0008] USCI Baud Rate Generator Register */ 373 __I uint32_t RESERVE1[8]; 374 __IO uint32_t LINECTL; /*!< [0x002c] USCI Line Control Register */ 375 __O uint32_t TXDAT; /*!< [0x0030] USCI Transmit Data Register */ 376 __I uint32_t RXDAT; /*!< [0x0034] USCI Receive Data Register */ 377 __I uint32_t RESERVE2[3]; 378 __IO uint32_t DEVADDR0; /*!< [0x0044] USCI Device Address Register 0 */ 379 __IO uint32_t DEVADDR1; /*!< [0x0048] USCI Device Address Register 1 */ 380 __IO uint32_t ADDRMSK0; /*!< [0x004c] USCI Device Address Mask Register 0 */ 381 __IO uint32_t ADDRMSK1; /*!< [0x0050] USCI Device Address Mask Register 1 */ 382 __IO uint32_t WKCTL; /*!< [0x0054] USCI Wake-up Control Register */ 383 __IO uint32_t WKSTS; /*!< [0x0058] USCI Wake-up Status Register */ 384 __IO uint32_t PROTCTL; /*!< [0x005c] USCI Protocol Control Register */ 385 __IO uint32_t PROTIEN; /*!< [0x0060] USCI Protocol Interrupt Enable Register */ 386 __IO uint32_t PROTSTS; /*!< [0x0064] USCI Protocol Status Register */ 387 __I uint32_t RESERVE3[8]; 388 __IO uint32_t ADMAT; /*!< [0x0088] I2C Slave Match Address Register */ 389 __IO uint32_t TMCTL; /*!< [0x008c] I2C Timing Configure Control Register */ 390 391 } UI2C_T; 392 393 /** 394 @addtogroup UI2C_CONST UI2C Bit Field Definition 395 Constant Definitions for UI2C Controller 396 @{ 397 */ 398 399 #define UI2C_CTL_FUNMODE_Pos (0) /*!< UI2C_T::CTL: FUNMODE Position */ 400 #define UI2C_CTL_FUNMODE_Msk (0x7ul << UI2C_CTL_FUNMODE_Pos) /*!< UI2C_T::CTL: FUNMODE Mask */ 401 402 #define UI2C_BRGEN_RCLKSEL_Pos (0) /*!< UI2C_T::BRGEN: RCLKSEL Position */ 403 #define UI2C_BRGEN_RCLKSEL_Msk (0x1ul << UI2C_BRGEN_RCLKSEL_Pos) /*!< UI2C_T::BRGEN: RCLKSEL Mask */ 404 405 #define UI2C_BRGEN_PTCLKSEL_Pos (1) /*!< UI2C_T::BRGEN: PTCLKSEL Position */ 406 #define UI2C_BRGEN_PTCLKSEL_Msk (0x1ul << UI2C_BRGEN_PTCLKSEL_Pos) /*!< UI2C_T::BRGEN: PTCLKSEL Mask */ 407 408 #define UI2C_BRGEN_SPCLKSEL_Pos (2) /*!< UI2C_T::BRGEN: SPCLKSEL Position */ 409 #define UI2C_BRGEN_SPCLKSEL_Msk (0x3ul << UI2C_BRGEN_SPCLKSEL_Pos) /*!< UI2C_T::BRGEN: SPCLKSEL Mask */ 410 411 #define UI2C_BRGEN_TMCNTEN_Pos (4) /*!< UI2C_T::BRGEN: TMCNTEN Position */ 412 #define UI2C_BRGEN_TMCNTEN_Msk (0x1ul << UI2C_BRGEN_TMCNTEN_Pos) /*!< UI2C_T::BRGEN: TMCNTEN Mask */ 413 414 #define UI2C_BRGEN_TMCNTSRC_Pos (5) /*!< UI2C_T::BRGEN: TMCNTSRC Position */ 415 #define UI2C_BRGEN_TMCNTSRC_Msk (0x1ul << UI2C_BRGEN_TMCNTSRC_Pos) /*!< UI2C_T::BRGEN: TMCNTSRC Mask */ 416 417 #define UI2C_BRGEN_PDSCNT_Pos (8) /*!< UI2C_T::BRGEN: PDSCNT Position */ 418 #define UI2C_BRGEN_PDSCNT_Msk (0x3ul << UI2C_BRGEN_PDSCNT_Pos) /*!< UI2C_T::BRGEN: PDSCNT Mask */ 419 420 #define UI2C_BRGEN_DSCNT_Pos (10) /*!< UI2C_T::BRGEN: DSCNT Position */ 421 #define UI2C_BRGEN_DSCNT_Msk (0x1ful << UI2C_BRGEN_DSCNT_Pos) /*!< UI2C_T::BRGEN: DSCNT Mask */ 422 423 #define UI2C_BRGEN_CLKDIV_Pos (16) /*!< UI2C_T::BRGEN: CLKDIV Position */ 424 #define UI2C_BRGEN_CLKDIV_Msk (0x3fful << UI2C_BRGEN_CLKDIV_Pos) /*!< UI2C_T::BRGEN: CLKDIV Mask */ 425 426 #define UI2C_LINECTL_LSB_Pos (0) /*!< UI2C_T::LINECTL: LSB Position */ 427 #define UI2C_LINECTL_LSB_Msk (0x1ul << UI2C_LINECTL_LSB_Pos) /*!< UI2C_T::LINECTL: LSB Mask */ 428 429 #define UI2C_LINECTL_DWIDTH_Pos (8) /*!< UI2C_T::LINECTL: DWIDTH Position */ 430 #define UI2C_LINECTL_DWIDTH_Msk (0xful << UI2C_LINECTL_DWIDTH_Pos) /*!< UI2C_T::LINECTL: DWIDTH Mask */ 431 432 #define UI2C_TXDAT_TXDAT_Pos (0) /*!< UI2C_T::TXDAT: TXDAT Position */ 433 #define UI2C_TXDAT_TXDAT_Msk (0xfffful << UI2C_TXDAT_TXDAT_Pos) /*!< UI2C_T::TXDAT: TXDAT Mask */ 434 435 #define UI2C_RXDAT_RXDAT_Pos (0) /*!< UI2C_T::RXDAT: RXDAT Position */ 436 #define UI2C_RXDAT_RXDAT_Msk (0xfffful << UI2C_RXDAT_RXDAT_Pos) /*!< UI2C_T::RXDAT: RXDAT Mask */ 437 438 #define UI2C_DEVADDR0_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR0: DEVADDR Position */ 439 #define UI2C_DEVADDR0_DEVADDR_Msk (0x3fful << UI2C_DEVADDR0_DEVADDR_Pos) /*!< UI2C_T::DEVADDR0: DEVADDR Mask */ 440 441 #define UI2C_DEVADDR1_DEVADDR_Pos (0) /*!< UI2C_T::DEVADDR1: DEVADDR Position */ 442 #define UI2C_DEVADDR1_DEVADDR_Msk (0x3fful << UI2C_DEVADDR1_DEVADDR_Pos) /*!< UI2C_T::DEVADDR1: DEVADDR Mask */ 443 444 #define UI2C_ADDRMSK0_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK0: ADDRMSK Position */ 445 #define UI2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK0_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK0: ADDRMSK Mask */ 446 447 #define UI2C_ADDRMSK1_ADDRMSK_Pos (0) /*!< UI2C_T::ADDRMSK1: ADDRMSK Position */ 448 #define UI2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << UI2C_ADDRMSK1_ADDRMSK_Pos) /*!< UI2C_T::ADDRMSK1: ADDRMSK Mask */ 449 450 #define UI2C_WKCTL_WKEN_Pos (0) /*!< UI2C_T::WKCTL: WKEN Position */ 451 #define UI2C_WKCTL_WKEN_Msk (0x1ul << UI2C_WKCTL_WKEN_Pos) /*!< UI2C_T::WKCTL: WKEN Mask */ 452 453 #define UI2C_WKCTL_WKADDREN_Pos (1) /*!< UI2C_T::WKCTL: WKADDREN Position */ 454 #define UI2C_WKCTL_WKADDREN_Msk (0x1ul << UI2C_WKCTL_WKADDREN_Pos) /*!< UI2C_T::WKCTL: WKADDREN Mask */ 455 456 #define UI2C_WKSTS_WKF_Pos (0) /*!< UI2C_T::WKSTS: WKF Position */ 457 #define UI2C_WKSTS_WKF_Msk (0x1ul << UI2C_WKSTS_WKF_Pos) /*!< UI2C_T::WKSTS: WKF Mask */ 458 459 #define UI2C_PROTCTL_GCFUNC_Pos (0) /*!< UI2C_T::PROTCTL: GCFUNC Position */ 460 #define UI2C_PROTCTL_GCFUNC_Msk (0x1ul << UI2C_PROTCTL_GCFUNC_Pos) /*!< UI2C_T::PROTCTL: GCFUNC Mask */ 461 462 #define UI2C_PROTCTL_AA_Pos (1) /*!< UI2C_T::PROTCTL: AA Position */ 463 #define UI2C_PROTCTL_AA_Msk (0x1ul << UI2C_PROTCTL_AA_Pos) /*!< UI2C_T::PROTCTL: AA Mask */ 464 465 #define UI2C_PROTCTL_STO_Pos (2) /*!< UI2C_T::PROTCTL: STO Position */ 466 #define UI2C_PROTCTL_STO_Msk (0x1ul << UI2C_PROTCTL_STO_Pos) /*!< UI2C_T::PROTCTL: STO Mask */ 467 468 #define UI2C_PROTCTL_STA_Pos (3) /*!< UI2C_T::PROTCTL: STA Position */ 469 #define UI2C_PROTCTL_STA_Msk (0x1ul << UI2C_PROTCTL_STA_Pos) /*!< UI2C_T::PROTCTL: STA Mask */ 470 471 #define UI2C_PROTCTL_ADDR10EN_Pos (4) /*!< UI2C_T::PROTCTL: ADDR10EN Position */ 472 #define UI2C_PROTCTL_ADDR10EN_Msk (0x1ul << UI2C_PROTCTL_ADDR10EN_Pos) /*!< UI2C_T::PROTCTL: ADDR10EN Mask */ 473 474 #define UI2C_PROTCTL_PTRG_Pos (5) /*!< UI2C_T::PROTCTL: PTRG Position */ 475 #define UI2C_PROTCTL_PTRG_Msk (0x1ul << UI2C_PROTCTL_PTRG_Pos) /*!< UI2C_T::PROTCTL: PTRG Mask */ 476 477 #define UI2C_PROTCTL_SCLOUTEN_Pos (8) /*!< UI2C_T::PROTCTL: SCLOUTEN Position */ 478 #define UI2C_PROTCTL_SCLOUTEN_Msk (0x1ul << UI2C_PROTCTL_SCLOUTEN_Pos) /*!< UI2C_T::PROTCTL: SCLOUTEN Mask */ 479 480 #define UI2C_PROTCTL_MONEN_Pos (9) /*!< UI2C_T::PROTCTL: MONEN Position */ 481 #define UI2C_PROTCTL_MONEN_Msk (0x1ul << UI2C_PROTCTL_MONEN_Pos) /*!< UI2C_T::PROTCTL: MONEN Mask */ 482 483 #define UI2C_PROTCTL_TOCNT_Pos (16) /*!< UI2C_T::PROTCTL: TOCNT Position */ 484 #define UI2C_PROTCTL_TOCNT_Msk (0x3fful << UI2C_PROTCTL_TOCNT_Pos) /*!< UI2C_T::PROTCTL: TOCNT Mask */ 485 486 #define UI2C_PROTCTL_PROTEN_Pos (31) /*!< UI2C_T::PROTCTL: PROTEN Position */ 487 #define UI2C_PROTCTL_PROTEN_Msk (0x1ul << UI2C_PROTCTL_PROTEN_Pos) /*!< UI2C_T::PROTCTL: PROTEN Mask */ 488 489 #define UI2C_PROTIEN_TOIEN_Pos (0) /*!< UI2C_T::PROTIEN: TOIEN Position */ 490 #define UI2C_PROTIEN_TOIEN_Msk (0x1ul << UI2C_PROTIEN_TOIEN_Pos) /*!< UI2C_T::PROTIEN: TOIEN Mask */ 491 492 #define UI2C_PROTIEN_STARIEN_Pos (1) /*!< UI2C_T::PROTIEN: STARIEN Position */ 493 #define UI2C_PROTIEN_STARIEN_Msk (0x1ul << UI2C_PROTIEN_STARIEN_Pos) /*!< UI2C_T::PROTIEN: STARIEN Mask */ 494 495 #define UI2C_PROTIEN_STORIEN_Pos (2) /*!< UI2C_T::PROTIEN: STORIEN Position */ 496 #define UI2C_PROTIEN_STORIEN_Msk (0x1ul << UI2C_PROTIEN_STORIEN_Pos) /*!< UI2C_T::PROTIEN: STORIEN Mask */ 497 498 #define UI2C_PROTIEN_NACKIEN_Pos (3) /*!< UI2C_T::PROTIEN: NACKIEN Position */ 499 #define UI2C_PROTIEN_NACKIEN_Msk (0x1ul << UI2C_PROTIEN_NACKIEN_Pos) /*!< UI2C_T::PROTIEN: NACKIEN Mask */ 500 501 #define UI2C_PROTIEN_ARBLOIEN_Pos (4) /*!< UI2C_T::PROTIEN: ARBLOIEN Position */ 502 #define UI2C_PROTIEN_ARBLOIEN_Msk (0x1ul << UI2C_PROTIEN_ARBLOIEN_Pos) /*!< UI2C_T::PROTIEN: ARBLOIEN Mask */ 503 504 #define UI2C_PROTIEN_ERRIEN_Pos (5) /*!< UI2C_T::PROTIEN: ERRIEN Position */ 505 #define UI2C_PROTIEN_ERRIEN_Msk (0x1ul << UI2C_PROTIEN_ERRIEN_Pos) /*!< UI2C_T::PROTIEN: ERRIEN Mask */ 506 507 #define UI2C_PROTIEN_ACKIEN_Pos (6) /*!< UI2C_T::PROTIEN: ACKIEN Position */ 508 #define UI2C_PROTIEN_ACKIEN_Msk (0x1ul << UI2C_PROTIEN_ACKIEN_Pos) /*!< UI2C_T::PROTIEN: ACKIEN Mask */ 509 510 #define UI2C_PROTSTS_TOIF_Pos (5) /*!< UI2C_T::PROTSTS: TOIF Position */ 511 #define UI2C_PROTSTS_TOIF_Msk (0x1ul << UI2C_PROTSTS_TOIF_Pos) /*!< UI2C_T::PROTSTS: TOIF Mask */ 512 513 #define UI2C_PROTSTS_ONBUSY_Pos (6) /*!< UI2C_T::PROTSTS: ONBUSY Position */ 514 #define UI2C_PROTSTS_ONBUSY_Msk (0x1ul << UI2C_PROTSTS_ONBUSY_Pos) /*!< UI2C_T::PROTSTS: ONBUSY Mask */ 515 516 #define UI2C_PROTSTS_STARIF_Pos (8) /*!< UI2C_T::PROTSTS: STARIF Position */ 517 #define UI2C_PROTSTS_STARIF_Msk (0x1ul << UI2C_PROTSTS_STARIF_Pos) /*!< UI2C_T::PROTSTS: STARIF Mask */ 518 519 #define UI2C_PROTSTS_STORIF_Pos (9) /*!< UI2C_T::PROTSTS: STORIF Position */ 520 #define UI2C_PROTSTS_STORIF_Msk (0x1ul << UI2C_PROTSTS_STORIF_Pos) /*!< UI2C_T::PROTSTS: STORIF Mask */ 521 522 #define UI2C_PROTSTS_NACKIF_Pos (10) /*!< UI2C_T::PROTSTS: NACKIF Position */ 523 #define UI2C_PROTSTS_NACKIF_Msk (0x1ul << UI2C_PROTSTS_NACKIF_Pos) /*!< UI2C_T::PROTSTS: NACKIF Mask */ 524 525 #define UI2C_PROTSTS_ARBLOIF_Pos (11) /*!< UI2C_T::PROTSTS: ARBLOIF Position */ 526 #define UI2C_PROTSTS_ARBLOIF_Msk (0x1ul << UI2C_PROTSTS_ARBLOIF_Pos) /*!< UI2C_T::PROTSTS: ARBLOIF Mask */ 527 528 #define UI2C_PROTSTS_ERRIF_Pos (12) /*!< UI2C_T::PROTSTS: ERRIF Position */ 529 #define UI2C_PROTSTS_ERRIF_Msk (0x1ul << UI2C_PROTSTS_ERRIF_Pos) /*!< UI2C_T::PROTSTS: ERRIF Mask */ 530 531 #define UI2C_PROTSTS_ACKIF_Pos (13) /*!< UI2C_T::PROTSTS: ACKIF Position */ 532 #define UI2C_PROTSTS_ACKIF_Msk (0x1ul << UI2C_PROTSTS_ACKIF_Pos) /*!< UI2C_T::PROTSTS: ACKIF Mask */ 533 534 #define UI2C_PROTSTS_SLASEL_Pos (14) /*!< UI2C_T::PROTSTS: SLASEL Position */ 535 #define UI2C_PROTSTS_SLASEL_Msk (0x1ul << UI2C_PROTSTS_SLASEL_Pos) /*!< UI2C_T::PROTSTS: SLASEL Mask */ 536 537 #define UI2C_PROTSTS_SLAREAD_Pos (15) /*!< UI2C_T::PROTSTS: SLAREAD Position */ 538 #define UI2C_PROTSTS_SLAREAD_Msk (0x1ul << UI2C_PROTSTS_SLAREAD_Pos) /*!< UI2C_T::PROTSTS: SLAREAD Mask */ 539 540 #define UI2C_PROTSTS_WKAKDONE_Pos (16) /*!< UI2C_T::PROTSTS: WKAKDONE Position */ 541 #define UI2C_PROTSTS_WKAKDONE_Msk (0x1ul << UI2C_PROTSTS_WKAKDONE_Pos) /*!< UI2C_T::PROTSTS: WKAKDONE Mask */ 542 543 #define UI2C_PROTSTS_WRSTSWK_Pos (17) /*!< UI2C_T::PROTSTS: WRSTSWK Position */ 544 #define UI2C_PROTSTS_WRSTSWK_Msk (0x1ul << UI2C_PROTSTS_WRSTSWK_Pos) /*!< UI2C_T::PROTSTS: WRSTSWK Mask */ 545 546 #define UI2C_PROTSTS_BUSHANG_Pos (18) /*!< UI2C_T::PROTSTS: BUSHANG Position */ 547 #define UI2C_PROTSTS_BUSHANG_Msk (0x1ul << UI2C_PROTSTS_BUSHANG_Pos) /*!< UI2C_T::PROTSTS: BUSHANG Mask */ 548 549 #define UI2C_PROTSTS_ERRARBLO_Pos (19) /*!< UI2C_T::PROTSTS: ERRARBLO Position */ 550 #define UI2C_PROTSTS_ERRARBLO_Msk (0x1ul << UI2C_PROTSTS_ERRARBLO_Pos) /*!< UI2C_T::PROTSTS: ERRARBLO Mask */ 551 552 #define UI2C_ADMAT_ADMAT0_Pos (0) /*!< UI2C_T::ADMAT: ADMAT0 Position */ 553 #define UI2C_ADMAT_ADMAT0_Msk (0x1ul << UI2C_ADMAT_ADMAT0_Pos) /*!< UI2C_T::ADMAT: ADMAT0 Mask */ 554 555 #define UI2C_ADMAT_ADMAT1_Pos (1) /*!< UI2C_T::ADMAT: ADMAT1 Position */ 556 #define UI2C_ADMAT_ADMAT1_Msk (0x1ul << UI2C_ADMAT_ADMAT1_Pos) /*!< UI2C_T::ADMAT: ADMAT1 Mask */ 557 558 #define UI2C_TMCTL_STCTL_Pos (0) /*!< UI2C_T::TMCTL: STCTL Position */ 559 #define UI2C_TMCTL_STCTL_Msk (0x1fful << UI2C_TMCTL_STCTL_Pos) /*!< UI2C_T::TMCTL: STCTL Mask */ 560 561 #define UI2C_TMCTL_HTCTL_Pos (16) /*!< UI2C_T::TMCTL: HTCTL Position */ 562 #define UI2C_TMCTL_HTCTL_Msk (0x1fful << UI2C_TMCTL_HTCTL_Pos) /*!< UI2C_T::TMCTL: HTCTL Mask */ 563 564 /**@}*/ /* UI2C_CONST */ 565 /**@}*/ /* end of UI2C register group */ 566 /**@}*/ /* end of REGISTER group */ 567 568 #endif /* __UI2C_REG_H__ */ 569
