1 /***************************************************************************//** 2 * \file gpio_psoc6_02_124_bga.h 3 * 4 * \brief 5 * PSoC6_02 device GPIO header for 124-BGA package 6 * 7 * \note 8 * Generator version: 1.5.0.1286 9 * 10 ******************************************************************************** 11 * \copyright 12 * Copyright 2016-2019 Cypress Semiconductor Corporation 13 * SPDX-License-Identifier: Apache-2.0 14 * 15 * Licensed under the Apache License, Version 2.0 (the "License"); 16 * you may not use this file except in compliance with the License. 17 * You may obtain a copy of the License at 18 * 19 * http://www.apache.org/licenses/LICENSE-2.0 20 * 21 * Unless required by applicable law or agreed to in writing, software 22 * distributed under the License is distributed on an "AS IS" BASIS, 23 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 24 * See the License for the specific language governing permissions and 25 * limitations under the License. 26 *******************************************************************************/ 27 28 #ifndef _GPIO_PSOC6_02_124_BGA_H_ 29 #define _GPIO_PSOC6_02_124_BGA_H_ 30 31 /* Package type */ 32 enum 33 { 34 CY_GPIO_PACKAGE_QFN, 35 CY_GPIO_PACKAGE_BGA, 36 CY_GPIO_PACKAGE_CSP, 37 CY_GPIO_PACKAGE_WLCSP, 38 CY_GPIO_PACKAGE_LQFP, 39 CY_GPIO_PACKAGE_TQFP, 40 CY_GPIO_PACKAGE_SMT, 41 }; 42 43 #define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_BGA 44 #define CY_GPIO_PIN_COUNT 124u 45 46 /* AMUXBUS Segments */ 47 enum 48 { 49 AMUXBUS_MAIN, 50 AMUXBUS_ADFT0_VDDD, 51 AMUXBUS_NOISY, 52 AMUXBUS_CSD0, 53 AMUXBUS_VDDIO_1, 54 AMUXBUS_CSD1, 55 AMUXBUS_SAR, 56 AMUXBUS_ANALOG_VDDD, 57 AMUXBUS_ANALOG_VDDA, 58 }; 59 60 /* AMUX Splitter Controls */ 61 typedef enum 62 { 63 AMUX_SPLIT_CTL_0 = 0x0000u, /* Left = AMUXBUS_ADFT0_VDDD; Right = AMUXBUS_MAIN */ 64 AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_MAIN; Right = AMUXBUS_NOISY */ 65 AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_NOISY; Right = AMUXBUS_CSD0 */ 66 AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_CSD0 */ 67 AMUX_SPLIT_CTL_4 = 0x0004u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ 68 AMUX_SPLIT_CTL_5 = 0x0005u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ 69 AMUX_SPLIT_CTL_6 = 0x0006u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ 70 AMUX_SPLIT_CTL_7 = 0x0007u /* Left = AMUXBUS_ANALOG_VDDD; Right = AMUXBUS_ANALOG_VDDA */ 71 } cy_en_amux_split_t; 72 73 /* Port List */ 74 /* PORT 0 (GPIO) */ 75 #define P0_0_PORT GPIO_PRT0 76 #define P0_0_PIN 0u 77 #define P0_0_NUM 0u 78 #define P0_0_AMUXSEGMENT AMUXBUS_MAIN 79 #define P0_1_PORT GPIO_PRT0 80 #define P0_1_PIN 1u 81 #define P0_1_NUM 1u 82 #define P0_1_AMUXSEGMENT AMUXBUS_MAIN 83 #define P0_2_PORT GPIO_PRT0 84 #define P0_2_PIN 2u 85 #define P0_2_NUM 2u 86 #define P0_2_AMUXSEGMENT AMUXBUS_MAIN 87 #define P0_3_PORT GPIO_PRT0 88 #define P0_3_PIN 3u 89 #define P0_3_NUM 3u 90 #define P0_3_AMUXSEGMENT AMUXBUS_MAIN 91 #define P0_4_PORT GPIO_PRT0 92 #define P0_4_PIN 4u 93 #define P0_4_NUM 4u 94 #define P0_4_AMUXSEGMENT AMUXBUS_MAIN 95 #define P0_5_PORT GPIO_PRT0 96 #define P0_5_PIN 5u 97 #define P0_5_NUM 5u 98 #define P0_5_AMUXSEGMENT AMUXBUS_MAIN 99 100 /* PORT 1 (GPIO_OVT) */ 101 #define P1_0_PORT GPIO_PRT1 102 #define P1_0_PIN 0u 103 #define P1_0_NUM 0u 104 #define P1_0_AMUXSEGMENT AMUXBUS_NOISY 105 #define P1_1_PORT GPIO_PRT1 106 #define P1_1_PIN 1u 107 #define P1_1_NUM 1u 108 #define P1_1_AMUXSEGMENT AMUXBUS_NOISY 109 #define P1_2_PORT GPIO_PRT1 110 #define P1_2_PIN 2u 111 #define P1_2_NUM 2u 112 #define P1_2_AMUXSEGMENT AMUXBUS_NOISY 113 #define P1_3_PORT GPIO_PRT1 114 #define P1_3_PIN 3u 115 #define P1_3_NUM 3u 116 #define P1_3_AMUXSEGMENT AMUXBUS_NOISY 117 #define P1_4_PORT GPIO_PRT1 118 #define P1_4_PIN 4u 119 #define P1_4_NUM 4u 120 #define P1_4_AMUXSEGMENT AMUXBUS_NOISY 121 #define P1_5_PORT GPIO_PRT1 122 #define P1_5_PIN 5u 123 #define P1_5_NUM 5u 124 #define P1_5_AMUXSEGMENT AMUXBUS_NOISY 125 126 /* PORT 2 (GPIO) */ 127 #define P2_0_PORT GPIO_PRT2 128 #define P2_0_PIN 0u 129 #define P2_0_NUM 0u 130 #define P2_0_AMUXSEGMENT AMUXBUS_NOISY 131 #define P2_1_PORT GPIO_PRT2 132 #define P2_1_PIN 1u 133 #define P2_1_NUM 1u 134 #define P2_1_AMUXSEGMENT AMUXBUS_NOISY 135 #define P2_2_PORT GPIO_PRT2 136 #define P2_2_PIN 2u 137 #define P2_2_NUM 2u 138 #define P2_2_AMUXSEGMENT AMUXBUS_NOISY 139 #define P2_3_PORT GPIO_PRT2 140 #define P2_3_PIN 3u 141 #define P2_3_NUM 3u 142 #define P2_3_AMUXSEGMENT AMUXBUS_NOISY 143 #define P2_4_PORT GPIO_PRT2 144 #define P2_4_PIN 4u 145 #define P2_4_NUM 4u 146 #define P2_4_AMUXSEGMENT AMUXBUS_NOISY 147 #define P2_5_PORT GPIO_PRT2 148 #define P2_5_PIN 5u 149 #define P2_5_NUM 5u 150 #define P2_5_AMUXSEGMENT AMUXBUS_NOISY 151 #define P2_6_PORT GPIO_PRT2 152 #define P2_6_PIN 6u 153 #define P2_6_NUM 6u 154 #define P2_6_AMUXSEGMENT AMUXBUS_NOISY 155 #define P2_7_PORT GPIO_PRT2 156 #define P2_7_PIN 7u 157 #define P2_7_NUM 7u 158 #define P2_7_AMUXSEGMENT AMUXBUS_NOISY 159 160 /* PORT 3 (GPIO) */ 161 #define P3_0_PORT GPIO_PRT3 162 #define P3_0_PIN 0u 163 #define P3_0_NUM 0u 164 #define P3_0_AMUXSEGMENT AMUXBUS_NOISY 165 #define P3_1_PORT GPIO_PRT3 166 #define P3_1_PIN 1u 167 #define P3_1_NUM 1u 168 #define P3_1_AMUXSEGMENT AMUXBUS_NOISY 169 #define P3_2_PORT GPIO_PRT3 170 #define P3_2_PIN 2u 171 #define P3_2_NUM 2u 172 #define P3_2_AMUXSEGMENT AMUXBUS_NOISY 173 #define P3_3_PORT GPIO_PRT3 174 #define P3_3_PIN 3u 175 #define P3_3_NUM 3u 176 #define P3_3_AMUXSEGMENT AMUXBUS_NOISY 177 #define P3_4_PORT GPIO_PRT3 178 #define P3_4_PIN 4u 179 #define P3_4_NUM 4u 180 #define P3_4_AMUXSEGMENT AMUXBUS_NOISY 181 #define P3_5_PORT GPIO_PRT3 182 #define P3_5_PIN 5u 183 #define P3_5_NUM 5u 184 #define P3_5_AMUXSEGMENT AMUXBUS_NOISY 185 186 /* PORT 4 (GPIO) */ 187 #define P4_0_PORT GPIO_PRT4 188 #define P4_0_PIN 0u 189 #define P4_0_NUM 0u 190 #define P4_0_AMUXSEGMENT AMUXBUS_NOISY 191 #define P4_1_PORT GPIO_PRT4 192 #define P4_1_PIN 1u 193 #define P4_1_NUM 1u 194 #define P4_1_AMUXSEGMENT AMUXBUS_NOISY 195 196 /* PORT 5 (GPIO) */ 197 #define P5_0_PORT GPIO_PRT5 198 #define P5_0_PIN 0u 199 #define P5_0_NUM 0u 200 #define P5_0_AMUXSEGMENT AMUXBUS_CSD0 201 #define P5_1_PORT GPIO_PRT5 202 #define P5_1_PIN 1u 203 #define P5_1_NUM 1u 204 #define P5_1_AMUXSEGMENT AMUXBUS_CSD0 205 #define P5_2_PORT GPIO_PRT5 206 #define P5_2_PIN 2u 207 #define P5_2_NUM 2u 208 #define P5_2_AMUXSEGMENT AMUXBUS_CSD0 209 #define P5_3_PORT GPIO_PRT5 210 #define P5_3_PIN 3u 211 #define P5_3_NUM 3u 212 #define P5_3_AMUXSEGMENT AMUXBUS_CSD0 213 #define P5_4_PORT GPIO_PRT5 214 #define P5_4_PIN 4u 215 #define P5_4_NUM 4u 216 #define P5_4_AMUXSEGMENT AMUXBUS_CSD0 217 #define P5_5_PORT GPIO_PRT5 218 #define P5_5_PIN 5u 219 #define P5_5_NUM 5u 220 #define P5_5_AMUXSEGMENT AMUXBUS_CSD0 221 #define P5_6_PORT GPIO_PRT5 222 #define P5_6_PIN 6u 223 #define P5_6_NUM 6u 224 #define P5_6_AMUXSEGMENT AMUXBUS_CSD0 225 #define P5_7_PORT GPIO_PRT5 226 #define P5_7_PIN 7u 227 #define P5_7_NUM 7u 228 #define P5_7_AMUXSEGMENT AMUXBUS_CSD0 229 230 /* PORT 6 (GPIO) */ 231 #define P6_0_PORT GPIO_PRT6 232 #define P6_0_PIN 0u 233 #define P6_0_NUM 0u 234 #define P6_0_AMUXSEGMENT AMUXBUS_CSD0 235 #define P6_1_PORT GPIO_PRT6 236 #define P6_1_PIN 1u 237 #define P6_1_NUM 1u 238 #define P6_1_AMUXSEGMENT AMUXBUS_CSD0 239 #define P6_2_PORT GPIO_PRT6 240 #define P6_2_PIN 2u 241 #define P6_2_NUM 2u 242 #define P6_2_AMUXSEGMENT AMUXBUS_CSD0 243 #define P6_3_PORT GPIO_PRT6 244 #define P6_3_PIN 3u 245 #define P6_3_NUM 3u 246 #define P6_3_AMUXSEGMENT AMUXBUS_CSD0 247 #define P6_4_PORT GPIO_PRT6 248 #define P6_4_PIN 4u 249 #define P6_4_NUM 4u 250 #define P6_4_AMUXSEGMENT AMUXBUS_CSD0 251 #define P6_5_PORT GPIO_PRT6 252 #define P6_5_PIN 5u 253 #define P6_5_NUM 5u 254 #define P6_5_AMUXSEGMENT AMUXBUS_CSD0 255 #define P6_6_PORT GPIO_PRT6 256 #define P6_6_PIN 6u 257 #define P6_6_NUM 6u 258 #define P6_6_AMUXSEGMENT AMUXBUS_CSD0 259 #define P6_7_PORT GPIO_PRT6 260 #define P6_7_PIN 7u 261 #define P6_7_NUM 7u 262 #define P6_7_AMUXSEGMENT AMUXBUS_CSD0 263 264 /* PORT 7 (GPIO) */ 265 #define P7_0_PORT GPIO_PRT7 266 #define P7_0_PIN 0u 267 #define P7_0_NUM 0u 268 #define P7_0_AMUXSEGMENT AMUXBUS_CSD0 269 #define P7_1_PORT GPIO_PRT7 270 #define P7_1_PIN 1u 271 #define P7_1_NUM 1u 272 #define P7_1_AMUXSEGMENT AMUXBUS_CSD0 273 #define P7_2_PORT GPIO_PRT7 274 #define P7_2_PIN 2u 275 #define P7_2_NUM 2u 276 #define P7_2_AMUXSEGMENT AMUXBUS_CSD0 277 #define P7_3_PORT GPIO_PRT7 278 #define P7_3_PIN 3u 279 #define P7_3_NUM 3u 280 #define P7_3_AMUXSEGMENT AMUXBUS_CSD0 281 #define P7_4_PORT GPIO_PRT7 282 #define P7_4_PIN 4u 283 #define P7_4_NUM 4u 284 #define P7_4_AMUXSEGMENT AMUXBUS_CSD0 285 #define P7_5_PORT GPIO_PRT7 286 #define P7_5_PIN 5u 287 #define P7_5_NUM 5u 288 #define P7_5_AMUXSEGMENT AMUXBUS_CSD0 289 #define P7_6_PORT GPIO_PRT7 290 #define P7_6_PIN 6u 291 #define P7_6_NUM 6u 292 #define P7_6_AMUXSEGMENT AMUXBUS_CSD0 293 #define P7_7_PORT GPIO_PRT7 294 #define P7_7_PIN 7u 295 #define P7_7_NUM 7u 296 #define P7_7_AMUXSEGMENT AMUXBUS_CSD0 297 298 /* PORT 8 (GPIO) */ 299 #define P8_0_PORT GPIO_PRT8 300 #define P8_0_PIN 0u 301 #define P8_0_NUM 0u 302 #define P8_0_AMUXSEGMENT AMUXBUS_CSD0 303 #define P8_1_PORT GPIO_PRT8 304 #define P8_1_PIN 1u 305 #define P8_1_NUM 1u 306 #define P8_1_AMUXSEGMENT AMUXBUS_CSD0 307 #define P8_2_PORT GPIO_PRT8 308 #define P8_2_PIN 2u 309 #define P8_2_NUM 2u 310 #define P8_2_AMUXSEGMENT AMUXBUS_CSD0 311 #define P8_3_PORT GPIO_PRT8 312 #define P8_3_PIN 3u 313 #define P8_3_NUM 3u 314 #define P8_3_AMUXSEGMENT AMUXBUS_CSD0 315 #define P8_4_PORT GPIO_PRT8 316 #define P8_4_PIN 4u 317 #define P8_4_NUM 4u 318 #define P8_4_AMUXSEGMENT AMUXBUS_CSD0 319 #define P8_5_PORT GPIO_PRT8 320 #define P8_5_PIN 5u 321 #define P8_5_NUM 5u 322 #define P8_5_AMUXSEGMENT AMUXBUS_CSD0 323 #define P8_6_PORT GPIO_PRT8 324 #define P8_6_PIN 6u 325 #define P8_6_NUM 6u 326 #define P8_6_AMUXSEGMENT AMUXBUS_CSD0 327 #define P8_7_PORT GPIO_PRT8 328 #define P8_7_PIN 7u 329 #define P8_7_NUM 7u 330 #define P8_7_AMUXSEGMENT AMUXBUS_CSD0 331 332 /* PORT 9 (GPIO) */ 333 #define P9_0_PORT GPIO_PRT9 334 #define P9_0_PIN 0u 335 #define P9_0_NUM 0u 336 #define P9_0_AMUXSEGMENT AMUXBUS_SAR 337 #define P9_1_PORT GPIO_PRT9 338 #define P9_1_PIN 1u 339 #define P9_1_NUM 1u 340 #define P9_1_AMUXSEGMENT AMUXBUS_SAR 341 #define P9_2_PORT GPIO_PRT9 342 #define P9_2_PIN 2u 343 #define P9_2_NUM 2u 344 #define P9_2_AMUXSEGMENT AMUXBUS_SAR 345 #define P9_3_PORT GPIO_PRT9 346 #define P9_3_PIN 3u 347 #define P9_3_NUM 3u 348 #define P9_3_AMUXSEGMENT AMUXBUS_SAR 349 #define P9_4_PORT GPIO_PRT9 350 #define P9_4_PIN 4u 351 #define P9_4_NUM 4u 352 #define P9_4_AMUXSEGMENT AMUXBUS_SAR 353 #define P9_5_PORT GPIO_PRT9 354 #define P9_5_PIN 5u 355 #define P9_5_NUM 5u 356 #define P9_5_AMUXSEGMENT AMUXBUS_SAR 357 #define P9_6_PORT GPIO_PRT9 358 #define P9_6_PIN 6u 359 #define P9_6_NUM 6u 360 #define P9_6_AMUXSEGMENT AMUXBUS_SAR 361 #define P9_7_PORT GPIO_PRT9 362 #define P9_7_PIN 7u 363 #define P9_7_NUM 7u 364 #define P9_7_AMUXSEGMENT AMUXBUS_SAR 365 366 /* PORT 10 (GPIO) */ 367 #define P10_0_PORT GPIO_PRT10 368 #define P10_0_PIN 0u 369 #define P10_0_NUM 0u 370 #define P10_0_AMUXSEGMENT AMUXBUS_SAR 371 #define P10_1_PORT GPIO_PRT10 372 #define P10_1_PIN 1u 373 #define P10_1_NUM 1u 374 #define P10_1_AMUXSEGMENT AMUXBUS_SAR 375 #define P10_2_PORT GPIO_PRT10 376 #define P10_2_PIN 2u 377 #define P10_2_NUM 2u 378 #define P10_2_AMUXSEGMENT AMUXBUS_SAR 379 #define P10_3_PORT GPIO_PRT10 380 #define P10_3_PIN 3u 381 #define P10_3_NUM 3u 382 #define P10_3_AMUXSEGMENT AMUXBUS_SAR 383 #define P10_4_PORT GPIO_PRT10 384 #define P10_4_PIN 4u 385 #define P10_4_NUM 4u 386 #define P10_4_AMUXSEGMENT AMUXBUS_SAR 387 #define P10_5_PORT GPIO_PRT10 388 #define P10_5_PIN 5u 389 #define P10_5_NUM 5u 390 #define P10_5_AMUXSEGMENT AMUXBUS_SAR 391 #define P10_6_PORT GPIO_PRT10 392 #define P10_6_PIN 6u 393 #define P10_6_NUM 6u 394 #define P10_6_AMUXSEGMENT AMUXBUS_SAR 395 #define P10_7_PORT GPIO_PRT10 396 #define P10_7_PIN 7u 397 #define P10_7_NUM 7u 398 #define P10_7_AMUXSEGMENT AMUXBUS_SAR 399 400 /* PORT 11 (GPIO) */ 401 #define P11_0_PORT GPIO_PRT11 402 #define P11_0_PIN 0u 403 #define P11_0_NUM 0u 404 #define P11_0_AMUXSEGMENT AMUXBUS_MAIN 405 #define P11_1_PORT GPIO_PRT11 406 #define P11_1_PIN 1u 407 #define P11_1_NUM 1u 408 #define P11_1_AMUXSEGMENT AMUXBUS_MAIN 409 #define P11_2_PORT GPIO_PRT11 410 #define P11_2_PIN 2u 411 #define P11_2_NUM 2u 412 #define P11_2_AMUXSEGMENT AMUXBUS_MAIN 413 #define P11_3_PORT GPIO_PRT11 414 #define P11_3_PIN 3u 415 #define P11_3_NUM 3u 416 #define P11_3_AMUXSEGMENT AMUXBUS_MAIN 417 #define P11_4_PORT GPIO_PRT11 418 #define P11_4_PIN 4u 419 #define P11_4_NUM 4u 420 #define P11_4_AMUXSEGMENT AMUXBUS_MAIN 421 #define P11_5_PORT GPIO_PRT11 422 #define P11_5_PIN 5u 423 #define P11_5_NUM 5u 424 #define P11_5_AMUXSEGMENT AMUXBUS_MAIN 425 #define P11_6_PORT GPIO_PRT11 426 #define P11_6_PIN 6u 427 #define P11_6_NUM 6u 428 #define P11_6_AMUXSEGMENT AMUXBUS_MAIN 429 #define P11_7_PORT GPIO_PRT11 430 #define P11_7_PIN 7u 431 #define P11_7_NUM 7u 432 #define P11_7_AMUXSEGMENT AMUXBUS_MAIN 433 434 /* PORT 12 (GPIO) */ 435 #define P12_0_PORT GPIO_PRT12 436 #define P12_0_PIN 0u 437 #define P12_0_NUM 0u 438 #define P12_0_AMUXSEGMENT AMUXBUS_MAIN 439 #define P12_1_PORT GPIO_PRT12 440 #define P12_1_PIN 1u 441 #define P12_1_NUM 1u 442 #define P12_1_AMUXSEGMENT AMUXBUS_MAIN 443 #define P12_2_PORT GPIO_PRT12 444 #define P12_2_PIN 2u 445 #define P12_2_NUM 2u 446 #define P12_2_AMUXSEGMENT AMUXBUS_MAIN 447 #define P12_3_PORT GPIO_PRT12 448 #define P12_3_PIN 3u 449 #define P12_3_NUM 3u 450 #define P12_3_AMUXSEGMENT AMUXBUS_MAIN 451 #define P12_4_PORT GPIO_PRT12 452 #define P12_4_PIN 4u 453 #define P12_4_NUM 4u 454 #define P12_4_AMUXSEGMENT AMUXBUS_MAIN 455 #define P12_5_PORT GPIO_PRT12 456 #define P12_5_PIN 5u 457 #define P12_5_NUM 5u 458 #define P12_5_AMUXSEGMENT AMUXBUS_MAIN 459 #define P12_6_PORT GPIO_PRT12 460 #define P12_6_PIN 6u 461 #define P12_6_NUM 6u 462 #define P12_6_AMUXSEGMENT AMUXBUS_MAIN 463 #define P12_7_PORT GPIO_PRT12 464 #define P12_7_PIN 7u 465 #define P12_7_NUM 7u 466 #define P12_7_AMUXSEGMENT AMUXBUS_MAIN 467 468 /* PORT 13 (GPIO) */ 469 #define P13_0_PORT GPIO_PRT13 470 #define P13_0_PIN 0u 471 #define P13_0_NUM 0u 472 #define P13_0_AMUXSEGMENT AMUXBUS_MAIN 473 #define P13_1_PORT GPIO_PRT13 474 #define P13_1_PIN 1u 475 #define P13_1_NUM 1u 476 #define P13_1_AMUXSEGMENT AMUXBUS_MAIN 477 #define P13_2_PORT GPIO_PRT13 478 #define P13_2_PIN 2u 479 #define P13_2_NUM 2u 480 #define P13_2_AMUXSEGMENT AMUXBUS_MAIN 481 #define P13_3_PORT GPIO_PRT13 482 #define P13_3_PIN 3u 483 #define P13_3_NUM 3u 484 #define P13_3_AMUXSEGMENT AMUXBUS_MAIN 485 #define P13_4_PORT GPIO_PRT13 486 #define P13_4_PIN 4u 487 #define P13_4_NUM 4u 488 #define P13_4_AMUXSEGMENT AMUXBUS_MAIN 489 #define P13_5_PORT GPIO_PRT13 490 #define P13_5_PIN 5u 491 #define P13_5_NUM 5u 492 #define P13_5_AMUXSEGMENT AMUXBUS_MAIN 493 #define P13_6_PORT GPIO_PRT13 494 #define P13_6_PIN 6u 495 #define P13_6_NUM 6u 496 #define P13_6_AMUXSEGMENT AMUXBUS_MAIN 497 #define P13_7_PORT GPIO_PRT13 498 #define P13_7_PIN 7u 499 #define P13_7_NUM 7u 500 #define P13_7_AMUXSEGMENT AMUXBUS_MAIN 501 502 /* PORT 14 (AUX) */ 503 #define USBDP_PORT GPIO_PRT14 504 #define USBDP_PIN 0u 505 #define USBDP_NUM 0u 506 #define USBDP_AMUXSEGMENT AMUXBUS_NOISY 507 #define USBDM_PORT GPIO_PRT14 508 #define USBDM_PIN 1u 509 #define USBDM_NUM 1u 510 #define USBDM_AMUXSEGMENT AMUXBUS_NOISY 511 512 /* Analog Connections */ 513 #define CSD_CMODPADD_PORT 7u 514 #define CSD_CMODPADD_PIN 1u 515 #define CSD_CMODPADS_PORT 7u 516 #define CSD_CMODPADS_PIN 1u 517 #define CSD_CSH_TANKPADD_PORT 7u 518 #define CSD_CSH_TANKPADD_PIN 2u 519 #define CSD_CSH_TANKPADS_PORT 7u 520 #define CSD_CSH_TANKPADS_PIN 2u 521 #define CSD_CSHIELDPADS_PORT 7u 522 #define CSD_CSHIELDPADS_PIN 7u 523 #define CSD_VREF_EXT_PORT 7u 524 #define CSD_VREF_EXT_PIN 3u 525 #define IOSS_ADFT0_NET_PORT 10u 526 #define IOSS_ADFT0_NET_PIN 0u 527 #define IOSS_ADFT1_NET_PORT 10u 528 #define IOSS_ADFT1_NET_PIN 1u 529 #define LPCOMP_INN_COMP0_PORT 5u 530 #define LPCOMP_INN_COMP0_PIN 7u 531 #define LPCOMP_INN_COMP1_PORT 6u 532 #define LPCOMP_INN_COMP1_PIN 3u 533 #define LPCOMP_INP_COMP0_PORT 5u 534 #define LPCOMP_INP_COMP0_PIN 6u 535 #define LPCOMP_INP_COMP1_PORT 6u 536 #define LPCOMP_INP_COMP1_PIN 2u 537 #define PASS_AREF_EXT_VREF_PORT 9u 538 #define PASS_AREF_EXT_VREF_PIN 7u 539 #define PASS_SARMUX_PADS0_PORT 10u 540 #define PASS_SARMUX_PADS0_PIN 0u 541 #define PASS_SARMUX_PADS1_PORT 10u 542 #define PASS_SARMUX_PADS1_PIN 1u 543 #define PASS_SARMUX_PADS2_PORT 10u 544 #define PASS_SARMUX_PADS2_PIN 2u 545 #define PASS_SARMUX_PADS3_PORT 10u 546 #define PASS_SARMUX_PADS3_PIN 3u 547 #define PASS_SARMUX_PADS4_PORT 10u 548 #define PASS_SARMUX_PADS4_PIN 4u 549 #define PASS_SARMUX_PADS5_PORT 10u 550 #define PASS_SARMUX_PADS5_PIN 5u 551 #define PASS_SARMUX_PADS6_PORT 10u 552 #define PASS_SARMUX_PADS6_PIN 6u 553 #define PASS_SARMUX_PADS7_PORT 10u 554 #define PASS_SARMUX_PADS7_PIN 7u 555 #define SRSS_ADFT_PIN0_PORT 10u 556 #define SRSS_ADFT_PIN0_PIN 0u 557 #define SRSS_ADFT_PIN1_PORT 10u 558 #define SRSS_ADFT_PIN1_PIN 1u 559 #define SRSS_ECO_IN_PORT 12u 560 #define SRSS_ECO_IN_PIN 6u 561 #define SRSS_ECO_OUT_PORT 12u 562 #define SRSS_ECO_OUT_PIN 7u 563 #define SRSS_WCO_IN_PORT 0u 564 #define SRSS_WCO_IN_PIN 0u 565 #define SRSS_WCO_OUT_PORT 0u 566 #define SRSS_WCO_OUT_PIN 1u 567 568 /* HSIOM Connections */ 569 typedef enum 570 { 571 /* Generic HSIOM connections */ 572 HSIOM_SEL_GPIO = 0, /* GPIO controls 'out' */ 573 HSIOM_SEL_GPIO_DSI = 1, /* GPIO controls 'out', DSI controls 'output enable' */ 574 HSIOM_SEL_DSI_DSI = 2, /* DSI controls 'out' and 'output enable' */ 575 HSIOM_SEL_DSI_GPIO = 3, /* DSI controls 'out', GPIO controls 'output enable' */ 576 HSIOM_SEL_AMUXA = 4, /* Analog mux bus A */ 577 HSIOM_SEL_AMUXB = 5, /* Analog mux bus B */ 578 HSIOM_SEL_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 579 HSIOM_SEL_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 580 HSIOM_SEL_ACT_0 = 8, /* Active functionality 0 */ 581 HSIOM_SEL_ACT_1 = 9, /* Active functionality 1 */ 582 HSIOM_SEL_ACT_2 = 10, /* Active functionality 2 */ 583 HSIOM_SEL_ACT_3 = 11, /* Active functionality 3 */ 584 HSIOM_SEL_DS_0 = 12, /* DeepSleep functionality 0 */ 585 HSIOM_SEL_DS_1 = 13, /* DeepSleep functionality 1 */ 586 HSIOM_SEL_DS_2 = 14, /* DeepSleep functionality 2 */ 587 HSIOM_SEL_DS_3 = 15, /* DeepSleep functionality 3 */ 588 HSIOM_SEL_ACT_4 = 16, /* Active functionality 4 */ 589 HSIOM_SEL_ACT_5 = 17, /* Active functionality 5 */ 590 HSIOM_SEL_ACT_6 = 18, /* Active functionality 6 */ 591 HSIOM_SEL_ACT_7 = 19, /* Active functionality 7 */ 592 HSIOM_SEL_ACT_8 = 20, /* Active functionality 8 */ 593 HSIOM_SEL_ACT_9 = 21, /* Active functionality 9 */ 594 HSIOM_SEL_ACT_10 = 22, /* Active functionality 10 */ 595 HSIOM_SEL_ACT_11 = 23, /* Active functionality 11 */ 596 HSIOM_SEL_ACT_12 = 24, /* Active functionality 12 */ 597 HSIOM_SEL_ACT_13 = 25, /* Active functionality 13 */ 598 HSIOM_SEL_ACT_14 = 26, /* Active functionality 14 */ 599 HSIOM_SEL_ACT_15 = 27, /* Active functionality 15 */ 600 HSIOM_SEL_DS_4 = 28, /* DeepSleep functionality 4 */ 601 HSIOM_SEL_DS_5 = 29, /* DeepSleep functionality 5 */ 602 HSIOM_SEL_DS_6 = 30, /* DeepSleep functionality 6 */ 603 HSIOM_SEL_DS_7 = 31, /* DeepSleep functionality 7 */ 604 605 /* P0.0 */ 606 P0_0_GPIO = 0, /* GPIO controls 'out' */ 607 P0_0_AMUXA = 4, /* Analog mux bus A */ 608 P0_0_AMUXB = 5, /* Analog mux bus B */ 609 P0_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 610 P0_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 611 P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ 612 P0_0_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:0 */ 613 P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ 614 P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ 615 P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ 616 P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ 617 P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ 618 P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ 619 P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ 620 621 /* P0.1 */ 622 P0_1_GPIO = 0, /* GPIO controls 'out' */ 623 P0_1_AMUXA = 4, /* Analog mux bus A */ 624 P0_1_AMUXB = 5, /* Analog mux bus B */ 625 P0_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 626 P0_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 627 P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ 628 P0_1_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:0 */ 629 P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ 630 P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ 631 P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ 632 P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ 633 P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ 634 P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ 635 P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ 636 637 /* P0.2 */ 638 P0_2_GPIO = 0, /* GPIO controls 'out' */ 639 P0_2_AMUXA = 4, /* Analog mux bus A */ 640 P0_2_AMUXB = 5, /* Analog mux bus B */ 641 P0_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 642 P0_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 643 P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ 644 P0_2_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:0 */ 645 P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ 646 P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ 647 P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ 648 P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ 649 P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ 650 P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ 651 P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ 652 653 /* P0.3 */ 654 P0_3_GPIO = 0, /* GPIO controls 'out' */ 655 P0_3_AMUXA = 4, /* Analog mux bus A */ 656 P0_3_AMUXB = 5, /* Analog mux bus B */ 657 P0_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 658 P0_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 659 P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ 660 P0_3_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:0 */ 661 P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ 662 P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ 663 P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ 664 P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ 665 P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ 666 P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ 667 P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ 668 669 /* P0.4 */ 670 P0_4_GPIO = 0, /* GPIO controls 'out' */ 671 P0_4_AMUXA = 4, /* Analog mux bus A */ 672 P0_4_AMUXB = 5, /* Analog mux bus B */ 673 P0_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 674 P0_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 675 P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ 676 P0_4_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:0 */ 677 P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ 678 P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ 679 P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ 680 P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ 681 P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ 682 P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ 683 P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ 684 685 /* P0.5 */ 686 P0_5_GPIO = 0, /* GPIO controls 'out' */ 687 P0_5_AMUXA = 4, /* Analog mux bus A */ 688 P0_5_AMUXB = 5, /* Analog mux bus B */ 689 P0_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 690 P0_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 691 P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ 692 P0_5_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:0 */ 693 P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ 694 P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ 695 P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ 696 P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ 697 P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ 698 P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ 699 P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ 700 P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ 701 702 /* P1.0 */ 703 P1_0_GPIO = 0, /* GPIO controls 'out' */ 704 P1_0_AMUXA = 4, /* Analog mux bus A */ 705 P1_0_AMUXB = 5, /* Analog mux bus B */ 706 P1_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 707 P1_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 708 P1_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ 709 P1_0_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:0 */ 710 P1_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:6 */ 711 P1_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:6 */ 712 P1_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ 713 P1_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ 714 P1_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:0 */ 715 P1_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:0 */ 716 P1_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:0 */ 717 P1_0_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ 718 719 /* P1.1 */ 720 P1_1_GPIO = 0, /* GPIO controls 'out' */ 721 P1_1_AMUXA = 4, /* Analog mux bus A */ 722 P1_1_AMUXB = 5, /* Analog mux bus B */ 723 P1_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 724 P1_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 725 P1_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ 726 P1_1_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:0 */ 727 P1_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:7 */ 728 P1_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:7 */ 729 P1_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ 730 P1_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ 731 P1_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:0 */ 732 P1_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:0 */ 733 P1_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:0 */ 734 P1_1_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ 735 736 /* P1.2 */ 737 P1_2_GPIO = 0, /* GPIO controls 'out' */ 738 P1_2_AMUXA = 4, /* Analog mux bus A */ 739 P1_2_AMUXB = 5, /* Analog mux bus B */ 740 P1_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 741 P1_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 742 P1_2_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:4 */ 743 P1_2_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:1 */ 744 P1_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:8 */ 745 P1_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:8 */ 746 P1_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ 747 P1_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ 748 P1_2_SCB7_UART_RTS = 18, /* Digital Active - scb[7].uart_rts:0 */ 749 P1_2_SCB7_SPI_CLK = 20, /* Digital Active - scb[7].spi_clk:0 */ 750 751 /* P1.3 */ 752 P1_3_GPIO = 0, /* GPIO controls 'out' */ 753 P1_3_AMUXA = 4, /* Analog mux bus A */ 754 P1_3_AMUXB = 5, /* Analog mux bus B */ 755 P1_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 756 P1_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 757 P1_3_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:4 */ 758 P1_3_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:1 */ 759 P1_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ 760 P1_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ 761 P1_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ 762 P1_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ 763 P1_3_SCB7_UART_CTS = 18, /* Digital Active - scb[7].uart_cts:0 */ 764 P1_3_SCB7_SPI_SELECT0 = 20, /* Digital Active - scb[7].spi_select0:0 */ 765 766 /* P1.4 */ 767 P1_4_GPIO = 0, /* GPIO controls 'out' */ 768 P1_4_AMUXA = 4, /* Analog mux bus A */ 769 P1_4_AMUXB = 5, /* Analog mux bus B */ 770 P1_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 771 P1_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 772 P1_4_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:4 */ 773 P1_4_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:1 */ 774 P1_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ 775 P1_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ 776 P1_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ 777 P1_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ 778 P1_4_SCB7_SPI_SELECT1 = 20, /* Digital Active - scb[7].spi_select1:0 */ 779 780 /* P1.5 */ 781 P1_5_GPIO = 0, /* GPIO controls 'out' */ 782 P1_5_AMUXA = 4, /* Analog mux bus A */ 783 P1_5_AMUXB = 5, /* Analog mux bus B */ 784 P1_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 785 P1_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 786 P1_5_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:4 */ 787 P1_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:1 */ 788 P1_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ 789 P1_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ 790 P1_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ 791 P1_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ 792 P1_5_SCB7_SPI_SELECT2 = 20, /* Digital Active - scb[7].spi_select2:0 */ 793 794 /* USBDM */ 795 USBDM_GPIO = 0, /* GPIO controls 'out' */ 796 797 /* USBDP */ 798 USBDP_GPIO = 0, /* GPIO controls 'out' */ 799 800 /* P2.0 */ 801 P2_0_GPIO = 0, /* GPIO controls 'out' */ 802 P2_0_AMUXA = 4, /* Analog mux bus A */ 803 P2_0_AMUXB = 5, /* Analog mux bus B */ 804 P2_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 805 P2_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 806 P2_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:4 */ 807 P2_0_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:1 */ 808 P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ 809 P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ 810 P2_0_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ 811 P2_0_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ 812 P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ 813 P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ 814 P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ 815 P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ 816 P2_0_SDHC0_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[0].card_dat_3to0[0] */ 817 818 /* P2.1 */ 819 P2_1_GPIO = 0, /* GPIO controls 'out' */ 820 P2_1_AMUXA = 4, /* Analog mux bus A */ 821 P2_1_AMUXB = 5, /* Analog mux bus B */ 822 P2_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 823 P2_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 824 P2_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:4 */ 825 P2_1_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:1 */ 826 P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ 827 P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ 828 P2_1_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ 829 P2_1_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ 830 P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ 831 P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ 832 P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ 833 P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ 834 P2_1_SDHC0_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[0].card_dat_3to0[1] */ 835 836 /* P2.2 */ 837 P2_2_GPIO = 0, /* GPIO controls 'out' */ 838 P2_2_AMUXA = 4, /* Analog mux bus A */ 839 P2_2_AMUXB = 5, /* Analog mux bus B */ 840 P2_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 841 P2_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 842 P2_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:4 */ 843 P2_2_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:1 */ 844 P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ 845 P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ 846 P2_2_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ 847 P2_2_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ 848 P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ 849 P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ 850 P2_2_SDHC0_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[0].card_dat_3to0[2] */ 851 852 /* P2.3 */ 853 P2_3_GPIO = 0, /* GPIO controls 'out' */ 854 P2_3_AMUXA = 4, /* Analog mux bus A */ 855 P2_3_AMUXB = 5, /* Analog mux bus B */ 856 P2_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 857 P2_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 858 P2_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:4 */ 859 P2_3_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:1 */ 860 P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ 861 P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ 862 P2_3_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ 863 P2_3_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ 864 P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ 865 P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ 866 P2_3_SDHC0_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[0].card_dat_3to0[3] */ 867 868 /* P2.4 */ 869 P2_4_GPIO = 0, /* GPIO controls 'out' */ 870 P2_4_AMUXA = 4, /* Analog mux bus A */ 871 P2_4_AMUXB = 5, /* Analog mux bus B */ 872 P2_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 873 P2_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 874 P2_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ 875 P2_4_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:1 */ 876 P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ 877 P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ 878 P2_4_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ 879 P2_4_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ 880 P2_4_SCB9_UART_RX = 18, /* Digital Active - scb[9].uart_rx:0 */ 881 P2_4_SCB9_I2C_SCL = 19, /* Digital Active - scb[9].i2c_scl:0 */ 882 P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ 883 P2_4_SDHC0_CARD_CMD = 26, /* Digital Active - sdhc[0].card_cmd */ 884 885 /* P2.5 */ 886 P2_5_GPIO = 0, /* GPIO controls 'out' */ 887 P2_5_AMUXA = 4, /* Analog mux bus A */ 888 P2_5_AMUXB = 5, /* Analog mux bus B */ 889 P2_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 890 P2_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 891 P2_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ 892 P2_5_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:1 */ 893 P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ 894 P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ 895 P2_5_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ 896 P2_5_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ 897 P2_5_SCB9_UART_TX = 18, /* Digital Active - scb[9].uart_tx:0 */ 898 P2_5_SCB9_I2C_SDA = 19, /* Digital Active - scb[9].i2c_sda:0 */ 899 P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ 900 P2_5_SDHC0_CLK_CARD = 26, /* Digital Active - sdhc[0].clk_card */ 901 902 /* P2.6 */ 903 P2_6_GPIO = 0, /* GPIO controls 'out' */ 904 P2_6_AMUXA = 4, /* Analog mux bus A */ 905 P2_6_AMUXB = 5, /* Analog mux bus B */ 906 P2_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 907 P2_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 908 P2_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ 909 P2_6_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:1 */ 910 P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ 911 P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ 912 P2_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ 913 P2_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ 914 P2_6_SCB9_UART_RTS = 18, /* Digital Active - scb[9].uart_rts:0 */ 915 P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ 916 P2_6_SDHC0_CARD_DETECT_N = 26, /* Digital Active - sdhc[0].card_detect_n */ 917 918 /* P2.7 */ 919 P2_7_GPIO = 0, /* GPIO controls 'out' */ 920 P2_7_AMUXA = 4, /* Analog mux bus A */ 921 P2_7_AMUXB = 5, /* Analog mux bus B */ 922 P2_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 923 P2_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 924 P2_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ 925 P2_7_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:1 */ 926 P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ 927 P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ 928 P2_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ 929 P2_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ 930 P2_7_SCB9_UART_CTS = 18, /* Digital Active - scb[9].uart_cts:0 */ 931 P2_7_SDHC0_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[0].card_mech_write_prot */ 932 933 /* P3.0 */ 934 P3_0_GPIO = 0, /* GPIO controls 'out' */ 935 P3_0_AMUXA = 4, /* Analog mux bus A */ 936 P3_0_AMUXB = 5, /* Analog mux bus B */ 937 P3_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 938 P3_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 939 P3_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:5 */ 940 P3_0_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:1 */ 941 P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ 942 P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ 943 P3_0_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:0 */ 944 P3_0_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:0 */ 945 P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ 946 P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ 947 P3_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:1 */ 948 P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ 949 P3_0_SDHC0_IO_VOLT_SEL = 26, /* Digital Active - sdhc[0].io_volt_sel */ 950 951 /* P3.1 */ 952 P3_1_GPIO = 0, /* GPIO controls 'out' */ 953 P3_1_AMUXA = 4, /* Analog mux bus A */ 954 P3_1_AMUXB = 5, /* Analog mux bus B */ 955 P3_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 956 P3_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 957 P3_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:5 */ 958 P3_1_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:1 */ 959 P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:21 */ 960 P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:21 */ 961 P3_1_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:0 */ 962 P3_1_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:0 */ 963 P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ 964 P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ 965 P3_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:1 */ 966 P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ 967 P3_1_SDHC0_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[0].card_if_pwr_en */ 968 969 /* P3.2 */ 970 P3_2_GPIO = 0, /* GPIO controls 'out' */ 971 P3_2_AMUXA = 4, /* Analog mux bus A */ 972 P3_2_AMUXB = 5, /* Analog mux bus B */ 973 P3_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 974 P3_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 975 P3_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ 976 P3_2_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:1 */ 977 P3_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ 978 P3_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ 979 P3_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ 980 P3_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ 981 P3_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:1 */ 982 P3_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:1 */ 983 984 /* P3.3 */ 985 P3_3_GPIO = 0, /* GPIO controls 'out' */ 986 P3_3_AMUXA = 4, /* Analog mux bus A */ 987 P3_3_AMUXB = 5, /* Analog mux bus B */ 988 P3_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 989 P3_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 990 P3_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ 991 P3_3_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:1 */ 992 P3_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ 993 P3_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ 994 P3_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ 995 P3_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ 996 P3_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:1 */ 997 P3_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:1 */ 998 999 /* P3.4 */ 1000 P3_4_GPIO = 0, /* GPIO controls 'out' */ 1001 P3_4_AMUXA = 4, /* Analog mux bus A */ 1002 P3_4_AMUXB = 5, /* Analog mux bus B */ 1003 P3_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1004 P3_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1005 P3_4_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:5 */ 1006 P3_4_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:1 */ 1007 P3_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ 1008 P3_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ 1009 P3_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ 1010 P3_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ 1011 P3_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:1 */ 1012 1013 /* P3.5 */ 1014 P3_5_GPIO = 0, /* GPIO controls 'out' */ 1015 P3_5_AMUXA = 4, /* Analog mux bus A */ 1016 P3_5_AMUXB = 5, /* Analog mux bus B */ 1017 P3_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1018 P3_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1019 P3_5_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:5 */ 1020 P3_5_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:1 */ 1021 P3_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ 1022 P3_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ 1023 P3_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ 1024 P3_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ 1025 P3_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:1 */ 1026 1027 /* P4.0 */ 1028 P4_0_GPIO = 0, /* GPIO controls 'out' */ 1029 P4_0_AMUXA = 4, /* Analog mux bus A */ 1030 P4_0_AMUXB = 5, /* Analog mux bus B */ 1031 P4_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1032 P4_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1033 P4_0_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:5 */ 1034 P4_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:1 */ 1035 P4_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ 1036 P4_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ 1037 P4_0_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ 1038 P4_0_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ 1039 P4_0_SCB7_UART_RX = 18, /* Digital Active - scb[7].uart_rx:1 */ 1040 P4_0_SCB7_I2C_SCL = 19, /* Digital Active - scb[7].i2c_scl:1 */ 1041 P4_0_SCB7_SPI_MOSI = 20, /* Digital Active - scb[7].spi_mosi:1 */ 1042 P4_0_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ 1043 1044 /* P4.1 */ 1045 P4_1_GPIO = 0, /* GPIO controls 'out' */ 1046 P4_1_AMUXA = 4, /* Analog mux bus A */ 1047 P4_1_AMUXB = 5, /* Analog mux bus B */ 1048 P4_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1049 P4_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1050 P4_1_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:5 */ 1051 P4_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:1 */ 1052 P4_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ 1053 P4_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ 1054 P4_1_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ 1055 P4_1_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ 1056 P4_1_SCB7_UART_TX = 18, /* Digital Active - scb[7].uart_tx:1 */ 1057 P4_1_SCB7_I2C_SDA = 19, /* Digital Active - scb[7].i2c_sda:1 */ 1058 P4_1_SCB7_SPI_MISO = 20, /* Digital Active - scb[7].spi_miso:1 */ 1059 P4_1_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ 1060 1061 /* P5.0 */ 1062 P5_0_GPIO = 0, /* GPIO controls 'out' */ 1063 P5_0_AMUXA = 4, /* Analog mux bus A */ 1064 P5_0_AMUXB = 5, /* Analog mux bus B */ 1065 P5_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1066 P5_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1067 P5_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:0 */ 1068 P5_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:0 */ 1069 P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ 1070 P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ 1071 P5_0_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ 1072 P5_0_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ 1073 P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ 1074 P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ 1075 P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ 1076 P5_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:0 */ 1077 P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ 1078 1079 /* P5.1 */ 1080 P5_1_GPIO = 0, /* GPIO controls 'out' */ 1081 P5_1_AMUXA = 4, /* Analog mux bus A */ 1082 P5_1_AMUXB = 5, /* Analog mux bus B */ 1083 P5_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1084 P5_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1085 P5_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:0 */ 1086 P5_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:0 */ 1087 P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ 1088 P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ 1089 P5_1_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ 1090 P5_1_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ 1091 P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ 1092 P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ 1093 P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ 1094 P5_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:0 */ 1095 P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ 1096 1097 /* P5.2 */ 1098 P5_2_GPIO = 0, /* GPIO controls 'out' */ 1099 P5_2_AMUXA = 4, /* Analog mux bus A */ 1100 P5_2_AMUXB = 5, /* Analog mux bus B */ 1101 P5_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1102 P5_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1103 P5_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:0 */ 1104 P5_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:0 */ 1105 P5_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ 1106 P5_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ 1107 P5_2_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:0 */ 1108 P5_2_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:0 */ 1109 P5_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ 1110 P5_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ 1111 P5_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:0 */ 1112 1113 /* P5.3 */ 1114 P5_3_GPIO = 0, /* GPIO controls 'out' */ 1115 P5_3_AMUXA = 4, /* Analog mux bus A */ 1116 P5_3_AMUXB = 5, /* Analog mux bus B */ 1117 P5_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1118 P5_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1119 P5_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:0 */ 1120 P5_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:0 */ 1121 P5_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ 1122 P5_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ 1123 P5_3_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:0 */ 1124 P5_3_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:0 */ 1125 P5_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ 1126 P5_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ 1127 P5_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:0 */ 1128 1129 /* P5.4 */ 1130 P5_4_GPIO = 0, /* GPIO controls 'out' */ 1131 P5_4_AMUXA = 4, /* Analog mux bus A */ 1132 P5_4_AMUXB = 5, /* Analog mux bus B */ 1133 P5_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1134 P5_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1135 P5_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:0 */ 1136 P5_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:0 */ 1137 P5_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:34 */ 1138 P5_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:34 */ 1139 P5_4_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:0 */ 1140 P5_4_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:0 */ 1141 P5_4_SCB10_UART_RX = 18, /* Digital Active - scb[10].uart_rx:0 */ 1142 P5_4_SCB10_I2C_SCL = 19, /* Digital Active - scb[10].i2c_scl:0 */ 1143 P5_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ 1144 P5_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:0 */ 1145 1146 /* P5.5 */ 1147 P5_5_GPIO = 0, /* GPIO controls 'out' */ 1148 P5_5_AMUXA = 4, /* Analog mux bus A */ 1149 P5_5_AMUXB = 5, /* Analog mux bus B */ 1150 P5_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1151 P5_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1152 P5_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:0 */ 1153 P5_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:0 */ 1154 P5_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:35 */ 1155 P5_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:35 */ 1156 P5_5_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ 1157 P5_5_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ 1158 P5_5_SCB10_UART_TX = 18, /* Digital Active - scb[10].uart_tx:0 */ 1159 P5_5_SCB10_I2C_SDA = 19, /* Digital Active - scb[10].i2c_sda:0 */ 1160 P5_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ 1161 P5_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:0 */ 1162 1163 /* P5.6 */ 1164 P5_6_GPIO = 0, /* GPIO controls 'out' */ 1165 P5_6_AMUXA = 4, /* Analog mux bus A */ 1166 P5_6_AMUXB = 5, /* Analog mux bus B */ 1167 P5_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1168 P5_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1169 P5_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:0 */ 1170 P5_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:0 */ 1171 P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ 1172 P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ 1173 P5_6_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ 1174 P5_6_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ 1175 P5_6_SCB10_UART_RTS = 18, /* Digital Active - scb[10].uart_rts:0 */ 1176 P5_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ 1177 P5_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:0 */ 1178 1179 /* P5.7 */ 1180 P5_7_GPIO = 0, /* GPIO controls 'out' */ 1181 P5_7_AMUXA = 4, /* Analog mux bus A */ 1182 P5_7_AMUXB = 5, /* Analog mux bus B */ 1183 P5_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1184 P5_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1185 P5_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:0 */ 1186 P5_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:0 */ 1187 P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ 1188 P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ 1189 P5_7_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ 1190 P5_7_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ 1191 P5_7_SCB10_UART_CTS = 18, /* Digital Active - scb[10].uart_cts:0 */ 1192 P5_7_SCB3_SPI_SELECT3 = 20, /* Digital Active - scb[3].spi_select3:0 */ 1193 1194 /* P6.0 */ 1195 P6_0_GPIO = 0, /* GPIO controls 'out' */ 1196 P6_0_AMUXA = 4, /* Analog mux bus A */ 1197 P6_0_AMUXB = 5, /* Analog mux bus B */ 1198 P6_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1199 P6_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1200 P6_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ 1201 P6_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:0 */ 1202 P6_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ 1203 P6_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ 1204 P6_0_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:0 */ 1205 P6_0_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:0 */ 1206 P6_0_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:0 */ 1207 P6_0_SCB3_UART_RX = 18, /* Digital Active - scb[3].uart_rx:0 */ 1208 P6_0_SCB3_I2C_SCL = 19, /* Digital Active - scb[3].i2c_scl:0 */ 1209 P6_0_SCB3_SPI_MOSI = 20, /* Digital Active - scb[3].spi_mosi:0 */ 1210 P6_0_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ 1211 P6_0_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:0 */ 1212 1213 /* P6.1 */ 1214 P6_1_GPIO = 0, /* GPIO controls 'out' */ 1215 P6_1_AMUXA = 4, /* Analog mux bus A */ 1216 P6_1_AMUXB = 5, /* Analog mux bus B */ 1217 P6_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1218 P6_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1219 P6_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ 1220 P6_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:0 */ 1221 P6_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ 1222 P6_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ 1223 P6_1_LCD_COM39 = 12, /* Digital Deep Sleep - lcd.com[39]:0 */ 1224 P6_1_LCD_SEG39 = 13, /* Digital Deep Sleep - lcd.seg[39]:0 */ 1225 P6_1_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:0 */ 1226 P6_1_SCB3_UART_TX = 18, /* Digital Active - scb[3].uart_tx:0 */ 1227 P6_1_SCB3_I2C_SDA = 19, /* Digital Active - scb[3].i2c_sda:0 */ 1228 P6_1_SCB3_SPI_MISO = 20, /* Digital Active - scb[3].spi_miso:0 */ 1229 P6_1_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ 1230 P6_1_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:0 */ 1231 1232 /* P6.2 */ 1233 P6_2_GPIO = 0, /* GPIO controls 'out' */ 1234 P6_2_AMUXA = 4, /* Analog mux bus A */ 1235 P6_2_AMUXB = 5, /* Analog mux bus B */ 1236 P6_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1237 P6_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1238 P6_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ 1239 P6_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:0 */ 1240 P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ 1241 P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ 1242 P6_2_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ 1243 P6_2_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ 1244 P6_2_SCB3_UART_RTS = 18, /* Digital Active - scb[3].uart_rts:0 */ 1245 P6_2_SCB3_SPI_CLK = 20, /* Digital Active - scb[3].spi_clk:0 */ 1246 P6_2_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:0 */ 1247 1248 /* P6.3 */ 1249 P6_3_GPIO = 0, /* GPIO controls 'out' */ 1250 P6_3_AMUXA = 4, /* Analog mux bus A */ 1251 P6_3_AMUXB = 5, /* Analog mux bus B */ 1252 P6_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1253 P6_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1254 P6_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ 1255 P6_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:0 */ 1256 P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ 1257 P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ 1258 P6_3_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ 1259 P6_3_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ 1260 P6_3_SCB3_UART_CTS = 18, /* Digital Active - scb[3].uart_cts:0 */ 1261 P6_3_SCB3_SPI_SELECT0 = 20, /* Digital Active - scb[3].spi_select0:0 */ 1262 P6_3_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:0 */ 1263 1264 /* P6.4 */ 1265 P6_4_GPIO = 0, /* GPIO controls 'out' */ 1266 P6_4_AMUXA = 4, /* Analog mux bus A */ 1267 P6_4_AMUXB = 5, /* Analog mux bus B */ 1268 P6_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1269 P6_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1270 P6_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ 1271 P6_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:0 */ 1272 P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ 1273 P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ 1274 P6_4_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ 1275 P6_4_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ 1276 P6_4_SCB8_I2C_SCL = 14, /* Digital Deep Sleep - scb[8].i2c_scl:1 */ 1277 P6_4_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:2 */ 1278 P6_4_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:2 */ 1279 P6_4_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:2 */ 1280 P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ 1281 P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ 1282 P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ 1283 P6_4_SCB8_SPI_MOSI = 30, /* Digital Deep Sleep - scb[8].spi_mosi:1 */ 1284 P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ 1285 1286 /* P6.5 */ 1287 P6_5_GPIO = 0, /* GPIO controls 'out' */ 1288 P6_5_AMUXA = 4, /* Analog mux bus A */ 1289 P6_5_AMUXB = 5, /* Analog mux bus B */ 1290 P6_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1291 P6_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1292 P6_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ 1293 P6_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:0 */ 1294 P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:43 */ 1295 P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:43 */ 1296 P6_5_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ 1297 P6_5_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ 1298 P6_5_SCB8_I2C_SDA = 14, /* Digital Deep Sleep - scb[8].i2c_sda:1 */ 1299 P6_5_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:2 */ 1300 P6_5_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:2 */ 1301 P6_5_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:2 */ 1302 P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ 1303 P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ 1304 P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ 1305 P6_5_SCB8_SPI_MISO = 30, /* Digital Deep Sleep - scb[8].spi_miso:1 */ 1306 P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ 1307 1308 /* P6.6 */ 1309 P6_6_GPIO = 0, /* GPIO controls 'out' */ 1310 P6_6_AMUXA = 4, /* Analog mux bus A */ 1311 P6_6_AMUXB = 5, /* Analog mux bus B */ 1312 P6_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1313 P6_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1314 P6_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ 1315 P6_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:0 */ 1316 P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:44 */ 1317 P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:44 */ 1318 P6_6_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ 1319 P6_6_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ 1320 P6_6_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:2 */ 1321 P6_6_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:2 */ 1322 P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ 1323 P6_6_SCB8_SPI_CLK = 30, /* Digital Deep Sleep - scb[8].spi_clk:1 */ 1324 1325 /* P6.7 */ 1326 P6_7_GPIO = 0, /* GPIO controls 'out' */ 1327 P6_7_AMUXA = 4, /* Analog mux bus A */ 1328 P6_7_AMUXB = 5, /* Analog mux bus B */ 1329 P6_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1330 P6_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1331 P6_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ 1332 P6_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:0 */ 1333 P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ 1334 P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ 1335 P6_7_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ 1336 P6_7_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ 1337 P6_7_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:2 */ 1338 P6_7_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:2 */ 1339 P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ 1340 P6_7_SCB8_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[8].spi_select0:1 */ 1341 1342 /* P7.0 */ 1343 P7_0_GPIO = 0, /* GPIO controls 'out' */ 1344 P7_0_AMUXA = 4, /* Analog mux bus A */ 1345 P7_0_AMUXB = 5, /* Analog mux bus B */ 1346 P7_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1347 P7_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1348 P7_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:1 */ 1349 P7_0_TCPWM1_LINE12 = 9, /* Digital Active - tcpwm[1].line[12]:0 */ 1350 P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ 1351 P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ 1352 P7_0_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ 1353 P7_0_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ 1354 P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ 1355 P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ 1356 P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ 1357 P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ 1358 P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ 1359 1360 /* P7.1 */ 1361 P7_1_GPIO = 0, /* GPIO controls 'out' */ 1362 P7_1_AMUXA = 4, /* Analog mux bus A */ 1363 P7_1_AMUXB = 5, /* Analog mux bus B */ 1364 P7_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1365 P7_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1366 P7_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:1 */ 1367 P7_1_TCPWM1_LINE_COMPL12 = 9, /* Digital Active - tcpwm[1].line_compl[12]:0 */ 1368 P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ 1369 P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ 1370 P7_1_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ 1371 P7_1_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ 1372 P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ 1373 P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ 1374 P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ 1375 P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ 1376 1377 /* P7.2 */ 1378 P7_2_GPIO = 0, /* GPIO controls 'out' */ 1379 P7_2_AMUXA = 4, /* Analog mux bus A */ 1380 P7_2_AMUXB = 5, /* Analog mux bus B */ 1381 P7_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1382 P7_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1383 P7_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:1 */ 1384 P7_2_TCPWM1_LINE13 = 9, /* Digital Active - tcpwm[1].line[13]:0 */ 1385 P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ 1386 P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ 1387 P7_2_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ 1388 P7_2_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ 1389 P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:1 */ 1390 P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:1 */ 1391 1392 /* P7.3 */ 1393 P7_3_GPIO = 0, /* GPIO controls 'out' */ 1394 P7_3_AMUXA = 4, /* Analog mux bus A */ 1395 P7_3_AMUXB = 5, /* Analog mux bus B */ 1396 P7_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1397 P7_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1398 P7_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:1 */ 1399 P7_3_TCPWM1_LINE_COMPL13 = 9, /* Digital Active - tcpwm[1].line_compl[13]:0 */ 1400 P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ 1401 P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ 1402 P7_3_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ 1403 P7_3_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ 1404 P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:1 */ 1405 P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:1 */ 1406 1407 /* P7.4 */ 1408 P7_4_GPIO = 0, /* GPIO controls 'out' */ 1409 P7_4_AMUXA = 4, /* Analog mux bus A */ 1410 P7_4_AMUXB = 5, /* Analog mux bus B */ 1411 P7_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1412 P7_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1413 P7_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:1 */ 1414 P7_4_TCPWM1_LINE14 = 9, /* Digital Active - tcpwm[1].line[14]:0 */ 1415 P7_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ 1416 P7_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ 1417 P7_4_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ 1418 P7_4_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ 1419 P7_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:1 */ 1420 P7_4_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:2 */ 1421 1422 /* P7.5 */ 1423 P7_5_GPIO = 0, /* GPIO controls 'out' */ 1424 P7_5_AMUXA = 4, /* Analog mux bus A */ 1425 P7_5_AMUXB = 5, /* Analog mux bus B */ 1426 P7_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1427 P7_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1428 P7_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:1 */ 1429 P7_5_TCPWM1_LINE_COMPL14 = 9, /* Digital Active - tcpwm[1].line_compl[14]:0 */ 1430 P7_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ 1431 P7_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ 1432 P7_5_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ 1433 P7_5_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ 1434 P7_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:1 */ 1435 P7_5_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:2 */ 1436 1437 /* P7.6 */ 1438 P7_6_GPIO = 0, /* GPIO controls 'out' */ 1439 P7_6_AMUXA = 4, /* Analog mux bus A */ 1440 P7_6_AMUXB = 5, /* Analog mux bus B */ 1441 P7_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1442 P7_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1443 P7_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:1 */ 1444 P7_6_TCPWM1_LINE15 = 9, /* Digital Active - tcpwm[1].line[15]:0 */ 1445 P7_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ 1446 P7_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ 1447 P7_6_LCD_COM52 = 12, /* Digital Deep Sleep - lcd.com[52]:0 */ 1448 P7_6_LCD_SEG52 = 13, /* Digital Deep Sleep - lcd.seg[52]:0 */ 1449 P7_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:1 */ 1450 P7_6_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:2 */ 1451 1452 /* P7.7 */ 1453 P7_7_GPIO = 0, /* GPIO controls 'out' */ 1454 P7_7_AMUXA = 4, /* Analog mux bus A */ 1455 P7_7_AMUXB = 5, /* Analog mux bus B */ 1456 P7_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1457 P7_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1458 P7_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:1 */ 1459 P7_7_TCPWM1_LINE_COMPL15 = 9, /* Digital Active - tcpwm[1].line_compl[15]:0 */ 1460 P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:53 */ 1461 P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:53 */ 1462 P7_7_LCD_COM53 = 12, /* Digital Deep Sleep - lcd.com[53]:0 */ 1463 P7_7_LCD_SEG53 = 13, /* Digital Deep Sleep - lcd.seg[53]:0 */ 1464 P7_7_SCB3_SPI_SELECT1 = 20, /* Digital Active - scb[3].spi_select1:0 */ 1465 P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ 1466 P7_7_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:2 */ 1467 1468 /* P8.0 */ 1469 P8_0_GPIO = 0, /* GPIO controls 'out' */ 1470 P8_0_AMUXA = 4, /* Analog mux bus A */ 1471 P8_0_AMUXB = 5, /* Analog mux bus B */ 1472 P8_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1473 P8_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1474 P8_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ 1475 P8_0_TCPWM1_LINE16 = 9, /* Digital Active - tcpwm[1].line[16]:0 */ 1476 P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ 1477 P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ 1478 P8_0_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ 1479 P8_0_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ 1480 P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ 1481 P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ 1482 P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ 1483 P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ 1484 1485 /* P8.1 */ 1486 P8_1_GPIO = 0, /* GPIO controls 'out' */ 1487 P8_1_AMUXA = 4, /* Analog mux bus A */ 1488 P8_1_AMUXB = 5, /* Analog mux bus B */ 1489 P8_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1490 P8_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1491 P8_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ 1492 P8_1_TCPWM1_LINE_COMPL16 = 9, /* Digital Active - tcpwm[1].line_compl[16]:0 */ 1493 P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ 1494 P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ 1495 P8_1_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ 1496 P8_1_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ 1497 P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ 1498 P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ 1499 P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ 1500 P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ 1501 1502 /* P8.2 */ 1503 P8_2_GPIO = 0, /* GPIO controls 'out' */ 1504 P8_2_AMUXA = 4, /* Analog mux bus A */ 1505 P8_2_AMUXB = 5, /* Analog mux bus B */ 1506 P8_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1507 P8_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1508 P8_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ 1509 P8_2_TCPWM1_LINE17 = 9, /* Digital Active - tcpwm[1].line[17]:0 */ 1510 P8_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ 1511 P8_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ 1512 P8_2_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ 1513 P8_2_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ 1514 P8_2_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ 1515 P8_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ 1516 P8_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ 1517 1518 /* P8.3 */ 1519 P8_3_GPIO = 0, /* GPIO controls 'out' */ 1520 P8_3_AMUXA = 4, /* Analog mux bus A */ 1521 P8_3_AMUXB = 5, /* Analog mux bus B */ 1522 P8_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1523 P8_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1524 P8_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ 1525 P8_3_TCPWM1_LINE_COMPL17 = 9, /* Digital Active - tcpwm[1].line_compl[17]:0 */ 1526 P8_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ 1527 P8_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ 1528 P8_3_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ 1529 P8_3_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ 1530 P8_3_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ 1531 P8_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ 1532 P8_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ 1533 1534 /* P8.4 */ 1535 P8_4_GPIO = 0, /* GPIO controls 'out' */ 1536 P8_4_AMUXA = 4, /* Analog mux bus A */ 1537 P8_4_AMUXB = 5, /* Analog mux bus B */ 1538 P8_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1539 P8_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1540 P8_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ 1541 P8_4_TCPWM1_LINE18 = 9, /* Digital Active - tcpwm[1].line[18]:0 */ 1542 P8_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ 1543 P8_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ 1544 P8_4_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ 1545 P8_4_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ 1546 P8_4_SCB11_UART_RX = 18, /* Digital Active - scb[11].uart_rx:0 */ 1547 P8_4_SCB11_I2C_SCL = 19, /* Digital Active - scb[11].i2c_scl:0 */ 1548 P8_4_SCB4_SPI_SELECT1 = 20, /* Digital Active - scb[4].spi_select1:0 */ 1549 1550 /* P8.5 */ 1551 P8_5_GPIO = 0, /* GPIO controls 'out' */ 1552 P8_5_AMUXA = 4, /* Analog mux bus A */ 1553 P8_5_AMUXB = 5, /* Analog mux bus B */ 1554 P8_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1555 P8_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1556 P8_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ 1557 P8_5_TCPWM1_LINE_COMPL18 = 9, /* Digital Active - tcpwm[1].line_compl[18]:0 */ 1558 P8_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ 1559 P8_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ 1560 P8_5_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ 1561 P8_5_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ 1562 P8_5_SCB11_UART_TX = 18, /* Digital Active - scb[11].uart_tx:0 */ 1563 P8_5_SCB11_I2C_SDA = 19, /* Digital Active - scb[11].i2c_sda:0 */ 1564 P8_5_SCB4_SPI_SELECT2 = 20, /* Digital Active - scb[4].spi_select2:0 */ 1565 1566 /* P8.6 */ 1567 P8_6_GPIO = 0, /* GPIO controls 'out' */ 1568 P8_6_AMUXA = 4, /* Analog mux bus A */ 1569 P8_6_AMUXB = 5, /* Analog mux bus B */ 1570 P8_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1571 P8_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1572 P8_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ 1573 P8_6_TCPWM1_LINE19 = 9, /* Digital Active - tcpwm[1].line[19]:0 */ 1574 P8_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ 1575 P8_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ 1576 P8_6_LCD_COM60 = 12, /* Digital Deep Sleep - lcd.com[60]:0 */ 1577 P8_6_LCD_SEG60 = 13, /* Digital Deep Sleep - lcd.seg[60]:0 */ 1578 P8_6_SCB11_UART_RTS = 18, /* Digital Active - scb[11].uart_rts:0 */ 1579 P8_6_SCB4_SPI_SELECT3 = 20, /* Digital Active - scb[4].spi_select3:0 */ 1580 1581 /* P8.7 */ 1582 P8_7_GPIO = 0, /* GPIO controls 'out' */ 1583 P8_7_AMUXA = 4, /* Analog mux bus A */ 1584 P8_7_AMUXB = 5, /* Analog mux bus B */ 1585 P8_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1586 P8_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1587 P8_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ 1588 P8_7_TCPWM1_LINE_COMPL19 = 9, /* Digital Active - tcpwm[1].line_compl[19]:0 */ 1589 P8_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ 1590 P8_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ 1591 P8_7_LCD_COM61 = 12, /* Digital Deep Sleep - lcd.com[61]:0 */ 1592 P8_7_LCD_SEG61 = 13, /* Digital Deep Sleep - lcd.seg[61]:0 */ 1593 P8_7_SCB11_UART_CTS = 18, /* Digital Active - scb[11].uart_cts:0 */ 1594 P8_7_SCB3_SPI_SELECT2 = 20, /* Digital Active - scb[3].spi_select2:0 */ 1595 1596 /* P9.0 */ 1597 P9_0_GPIO = 0, /* GPIO controls 'out' */ 1598 P9_0_AMUXA = 4, /* Analog mux bus A */ 1599 P9_0_AMUXB = 5, /* Analog mux bus B */ 1600 P9_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1601 P9_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1602 P9_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:2 */ 1603 P9_0_TCPWM1_LINE20 = 9, /* Digital Active - tcpwm[1].line[20]:0 */ 1604 P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:62 */ 1605 P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:62 */ 1606 P9_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:1 */ 1607 P9_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:1 */ 1608 P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ 1609 P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ 1610 P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ 1611 P9_0_AUDIOSS0_CLK_I2S_IF = 22, /* Digital Active - audioss[0].clk_i2s_if:1 */ 1612 P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ 1613 P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ 1614 1615 /* P9.1 */ 1616 P9_1_GPIO = 0, /* GPIO controls 'out' */ 1617 P9_1_AMUXA = 4, /* Analog mux bus A */ 1618 P9_1_AMUXB = 5, /* Analog mux bus B */ 1619 P9_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1620 P9_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1621 P9_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:2 */ 1622 P9_1_TCPWM1_LINE_COMPL20 = 9, /* Digital Active - tcpwm[1].line_compl[20]:0 */ 1623 P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:63 */ 1624 P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:63 */ 1625 P9_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:1 */ 1626 P9_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:1 */ 1627 P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ 1628 P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ 1629 P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ 1630 P9_1_AUDIOSS0_TX_SCK = 22, /* Digital Active - audioss[0].tx_sck:1 */ 1631 P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ 1632 P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ 1633 P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ 1634 1635 /* P9.2 */ 1636 P9_2_GPIO = 0, /* GPIO controls 'out' */ 1637 P9_2_AMUXA = 4, /* Analog mux bus A */ 1638 P9_2_AMUXB = 5, /* Analog mux bus B */ 1639 P9_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1640 P9_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1641 P9_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:2 */ 1642 P9_2_TCPWM1_LINE21 = 9, /* Digital Active - tcpwm[1].line[21]:0 */ 1643 P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:64 */ 1644 P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:64 */ 1645 P9_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ 1646 P9_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ 1647 P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ 1648 P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ 1649 P9_2_AUDIOSS0_TX_WS = 22, /* Digital Active - audioss[0].tx_ws:1 */ 1650 P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ 1651 1652 /* P9.3 */ 1653 P9_3_GPIO = 0, /* GPIO controls 'out' */ 1654 P9_3_AMUXA = 4, /* Analog mux bus A */ 1655 P9_3_AMUXB = 5, /* Analog mux bus B */ 1656 P9_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1657 P9_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1658 P9_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:2 */ 1659 P9_3_TCPWM1_LINE_COMPL21 = 9, /* Digital Active - tcpwm[1].line_compl[21]:0 */ 1660 P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:65 */ 1661 P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:65 */ 1662 P9_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ 1663 P9_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ 1664 P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ 1665 P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ 1666 P9_3_AUDIOSS0_TX_SDO = 22, /* Digital Active - audioss[0].tx_sdo:1 */ 1667 P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ 1668 P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ 1669 1670 /* P9.4 */ 1671 P9_4_GPIO = 0, /* GPIO controls 'out' */ 1672 P9_4_AMUXA = 4, /* Analog mux bus A */ 1673 P9_4_AMUXB = 5, /* Analog mux bus B */ 1674 P9_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1675 P9_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1676 P9_4_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:5 */ 1677 P9_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:2 */ 1678 P9_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:66 */ 1679 P9_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:66 */ 1680 P9_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:1 */ 1681 P9_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:1 */ 1682 P9_4_SCB2_SPI_SELECT1 = 20, /* Digital Active - scb[2].spi_select1:0 */ 1683 P9_4_AUDIOSS0_RX_SCK = 22, /* Digital Active - audioss[0].rx_sck:1 */ 1684 1685 /* P9.5 */ 1686 P9_5_GPIO = 0, /* GPIO controls 'out' */ 1687 P9_5_AMUXA = 4, /* Analog mux bus A */ 1688 P9_5_AMUXB = 5, /* Analog mux bus B */ 1689 P9_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1690 P9_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1691 P9_5_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:5 */ 1692 P9_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:2 */ 1693 P9_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:67 */ 1694 P9_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:67 */ 1695 P9_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:1 */ 1696 P9_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:1 */ 1697 P9_5_SCB2_SPI_SELECT2 = 20, /* Digital Active - scb[2].spi_select2:0 */ 1698 P9_5_AUDIOSS0_RX_WS = 22, /* Digital Active - audioss[0].rx_ws:1 */ 1699 1700 /* P9.6 */ 1701 P9_6_GPIO = 0, /* GPIO controls 'out' */ 1702 P9_6_AMUXA = 4, /* Analog mux bus A */ 1703 P9_6_AMUXB = 5, /* Analog mux bus B */ 1704 P9_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1705 P9_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1706 P9_6_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ 1707 P9_6_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:2 */ 1708 P9_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:68 */ 1709 P9_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:68 */ 1710 P9_6_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:1 */ 1711 P9_6_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:1 */ 1712 P9_6_SCB2_SPI_SELECT3 = 20, /* Digital Active - scb[2].spi_select3:0 */ 1713 P9_6_AUDIOSS0_RX_SDI = 22, /* Digital Active - audioss[0].rx_sdi:1 */ 1714 1715 /* P9.7 */ 1716 P9_7_GPIO = 0, /* GPIO controls 'out' */ 1717 P9_7_AMUXA = 4, /* Analog mux bus A */ 1718 P9_7_AMUXB = 5, /* Analog mux bus B */ 1719 P9_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1720 P9_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1721 P9_7_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ 1722 P9_7_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:2 */ 1723 P9_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:69 */ 1724 P9_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:69 */ 1725 P9_7_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:1 */ 1726 P9_7_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:1 */ 1727 1728 /* P10.0 */ 1729 P10_0_GPIO = 0, /* GPIO controls 'out' */ 1730 P10_0_AMUXA = 4, /* Analog mux bus A */ 1731 P10_0_AMUXB = 5, /* Analog mux bus B */ 1732 P10_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1733 P10_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1734 P10_0_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:2 */ 1735 P10_0_TCPWM1_LINE22 = 9, /* Digital Active - tcpwm[1].line[22]:0 */ 1736 P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:70 */ 1737 P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:70 */ 1738 P10_0_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:1 */ 1739 P10_0_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:1 */ 1740 P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ 1741 P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ 1742 P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ 1743 P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ 1744 P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ 1745 1746 /* P10.1 */ 1747 P10_1_GPIO = 0, /* GPIO controls 'out' */ 1748 P10_1_AMUXA = 4, /* Analog mux bus A */ 1749 P10_1_AMUXB = 5, /* Analog mux bus B */ 1750 P10_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1751 P10_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1752 P10_1_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:2 */ 1753 P10_1_TCPWM1_LINE_COMPL22 = 9, /* Digital Active - tcpwm[1].line_compl[22]:0 */ 1754 P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:71 */ 1755 P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:71 */ 1756 P10_1_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:1 */ 1757 P10_1_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:1 */ 1758 P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ 1759 P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ 1760 P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ 1761 P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ 1762 P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ 1763 1764 /* P10.2 */ 1765 P10_2_GPIO = 0, /* GPIO controls 'out' */ 1766 P10_2_AMUXA = 4, /* Analog mux bus A */ 1767 P10_2_AMUXB = 5, /* Analog mux bus B */ 1768 P10_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1769 P10_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1770 P10_2_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:2 */ 1771 P10_2_TCPWM1_LINE23 = 9, /* Digital Active - tcpwm[1].line[23]:0 */ 1772 P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:72 */ 1773 P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:72 */ 1774 P10_2_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:1 */ 1775 P10_2_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:1 */ 1776 P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ 1777 P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ 1778 P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ 1779 1780 /* P10.3 */ 1781 P10_3_GPIO = 0, /* GPIO controls 'out' */ 1782 P10_3_AMUXA = 4, /* Analog mux bus A */ 1783 P10_3_AMUXB = 5, /* Analog mux bus B */ 1784 P10_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1785 P10_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1786 P10_3_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:2 */ 1787 P10_3_TCPWM1_LINE_COMPL23 = 9, /* Digital Active - tcpwm[1].line_compl[23]:0 */ 1788 P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:73 */ 1789 P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:73 */ 1790 P10_3_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:1 */ 1791 P10_3_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:1 */ 1792 P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ 1793 P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ 1794 P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ 1795 1796 /* P10.4 */ 1797 P10_4_GPIO = 0, /* GPIO controls 'out' */ 1798 P10_4_AMUXA = 4, /* Analog mux bus A */ 1799 P10_4_AMUXB = 5, /* Analog mux bus B */ 1800 P10_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1801 P10_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1802 P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ 1803 P10_4_TCPWM1_LINE0 = 9, /* Digital Active - tcpwm[1].line[0]:1 */ 1804 P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:74 */ 1805 P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:74 */ 1806 P10_4_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:1 */ 1807 P10_4_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:1 */ 1808 P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ 1809 P10_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:0 */ 1810 1811 /* P10.5 */ 1812 P10_5_GPIO = 0, /* GPIO controls 'out' */ 1813 P10_5_AMUXA = 4, /* Analog mux bus A */ 1814 P10_5_AMUXB = 5, /* Analog mux bus B */ 1815 P10_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1816 P10_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1817 P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ 1818 P10_5_TCPWM1_LINE_COMPL0 = 9, /* Digital Active - tcpwm[1].line_compl[0]:1 */ 1819 P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:75 */ 1820 P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:75 */ 1821 P10_5_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:1 */ 1822 P10_5_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:1 */ 1823 P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ 1824 P10_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:0 */ 1825 1826 /* P10.6 */ 1827 P10_6_GPIO = 0, /* GPIO controls 'out' */ 1828 P10_6_AMUXA = 4, /* Analog mux bus A */ 1829 P10_6_AMUXB = 5, /* Analog mux bus B */ 1830 P10_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1831 P10_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1832 P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ 1833 P10_6_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:2 */ 1834 P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:76 */ 1835 P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:76 */ 1836 P10_6_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:1 */ 1837 P10_6_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:1 */ 1838 P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ 1839 1840 /* P10.7 */ 1841 P10_7_GPIO = 0, /* GPIO controls 'out' */ 1842 P10_7_AMUXA = 4, /* Analog mux bus A */ 1843 P10_7_AMUXB = 5, /* Analog mux bus B */ 1844 P10_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1845 P10_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1846 P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ 1847 P10_7_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:2 */ 1848 P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:77 */ 1849 P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:77 */ 1850 P10_7_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:1 */ 1851 P10_7_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:1 */ 1852 1853 /* P11.0 */ 1854 P11_0_GPIO = 0, /* GPIO controls 'out' */ 1855 P11_0_AMUXA = 4, /* Analog mux bus A */ 1856 P11_0_AMUXB = 5, /* Analog mux bus B */ 1857 P11_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1858 P11_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1859 P11_0_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ 1860 P11_0_TCPWM1_LINE1 = 9, /* Digital Active - tcpwm[1].line[1]:1 */ 1861 P11_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:78 */ 1862 P11_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:78 */ 1863 P11_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:1 */ 1864 P11_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:1 */ 1865 P11_0_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ 1866 P11_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:1 */ 1867 P11_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:1 */ 1868 P11_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:1 */ 1869 P11_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:1 */ 1870 P11_0_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ 1871 1872 /* P11.1 */ 1873 P11_1_GPIO = 0, /* GPIO controls 'out' */ 1874 P11_1_AMUXA = 4, /* Analog mux bus A */ 1875 P11_1_AMUXB = 5, /* Analog mux bus B */ 1876 P11_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1877 P11_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1878 P11_1_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ 1879 P11_1_TCPWM1_LINE_COMPL1 = 9, /* Digital Active - tcpwm[1].line_compl[1]:1 */ 1880 P11_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:79 */ 1881 P11_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:79 */ 1882 P11_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:1 */ 1883 P11_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:1 */ 1884 P11_1_SMIF_SPI_SELECT1 = 17, /* Digital Active - smif.spi_select1 */ 1885 P11_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:1 */ 1886 P11_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:1 */ 1887 P11_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:1 */ 1888 P11_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:1 */ 1889 P11_1_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ 1890 1891 /* P11.2 */ 1892 P11_2_GPIO = 0, /* GPIO controls 'out' */ 1893 P11_2_AMUXA = 4, /* Analog mux bus A */ 1894 P11_2_AMUXB = 5, /* Analog mux bus B */ 1895 P11_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1896 P11_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1897 P11_2_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ 1898 P11_2_TCPWM1_LINE2 = 9, /* Digital Active - tcpwm[1].line[2]:1 */ 1899 P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:80 */ 1900 P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:80 */ 1901 P11_2_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:1 */ 1902 P11_2_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:1 */ 1903 P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ 1904 P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:1 */ 1905 P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:1 */ 1906 P11_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:1 */ 1907 1908 /* P11.3 */ 1909 P11_3_GPIO = 0, /* GPIO controls 'out' */ 1910 P11_3_AMUXA = 4, /* Analog mux bus A */ 1911 P11_3_AMUXB = 5, /* Analog mux bus B */ 1912 P11_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1913 P11_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1914 P11_3_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ 1915 P11_3_TCPWM1_LINE_COMPL2 = 9, /* Digital Active - tcpwm[1].line_compl[2]:1 */ 1916 P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:81 */ 1917 P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:81 */ 1918 P11_3_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:1 */ 1919 P11_3_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:1 */ 1920 P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ 1921 P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:1 */ 1922 P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:1 */ 1923 P11_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:1 */ 1924 P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ 1925 1926 /* P11.4 */ 1927 P11_4_GPIO = 0, /* GPIO controls 'out' */ 1928 P11_4_AMUXA = 4, /* Analog mux bus A */ 1929 P11_4_AMUXB = 5, /* Analog mux bus B */ 1930 P11_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1931 P11_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1932 P11_4_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ 1933 P11_4_TCPWM1_LINE3 = 9, /* Digital Active - tcpwm[1].line[3]:1 */ 1934 P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:82 */ 1935 P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:82 */ 1936 P11_4_LCD_COM20 = 12, /* Digital Deep Sleep - lcd.com[20]:1 */ 1937 P11_4_LCD_SEG20 = 13, /* Digital Deep Sleep - lcd.seg[20]:1 */ 1938 P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ 1939 P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:1 */ 1940 P11_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:1 */ 1941 P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ 1942 1943 /* P11.5 */ 1944 P11_5_GPIO = 0, /* GPIO controls 'out' */ 1945 P11_5_AMUXA = 4, /* Analog mux bus A */ 1946 P11_5_AMUXB = 5, /* Analog mux bus B */ 1947 P11_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1948 P11_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1949 P11_5_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ 1950 P11_5_TCPWM1_LINE_COMPL3 = 9, /* Digital Active - tcpwm[1].line_compl[3]:1 */ 1951 P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:83 */ 1952 P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:83 */ 1953 P11_5_LCD_COM21 = 12, /* Digital Deep Sleep - lcd.com[21]:1 */ 1954 P11_5_LCD_SEG21 = 13, /* Digital Deep Sleep - lcd.seg[21]:1 */ 1955 P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ 1956 P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:1 */ 1957 P11_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:1 */ 1958 1959 /* P11.6 */ 1960 P11_6_GPIO = 0, /* GPIO controls 'out' */ 1961 P11_6_AMUXA = 4, /* Analog mux bus A */ 1962 P11_6_AMUXB = 5, /* Analog mux bus B */ 1963 P11_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1964 P11_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1965 P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:84 */ 1966 P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:84 */ 1967 P11_6_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:1 */ 1968 P11_6_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:1 */ 1969 P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ 1970 P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:1 */ 1971 P11_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:1 */ 1972 1973 /* P11.7 */ 1974 P11_7_GPIO = 0, /* GPIO controls 'out' */ 1975 P11_7_AMUXA = 4, /* Analog mux bus A */ 1976 P11_7_AMUXB = 5, /* Analog mux bus B */ 1977 P11_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1978 P11_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1979 P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ 1980 1981 /* P12.0 */ 1982 P12_0_GPIO = 0, /* GPIO controls 'out' */ 1983 P12_0_AMUXA = 4, /* Analog mux bus A */ 1984 P12_0_AMUXB = 5, /* Analog mux bus B */ 1985 P12_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 1986 P12_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 1987 P12_0_TCPWM0_LINE4 = 8, /* Digital Active - tcpwm[0].line[4]:3 */ 1988 P12_0_TCPWM1_LINE4 = 9, /* Digital Active - tcpwm[1].line[4]:1 */ 1989 P12_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:85 */ 1990 P12_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:85 */ 1991 P12_0_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:1 */ 1992 P12_0_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:1 */ 1993 P12_0_SMIF_SPI_DATA4 = 17, /* Digital Active - smif.spi_data4 */ 1994 P12_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:0 */ 1995 P12_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:0 */ 1996 P12_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:0 */ 1997 P12_0_PERI_TR_IO_INPUT24 = 24, /* Digital Active - peri.tr_io_input[24]:0 */ 1998 P12_0_SDHC1_CARD_EMMC_RESET_N = 26, /* Digital Active - sdhc[1].card_emmc_reset_n */ 1999 2000 /* P12.1 */ 2001 P12_1_GPIO = 0, /* GPIO controls 'out' */ 2002 P12_1_AMUXA = 4, /* Analog mux bus A */ 2003 P12_1_AMUXB = 5, /* Analog mux bus B */ 2004 P12_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2005 P12_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2006 P12_1_TCPWM0_LINE_COMPL4 = 8, /* Digital Active - tcpwm[0].line_compl[4]:3 */ 2007 P12_1_TCPWM1_LINE_COMPL4 = 9, /* Digital Active - tcpwm[1].line_compl[4]:1 */ 2008 P12_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:86 */ 2009 P12_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:86 */ 2010 P12_1_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:1 */ 2011 P12_1_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:1 */ 2012 P12_1_SMIF_SPI_DATA5 = 17, /* Digital Active - smif.spi_data5 */ 2013 P12_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:0 */ 2014 P12_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:0 */ 2015 P12_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:0 */ 2016 P12_1_PERI_TR_IO_INPUT25 = 24, /* Digital Active - peri.tr_io_input[25]:0 */ 2017 P12_1_SDHC1_CARD_DETECT_N = 26, /* Digital Active - sdhc[1].card_detect_n */ 2018 2019 /* P12.2 */ 2020 P12_2_GPIO = 0, /* GPIO controls 'out' */ 2021 P12_2_AMUXA = 4, /* Analog mux bus A */ 2022 P12_2_AMUXB = 5, /* Analog mux bus B */ 2023 P12_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2024 P12_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2025 P12_2_TCPWM0_LINE5 = 8, /* Digital Active - tcpwm[0].line[5]:3 */ 2026 P12_2_TCPWM1_LINE5 = 9, /* Digital Active - tcpwm[1].line[5]:1 */ 2027 P12_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:87 */ 2028 P12_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:87 */ 2029 P12_2_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:1 */ 2030 P12_2_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:1 */ 2031 P12_2_SMIF_SPI_DATA6 = 17, /* Digital Active - smif.spi_data6 */ 2032 P12_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:0 */ 2033 P12_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:0 */ 2034 P12_2_SDHC1_CARD_MECH_WRITE_PROT = 26, /* Digital Active - sdhc[1].card_mech_write_prot */ 2035 2036 /* P12.3 */ 2037 P12_3_GPIO = 0, /* GPIO controls 'out' */ 2038 P12_3_AMUXA = 4, /* Analog mux bus A */ 2039 P12_3_AMUXB = 5, /* Analog mux bus B */ 2040 P12_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2041 P12_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2042 P12_3_TCPWM0_LINE_COMPL5 = 8, /* Digital Active - tcpwm[0].line_compl[5]:3 */ 2043 P12_3_TCPWM1_LINE_COMPL5 = 9, /* Digital Active - tcpwm[1].line_compl[5]:1 */ 2044 P12_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:88 */ 2045 P12_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:88 */ 2046 P12_3_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:1 */ 2047 P12_3_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:1 */ 2048 P12_3_SMIF_SPI_DATA7 = 17, /* Digital Active - smif.spi_data7 */ 2049 P12_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:0 */ 2050 P12_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:0 */ 2051 P12_3_SDHC1_LED_CTRL = 26, /* Digital Active - sdhc[1].led_ctrl */ 2052 2053 /* P12.4 */ 2054 P12_4_GPIO = 0, /* GPIO controls 'out' */ 2055 P12_4_AMUXA = 4, /* Analog mux bus A */ 2056 P12_4_AMUXB = 5, /* Analog mux bus B */ 2057 P12_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2058 P12_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2059 P12_4_TCPWM0_LINE6 = 8, /* Digital Active - tcpwm[0].line[6]:3 */ 2060 P12_4_TCPWM1_LINE6 = 9, /* Digital Active - tcpwm[1].line[6]:1 */ 2061 P12_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:89 */ 2062 P12_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:89 */ 2063 P12_4_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:1 */ 2064 P12_4_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:1 */ 2065 P12_4_SMIF_SPI_SELECT3 = 17, /* Digital Active - smif.spi_select3 */ 2066 P12_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:0 */ 2067 P12_4_AUDIOSS0_PDM_CLK = 21, /* Digital Active - audioss[0].pdm_clk:1 */ 2068 P12_4_SDHC1_CARD_CMD = 26, /* Digital Active - sdhc[1].card_cmd */ 2069 2070 /* P12.5 */ 2071 P12_5_GPIO = 0, /* GPIO controls 'out' */ 2072 P12_5_AMUXA = 4, /* Analog mux bus A */ 2073 P12_5_AMUXB = 5, /* Analog mux bus B */ 2074 P12_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2075 P12_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2076 P12_5_TCPWM0_LINE_COMPL6 = 8, /* Digital Active - tcpwm[0].line_compl[6]:3 */ 2077 P12_5_TCPWM1_LINE_COMPL6 = 9, /* Digital Active - tcpwm[1].line_compl[6]:1 */ 2078 P12_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:90 */ 2079 P12_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:90 */ 2080 P12_5_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:1 */ 2081 P12_5_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:1 */ 2082 P12_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:0 */ 2083 P12_5_AUDIOSS0_PDM_DATA = 21, /* Digital Active - audioss[0].pdm_data:1 */ 2084 P12_5_SDHC1_CLK_CARD = 26, /* Digital Active - sdhc[1].clk_card */ 2085 2086 /* P12.6 */ 2087 P12_6_GPIO = 0, /* GPIO controls 'out' */ 2088 P12_6_AMUXA = 4, /* Analog mux bus A */ 2089 P12_6_AMUXB = 5, /* Analog mux bus B */ 2090 P12_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2091 P12_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2092 P12_6_TCPWM0_LINE7 = 8, /* Digital Active - tcpwm[0].line[7]:3 */ 2093 P12_6_TCPWM1_LINE7 = 9, /* Digital Active - tcpwm[1].line[7]:1 */ 2094 P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:91 */ 2095 P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:91 */ 2096 P12_6_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:1 */ 2097 P12_6_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:1 */ 2098 P12_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:0 */ 2099 P12_6_SDHC1_CARD_IF_PWR_EN = 26, /* Digital Active - sdhc[1].card_if_pwr_en */ 2100 2101 /* P12.7 */ 2102 P12_7_GPIO = 0, /* GPIO controls 'out' */ 2103 P12_7_AMUXA = 4, /* Analog mux bus A */ 2104 P12_7_AMUXB = 5, /* Analog mux bus B */ 2105 P12_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2106 P12_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2107 P12_7_TCPWM0_LINE_COMPL7 = 8, /* Digital Active - tcpwm[0].line_compl[7]:3 */ 2108 P12_7_TCPWM1_LINE_COMPL7 = 9, /* Digital Active - tcpwm[1].line_compl[7]:1 */ 2109 P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:92 */ 2110 P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:92 */ 2111 P12_7_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:1 */ 2112 P12_7_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:1 */ 2113 P12_7_SDHC1_IO_VOLT_SEL = 26, /* Digital Active - sdhc[1].io_volt_sel */ 2114 2115 /* P13.0 */ 2116 P13_0_GPIO = 0, /* GPIO controls 'out' */ 2117 P13_0_AMUXA = 4, /* Analog mux bus A */ 2118 P13_0_AMUXB = 5, /* Analog mux bus B */ 2119 P13_0_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2120 P13_0_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2121 P13_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ 2122 P13_0_TCPWM1_LINE8 = 9, /* Digital Active - tcpwm[1].line[8]:1 */ 2123 P13_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:93 */ 2124 P13_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:93 */ 2125 P13_0_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:1 */ 2126 P13_0_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:1 */ 2127 P13_0_SCB6_UART_RX = 18, /* Digital Active - scb[6].uart_rx:1 */ 2128 P13_0_SCB6_I2C_SCL = 19, /* Digital Active - scb[6].i2c_scl:1 */ 2129 P13_0_SCB6_SPI_MOSI = 20, /* Digital Active - scb[6].spi_mosi:1 */ 2130 P13_0_AUDIOSS1_CLK_I2S_IF = 22, /* Digital Active - audioss[1].clk_i2s_if:0 */ 2131 P13_0_PERI_TR_IO_INPUT26 = 24, /* Digital Active - peri.tr_io_input[26]:0 */ 2132 P13_0_SDHC1_CARD_DAT_3TO00 = 26, /* Digital Active - sdhc[1].card_dat_3to0[0] */ 2133 2134 /* P13.1 */ 2135 P13_1_GPIO = 0, /* GPIO controls 'out' */ 2136 P13_1_AMUXA = 4, /* Analog mux bus A */ 2137 P13_1_AMUXB = 5, /* Analog mux bus B */ 2138 P13_1_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2139 P13_1_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2140 P13_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ 2141 P13_1_TCPWM1_LINE_COMPL8 = 9, /* Digital Active - tcpwm[1].line_compl[8]:1 */ 2142 P13_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:94 */ 2143 P13_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:94 */ 2144 P13_1_LCD_COM32 = 12, /* Digital Deep Sleep - lcd.com[32]:1 */ 2145 P13_1_LCD_SEG32 = 13, /* Digital Deep Sleep - lcd.seg[32]:1 */ 2146 P13_1_SCB6_UART_TX = 18, /* Digital Active - scb[6].uart_tx:1 */ 2147 P13_1_SCB6_I2C_SDA = 19, /* Digital Active - scb[6].i2c_sda:1 */ 2148 P13_1_SCB6_SPI_MISO = 20, /* Digital Active - scb[6].spi_miso:1 */ 2149 P13_1_AUDIOSS1_TX_SCK = 22, /* Digital Active - audioss[1].tx_sck:0 */ 2150 P13_1_PERI_TR_IO_INPUT27 = 24, /* Digital Active - peri.tr_io_input[27]:0 */ 2151 P13_1_SDHC1_CARD_DAT_3TO01 = 26, /* Digital Active - sdhc[1].card_dat_3to0[1] */ 2152 2153 /* P13.2 */ 2154 P13_2_GPIO = 0, /* GPIO controls 'out' */ 2155 P13_2_AMUXA = 4, /* Analog mux bus A */ 2156 P13_2_AMUXB = 5, /* Analog mux bus B */ 2157 P13_2_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2158 P13_2_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2159 P13_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ 2160 P13_2_TCPWM1_LINE9 = 9, /* Digital Active - tcpwm[1].line[9]:1 */ 2161 P13_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:95 */ 2162 P13_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:95 */ 2163 P13_2_LCD_COM33 = 12, /* Digital Deep Sleep - lcd.com[33]:1 */ 2164 P13_2_LCD_SEG33 = 13, /* Digital Deep Sleep - lcd.seg[33]:1 */ 2165 P13_2_SCB6_UART_RTS = 18, /* Digital Active - scb[6].uart_rts:1 */ 2166 P13_2_SCB6_SPI_CLK = 20, /* Digital Active - scb[6].spi_clk:1 */ 2167 P13_2_AUDIOSS1_TX_WS = 22, /* Digital Active - audioss[1].tx_ws:0 */ 2168 P13_2_SDHC1_CARD_DAT_3TO02 = 26, /* Digital Active - sdhc[1].card_dat_3to0[2] */ 2169 2170 /* P13.3 */ 2171 P13_3_GPIO = 0, /* GPIO controls 'out' */ 2172 P13_3_AMUXA = 4, /* Analog mux bus A */ 2173 P13_3_AMUXB = 5, /* Analog mux bus B */ 2174 P13_3_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2175 P13_3_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2176 P13_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ 2177 P13_3_TCPWM1_LINE_COMPL9 = 9, /* Digital Active - tcpwm[1].line_compl[9]:1 */ 2178 P13_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:96 */ 2179 P13_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:96 */ 2180 P13_3_LCD_COM34 = 12, /* Digital Deep Sleep - lcd.com[34]:1 */ 2181 P13_3_LCD_SEG34 = 13, /* Digital Deep Sleep - lcd.seg[34]:1 */ 2182 P13_3_SCB6_UART_CTS = 18, /* Digital Active - scb[6].uart_cts:1 */ 2183 P13_3_SCB6_SPI_SELECT0 = 20, /* Digital Active - scb[6].spi_select0:1 */ 2184 P13_3_AUDIOSS1_TX_SDO = 22, /* Digital Active - audioss[1].tx_sdo:0 */ 2185 P13_3_SDHC1_CARD_DAT_3TO03 = 26, /* Digital Active - sdhc[1].card_dat_3to0[3] */ 2186 2187 /* P13.4 */ 2188 P13_4_GPIO = 0, /* GPIO controls 'out' */ 2189 P13_4_AMUXA = 4, /* Analog mux bus A */ 2190 P13_4_AMUXB = 5, /* Analog mux bus B */ 2191 P13_4_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2192 P13_4_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2193 P13_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ 2194 P13_4_TCPWM1_LINE10 = 9, /* Digital Active - tcpwm[1].line[10]:1 */ 2195 P13_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:97 */ 2196 P13_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:97 */ 2197 P13_4_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:1 */ 2198 P13_4_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:1 */ 2199 P13_4_SCB12_UART_RX = 18, /* Digital Active - scb[12].uart_rx:0 */ 2200 P13_4_SCB12_I2C_SCL = 19, /* Digital Active - scb[12].i2c_scl:0 */ 2201 P13_4_SCB6_SPI_SELECT1 = 20, /* Digital Active - scb[6].spi_select1:1 */ 2202 P13_4_AUDIOSS1_RX_SCK = 22, /* Digital Active - audioss[1].rx_sck:0 */ 2203 P13_4_SDHC1_CARD_DAT_7TO40 = 26, /* Digital Active - sdhc[1].card_dat_7to4[0] */ 2204 2205 /* P13.5 */ 2206 P13_5_GPIO = 0, /* GPIO controls 'out' */ 2207 P13_5_AMUXA = 4, /* Analog mux bus A */ 2208 P13_5_AMUXB = 5, /* Analog mux bus B */ 2209 P13_5_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2210 P13_5_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2211 P13_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ 2212 P13_5_TCPWM1_LINE_COMPL10 = 9, /* Digital Active - tcpwm[1].line_compl[10]:1 */ 2213 P13_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:98 */ 2214 P13_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:98 */ 2215 P13_5_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:1 */ 2216 P13_5_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:1 */ 2217 P13_5_SCB12_UART_TX = 18, /* Digital Active - scb[12].uart_tx:0 */ 2218 P13_5_SCB12_I2C_SDA = 19, /* Digital Active - scb[12].i2c_sda:0 */ 2219 P13_5_SCB6_SPI_SELECT2 = 20, /* Digital Active - scb[6].spi_select2:1 */ 2220 P13_5_AUDIOSS1_RX_WS = 22, /* Digital Active - audioss[1].rx_ws:0 */ 2221 P13_5_SDHC1_CARD_DAT_7TO41 = 26, /* Digital Active - sdhc[1].card_dat_7to4[1] */ 2222 2223 /* P13.6 */ 2224 P13_6_GPIO = 0, /* GPIO controls 'out' */ 2225 P13_6_AMUXA = 4, /* Analog mux bus A */ 2226 P13_6_AMUXB = 5, /* Analog mux bus B */ 2227 P13_6_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2228 P13_6_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2229 P13_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ 2230 P13_6_TCPWM1_LINE11 = 9, /* Digital Active - tcpwm[1].line[11]:1 */ 2231 P13_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:99 */ 2232 P13_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:99 */ 2233 P13_6_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:1 */ 2234 P13_6_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:1 */ 2235 P13_6_SCB12_UART_RTS = 18, /* Digital Active - scb[12].uart_rts:0 */ 2236 P13_6_SCB6_SPI_SELECT3 = 20, /* Digital Active - scb[6].spi_select3:1 */ 2237 P13_6_AUDIOSS1_RX_SDI = 22, /* Digital Active - audioss[1].rx_sdi:0 */ 2238 P13_6_SDHC1_CARD_DAT_7TO42 = 26, /* Digital Active - sdhc[1].card_dat_7to4[2] */ 2239 2240 /* P13.7 */ 2241 P13_7_GPIO = 0, /* GPIO controls 'out' */ 2242 P13_7_AMUXA = 4, /* Analog mux bus A */ 2243 P13_7_AMUXB = 5, /* Analog mux bus B */ 2244 P13_7_AMUXA_DSI = 6, /* Analog mux bus A, DSI control */ 2245 P13_7_AMUXB_DSI = 7, /* Analog mux bus B, DSI control */ 2246 P13_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ 2247 P13_7_TCPWM1_LINE_COMPL11 = 9, /* Digital Active - tcpwm[1].line_compl[11]:1 */ 2248 P13_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:100 */ 2249 P13_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:100 */ 2250 P13_7_LCD_COM38 = 12, /* Digital Deep Sleep - lcd.com[38]:1 */ 2251 P13_7_LCD_SEG38 = 13, /* Digital Deep Sleep - lcd.seg[38]:1 */ 2252 P13_7_SCB12_UART_CTS = 18, /* Digital Active - scb[12].uart_cts:0 */ 2253 P13_7_SDHC1_CARD_DAT_7TO43 = 26 /* Digital Active - sdhc[1].card_dat_7to4[3] */ 2254 } en_hsiom_sel_t; 2255 2256 #endif /* _GPIO_PSOC6_02_124_BGA_H_ */ 2257 2258 2259 /* [] END OF FILE */ 2260
