1 /****************************************************************************//**
2 * @file i2s.h
3 * @version V3.00
4 * @brief I2S driver header file
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
8 *****************************************************************************/
9 #ifndef __I2S_H__
10 #define __I2S_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup I2S_Driver I2S Driver
23 @{
24 */
25
26 /** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
27 @{
28 */
29
30 #define I2S_DATABIT_8 (0UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
31 #define I2S_DATABIT_16 (1UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
32 #define I2S_DATABIT_24 (2UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
33 #define I2S_DATABIT_32 (3UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
34
35 /* Audio Format */
36 #define I2S_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */
37 #define I2S_STEREO (0UL) /*!< Stereo channel \hideinitializer */
38 #define I2S_ENABLE_MONO I2S_MONO
39 #define I2S_DISABLE_MONO I2S_STEREO
40
41 /* I2S Data Format */
42 #define I2S_FORMAT_I2S (0UL << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */
43 #define I2S_FORMAT_I2S_MSB (1UL << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */
44 #define I2S_FORMAT_I2S_LSB (2UL << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */
45 #define I2S_FORMAT_PCM (4UL << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */
46 #define I2S_FORMAT_PCM_MSB (5UL << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */
47 #define I2S_FORMAT_PCM_LSB (6UL << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */
48
49 /* I2S Data Format */
50 #define I2S_ORDER_AT_MSB 0UL /*!< Channel data is at MSB \hideinitializer */
51 #define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */
52
53 /* I2S TDM Channel Number */
54 #define I2S_TDM_2CH 0UL /*!< Use TDM 2 channel \hideinitializer */
55 #define I2S_TDM_4CH 1UL /*!< Use TDM 4 channel \hideinitializer */
56 #define I2S_TDM_6CH 2UL /*!< Use TDM 6 channel \hideinitializer */
57 #define I2S_TDM_8CH 3UL /*!< Use TDM 8 channel \hideinitializer */
58
59 /* I2S TDM Channel Width */
60 #define I2S_TDM_WIDTH_8BIT 0UL /*!< TDM channel witch is 8-bit \hideinitializer */
61 #define I2S_TDM_WIDTH_16BIT 1UL /*!< TDM channel witch is 16-bit \hideinitializer */
62 #define I2S_TDM_WIDTH_24BIT 2UL /*!< TDM channel witch is 24-bit \hideinitializer */
63 #define I2S_TDM_WIDTH_32BIT 3UL /*!< TDM channel witch is 32-bit \hideinitializer */
64
65 /* I2S TDM Sync Width */
66 #define I2S_TDM_SYNC_ONE_BCLK 0UL /*!< TDM sync widht is one BLCK period \hideinitializer */
67 #define I2S_TDM_SYNC_ONE_CHANNEL 1UL /*!< TDM sync widht is one channel period \hideinitializer */
68
69 /* I2S Operation mode */
70 #define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */
71 #define I2S_MODE_MASTER 0UL /*!< As master mode \hideinitializer */
72
73 /* I2S FIFO Threshold */
74 #define I2S_FIFO_TX_LEVEL_WORD_0 0UL /*!< TX threshold is 0 word \hideinitializer */
75 #define I2S_FIFO_TX_LEVEL_WORD_1 (1UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
76 #define I2S_FIFO_TX_LEVEL_WORD_2 (2UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
77 #define I2S_FIFO_TX_LEVEL_WORD_3 (3UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
78 #define I2S_FIFO_TX_LEVEL_WORD_4 (4UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
79 #define I2S_FIFO_TX_LEVEL_WORD_5 (5UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
80 #define I2S_FIFO_TX_LEVEL_WORD_6 (6UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
81 #define I2S_FIFO_TX_LEVEL_WORD_7 (7UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
82 #define I2S_FIFO_TX_LEVEL_WORD_8 (8UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */
83 #define I2S_FIFO_TX_LEVEL_WORD_9 (9UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */
84 #define I2S_FIFO_TX_LEVEL_WORD_10 (10UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */
85 #define I2S_FIFO_TX_LEVEL_WORD_11 (11UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */
86 #define I2S_FIFO_TX_LEVEL_WORD_12 (12UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */
87 #define I2S_FIFO_TX_LEVEL_WORD_13 (13UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */
88 #define I2S_FIFO_TX_LEVEL_WORD_14 (14UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */
89 #define I2S_FIFO_TX_LEVEL_WORD_15 (15UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */
90
91 #define I2S_FIFO_RX_LEVEL_WORD_1 0UL /*!< RX threshold is 1 word \hideinitializer */
92 #define I2S_FIFO_RX_LEVEL_WORD_2 (1UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
93 #define I2S_FIFO_RX_LEVEL_WORD_3 (2UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
94 #define I2S_FIFO_RX_LEVEL_WORD_4 (3UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
95 #define I2S_FIFO_RX_LEVEL_WORD_5 (4UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
96 #define I2S_FIFO_RX_LEVEL_WORD_6 (5UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
97 #define I2S_FIFO_RX_LEVEL_WORD_7 (6UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
98 #define I2S_FIFO_RX_LEVEL_WORD_8 (7UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
99 #define I2S_FIFO_RX_LEVEL_WORD_9 (8UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */
100 #define I2S_FIFO_RX_LEVEL_WORD_10 (9UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */
101 #define I2S_FIFO_RX_LEVEL_WORD_11 (10UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */
102 #define I2S_FIFO_RX_LEVEL_WORD_12 (11UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */
103 #define I2S_FIFO_RX_LEVEL_WORD_13 (12UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */
104 #define I2S_FIFO_RX_LEVEL_WORD_14 (13UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */
105 #define I2S_FIFO_RX_LEVEL_WORD_15 (14UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */
106 #define I2S_FIFO_RX_LEVEL_WORD_16 (15UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */
107
108 /* I2S Record Channel */
109 #define I2S_MONO_RIGHT 0UL /*!< Record mono right channel \hideinitializer */
110 #define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
111
112 /* I2S Channel */
113 #define I2S_RIGHT 0UL /*!< Select right channel \hideinitializer */
114 #define I2S_LEFT 1UL /*!< Select left channel \hideinitializer */
115
116 /**@}*/ /* end of group I2S_EXPORTED_CONSTANTS */
117
118
119 /** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
120 @{
121 */
122
123
124 /**
125 * @brief Enable zero cross detect function.
126 * @param[in] i2s is the base address of I2S module.
127 * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
128 * @return none
129 * \hideinitializer
130 */
I2S_ENABLE_TX_ZCD(I2S_T * i2s,uint32_t u32ChMask)131 __STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
132 {
133 if((u32ChMask > 0UL) && (u32ChMask < 9UL))
134 {
135 i2s->CTL1 |= (1UL << (u32ChMask - 1UL));
136 }
137 }
138
139 /**
140 * @brief Disable zero cross detect function.
141 * @param[in] i2s is the base address of I2S module.
142 * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
143 * @return none
144 * \hideinitializer
145 */
I2S_DISABLE_TX_ZCD(I2S_T * i2s,uint32_t u32ChMask)146 __STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
147 {
148 if((u32ChMask > 0UL) && (u32ChMask < 9UL))
149 {
150 i2s->CTL1 &= ~(1UL << (u32ChMask - 1UL));
151 }
152 }
153
154 /**
155 * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
156 * @param[in] i2s is the base address of I2S module.
157 * @return none
158 * \hideinitializer
159 */
160 #define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
161
162 /**
163 * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
164 * @param[in] i2s is the base address of I2S module.
165 * @return none
166 * \hideinitializer
167 */
168 #define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
169
170 /**
171 * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
172 * @param[in] i2s is the base address of I2S module.
173 * @return none
174 * \hideinitializer
175 */
176 #define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
177
178 /**
179 * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
180 * @param[in] i2s is the base address of I2S module.
181 * @return none
182 * \hideinitializer
183 */
184 #define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
185
186 /**
187 * @brief Enable I2S Tx function .
188 * @param[in] i2s is the base address of I2S module.
189 * @return none
190 * \hideinitializer
191 */
192 #define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
193
194 /**
195 * @brief Disable I2S Tx function .
196 * @param[in] i2s is the base address of I2S module.
197 * @return none
198 * \hideinitializer
199 */
200 #define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
201
202 /**
203 * @brief Enable I2S Rx function .
204 * @param[in] i2s is the base address of I2S module.
205 * @return none
206 * \hideinitializer
207 */
208 #define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
209
210 /**
211 * @brief Disable I2S Rx function .
212 * @param[in] i2s is the base address of I2S module.
213 * @return none
214 * \hideinitializer
215 */
216 #define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
217
218 /**
219 * @brief Enable Tx Mute function .
220 * @param[in] i2s is the base address of I2S module.
221 * @return none
222 * \hideinitializer
223 */
224 #define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
225
226 /**
227 * @brief Disable Tx Mute function .
228 * @param[in] i2s is the base address of I2S module.
229 * @return none
230 * \hideinitializer
231 */
232 #define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
233
234 /**
235 * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
236 * @param[in] i2s is the base address of I2S module.
237 * @return none
238 * \hideinitializer
239 */
240 #define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
241
242 /**
243 * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
244 * @param[in] i2s is the base address of I2S module.
245 * @return none
246 * \hideinitializer
247 */
248 #define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
249
250 /**
251 * @brief This function sets the recording source channel when mono mode is used.
252 * @param[in] i2s is the base address of I2S module.
253 * @param[in] u32Ch left or right channel. Valid values are:
254 * - \ref I2S_MONO_LEFT
255 * - \ref I2S_MONO_RIGHT
256 * @return none
257 * \hideinitializer
258 */
I2S_SET_MONO_RX_CHANNEL(I2S_T * i2s,uint32_t u32Ch)259 __STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
260 {
261 u32Ch == I2S_MONO_LEFT ?
262 (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
263 (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
264 }
265
266 /**
267 * @brief Write data to I2S Tx FIFO.
268 * @param[in] i2s is the base address of I2S module.
269 * @param[in] u32Data: The data written to FIFO.
270 * @return none
271 * \hideinitializer
272 */
273 #define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) )
274
275 /**
276 * @brief Read Rx FIFO.
277 * @param[in] i2s is the base address of I2S module.
278 * @return Data in Rx FIFO.
279 * \hideinitializer
280 */
281 #define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
282
283 /**
284 * @brief This function gets the interrupt flag according to the mask parameter.
285 * @param[in] i2s is the base address of I2S module.
286 * @param[in] u32Mask is the mask for the all interrupt flags.
287 * @return The masked bit value of interrupt flag.
288 * \hideinitializer
289 */
290 #define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
291
292 /**
293 * @brief This function clears the interrupt flag according to the mask parameter.
294 * @param[in] i2s is the base address of I2S module.
295 * @param[in] u32Mask is the mask for the all interrupt flags.
296 * @return none
297 * \hideinitializer
298 */
299 #define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
300
301 /**
302 * @brief This function gets the zero crossing interrupt flag according to the mask parameter.
303 * @param[in] i2s is the base address of I2S module.
304 * @param[in] u32Mask is the mask for the all interrupt flags.
305 * @return The masked bit value of interrupt flag.
306 * \hideinitializer
307 */
308 #define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
309
310 /**
311 * @brief This function clears the zero crossing interrupt flag according to the mask parameter.
312 * @param[in] i2s is the base address of I2S module.
313 * @param[in] u32Mask is the mask for the all interrupt flags.
314 * @return none
315 * \hideinitializer
316 */
317 #define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
318
319 /**
320 * @brief Get transmit FIFO level
321 * @param[in] i2s is the base address of I2S module.
322 * @return FIFO level
323 * \hideinitializer
324 */
325 #define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
326
327 /**
328 * @brief Get receive FIFO level
329 * @param[in] i2s is the base address of I2S module.
330 * @return FIFO level
331 * \hideinitializer
332 */
333 #define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
334
335 uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat);
336 void I2S_Close(I2S_T *i2s);
337 void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
338 void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
339 uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
340 void I2S_DisableMCLK(I2S_T *i2s);
341 void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
342 void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
343
344
345 /**@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
346
347 /**@}*/ /* end of group I2S_Driver */
348
349 /**@}*/ /* end of group Standard_Driver */
350
351 #ifdef __cplusplus
352 }
353 #endif
354
355 #endif /* __I2S_H__ */
356
