1 /**************************************************************************//** 2 * @file fmc_reg.h 3 * @version V1.00 4 * @brief FMC register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __FMC_REG_H__ 10 #define __FMC_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- Flash Memory Controller -------------------------*/ 20 /** 21 @addtogroup FMC Flash Memory Controller(FMC) 22 Memory Mapped Structure for FMC Controller 23 @{ */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var FMC_T::ISPCTL 31 * Offset: 0x00 ISP Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |ISPEN |ISP Enable Bit (Write Protect) 36 * | | |ISP function enable bit. Set this bit to enable ISP function. 37 * | | |0 = ISP function Disabled. 38 * | | |1 = ISP function Enabled. 39 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 40 * |[1] |BS |Boot Select (Write Protect) 41 * | | |When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively 42 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from 43 * | | |This bit is initiated with the inverse value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 44 * | | |0 = Booting from APROM when MBS (CONFIG0[5]) is 1. 45 * | | |1 = Booting from LDROM when MBS (CONFIG0[5]) is 1. 46 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 47 * |[3] |APUEN |APROM Update Enable Bit (Write Protect) 48 * | | |0 = APROM cannot be updated when the chip runs in APROM. 49 * | | |1 = APROM can be updated when the chip runs in APROM. 50 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 51 * |[4] |CFGUEN |CONFIG Update Enable Bit (Write Protect) 52 * | | |0 = CONFIG cannot be updated. 53 * | | |1 = CONFIG can be updated. 54 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 55 * |[5] |LDUEN |LDROM Update Enable Bit (Write Protect) 56 * | | |LDROM update enable bit. 57 * | | |0 = LDROM cannot be updated. 58 * | | |1 = LDROM can be updated. 59 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 60 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 61 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 62 * | | |This bit needs to be cleared by writing 1 to it. 63 * | | |(1) APROM writes to itself if APUEN is set to 0. 64 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 65 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 66 * | | |(4) Page Erase command at LOCK mode with ICE connection 67 * | | |(5) Erase or Program command at brown-out detected 68 * | | |(6) Destination address is illegal, such as over an available range. 69 * | | |(7) Invalid ISP commands 70 * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 71 * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 72 * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 73 * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0 74 * | | |(12) Read any content of boot loader with ICE connection 75 * | | |(13) The address of block erase and bank erase is not in APROM 76 * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command 77 * | | |(15) The wrong setting of page erase ISP CMD in XOM 78 * | | |(16) Violate XOM setting one time protection 79 * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page 80 * | | |(18) Mass erase when MERASE (CFG0[13]) is disable 81 * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP 82 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 83 * |[16] |BL |Boot Loader Booting (Write Protect) 84 * | | |This bit is initiated with the inverses value of MBS (CONFIG0[5]) 85 * | | |Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded 86 * | | |This bit is used to check chip boot from Boot Loader or not 87 * | | |User should keep original value of this bit when updating FMC_ISPCTL register. 88 * | | |0 = Booting from APROM or LDROM. 89 * | | |1 = Booting from Boot Loader. 90 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 91 * |[24] |INTEN |Interrupt Enable (Write Protect) 92 * | | |0 = ISP INT Disabled. 93 * | | |1 = ISP INT Enabled. 94 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. Before use INT, user need to clear the INTFLAG(FMC_ISPSTS[24]) make sure INT happen at correct time. 95 * @var FMC_T::ISPADDR 96 * Offset: 0x04 ISP Address Register 97 * --------------------------------------------------------------------------------------------------- 98 * |Bits |Field |Descriptions 99 * | :----: | :----: | :---- | 100 * |[31:0] |ISPADDR |ISP Address 101 * | | |The NuMicro M2351 series is equipped with embedded flash 102 * | | |ISPADDR[1:0] must be kept 00 for ISP 32-bit operation 103 * | | |ISPADDR[2:0] must be kept 000 for ISP 64-bit operation. 104 * | | |For CRC32 Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 KBytes alignment is necessary for CRC32 checksum calculation. 105 * | | |For FLASH 32-bit Program, ISP address needs word alignment (4-byte) 106 * | | |For FLASH 64-bit Program, ISP address needs double word alignment (8-byte). 107 * @var FMC_T::ISPDAT 108 * Offset: 0x08 ISP Data Register 109 * --------------------------------------------------------------------------------------------------- 110 * |Bits |Field |Descriptions 111 * | :----: | :----: | :---- | 112 * |[31:0] |ISPDAT |ISP Data 113 * | | |Write data to this register before ISP program operation. 114 * | | |Read data from this register after ISP read operation. 115 * | | |When ISPFF (FMC_ISPCTL[6]) is 1, ISPDAT = 0xffff_ffff 116 * | | |For Run CRC32 Checksum Calculation command, ISPDAT is the memory size (byte) and 2 KBytes alignment 117 * | | |For ISP Read CRC32 Checksum command, ISPDAT is the checksum result 118 * | | |If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, or (2) the memory range for checksum calculation is incorrect 119 * | | |For XOM page erase function, , ISPDAT = 0x0055_aa03. 120 * @var FMC_T::ISPCMD 121 * Offset: 0x0C ISP Command Register 122 * --------------------------------------------------------------------------------------------------- 123 * |Bits |Field |Descriptions 124 * | :----: | :----: | :---- | 125 * |[6:0] |CMD |ISP Command 126 * | | |ISP command table is shown below: 127 * | | |0x00= FLASH Read. 128 * | | |0x04= Read Unique ID. 129 * | | |0x08= Read Flash All-One Result. 130 * | | |0x0B= Read Company ID. 131 * | | |0x0C= Read Device ID. 132 * | | |0x0D= Read Checksum. 133 * | | |0x21= FLASH 32-bit Program. 134 * | | |0x22= FLASH Page Erase. Erase any page in two banks, except for OTP. 135 * | | |0x23= FLASH Bank Erase. Erase all pages of APROM in BANK0 or BANK1. 136 * | | |0x25= FLASH Block Erase Erase four pages alignment of APROM in BANK0 or BANK1.. 137 * | | |0x27= FLASH Multi-Word Program. 138 * | | |0x28= Run Flash All-One Verification. 139 * | | |0x2D= Run Checksum Calculation. 140 * | | |0x2E= Vector Remap. 141 * | | |0x40= FLASH 64-bit Read. 142 * | | |0x61= FLASH 64-bit Program. 143 * | | |The other commands are invalid. 144 * @var FMC_T::ISPTRG 145 * Offset: 0x10 ISP Trigger Control Register 146 * --------------------------------------------------------------------------------------------------- 147 * |Bits |Field |Descriptions 148 * | :----: | :----: | :---- | 149 * |[0] |ISPGO |ISP Start Trigger (Write Protect) 150 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished 151 * | | |When ISPGO=1, the operation of accessing value from address FMC_BA+0x00 to FMC_BA+0x68 would halt CPU still ISPGO =0 152 * | | |If user want to monitor whether ISP finish or not,user can access FMC_MPSTS[0] MPBUSY. 153 * | | |0 = ISP operation is finished. 154 * | | |1 = ISP is progressed. 155 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 156 * @var FMC_T::ISPSTS 157 * Offset: 0x40 ISP Status Register 158 * --------------------------------------------------------------------------------------------------- 159 * |Bits |Field |Descriptions 160 * | :----: | :----: | :---- | 161 * |[0] |ISPBUSY |ISP Busy Flag (Read Only) 162 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished. 163 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 164 * | | |0 = ISP operation is finished. 165 * | | |1 = ISP is progressed. 166 * |[2] |CBS |Boot Selection of CONFIG (Read Only) 167 * | | |This bit is initiated with the CBS (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened. 168 * | | |The following function is valid when MBS (FMC_ISPSTS[3])= 1. 169 * | | |0 = LDROM with IAP mode. 170 * | | |1 = APROM with IAP mode. 171 * |[3] |MBS |Boot From Boot Loader Selection Flag (Read Only) 172 * | | |This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened 173 * | | |0 = Booting from Boot Loader. 174 * | | |1 = Booting from LDROM/APROM.(.see CBS bit setting) 175 * |[4] |FCYCDIS |Flash Access Cycle Auto-tuning Disabled Flag (Read Only) 176 * | | |This bit is set if flash access cycle auto-tuning function is disabled 177 * | | |The auto-tuning function is disabled by FADIS(FMC_CYCCTL[8]) or HIRC clock is not ready. 178 * | | |0 = Flash access cycle auto-tuning is Enabled. 179 * | | |1 = Flash access cycle auto-tuning is Disabled. 180 * |[5] |PGFF |Flash Program with Fast Verification Flag (Read Only) 181 * | | |This bit is set if data is mismatched at ISP programming verification 182 * | | |This bit is clear by performing ISP flash erase or ISP read CID operation 183 * | | |0 = Flash Program is success. 184 * | | |1 = Flash Program is fail. Program data is different with data in the flash memory 185 * |[6] |ISPFF |ISP Fail Flag (Write Protect) 186 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] if this bit is set. 187 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 188 * | | |(1) APROM writes to itself if APUEN is set to 0. 189 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 190 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 191 * | | |(4) Page Erase command at LOCK mode with ICE connection 192 * | | |(5) Erase or Program command at brown-out detected 193 * | | |(6) Destination address is illegal, such as over an available range. 194 * | | |(7) Invalid ISP commands 195 * | | |(8) KPROM is erased/programmed if KEYLOCK is set to 1 196 * | | |(9) APROM is erased/programmed if KEYLOCK is set to 1 197 * | | |(10) LDROM is erased/programmed if KEYLOCK is set to 1 198 * | | |(11) CONFIG is erased/programmed if KEYLOCK is set to 1 and KEYENROM[0] is 0. 199 * | | |(12) Read any content of boot loader with ICE connection 200 * | | |(13) The address of block erase and bank erase is not in APROM 201 * | | |(14) ISP CMD in XOM region, except mass erase, page erase and chksum command 202 * | | |(15) The wrong setting of page erase ISP CMD in XOM 203 * | | |(16) Violate XOM setting one time protection 204 * | | |(17) Page erase ISP CMD in Secure/Non-secure region setting page 205 * | | |(18) Mass erase when MERASE (CFG0[13]) is disable 206 * | | |(19) Page erase, mass erase , multi-word program or 64-bit word program in OTP 207 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 208 * |[7] |ALLONE |Flash All-one Verification Flag 209 * | | |This bit is set by hardware if all of flash bits are 1, and clear if flash bits are not all 1 after Run Flash All-One Verification complete; this bit also can be clear by writing 1 210 * | | |0 = All of flash bits are 1 after Run Flash All-One Verification complete. 211 * | | |1 = Flash bits are not all 1 after Run Flash All-One Verification complete. 212 * |[23:9] |VECMAP |Vector Page Mapping Address (Read Only) 213 * | | |All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF} 214 * |[24] |INTFLAG |Interrupt Flag 215 * | | |0 = ISP is not finish. 216 * | | |1 = ISP done or ISPFF set. 217 * @var FMC_T::CYCCTL 218 * Offset: 0x4C Flash Access Cycle Control Register 219 * --------------------------------------------------------------------------------------------------- 220 * |Bits |Field |Descriptions 221 * | :----: | :----: | :---- | 222 * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) 223 * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1). 224 * | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0. 225 * | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware. 226 * | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz. 227 * | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz. 228 * | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz. 229 * | | |Others = Reserved. 230 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 231 * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect) 232 * | | |Set this bit to disable flash access cycle auto-tuning function 233 * | | |0 = Flash access cycle auto-tuning is enabled. 234 * | | |1 = Flash access cycle auto-tuning is disabled. 235 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 236 * @var FMC_T::KPKEY0 237 * Offset: 0x50 KPROM KEY0 Data Register 238 * --------------------------------------------------------------------------------------------------- 239 * |Bits |Field |Descriptions 240 * | :----: | :----: | :---- | 241 * |[31:0] |KPKEY0 |KPROM KEY0 Data (Write Only) 242 * | | |Write KPKEY0 data to this register before KEY Comparison operation. 243 * @var FMC_T::KPKEY1 244 * Offset: 0x54 KPROM KEY1 Data Register 245 * --------------------------------------------------------------------------------------------------- 246 * |Bits |Field |Descriptions 247 * | :----: | :----: | :---- | 248 * |[31:0] |KPKEY1 |KPROM KEY1 Data (Write Only) 249 * | | |Write KPKEY1 data to this register before KEY Comparison operation. 250 * @var FMC_T::KPKEY2 251 * Offset: 0x58 KPROM KEY2 Data Register 252 * --------------------------------------------------------------------------------------------------- 253 * |Bits |Field |Descriptions 254 * | :----: | :----: | :---- | 255 * |[31:0] |KPKEY2 |KPROM KEY2 Data (Write Only) 256 * | | |Write KPKEY2 data to this register before KEY Comparison operation. 257 * @var FMC_T::KPKEYTRG 258 * Offset: 0x5C KPROM KEY Comparison Trigger Control Register 259 * --------------------------------------------------------------------------------------------------- 260 * |Bits |Field |Descriptions 261 * | :----: | :----: | :---- | 262 * |[0] |KPKEYGO |KPROM KEY Comparison Start Trigger (Write Protection) 263 * | | |Write 1 to start KEY comparison operation and this bit will be cleared to 0 by hardware automatically when KEY comparison operation is finished 264 * | | |This trigger operation is valid while FORBID (FMC_KPKEYSTS [3]) is 0. 265 * | | |0 = KEY comparison operation is finished. 266 * | | |1 = KEY comparison is progressed. 267 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 268 * |[1] |TCEN |Timeout Counting Enable (Write Protection) 269 * | | |0 = Timeout counting is disabled. 270 * | | |1 = Timeout counting is enabled if input key is matched after key comparison finish. 271 * | | |10 minutes is at least for timeout, and average is about 20 minutes. 272 * | | |Note: This bit is write-protected. Refer to the SYS_REGLCTL register. 273 * @var FMC_T::KPKEYSTS 274 * Offset: 0x60 KPROM KEY Comparison Status Register 275 * --------------------------------------------------------------------------------------------------- 276 * |Bits |Field |Descriptions 277 * | :----: | :----: | :---- | 278 * |[0] |KEYBUSY |KEY Comparison Busy (Read Only) 279 * | | |0 = KEY comparison is finished. 280 * | | |1 = KEY comparison is busy. 281 * |[1] |KEYLOCK |KEY LOCK Flag 282 * | | |This bit is set to 1 if KEYMATCH (FMC_KPKEYSTS [2]) is 0 and cleared to 0 if KEYMATCH is 1 in Security Key protection 283 * | | |After Mass Erase operation, users must reset or power on /off to clear this bit to 0 284 * | | |This bit also can be set to 1 while 285 * | | |l CPU write 1 to KEYLOCK(FMC_KPKEYSTS[1]) or 286 * | | |l KEYFLAG(FMC_KPKEYSTS[4]) is 1 at power-on or reset or 287 * | | |l KEYENROM is programmed a non-0x5a value or 288 * | | |l Timeout event or 289 * | | |l FORBID(FMC_KPKEYSTS[3]) is 1 290 * | | |0 = KPROM, LDROM and APROM (not include Data Flash) is not in write protection. 291 * | | |1 = KPROM, LDROM and APROM (not include Data Flash) is in write protection. 292 * | | |CONFIG write protect is depended on CFGFLAG 293 * |[2] |KEYMATCH |KEY Match Flag (Read Only) 294 * | | |This bit is set to 1 after KEY comparison complete if the KEY0, KEY1 and KEY2 are matched with the 96-bit security keys in KPROM; and cleared to 0 if KEYs are unmatched 295 * | | |This bit is also cleared to 0 while 296 * | | |l CPU writing 1 to KEYLOCK(FMC_KPKEYSTS[1]) or 297 * | | |l Timeout event or 298 * | | |l KPROM is erased or 299 * | | |l KEYENROM is programmed to a non-0x5a value. 300 * | | |l Chip is in power down mode. 301 * | | |0 = KEY0, KEY1, and KEY2 are unmatched with the KPROM setting. 302 * | | |1 = KEY0, KEY1, and KEY2 are matched with the KPROM setting. 303 * |[3] |FORBID |KEY Comparison Forbidden Flag (Read Only) 304 * | | |This bit is set to 1 when KPKECNT(FMC_KPKEY0[4:0]) is more than KPKEMAX (FMC_KPKEY0[12:8]) or KPCNT (FMC_KPCNT [2:0]) is more than KPMAX (FMC_KPCNT [10:8]). 305 * | | |0 = KEY comparison is not forbidden. 306 * | | |1 = KEY comparison is forbidden, KEYGO (FMC_KEYTRG [0]) cannot trigger. 307 * |[4] |KEYFLAG |KEY Protection Enabled Flag (Read Only) 308 * | | |This bit is set while the KEYENROM [7:0] is not 0x5a at power-on or reset 309 * | | |This bit is cleared to 0 by hardware while KPROM is erased 310 * | | |This bit is set to 1 by hardware while KEYENROM is programmed to a non-0x5a value. 311 * | | |0 = Security Key protection is disabled. 312 * | | |1 = Security Key protection is enabled. 313 * |[5] |CFGFLAG |CONFIG Write-protection Enabled Flag (Read Only) 314 * | | |This bit is set while the KEYENROM [0] is 0 at power-on or reset 315 * | | |This bit is cleared to 0 by hardware while KPROM is erased 316 * | | |This bit is set to 1 by hardware while KEYENROM[0] is programmed to 0. 317 * | | |0 = CONFIG write-protection is disabled. 318 * | | |1 = CONFIG write-protection is enabled. 319 * |[8] |SBKPBUSY |Secure Boot Key Programming BUSY (Read Only) 320 * | | |This bit is set to 1 while secure boot key program function is running 321 * | | |This bit is cleared to 0 while secure boot key key program function had been done. 322 * | | |0 = Secure boot key program function is done. 323 * | | |1 = Secure boot key program function is busy. 324 * |[9] |SBKPFLAG |Secure Boot Key Programming Flag (Read Only) 325 * | | |This bit is set to 1 while secure boot key program function fails 326 * | | |This bit is cleared to 0 while secure boot key had been programmed into flash memory. 327 * | | |0 = Secure boot key program function is successful. 328 * | | |1 = Secure boot key program function fails. 329 * @var FMC_T::KPKEYCNT 330 * Offset: 0x64 KPROM KEY-Unmatched Counting Register 331 * --------------------------------------------------------------------------------------------------- 332 * |Bits |Field |Descriptions 333 * | :----: | :----: | :---- | 334 * |[5:0] |KPKECNT |Error Key Entry Counter at Each Power-on (Read Only) 335 * | | |KPKECNT is increased when entry keys is wrong in Security Key protection 336 * | | |KPKECNT is cleared to 0 if key comparison is matched or system power-on. 337 * |[13:8] |KPKEMAX |Maximum Number for Error Key Entry at Each Power-on (Read Only) 338 * | | |KPKEMAX is the maximum error key entry number at each power-on 339 * | | |When KPKEMAXROM of KPROM is erased or programmed, KPKEMAX will also be updated 340 * | | |KPKEMAX is used to limit KPKECNT(FMC_KPKEY0[5:0]) maximum counting 341 * | | |The FORBID (FMC_KPKEYSTS [3]) will be set to 1 when KPKECNT is more than KPKEMAX. 342 * @var FMC_T::KPCNT 343 * Offset: 0x68 KPROM KEY-Unmatched Power-On Counting Register 344 * --------------------------------------------------------------------------------------------------- 345 * |Bits |Field |Descriptions 346 * | :----: | :----: | :---- | 347 * |[3:0] |KPCNT |Power-on Counter for Error Key Entry(Read Only) 348 * | | |KPCNT is the power-on counting for error key entry in Security Key protection 349 * | | |KPCNT is cleared to 0 if key comparison is matched. 350 * |[11:8] |KPMAX |Power-on Maximum Number for Error Key Entry (Read Only) 351 * | | |KPMAX is the power-on maximum number for error key entry 352 * | | |When KPMAXROM of KPROM is erased or programmed, KPMAX will also be updated 353 * | | |KPMAX is used to limit KPCNT (FMC_KPCNT [3:0]) maximum counting 354 * | | |The FORBID(FMC_KPKEYSTS[3]) will be set to 1 when KPCNT is more than KPMAX 355 * @var FMC_T::MPDAT0 356 * Offset: 0x80 ISP Data0 Register 357 * --------------------------------------------------------------------------------------------------- 358 * |Bits |Field |Descriptions 359 * | :----: | :----: | :---- | 360 * |[31:0] |ISPDAT0 |ISP Data 0 361 * | | |This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data 362 * @var FMC_T::MPDAT1 363 * Offset: 0x84 ISP Data1 Register 364 * --------------------------------------------------------------------------------------------------- 365 * |Bits |Field |Descriptions 366 * | :----: | :----: | :---- | 367 * |[31:0] |ISPDAT1 |ISP Data 1 368 * | | |This register is the second 32-bit data for 64-bit/multi-word programming. 369 * @var FMC_T::MPDAT2 370 * Offset: 0x88 ISP Data2 Register 371 * --------------------------------------------------------------------------------------------------- 372 * |Bits |Field |Descriptions 373 * | :----: | :----: | :---- | 374 * |[31:0] |ISPDAT2 |ISP Data 2 375 * | | |This register is the third 32-bit data for multi-word programming. 376 * @var FMC_T::MPDAT3 377 * Offset: 0x8C ISP Data3 Register 378 * --------------------------------------------------------------------------------------------------- 379 * |Bits |Field |Descriptions 380 * | :----: | :----: | :---- | 381 * |[31:0] |ISPDAT3 |ISP Data 3 382 * | | |This register is the fourth 32-bit data for multi-word programming. 383 * @var FMC_T::MPSTS 384 * Offset: 0xC0 ISP Multi-Program Status Register 385 * --------------------------------------------------------------------------------------------------- 386 * |Bits |Field |Descriptions 387 * | :----: | :----: | :---- | 388 * |[0] |MPBUSY |ISP Multi-word Program Busy Flag (Read Only) 389 * | | |Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished. 390 * | | |This bit is the mirror of ISPGO(FMC_ISPTRG[0]). 391 * | | |0 = ISP Multi-Word program operation is finished. 392 * | | |1 = ISP Multi-Word program operation is progressed. 393 * |[1] |PPGO |ISP Multi-program Status (Read Only) 394 * | | |0 = ISP multi-word program operation is not active. 395 * | | |1 = ISP multi-word program operation is in progress. 396 * |[2] |ISPFF |ISP Fail Flag (Read Only) 397 * | | |This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6] 398 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions: 399 * | | |(1) APROM writes to itself if APUEN is set to 0. 400 * | | |(2) LDROM writes to itself if LDUEN is set to 0. 401 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0. 402 * | | |(4) Page Erase command at LOCK mode with ICE connection 403 * | | |(5) Erase or Program command at brown-out detected 404 * | | |(6) Destination address is illegal, such as over an available range. 405 * | | |(7) Invalid ISP commands 406 * |[4] |D0 |ISP DATA 0 Flag (Read Only) 407 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete. 408 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete. 409 * | | |1 = FMC_MPDAT0 register has been written, and not program to flash complete. 410 * |[5] |D1 |ISP DATA 1 Flag (Read Only) 411 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete. 412 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete. 413 * | | |1 = FMC_MPDAT1 register has been written, and not program to flash complete. 414 * |[6] |D2 |ISP DATA 2 Flag (Read Only) 415 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete. 416 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete. 417 * | | |1 = FMC_MPDAT2 register has been written, and not program to flash complete. 418 * |[7] |D3 |ISP DATA 3 Flag (Read Only) 419 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete. 420 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete. 421 * | | |1 = FMC_MPDAT3 register has been written, and not program to flash complete. 422 * @var FMC_T::MPADDR 423 * Offset: 0xC4 ISP Multi-Program Address Register 424 * --------------------------------------------------------------------------------------------------- 425 * |Bits |Field |Descriptions 426 * | :----: | :----: | :---- | 427 * |[31:0] |MPADDR |ISP Multi-word Program Address 428 * | | |MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1. 429 * | | |MPADDR will keep the final ISP address when ISP multi-word program is complete. 430 * @var FMC_T::XOMR0STS 431 * Offset: 0xD0 XOM Region 0 Status Register 432 * --------------------------------------------------------------------------------------------------- 433 * |Bits |Field |Descriptions 434 * | :----: | :----: | :---- | 435 * |[7:0] |SIZE |XOM Region 0 Size (Page-aligned) 436 * | | |SIZE is the page number of XOM Region 0. 437 * |[31:8] |BASE |XOM Region 0 Base Address (Page-aligned) 438 * | | |BASE is the base address of XOM Region 0. 439 * @var FMC_T::XOMR1STS 440 * Offset: 0xD4 XOM Region 1 Status Register 441 * --------------------------------------------------------------------------------------------------- 442 * |Bits |Field |Descriptions 443 * | :----: | :----: | :---- | 444 * |[7:0] |SIZE |XOM Region 1 Size (Page-aligned) 445 * | | |SIZE is the page number of XOM Region 1. 446 * |[31:8] |BASE |XOM Region 1 Base Address (Page-aligned) 447 * | | |BASE is the base address of XOM Region 1. 448 * @var FMC_T::XOMR2STS 449 * Offset: 0xD8 XOM Region 2 Status Register 450 * --------------------------------------------------------------------------------------------------- 451 * |Bits |Field |Descriptions 452 * | :----: | :----: | :---- | 453 * |[7:0] |SIZE |XOM Region 2 Size (Page-aligned) 454 * | | |SIZE is the page number of XOM Region 2. 455 * |[31:8] |BASE |XOM Region 2 Base Address (Page-aligned) 456 * | | |BASE is the base address of XOM Region 2. 457 * @var FMC_T::XOMR3STS 458 * Offset: 0xDC XOM Region 3 Status Register 459 * --------------------------------------------------------------------------------------------------- 460 * |Bits |Field |Descriptions 461 * | :----: | :----: | :---- | 462 * |[7:0] |SIZE |XOM Region 3 Size (Page-aligned) 463 * | | |SIZE is the page number of XOM Region 3. 464 * |[31:8] |BASE |XOM Region 3 Base Address (Page-aligned) 465 * | | |BASE is the base address of XOM Region 3. 466 * @var FMC_T::XOMSTS 467 * Offset: 0xE0 XOM Status Register 468 * --------------------------------------------------------------------------------------------------- 469 * |Bits |Field |Descriptions 470 * | :----: | :----: | :---- | 471 * |[0] |XOMR0ON |XOM Region 0 On 472 * | | |XOM Region 0 active status. 473 * | | |0 = No active. 474 * | | |1 = XOM region 0 is active. 475 * |[1] |XOMR1ON |XOM Region 1 On 476 * | | |XOM Region 1 active status. 477 * | | |0 = No active. 478 * | | |1 = XOM region 1 is active. 479 * |[2] |XOMR2ON |XOM Region 2 On 480 * | | |XOM Region 2 active status. 481 * | | |0 = No active. 482 * | | |1 = XOM region 2 is active. 483 * |[3] |XOMR3ON |XOM Region 3 On 484 * | | |XOM Region 3 active status. 485 * | | |0 = No active. 486 * | | |1 = XOM region 3 is active. 487 * |[4] |XOMPEF |XOM Page Erase Function Fail 488 * | | |XOM page erase function status. If XOMPEF is set to 1, user needs to erase XOM region again. 489 * | | |0 = Success. 490 * | | |1 = Fail. 491 */ 492 __IO uint32_t ISPCTL; /*!< [0x0000] ISP Control Register */ 493 __IO uint32_t ISPADDR; /*!< [0x0004] ISP Address Register */ 494 __IO uint32_t ISPDAT; /*!< [0x0008] ISP Data Register */ 495 __IO uint32_t ISPCMD; /*!< [0x000c] ISP Command Register */ 496 __IO uint32_t ISPTRG; /*!< [0x0010] ISP Trigger Control Register */ 497 __I uint32_t RESERVE0[11]; 498 __IO uint32_t ISPSTS; /*!< [0x0040] ISP Status Register */ 499 __I uint32_t RESERVE1[2]; 500 __IO uint32_t CYCCTL; /*!< [0x004c] Flash Access Cycle Control Register */ 501 __O uint32_t KPKEY0; /*!< [0x0050] KPROM KEY0 Data Register */ 502 __O uint32_t KPKEY1; /*!< [0x0054] KPROM KEY1 Data Register */ 503 __O uint32_t KPKEY2; /*!< [0x0058] KPROM KEY2 Data Register */ 504 __IO uint32_t KPKEYTRG; /*!< [0x005c] KPROM KEY Comparison Trigger Control Register */ 505 __IO uint32_t KPKEYSTS; /*!< [0x0060] KPROM KEY Comparison Status Register */ 506 __I uint32_t KPKEYCNT; /*!< [0x0064] KPROM KEY-Unmatched Counting Register */ 507 __I uint32_t KPCNT; /*!< [0x0068] KPROM KEY-Unmatched Power-On Counting Register */ 508 __I uint32_t RESERVE2[5]; 509 __IO uint32_t MPDAT0; /*!< [0x0080] ISP Data0 Register */ 510 __IO uint32_t MPDAT1; /*!< [0x0084] ISP Data1 Register */ 511 __IO uint32_t MPDAT2; /*!< [0x0088] ISP Data2 Register */ 512 __IO uint32_t MPDAT3; /*!< [0x008c] ISP Data3 Register */ 513 __I uint32_t RESERVE3[12]; 514 __I uint32_t MPSTS; /*!< [0x00c0] ISP Multi-Program Status Register */ 515 __I uint32_t MPADDR; /*!< [0x00c4] ISP Multi-Program Address Register */ 516 __I uint32_t RESERVE4[2]; 517 __I uint32_t XOMR0STS; /*!< [0x00d0] XOM Region 0 Status Register */ 518 __I uint32_t XOMR1STS; /*!< [0x00d4] XOM Region 1 Status Register */ 519 __I uint32_t XOMR2STS; /*!< [0x00d8] XOM Region 2 Status Register */ 520 __I uint32_t XOMR3STS; /*!< [0x00dc] XOM Region 3 Status Register */ 521 __I uint32_t XOMSTS; /*!< [0x00e0] XOM Status Register */ 522 523 } FMC_T; 524 525 /** 526 @addtogroup FMC_CONST FMC Bit Field Definition 527 Constant Definitions for FMC Controller 528 @{ */ 529 530 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC_T::ISPCTL: ISPEN Position */ 531 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC_T::ISPCTL: ISPEN Mask */ 532 533 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC_T::ISPCTL: BS Position */ 534 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC_T::ISPCTL: BS Mask */ 535 536 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC_T::ISPCTL: APUEN Position */ 537 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC_T::ISPCTL: APUEN Mask */ 538 539 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC_T::ISPCTL: CFGUEN Position */ 540 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC_T::ISPCTL: CFGUEN Mask */ 541 542 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC_T::ISPCTL: LDUEN Position */ 543 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC_T::ISPCTL: LDUEN Mask */ 544 545 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC_T::ISPCTL: ISPFF Position */ 546 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC_T::ISPCTL: ISPFF Mask */ 547 548 #define FMC_ISPCTL_BL_Pos (16) /*!< FMC_T::ISPCTL: BL Position */ 549 #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) /*!< FMC_T::ISPCTL: BL Mask */ 550 551 #define FMC_ISPCTL_INTEN_Pos (24) /*!< FMC_T::ISPCTL: INTEN Position */ 552 #define FMC_ISPCTL_INTEN_Msk (0x1ul << FMC_ISPCTL_INTEN_Pos) /*!< FMC_T::ISPCTL: INTEN Mask */ 553 554 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC_T::ISPADDR: ISPADDR Position */ 555 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC_T::ISPADDR: ISPADDR Mask */ 556 557 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC_T::ISPDAT: ISPDAT Position */ 558 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */ 559 560 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC_T::ISPCMD: CMD Position */ 561 #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) /*!< FMC_T::ISPCMD: CMD Mask */ 562 563 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC_T::ISPTRG: ISPGO Position */ 564 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */ 565 566 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC_T::ISPSTS: ISPBUSY Position */ 567 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC_T::ISPSTS: ISPBUSY Mask */ 568 569 #define FMC_ISPSTS_CBS_Pos (2) /*!< FMC_T::ISPSTS: CBS Position */ 570 #define FMC_ISPSTS_CBS_Msk (0x1ul << FMC_ISPSTS_CBS_Pos) /*!< FMC_T::ISPSTS: CBS Mask */ 571 572 #define FMC_ISPSTS_MBS_Pos (3) /*!< FMC_T::ISPSTS: MBS Position */ 573 #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) /*!< FMC_T::ISPSTS: MBS Mask */ 574 575 #define FMC_ISPSTS_FCYCDIS_Pos (4) /*!< FMC_T::ISPSTS: FCYCDIS Position */ 576 #define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) /*!< FMC_T::ISPSTS: FCYCDIS Mask */ 577 578 #define FMC_ISPSTS_PGFF_Pos (5) /*!< FMC_T::ISPSTS: PGFF Position */ 579 #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) /*!< FMC_T::ISPSTS: PGFF Mask */ 580 581 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC_T::ISPSTS: ISPFF Position */ 582 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC_T::ISPSTS: ISPFF Mask */ 583 584 #define FMC_ISPSTS_ALLONE_Pos (7) /*!< FMC_T::ISPSTS: ALLONE Position */ 585 #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) /*!< FMC_T::ISPSTS: ALLONE Mask */ 586 587 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC_T::ISPSTS: VECMAP Position */ 588 #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC_T::ISPSTS: VECMAP Mask */ 589 590 #define FMC_ISPSTS_INTFLAG_Pos (24) /*!< FMC_T::ISPSTS: INTFLAG Position */ 591 #define FMC_ISPSTS_INTFLAG_Msk (0x1ul << FMC_ISPSTS_INTFLAG_Pos) /*!< FMC_T::ISPSTS: INTFLAG Mask */ 592 593 #define FMC_CYCCTL_CYCLE_Pos (0) /*!< FMC_T::CYCCTL: CYCLE Position */ 594 #define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) /*!< FMC_T::CYCCTL: CYCLE Mask */ 595 596 #define FMC_CYCCTL_FADIS_Pos (8) /*!< FMC_T::CYCCTL: FADIS Position */ 597 #define FMC_CYCCTL_FADIS_Msk (0x1ul << FMC_CYCCTL_FADIS_Pos) /*!< FMC_T::CYCCTL: FADIS Mask */ 598 599 #define FMC_KPKEY0_KPKEY0_Pos (0) /*!< FMC_T::KPKEY0: KPKEY0 Position */ 600 #define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) /*!< FMC_T::KPKEY0: KPKEY0 Mask */ 601 602 #define FMC_KPKEY1_KPKEY1_Pos (0) /*!< FMC_T::KPKEY1: KPKEY1 Position */ 603 #define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) /*!< FMC_T::KPKEY1: KPKEY1 Mask */ 604 605 #define FMC_KPKEY2_KPKEY2_Pos (0) /*!< FMC_T::KPKEY2: KPKEY2 Position */ 606 #define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) /*!< FMC_T::KPKEY2: KPKEY2 Mask */ 607 608 #define FMC_KPKEYTRG_KPKEYGO_Pos (0) /*!< FMC_T::KPKEYTRG: KPKEYGO Position */ 609 #define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) /*!< FMC_T::KPKEYTRG: KPKEYGO Mask */ 610 611 #define FMC_KPKEYTRG_TCEN_Pos (1) /*!< FMC_T::KPKEYTRG: TCEN Position */ 612 #define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) /*!< FMC_T::KPKEYTRG: TCEN Mask */ 613 614 #define FMC_KPKEYSTS_KEYBUSY_Pos (0) /*!< FMC_T::KPKEYSTS: KEYBUSY Position */ 615 #define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) /*!< FMC_T::KPKEYSTS: KEYBUSY Mask */ 616 617 #define FMC_KPKEYSTS_KEYLOCK_Pos (1) /*!< FMC_T::KPKEYSTS: KEYLOCK Position */ 618 #define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) /*!< FMC_T::KPKEYSTS: KEYLOCK Mask */ 619 620 #define FMC_KPKEYSTS_KEYMATCH_Pos (2) /*!< FMC_T::KPKEYSTS: KEYMATCH Position */ 621 #define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) /*!< FMC_T::KPKEYSTS: KEYMATCH Mask */ 622 623 #define FMC_KPKEYSTS_FORBID_Pos (3) /*!< FMC_T::KPKEYSTS: FORBID Position */ 624 #define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) /*!< FMC_T::KPKEYSTS: FORBID Mask */ 625 626 #define FMC_KPKEYSTS_KEYFLAG_Pos (4) /*!< FMC_T::KPKEYSTS: KEYFLAG Position */ 627 #define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) /*!< FMC_T::KPKEYSTS: KEYFLAG Mask */ 628 629 #define FMC_KPKEYSTS_CFGFLAG_Pos (5) /*!< FMC_T::KPKEYSTS: CFGFLAG Position */ 630 #define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) /*!< FMC_T::KPKEYSTS: CFGFLAG Mask */ 631 632 #define FMC_KPKEYSTS_SBKPBUSY_Pos (8) /*!< FMC_T::KPKEYSTS: SBKPBUSY Position */ 633 #define FMC_KPKEYSTS_SBKPBUSY_Msk (0x1ul << FMC_KPKEYSTS_SBKPBUSY_Pos) /*!< FMC_T::KPKEYSTS: SBKPBUSY Mask */ 634 635 #define FMC_KPKEYSTS_SBKPFLAG_Pos (9) /*!< FMC_T::KPKEYSTS: SBKPFLAG Position */ 636 #define FMC_KPKEYSTS_SBKPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SBKPFLAG_Pos) /*!< FMC_T::KPKEYSTS: SBKPFLAG Mask */ 637 638 #define FMC_KPKEYCNT_KPKECNT_Pos (0) /*!< FMC_T::KPKEYCNT: KPKECNT Position */ 639 #define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) /*!< FMC_T::KPKEYCNT: KPKECNT Mask */ 640 641 #define FMC_KPKEYCNT_KPKEMAX_Pos (8) /*!< FMC_T::KPKEYCNT: KPKEMAX Position */ 642 #define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) /*!< FMC_T::KPKEYCNT: KPKEMAX Mask */ 643 644 #define FMC_KPCNT_KPCNT_Pos (0) /*!< FMC_T::KPCNT: KPCNT Position */ 645 #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) /*!< FMC_T::KPCNT: KPCNT Mask */ 646 647 #define FMC_KPCNT_KPMAX_Pos (8) /*!< FMC_T::KPCNT: KPMAX Position */ 648 #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /*!< FMC_T::KPCNT: KPMAX Mask */ 649 650 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC_T::MPDAT0: ISPDAT0 Position */ 651 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC_T::MPDAT0: ISPDAT0 Mask */ 652 653 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC_T::MPDAT1: ISPDAT1 Position */ 654 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC_T::MPDAT1: ISPDAT1 Mask */ 655 656 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC_T::MPDAT2: ISPDAT2 Position */ 657 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC_T::MPDAT2: ISPDAT2 Mask */ 658 659 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC_T::MPDAT3: ISPDAT3 Position */ 660 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC_T::MPDAT3: ISPDAT3 Mask */ 661 662 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC_T::MPSTS: MPBUSY Position */ 663 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC_T::MPSTS: MPBUSY Mask */ 664 665 #define FMC_MPSTS_PPGO_Pos (1) /*!< FMC_T::MPSTS: PPGO Position */ 666 #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) /*!< FMC_T::MPSTS: PPGO Mask */ 667 668 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC_T::MPSTS: ISPFF Position */ 669 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC_T::MPSTS: ISPFF Mask */ 670 671 #define FMC_MPSTS_D0_Pos (4) /*!< FMC_T::MPSTS: D0 Position */ 672 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC_T::MPSTS: D0 Mask */ 673 674 #define FMC_MPSTS_D1_Pos (5) /*!< FMC_T::MPSTS: D1 Position */ 675 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC_T::MPSTS: D1 Mask */ 676 677 #define FMC_MPSTS_D2_Pos (6) /*!< FMC_T::MPSTS: D2 Position */ 678 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC_T::MPSTS: D2 Mask */ 679 680 #define FMC_MPSTS_D3_Pos (7) /*!< FMC_T::MPSTS: D3 Position */ 681 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC_T::MPSTS: D3 Mask */ 682 683 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC_T::MPADDR: MPADDR Position */ 684 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC_T::MPADDR: MPADDR Mask */ 685 686 #define FMC_XOMR0STS_SIZE_Pos (0) /*!< FMC_T::XOMR0STS: SIZE Position */ 687 #define FMC_XOMR0STS_SIZE_Msk (0xfful << FMC_XOMR0STS_SIZE_Pos) /*!< FMC_T::XOMR0STS: SIZE Mask */ 688 689 #define FMC_XOMR0STS_BASE_Pos (8) /*!< FMC_T::XOMR0STS: BASE Position */ 690 #define FMC_XOMR0STS_BASE_Msk (0xfffffful << FMC_XOMR0STS_BASE_Pos) /*!< FMC_T::XOMR0STS: BASE Mask */ 691 692 #define FMC_XOMR1STS_SIZE_Pos (0) /*!< FMC_T::XOMR1STS: SIZE Position */ 693 #define FMC_XOMR1STS_SIZE_Msk (0xfful << FMC_XOMR1STS_SIZE_Pos) /*!< FMC_T::XOMR1STS: SIZE Mask */ 694 695 #define FMC_XOMR1STS_BASE_Pos (8) /*!< FMC_T::XOMR1STS: BASE Position */ 696 #define FMC_XOMR1STS_BASE_Msk (0xfffffful << FMC_XOMR1STS_BASE_Pos) /*!< FMC_T::XOMR1STS: BASE Mask */ 697 698 #define FMC_XOMR2STS_SIZE_Pos (0) /*!< FMC_T::XOMR2STS: SIZE Position */ 699 #define FMC_XOMR2STS_SIZE_Msk (0xfful << FMC_XOMR2STS_SIZE_Pos) /*!< FMC_T::XOMR2STS: SIZE Mask */ 700 701 #define FMC_XOMR2STS_BASE_Pos (8) /*!< FMC_T::XOMR2STS: BASE Position */ 702 #define FMC_XOMR2STS_BASE_Msk (0xfffffful << FMC_XOMR2STS_BASE_Pos) /*!< FMC_T::XOMR2STS: BASE Mask */ 703 704 #define FMC_XOMR3STS_SIZE_Pos (0) /*!< FMC_T::XOMR3STS: SIZE Position */ 705 #define FMC_XOMR3STS_SIZE_Msk (0xfful << FMC_XOMR3STS_SIZE_Pos) /*!< FMC_T::XOMR3STS: SIZE Mask */ 706 707 #define FMC_XOMR3STS_BASE_Pos (8) /*!< FMC_T::XOMR3STS: BASE Position */ 708 #define FMC_XOMR3STS_BASE_Msk (0xfffffful << FMC_XOMR3STS_BASE_Pos) /*!< FMC_T::XOMR3STS: BASE Mask */ 709 710 #define FMC_XOMSTS_XOMR0ON_Pos (0) /*!< FMC_T::XOMSTS: XOMR0ON Position */ 711 #define FMC_XOMSTS_XOMR0ON_Msk (0x1ul << FMC_XOMSTS_XOMR0ON_Pos) /*!< FMC_T::XOMSTS: XOMR0ON Mask */ 712 713 #define FMC_XOMSTS_XOMR1ON_Pos (1) /*!< FMC_T::XOMSTS: XOMR1ON Position */ 714 #define FMC_XOMSTS_XOMR1ON_Msk (0x1ul << FMC_XOMSTS_XOMR1ON_Pos) /*!< FMC_T::XOMSTS: XOMR1ON Mask */ 715 716 #define FMC_XOMSTS_XOMR2ON_Pos (2) /*!< FMC_T::XOMSTS: XOMR2ON Position */ 717 #define FMC_XOMSTS_XOMR2ON_Msk (0x1ul << FMC_XOMSTS_XOMR2ON_Pos) /*!< FMC_T::XOMSTS: XOMR2ON Mask */ 718 719 #define FMC_XOMSTS_XOMR3ON_Pos (3) /*!< FMC_T::XOMSTS: XOMR3ON Position */ 720 #define FMC_XOMSTS_XOMR3ON_Msk (0x1ul << FMC_XOMSTS_XOMR3ON_Pos) /*!< FMC_T::XOMSTS: XOMR3ON Mask */ 721 722 #define FMC_XOMSTS_XOMPEF_Pos (4) /*!< FMC_T::XOMSTS: XOMPEF Position */ 723 #define FMC_XOMSTS_XOMPEF_Msk (0x1ul << FMC_XOMSTS_XOMPEF_Pos) /*!< FMC_T::XOMSTS: XOMPEF Mask */ 724 725 /**@}*/ /* FMC_CONST */ 726 /**@}*/ /* end of FMC register group */ 727 /**@}*/ /* end of REGISTER group */ 728 729 #endif /* __FMC_REG_H__ */ 730
