1 /**************************************************************************//** 2 * @file crpt_reg.h 3 * @version V1.00 4 * @brief CRPT register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CRPT_REG_H__ 10 #define __CRPT_REG_H__ 11 12 13 /** @addtogroup REGISTER Control Register 14 15 @{ 16 17 */ 18 19 20 /*---------------------- Cryptographic Accelerator -------------------------*/ 21 /** 22 @addtogroup CRPT Cryptographic Accelerator(CRPT) 23 Memory Mapped Structure for CRPT Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var CRPT_T::INTEN 32 * Offset: 0x00 Crypto Interrupt Enable Control Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[0] |AESIEN |AES Interrupt Enable Control 37 * | | |0 = AES interrupt Disabled. 38 * | | |1 = AES interrupt Enabled. 39 * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine. 40 * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation. 41 * |[1] |AESEIEN |AES Error Flag Enable Control 42 * | | |0 = AES error interrupt flag Disabled. 43 * | | |1 = AES error interrupt flag Enabled. 44 * |[8] |TDESIEN |TDES/DES Interrupt Enable Control 45 * | | |0 = TDES/DES interrupt Disabled. 46 * | | |1 = TDES/DES interrupt Enabled. 47 * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine. 48 * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation. 49 * |[9] |TDESEIEN |TDES/DES Error Flag Enable Control 50 * | | |0 = TDES/DES error interrupt flag Disabled. 51 * | | |1 = TDES/DES error interrupt flag Enabled. 52 * |[16] |PRNGIEN |PRNG Interrupt Enable Control 53 * | | |0 = PRNG interrupt Disabled. 54 * | | |1 = PRNG interrupt Enabled. 55 * |[22] |ECCIEN |ECC Interrupt Enable Control 56 * | | |0 = ECC interrupt Disabled. 57 * | | |1 = ECC interrupt Enabled. 58 * | | |In DMA mode, an interrupt will be triggered when amount of data set in ECC_DMA_CNT is fed into the ECC engine. 59 * | | |In Non-DMA mode, an interrupt will be triggered when the ECC engine finishes the operation. 60 * |[23] |ECCEIEN |ECC Error Interrupt Enable Control 61 * | | |0 = ECC error interrupt flag Disabled. 62 * | | |1 = ECC error interrupt flag Enabled. 63 * |[24] |HMACIEN |SHA/HMAC Interrupt Enable Control 64 * | | |0 = SHA/HMAC interrupt Disabled. 65 * | | |1 = SHA/HMAC interrupt Enabled. 66 * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA/HMAC engine 67 * | | |In Non-DMA mode, an interrupt will be triggered when the SHA/HMAC engine finishes the operation. 68 * |[25] |HMACEIEN |SHA/HMAC Error Interrupt Enable Control 69 * | | |0 = SHA/HMAC error interrupt flag Disabled. 70 * | | |1 = SHA/HMAC error interrupt flag Enabled. 71 * @var CRPT_T::INTSTS 72 * Offset: 0x04 Crypto Interrupt Flag 73 * --------------------------------------------------------------------------------------------------- 74 * |Bits |Field |Descriptions 75 * | :----: | :----: | :---- | 76 * |[0] |AESIF |AES Finish Interrupt Flag 77 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 78 * | | |0 = No AES interrupt. 79 * | | |1 = AES encryption/decryption done interrupt. 80 * |[1] |AESEIF |AES Error Flag 81 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 82 * | | |0 = No AES error. 83 * | | |1 = AES encryption/decryption done interrupt. 84 * |[8] |TDESIF |TDES/DES Finish Interrupt Flag 85 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 86 * | | |0 = No TDES/DES interrupt. 87 * | | |1 = TDES/DES encryption/decryption done interrupt. 88 * |[9] |TDESEIF |TDES/DES Error Flag 89 * | | |This bit includes the operating and setting error 90 * | | |The detailed flag is shown in the TDES _FLAG register 91 * | | |This includes operating and setting error. 92 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 93 * | | |0 = No TDES/DES error. 94 * | | |1 = TDES/DES encryption/decryption error interrupt. 95 * |[16] |PRNGIF |PRNG Finish Interrupt Flag 96 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 97 * | | |0 = No PRNG interrupt. 98 * | | |1 = PRNG key generation done interrupt. 99 * |[22] |ECCIF |ECC Finish Interrupt Flag 100 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 101 * | | |0 = No ECC interrupt. 102 * | | |1 = ECC operation done interrupt. 103 * |[23] |ECCEIF |ECC Error Flag 104 * | | |This register includes operating and setting error. The detail flag is shown in ECC _FLAG register. 105 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 106 * | | |0 = No ECC error. 107 * | | |1 = ECC error interrupt. 108 * |[24] |HMACIF |SHA/HMAC Finish Interrupt Flag 109 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 110 * | | |0 = No SHA/HMAC interrupt. 111 * | | |1 = SHA/HMAC operation done interrupt. 112 * |[25] |HMACEIF |SHA/HMAC Error Flag 113 * | | |This register includes operating and setting error. The detail flag is shown in SHA _FLAG register. 114 * | | |This bit is cleared by writing 1, and it has no effect by writing 0. 115 * | | |0 = No SHA/HMAC error. 116 * | | |1 = SHA/HMAC error interrupt. 117 * @var CRPT_T::PRNG_CTL 118 * Offset: 0x08 PRNG Control Register 119 * --------------------------------------------------------------------------------------------------- 120 * |Bits |Field |Descriptions 121 * | :----: | :----: | :---- | 122 * |[0] |START |Start PRNG Engine 123 * | | |0 = Stop PRNG engine. 124 * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated. 125 * |[1] |SEEDRLD |Reload New Seed for PRNG Engine 126 * | | |0 = Generating key based on the current seed. 127 * | | |1 = Reload new seed. 128 * |[3:2] |KEYSZ |PRNG Generate Key Size 129 * | | |00 = 64 bits. 130 * | | |01 = 128 bits. 131 * | | |10 = 192 bits. 132 * | | |11 = 256 bits. 133 * |[8] |BUSY |PRNG Busy (Read Only) 134 * | | |0 = PRNG engine is idle. 135 * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx. 136 * @var CRPT_T::PRNG_SEED 137 * Offset: 0x0C Seed for PRNG 138 * --------------------------------------------------------------------------------------------------- 139 * |Bits |Field |Descriptions 140 * | :----: | :----: | :---- | 141 * |[31:0] |SEED |Seed for PRNG (Write Only) 142 * | | |The bits store the seed for PRNG engine. 143 * @var CRPT_T::PRNG_KEY[8] 144 * Offset: 0x10 PRNG Generated Key0~Key7 145 * --------------------------------------------------------------------------------------------------- 146 * |Bits |Field |Descriptions 147 * | :----: | :----: | :---- | 148 * |[31:0] |KEY |Store PRNG Generated Key (Read Only) 149 * | | |The bits store the key that is generated by PRNG. 150 * @var CRPT_T::AES_FDBCK[4] 151 * Offset: 0x50 AES Engine Output Feedback Data after Cryptographic Operation 152 * --------------------------------------------------------------------------------------------------- 153 * |Bits |Field |Descriptions 154 * | :----: | :----: | :---- | 155 * |[31:0] |FDBCK |AES Feedback Information 156 * | | |The feedback value is 128 bits in size. 157 * | | |The AES engine uses the data from CRPT_AES_FDBCKx as the data inputted to CRPT_AESn_IVx for the next block in DMA cascade mode. 158 * | | |The AES engine outputs feedback information for IV in the next block's operation 159 * | | |Software can use this feedback information to implement more than four DMA channels 160 * | | |Software can store that feedback value temporarily 161 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting. 162 * @var CRPT_T::TDES_FDBCKH 163 * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation 164 * --------------------------------------------------------------------------------------------------- 165 * |Bits |Field |Descriptions 166 * | :----: | :----: | :---- | 167 * |[31:0] |FDBCK |TDES/DES Feedback 168 * | | |The feedback value is 64 bits in size. 169 * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode 170 * | | |The feedback register is for CBC, CFB, and OFB mode. 171 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation 172 * | | |Software can use this feedback information to implement more than four DMA channels 173 * | | |Software can store that feedback value temporarily 174 * | | |After switching back, fill the stored feedback value to this register in the same channel operation 175 * | | |Then can continue the operation with the original setting. 176 * @var CRPT_T::TDES_FDBCKL 177 * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation 178 * --------------------------------------------------------------------------------------------------- 179 * |Bits |Field |Descriptions 180 * | :----: | :----: | :---- | 181 * |[31:0] |FDBCK |TDES/DES Feedback 182 * | | |The feedback value is 64 bits in size. 183 * | | |The TDES/DES engine uses the data from {CRPT_TDES_FDBCKH, CRPT_TDES_FDBCKL} as the data inputted to {CRPT_TDESn_IVH, CRPT_TDESn_IVL} for the next block in DMA cascade mode 184 * | | |The feedback register is for CBC, CFB, and OFB mode. 185 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation 186 * | | |Software can use this feedback information to implement more than four DMA channels 187 * | | |Software can store that feedback value temporarily 188 * | | |After switching back, fill the stored feedback value to this register in the same channel operation 189 * | | |Then can continue the operation with the original setting. 190 * @var CRPT_T::AES_CTL 191 * Offset: 0x100 AES Control Register 192 * --------------------------------------------------------------------------------------------------- 193 * |Bits |Field |Descriptions 194 * | :----: | :----: | :---- | 195 * |[0] |START |AES Engine Start 196 * | | |0 = No effect. 197 * | | |1 = Start AES engine. BUSY flag will be set. 198 * | | |Note: This bit is always 0 when it's read back. 199 * |[1] |STOP |AES Engine Stop 200 * | | |0 = No effect. 201 * | | |1 = Stop AES engine. 202 * | | |Note: This bit is always 0 when it's read back. 203 * |[3:2] |KEYSZ |AES Key Size 204 * | | |This bit defines three different key size for AES operation. 205 * | | |2'b00 = 128 bits key. 206 * | | |2'b01 = 192 bits key. 207 * | | |2'b10 = 256 bits key. 208 * | | |2'b11 = Reserved. 209 * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect. 210 * |[5] |DMALAST |AES Last Block 211 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. 212 * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode. 213 * | | |This bit is always 0 when it's read back. Must be written again once START is triggered. 214 * |[6] |DMACSCAD |AES Engine DMA with Cascade Mode 215 * | | |0 = DMA cascade function Disabled. 216 * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. 217 * |[7] |DMAEN |AES Engine DMA Enable Control 218 * | | |0 = AES DMA engine Disabled. 219 * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN. 220 * | | |1 = AES_DMA engine Enabled. 221 * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 222 * |[15:8] |OPMODE |AES Engine Operation Modes 223 * | | |0x00 = ECB (Electronic Codebook Mode) 0x01 = CBC (Cipher Block Chaining Mode). 224 * | | |0x02 = CFB (Cipher Feedback Mode). 225 * | | |0x03 = OFB (Output Feedback Mode). 226 * | | |0x04 = CTR (Counter Mode). 227 * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode). 228 * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode). 229 * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode). 230 * |[16] |ENCRPT |AES Encryption/Decryption 231 * | | |0 = AES engine executes decryption operation. 232 * | | |1 = AES engine executes encryption operation. 233 * |[22] |OUTSWAP |AES Engine Output Data Swap 234 * | | |0 = Keep the original order. 235 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 236 * |[23] |INSWAP |AES Engine Input Data Swap 237 * | | |0 = Keep the original order. 238 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 239 * |[25:24] |CHANNEL |AES Engine Working Channel 240 * | | |00 = Current control register setting is for channel 0. 241 * | | |01 = Current control register setting is for channel 1. 242 * | | |10 = Current control register setting is for channel 2. 243 * | | |11 = Current control register setting is for channel 3. 244 * |[30:26] |KEYUNPRT |Unprotect Key 245 * | | |Writing 0 to CRPT_AES_CTL[31] and ...10110 to CRPT_AES_CTL[30:26] is to unprotect the AES key. 246 * | | |The KEYUNPRT can be read and written 247 * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 248 * |[31] |KEYPRT |Protect Key 249 * | | |Read as a flag to reflect KEYPRT. 250 * | | |0 = No effect. 251 * | | |1 = Protect the content of the AES key from reading 252 * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx 253 * | | |Once it is set, it can be cleared by asserting KEYUNPRT 254 * | | |And the key content would be cleared as well. 255 * @var CRPT_T::AES_STS 256 * Offset: 0x104 AES Engine Flag 257 * --------------------------------------------------------------------------------------------------- 258 * |Bits |Field |Descriptions 259 * | :----: | :----: | :---- | 260 * |[0] |BUSY |AES Engine Busy 261 * | | |0 = The AES engine is idle or finished. 262 * | | |1 = The AES engine is under processing. 263 * |[8] |INBUFEMPTY|AES Input Buffer Empty 264 * | | |0 = There are some data in input buffer waiting for the AES engine to process. 265 * | | |1 = AES input buffer is empty 266 * | | |Software needs to feed data to the AES engine 267 * | | |Otherwise, the AES engine will be pending to wait for input data. 268 * |[9] |INBUFFULL |AES Input Buffer Full Flag 269 * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine. 270 * | | |1 = AES input buffer is full 271 * | | |Software cannot feed data to the AES engine 272 * | | |Otherwise, the flag INBUFERR will be set to 1. 273 * |[10] |INBUFERR |AES Input Buffer Error Flag 274 * | | |0 = No error. 275 * | | |1 = Error happens during feeding data to the AES engine. 276 * |[12] |CNTERR |CRPT_AESn_CNT Setting Error 277 * | | |0 = No error in CRPT_AESn_CNT setting. 278 * | | |1 = CRPT_AESn_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode. 279 * |[16] |OUTBUFEMPTY|AES Out Buffer Empty 280 * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer. 281 * | | |1 = AES output buffer is empty 282 * | | |Software cannot get data from CRPT_AES_DATOUT 283 * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty. 284 * |[17] |OUTBUFFULL|AES Out Buffer Full Flag 285 * | | |0 = AES output buffer is not full. 286 * | | |1 = AES output buffer is full, and software needs to get data from CRPT_AES_DATOUT 287 * | | |Otherwise, the AES engine will be pending since the output buffer is full. 288 * |[18] |OUTBUFERR |AES Out Buffer Error Flag 289 * | | |0 = No error. 290 * | | |1 = Error happens during getting the result from AES engine. 291 * |[20] |BUSERR |AES DMA Access Bus Error Flag 292 * | | |0 = No error. 293 * | | |1 = Bus error will stop DMA operation and AES engine. 294 * @var CRPT_T::AES_DATIN 295 * Offset: 0x108 AES Engine Data Input Port Register 296 * --------------------------------------------------------------------------------------------------- 297 * |Bits |Field |Descriptions 298 * | :----: | :----: | :---- | 299 * |[31:0] |DATIN |AES Engine Input Port 300 * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0. 301 * @var CRPT_T::AES_DATOUT 302 * Offset: 0x10C AES Engine Data Output Port Register 303 * --------------------------------------------------------------------------------------------------- 304 * |Bits |Field |Descriptions 305 * | :----: | :----: | :---- | 306 * |[31:0] |DATOUT |AES Engine Output Port 307 * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS 308 * | | |Get data as OUTBUFEMPTY is 0. 309 * @var CRPT_T::AES0_KEY[8] 310 * Offset: 0x110~0x12C AES Key Word 0~7 Register for Channel 0 311 * --------------------------------------------------------------------------------------------------- 312 * |Bits |Field |Descriptions 313 * | :----: | :----: | :---- | 314 * |[31:0] |KEY |CRPT_AESn_KEYx 315 * | | |The KEY keeps the security key for AES operation. 316 * | | |n = 0, 1..3. 317 * | | |x = 0, 1..7. 318 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 319 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 320 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 321 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 322 * @var CRPT_T::AES0_IV[4] 323 * Offset: 0x130~0x13C AES Initial Vector Word 0~3 Register for Channel 0 324 * --------------------------------------------------------------------------------------------------- 325 * |Bits |Field |Descriptions 326 * | :----: | :----: | :---- | 327 * |[31:0] |IV |AES Initial Vectors 328 * | | |n = 0, 1..3. 329 * | | |x = 0, 1..3. 330 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 331 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 332 * @var CRPT_T::AES0_SADDR 333 * Offset: 0x140 AES DMA Source Address Register for Channel 0 334 * --------------------------------------------------------------------------------------------------- 335 * |Bits |Field |Descriptions 336 * | :----: | :----: | :---- | 337 * |[31:0] |SADDR |AES DMA Source Address 338 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 339 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 340 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 341 * | | |The start of source address should be located at word boundary 342 * | | |In other words, bit 1 and 0 of SADDR are ignored. 343 * | | |SADDR can be read and written 344 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 345 * | | |But the value of SADDR will be updated later on 346 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 347 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 348 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 349 * @var CRPT_T::AES0_DADDR 350 * Offset: 0x144 AES DMA Destination Address Register for Channel 0 351 * --------------------------------------------------------------------------------------------------- 352 * |Bits |Field |Descriptions 353 * | :----: | :----: | :---- | 354 * |[31:0] |DADDR |AES DMA Destination Address 355 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 356 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 357 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 358 * | | |The start of destination address should be located at word boundary 359 * | | |In other words, bit 1 and 0 of DADDR are ignored. 360 * | | |DADDR can be read and written 361 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 362 * | | |But the value of DADDR will be updated later on 363 * | | |Consequently, software can prepare the destination address for the next AES operation. 364 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 365 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 366 * @var CRPT_T::AES0_CNT 367 * Offset: 0x148 AES Byte Count Register for Channel 0 368 * --------------------------------------------------------------------------------------------------- 369 * |Bits |Field |Descriptions 370 * | :----: | :----: | :---- | 371 * |[31:0] |CNT |AES Byte Count 372 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 373 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 374 * | | |CRPT_AESn_CNT can be read and written 375 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 376 * | | |But the value of CRPT_AESn_CNT will be updated later on 377 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 378 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 379 * | | |Operations that are less than one block will output unexpected result. 380 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 381 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 382 * @var CRPT_T::AES1_KEY[8] 383 * Offset: 0x14C~0x168 AES Key Word 0~7 Register for Channel 1 384 * --------------------------------------------------------------------------------------------------- 385 * |Bits |Field |Descriptions 386 * | :----: | :----: | :---- | 387 * |[31:0] |KEY |CRPT_AESn_KEYx 388 * | | |The KEY keeps the security key for AES operation. 389 * | | |n = 0, 1..3. 390 * | | |x = 0, 1..7. 391 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 392 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 393 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 394 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 395 * @var CRPT_T::AES1_IV[4] 396 * Offset: 0x16C~0x178 AES Initial Vector Word 0~3 Register for Channel 1 397 * --------------------------------------------------------------------------------------------------- 398 * |Bits |Field |Descriptions 399 * | :----: | :----: | :---- | 400 * |[31:0] |IV |AES Initial Vectors 401 * | | |n = 0, 1..3. 402 * | | |x = 0, 1..3. 403 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 404 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 405 * @var CRPT_T::AES1_SADDR 406 * Offset: 0x17C AES DMA Source Address Register for Channel 1 407 * --------------------------------------------------------------------------------------------------- 408 * |Bits |Field |Descriptions 409 * | :----: | :----: | :---- | 410 * |[31:0] |SADDR |AES DMA Source Address 411 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 412 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 413 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 414 * | | |The start of source address should be located at word boundary 415 * | | |In other words, bit 1 and 0 of SADDR are ignored. 416 * | | |SADDR can be read and written 417 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 418 * | | |But the value of SADDR will be updated later on 419 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 420 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 421 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 422 * @var CRPT_T::AES1_DADDR 423 * Offset: 0x180 AES DMA Destination Address Register for Channel 1 424 * --------------------------------------------------------------------------------------------------- 425 * |Bits |Field |Descriptions 426 * | :----: | :----: | :---- | 427 * |[31:0] |DADDR |AES DMA Destination Address 428 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 429 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 430 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 431 * | | |The start of destination address should be located at word boundary 432 * | | |In other words, bit 1 and 0 of DADDR are ignored. 433 * | | |DADDR can be read and written 434 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 435 * | | |But the value of DADDR will be updated later on 436 * | | |Consequently, software can prepare the destination address for the next AES operation. 437 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 438 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 439 * @var CRPT_T::AES1_CNT 440 * Offset: 0x184 AES Byte Count Register for Channel 1 441 * --------------------------------------------------------------------------------------------------- 442 * |Bits |Field |Descriptions 443 * | :----: | :----: | :---- | 444 * |[31:0] |CNT |AES Byte Count 445 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 446 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 447 * | | |CRPT_AESn_CNT can be read and written 448 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 449 * | | |But the value of CRPT_AESn_CNT will be updated later on 450 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 451 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 452 * | | |Operations that are less than one block will output unexpected result. 453 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 454 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 455 * @var CRPT_T::AES2_KEY[8] 456 * Offset: 0x188~0x1A4 AES Key Word 0~7 Register for Channel 2 457 * --------------------------------------------------------------------------------------------------- 458 * |Bits |Field |Descriptions 459 * | :----: | :----: | :---- | 460 * |[31:0] |KEY |CRPT_AESn_KEYx 461 * | | |The KEY keeps the security key for AES operation. 462 * | | |n = 0, 1..3. 463 * | | |x = 0, 1..7. 464 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 465 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 466 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 467 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 468 * @var CRPT_T::AES2_IV[4] 469 * Offset: 0x1A8~0x1B4 AES Initial Vector Word 0~3 Register for Channel 2 470 * --------------------------------------------------------------------------------------------------- 471 * |Bits |Field |Descriptions 472 * | :----: | :----: | :---- | 473 * |[31:0] |IV |AES Initial Vectors 474 * | | |n = 0, 1..3. 475 * | | |x = 0, 1..3. 476 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 477 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 478 * @var CRPT_T::AES2_SADDR 479 * Offset: 0x1B8 AES DMA Source Address Register for Channel 2 480 * --------------------------------------------------------------------------------------------------- 481 * |Bits |Field |Descriptions 482 * | :----: | :----: | :---- | 483 * |[31:0] |SADDR |AES DMA Source Address 484 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 485 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 486 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 487 * | | |The start of source address should be located at word boundary 488 * | | |In other words, bit 1 and 0 of SADDR are ignored. 489 * | | |SADDR can be read and written 490 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 491 * | | |But the value of SADDR will be updated later on 492 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 493 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 494 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 495 * @var CRPT_T::AES2_DADDR 496 * Offset: 0x1BC AES DMA Destination Address Register for Channel 2 497 * --------------------------------------------------------------------------------------------------- 498 * |Bits |Field |Descriptions 499 * | :----: | :----: | :---- | 500 * |[31:0] |DADDR |AES DMA Destination Address 501 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 502 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 503 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 504 * | | |The start of destination address should be located at word boundary 505 * | | |In other words, bit 1 and 0 of DADDR are ignored. 506 * | | |DADDR can be read and written 507 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 508 * | | |But the value of DADDR will be updated later on 509 * | | |Consequently, software can prepare the destination address for the next AES operation. 510 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 511 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 512 * @var CRPT_T::AES2_CNT 513 * Offset: 0x1C0 AES Byte Count Register for Channel 2 514 * --------------------------------------------------------------------------------------------------- 515 * |Bits |Field |Descriptions 516 * | :----: | :----: | :---- | 517 * |[31:0] |CNT |AES Byte Count 518 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 519 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 520 * | | |CRPT_AESn_CNT can be read and written 521 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 522 * | | |But the value of CRPT_AESn_CNT will be updated later on 523 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 524 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 525 * | | |Operations that are less than one block will output unexpected result. 526 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 527 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 528 * @var CRPT_T::AES3_KEY[8] 529 * Offset: 0x1C4~0x1E0 AES Key Word 0~7 Register for Channel 3 530 * --------------------------------------------------------------------------------------------------- 531 * |Bits |Field |Descriptions 532 * | :----: | :----: | :---- | 533 * |[31:0] |KEY |CRPT_AESn_KEYx 534 * | | |The KEY keeps the security key for AES operation. 535 * | | |n = 0, 1..3. 536 * | | |x = 0, 1..7. 537 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key 538 * | | |{CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 128-bit security key for AES operation 539 * | | |{CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 192-bit security key for AES operation 540 * | | |{CRPT_AESn_KEY7, CRPT_AESn_KEY6, CRPT_AESn_KEY5, CRPT_AESn_KEY4, CRPT_AESn_KEY3, CRPT_AESn_KEY2, CRPT_AESn_KEY1, CRPT_AESn_KEY0} stores the 256-bit security key for AES operation. 541 * @var CRPT_T::AES3_IV[4] 542 * Offset: 0x1E4~0x1F0 AES Initial Vector Word 0~3 Register for Channel 3 543 * --------------------------------------------------------------------------------------------------- 544 * |Bits |Field |Descriptions 545 * | :----: | :----: | :---- | 546 * |[31:0] |IV |AES Initial Vectors 547 * | | |n = 0, 1..3. 548 * | | |x = 0, 1..3. 549 * | | |Four initial vectors (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) are for AES operating in CBC, CFB, and OFB mode 550 * | | |Four registers (CRPT_AESn_IV0, CRPT_AESn_IV1, CRPT_AESn_IV2, and CRPT_AESn_IV3) act as Nonce counter when the AES engine is operating in CTR mode. 551 * @var CRPT_T::AES3_SADDR 552 * Offset: 0x1F4 AES DMA Source Address Register for Channel 3 553 * --------------------------------------------------------------------------------------------------- 554 * |Bits |Field |Descriptions 555 * | :----: | :----: | :---- | 556 * |[31:0] |SADDR |AES DMA Source Address 557 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 558 * | | |The SADDR keeps the source address of the data buffer where the source text is stored 559 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation 560 * | | |The start of source address should be located at word boundary 561 * | | |In other words, bit 1 and 0 of SADDR are ignored. 562 * | | |SADDR can be read and written 563 * | | |Writing to SADDR while the AES accelerator is operating doesn't affect the current AES operation 564 * | | |But the value of SADDR will be updated later on 565 * | | |Consequently, software can prepare the DMA source address for the next AES operation. 566 * | | |In DMA mode, software can update the next CRPT_AESn_SADDR before triggering START. 567 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 568 * @var CRPT_T::AES3_DADDR 569 * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3 570 * --------------------------------------------------------------------------------------------------- 571 * |Bits |Field |Descriptions 572 * | :----: | :----: | :---- | 573 * |[31:0] |DADDR |AES DMA Destination Address 574 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 575 * | | |The DADDR keeps the destination address of the data buffer where the engine output's text will be stored 576 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished 577 * | | |The start of destination address should be located at word boundary 578 * | | |In other words, bit 1 and 0 of DADDR are ignored. 579 * | | |DADDR can be read and written 580 * | | |Writing to DADDR while the AES accelerator is operating doesn't affect the current AES operation 581 * | | |But the value of DADDR will be updated later on 582 * | | |Consequently, software can prepare the destination address for the next AES operation. 583 * | | |In DMA mode, software can update the next CRPT_AESn_DADDR before triggering START. 584 * | | |The value of CRPT_AESn_SADDR and CRPT_AESn_DADDR can be the same. 585 * @var CRPT_T::AES3_CNT 586 * Offset: 0x1FC AES Byte Count Register for Channel 3 587 * --------------------------------------------------------------------------------------------------- 588 * |Bits |Field |Descriptions 589 * | :----: | :----: | :---- | 590 * |[31:0] |CNT |AES Byte Count 591 * | | |The CRPT_AESn_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode 592 * | | |The CRPT_AESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 593 * | | |CRPT_AESn_CNT can be read and written 594 * | | |Writing to CRPT_AESn_CNT while the AES accelerator is operating doesn't affect the current AES operation 595 * | | |But the value of CRPT_AESn_CNT will be updated later on 596 * | | |Consequently, software can prepare the byte count of data for the next AES operation. 597 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block 598 * | | |Operations that are less than one block will output unexpected result. 599 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_AESn_CNT must be set as byte count for the last block of data before feeding in the last block of data 600 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, CRPT_AESn_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data. 601 * @var CRPT_T::TDES_CTL 602 * Offset: 0x200 TDES/DES Control Register 603 * --------------------------------------------------------------------------------------------------- 604 * |Bits |Field |Descriptions 605 * | :----: | :----: | :---- | 606 * |[0] |START |TDES/DES Engine Start 607 * | | |0 = No effect. 608 * | | |1 = Start TDES/DES engine. The flag BUSY would be set. 609 * | | |Note: The bit is always 0 when it's read back. 610 * |[1] |STOP |TDES/DES Engine Stop 611 * | | |0 = No effect. 612 * | | |1 = Stop TDES/DES engine. 613 * | | |Note: The bit is always 0 when it's read back. 614 * |[2] |TMODE |TDES/DES Engine Operating Mode 615 * | | |0 = Set DES mode for TDES/DES engine. 616 * | | |1 = Set Triple DES mode for TDES/DES engine. 617 * |[3] |3KEYS |TDES/DES Key Number 618 * | | |0 = Select KEY1 and KEY2 in TDES/DES engine. 619 * | | |1 = Triple keys in TDES/DES engine Enabled. 620 * |[5] |DMALAST |TDES/DES Engine Start for the Last Block 621 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round. 622 * | | |In Non-DMA mode, this bit must be set as feeding in last block of data. 623 * |[6] |DMACSCAD |TDES/DES Engine DMA with Cascade Mode 624 * | | |0 = DMA cascade function Disabled. 625 * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation. 626 * |[7] |DMAEN |TDES/DES Engine DMA Enable Control 627 * | | |0 = TDES_DMA engine Disabled. 628 * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN. 629 * | | |1 = TDES_DMA engine Enabled. 630 * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 631 * |[10:8] |OPMODE |TDES/DES Engine Operation Mode 632 * | | |0x00 = ECB (Electronic Codebook Mode). 633 * | | |0x01 = CBC (Cipher Block Chaining Mode). 634 * | | |0x02 = CFB (Cipher Feedback Mode). 635 * | | |0x03 = OFB (Output Feedback Mode). 636 * | | |0x04 = CTR (Counter Mode). 637 * | | |Others = CTR (Counter Mode). 638 * |[16] |ENCRPT |TDES/DES Encryption/Decryption 639 * | | |0 = TDES engine executes decryption operation. 640 * | | |1 = TDES engine executes encryption operation. 641 * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap 642 * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}. 643 * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}. 644 * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap 645 * | | |0 = Keep the original order. 646 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 647 * |[23] |INSWAP |TDES/DES Engine Input Data Swap 648 * | | |0 = Keep the original order. 649 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 650 * |[25:24] |CHANNEL |TDES/DES Engine Working Channel 651 * | | |00 = Current control register setting is for channel 0. 652 * | | |01 = Current control register setting is for channel 1. 653 * | | |10 = Current control register setting is for channel 2. 654 * | | |11 = Current control register setting is for channel 3. 655 * |[30:26] |KEYUNPRT |Unprotect Key 656 * | | |Writing 0 to CRPT_TDES_CTL [31] and ...10110 to CRPT_TDES_CTL [30:26] is to unprotect TDES key. 657 * | | |The KEYUNPRT can be read and written 658 * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT. 659 * |[31] |KEYPRT |Protect Key 660 * | | |Read as a flag to reflect KEYPRT. 661 * | | |0 = No effect. 662 * | | |1 = This bit is to protect the content of TDES key from reading 663 * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L 664 * | | |Once it is set, it can be cleared by asserting KEYUNPRT 665 * | | |The key content would be cleared as well. 666 * @var CRPT_T::TDES_STS 667 * Offset: 0x204 TDES/DES Engine Flag 668 * --------------------------------------------------------------------------------------------------- 669 * |Bits |Field |Descriptions 670 * | :----: | :----: | :---- | 671 * |[0] |BUSY |TDES/DES Engine Busy 672 * | | |0 = TDES/DES engine is idle or finished. 673 * | | |1 = TDES/DES engine is under processing. 674 * |[8] |INBUFEMPTY|TDES/DES in Buffer Empty 675 * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process. 676 * | | |1 = TDES/DES input buffer is empty 677 * | | |Software needs to feed data to the TDES/DES engine 678 * | | |Otherwise, the TDES/DES engine will be pending to wait for input data. 679 * |[9] |INBUFFULL |TDES/DES in Buffer Full Flag 680 * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine. 681 * | | |1 = TDES input buffer is full 682 * | | |Software cannot feed data to the TDES/DES engine 683 * | | |Otherwise, the flag INBUFERR will be set to 1. 684 * |[10] |INBUFERR |TDES/DES in Buffer Error Flag 685 * | | |0 = No error. 686 * | | |1 = Error happens during feeding data to the TDES/DES engine. 687 * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag 688 * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer. 689 * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT 690 * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty. 691 * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag 692 * | | |0 = TDES/DES output buffer is not full. 693 * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT 694 * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full. 695 * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag 696 * | | |0 = No error. 697 * | | |1 = Error happens during getting test result from TDES/DES engine. 698 * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag 699 * | | |0 = No error. 700 * | | |1 = Bus error will stop DMA operation and TDES/DES engine. 701 * @var CRPT_T::TDES0_KEY1H 702 * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0 703 * --------------------------------------------------------------------------------------------------- 704 * |Bits |Field |Descriptions 705 * | :----: | :----: | :---- | 706 * |[31:0] |KEY |TDES/DES Key High/Low Word 707 * | | |The key registers for TDES/DES algorithm calculation 708 * | | |The security key for the TDES/DES accelerator is 64 bits 709 * | | |Thus, it needs two 32-bit registers to store a security key 710 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 711 * @var CRPT_T::TDES0_KEY1L 712 * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0 713 * --------------------------------------------------------------------------------------------------- 714 * |Bits |Field |Descriptions 715 * | :----: | :----: | :---- | 716 * |[31:0] |KEY |TDES/DES Key High/Low Word 717 * | | |The key registers for TDES/DES algorithm calculation 718 * | | |The security key for the TDES/DES accelerator is 64 bits 719 * | | |Thus, it needs two 32-bit registers to store a security key 720 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 721 * @var CRPT_T::TDES0_KEY2H 722 * Offset: 0x210 TDES Key 2 High Word Register for Channel 0 723 * --------------------------------------------------------------------------------------------------- 724 * |Bits |Field |Descriptions 725 * | :----: | :----: | :---- | 726 * |[31:0] |KEY |TDES/DES Key High/Low Word 727 * | | |The key registers for TDES/DES algorithm calculation 728 * | | |The security key for the TDES/DES accelerator is 64 bits 729 * | | |Thus, it needs two 32-bit registers to store a security key 730 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 731 * @var CRPT_T::TDES0_KEY2L 732 * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0 733 * --------------------------------------------------------------------------------------------------- 734 * |Bits |Field |Descriptions 735 * | :----: | :----: | :---- | 736 * |[31:0] |KEY |TDES/DES Key High/Low Word 737 * | | |The key registers for TDES/DES algorithm calculation 738 * | | |The security key for the TDES/DES accelerator is 64 bits 739 * | | |Thus, it needs two 32-bit registers to store a security key 740 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 741 * @var CRPT_T::TDES0_KEY3H 742 * Offset: 0x218 TDES Key 3 High Word Register for Channel 0 743 * --------------------------------------------------------------------------------------------------- 744 * |Bits |Field |Descriptions 745 * | :----: | :----: | :---- | 746 * |[31:0] |KEY |TDES/DES Key High/Low Word 747 * | | |The key registers for TDES/DES algorithm calculation 748 * | | |The security key for the TDES/DES accelerator is 64 bits 749 * | | |Thus, it needs two 32-bit registers to store a security key 750 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 751 * @var CRPT_T::TDES0_KEY3L 752 * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0 753 * --------------------------------------------------------------------------------------------------- 754 * |Bits |Field |Descriptions 755 * | :----: | :----: | :---- | 756 * |[31:0] |KEY |TDES/DES Key High/Low Word 757 * | | |The key registers for TDES/DES algorithm calculation 758 * | | |The security key for the TDES/DES accelerator is 64 bits 759 * | | |Thus, it needs two 32-bit registers to store a security key 760 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 761 * @var CRPT_T::TDES0_IVH 762 * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0 763 * --------------------------------------------------------------------------------------------------- 764 * |Bits |Field |Descriptions 765 * | :----: | :----: | :---- | 766 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 767 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 768 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 769 * @var CRPT_T::TDES0_IVL 770 * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0 771 * --------------------------------------------------------------------------------------------------- 772 * |Bits |Field |Descriptions 773 * | :----: | :----: | :---- | 774 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 775 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 776 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 777 * @var CRPT_T::TDES0_SADDR 778 * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0 779 * --------------------------------------------------------------------------------------------------- 780 * |Bits |Field |Descriptions 781 * | :----: | :----: | :---- | 782 * |[31:0] |SA |TDES/DES DMA Source Address 783 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 784 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 785 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 786 * | | |The start of source address should be located at word boundary 787 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 788 * | | |CRPT_TDESn_SA can be read and written 789 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 790 * | | |But the value of CRPT_TDESn_SA will be updated later on 791 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 792 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 793 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 794 * @var CRPT_T::TDES0_DADDR 795 * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0 796 * --------------------------------------------------------------------------------------------------- 797 * |Bits |Field |Descriptions 798 * | :----: | :----: | :---- | 799 * |[31:0] |DA |TDES/DES DMA Destination Address 800 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 801 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 802 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 803 * | | |The start of destination address should be located at word boundary 804 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 805 * | | |CRPT_TDESn_DA can be read and written 806 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 807 * | | |But the value of CRPT_TDESn_DA will be updated later on 808 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 809 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 810 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 811 * @var CRPT_T::TDES0_CNT 812 * Offset: 0x230 TDES/DES Byte Count Register for Channel 0 813 * --------------------------------------------------------------------------------------------------- 814 * |Bits |Field |Descriptions 815 * | :----: | :----: | :---- | 816 * |[31:0] |CNT |TDES/DES Byte Count 817 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 818 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 819 * | | |CRPT_TDESn_CNT can be read and written 820 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 821 * | | |But the value of CRPT_TDESn_CNT will be updated later on 822 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 823 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 824 * @var CRPT_T::TDES_DATIN 825 * Offset: 0x234 TDES/DES Engine Input data Word Register 826 * --------------------------------------------------------------------------------------------------- 827 * |Bits |Field |Descriptions 828 * | :----: | :----: | :---- | 829 * |[31:0] |DATIN |TDES/DES Engine Input Port 830 * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS 831 * | | |Feed data as INBUFFULL is 0. 832 * @var CRPT_T::TDES_DATOUT 833 * Offset: 0x238 TDES/DES Engine Output data Word Register 834 * --------------------------------------------------------------------------------------------------- 835 * |Bits |Field |Descriptions 836 * | :----: | :----: | :---- | 837 * |[31:0] |DATOUT |TDES/DES Engine Output Port 838 * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS 839 * | | |Get data as OUTBUFEMPTY is 0. 840 * @var CRPT_T::TDES1_KEY1H 841 * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1 842 * --------------------------------------------------------------------------------------------------- 843 * |Bits |Field |Descriptions 844 * | :----: | :----: | :---- | 845 * |[31:0] |KEY |TDES/DES Key High/Low Word 846 * | | |The key registers for TDES/DES algorithm calculation 847 * | | |The security key for the TDES/DES accelerator is 64 bits 848 * | | |Thus, it needs two 32-bit registers to store a security key 849 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 850 * @var CRPT_T::TDES1_KEY1L 851 * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1 852 * --------------------------------------------------------------------------------------------------- 853 * |Bits |Field |Descriptions 854 * | :----: | :----: | :---- | 855 * |[31:0] |KEY |TDES/DES Key High/Low Word 856 * | | |The key registers for TDES/DES algorithm calculation 857 * | | |The security key for the TDES/DES accelerator is 64 bits 858 * | | |Thus, it needs two 32-bit registers to store a security key 859 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 860 * @var CRPT_T::TDES1_KEY2H 861 * Offset: 0x250 TDES Key 2 High Word Register for Channel 1 862 * --------------------------------------------------------------------------------------------------- 863 * |Bits |Field |Descriptions 864 * | :----: | :----: | :---- | 865 * |[31:0] |KEY |TDES/DES Key High/Low Word 866 * | | |The key registers for TDES/DES algorithm calculation 867 * | | |The security key for the TDES/DES accelerator is 64 bits 868 * | | |Thus, it needs two 32-bit registers to store a security key 869 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 870 * @var CRPT_T::TDES1_KEY2L 871 * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1 872 * --------------------------------------------------------------------------------------------------- 873 * |Bits |Field |Descriptions 874 * | :----: | :----: | :---- | 875 * |[31:0] |KEY |TDES/DES Key High/Low Word 876 * | | |The key registers for TDES/DES algorithm calculation 877 * | | |The security key for the TDES/DES accelerator is 64 bits 878 * | | |Thus, it needs two 32-bit registers to store a security key 879 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 880 * @var CRPT_T::TDES1_KEY3H 881 * Offset: 0x258 TDES Key 3 High Word Register for Channel 1 882 * --------------------------------------------------------------------------------------------------- 883 * |Bits |Field |Descriptions 884 * | :----: | :----: | :---- | 885 * |[31:0] |KEY |TDES/DES Key High/Low Word 886 * | | |The key registers for TDES/DES algorithm calculation 887 * | | |The security key for the TDES/DES accelerator is 64 bits 888 * | | |Thus, it needs two 32-bit registers to store a security key 889 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 890 * @var CRPT_T::TDES1_KEY3L 891 * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1 892 * --------------------------------------------------------------------------------------------------- 893 * |Bits |Field |Descriptions 894 * | :----: | :----: | :---- | 895 * |[31:0] |KEY |TDES/DES Key High/Low Word 896 * | | |The key registers for TDES/DES algorithm calculation 897 * | | |The security key for the TDES/DES accelerator is 64 bits 898 * | | |Thus, it needs two 32-bit registers to store a security key 899 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 900 * @var CRPT_T::TDES1_IVH 901 * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1 902 * --------------------------------------------------------------------------------------------------- 903 * |Bits |Field |Descriptions 904 * | :----: | :----: | :---- | 905 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 906 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 907 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 908 * @var CRPT_T::TDES1_IVL 909 * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1 910 * --------------------------------------------------------------------------------------------------- 911 * |Bits |Field |Descriptions 912 * | :----: | :----: | :---- | 913 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 914 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 915 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 916 * @var CRPT_T::TDES1_SADDR 917 * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1 918 * --------------------------------------------------------------------------------------------------- 919 * |Bits |Field |Descriptions 920 * | :----: | :----: | :---- | 921 * |[31:0] |SA |TDES/DES DMA Source Address 922 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 923 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 924 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 925 * | | |The start of source address should be located at word boundary 926 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 927 * | | |CRPT_TDESn_SA can be read and written 928 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 929 * | | |But the value of CRPT_TDESn_SA will be updated later on 930 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 931 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 932 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 933 * @var CRPT_T::TDES1_DADDR 934 * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1 935 * --------------------------------------------------------------------------------------------------- 936 * |Bits |Field |Descriptions 937 * | :----: | :----: | :---- | 938 * |[31:0] |DA |TDES/DES DMA Destination Address 939 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 940 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 941 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 942 * | | |The start of destination address should be located at word boundary 943 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 944 * | | |CRPT_TDESn_DA can be read and written 945 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 946 * | | |But the value of CRPT_TDESn_DA will be updated later on 947 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 948 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 949 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 950 * @var CRPT_T::TDES1_CNT 951 * Offset: 0x270 TDES/DES Byte Count Register for Channel 1 952 * --------------------------------------------------------------------------------------------------- 953 * |Bits |Field |Descriptions 954 * | :----: | :----: | :---- | 955 * |[31:0] |CNT |TDES/DES Byte Count 956 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 957 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 958 * | | |CRPT_TDESn_CNT can be read and written 959 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 960 * | | |But the value of CRPT_TDESn_CNT will be updated later on 961 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 962 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 963 * @var CRPT_T::TDES2_KEY1H 964 * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2 965 * --------------------------------------------------------------------------------------------------- 966 * |Bits |Field |Descriptions 967 * | :----: | :----: | :---- | 968 * |[31:0] |KEY |TDES/DES Key High/Low Word 969 * | | |The key registers for TDES/DES algorithm calculation 970 * | | |The security key for the TDES/DES accelerator is 64 bits 971 * | | |Thus, it needs two 32-bit registers to store a security key 972 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 973 * @var CRPT_T::TDES2_KEY1L 974 * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2 975 * --------------------------------------------------------------------------------------------------- 976 * |Bits |Field |Descriptions 977 * | :----: | :----: | :---- | 978 * |[31:0] |KEY |TDES/DES Key High/Low Word 979 * | | |The key registers for TDES/DES algorithm calculation 980 * | | |The security key for the TDES/DES accelerator is 64 bits 981 * | | |Thus, it needs two 32-bit registers to store a security key 982 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 983 * @var CRPT_T::TDES2_KEY2H 984 * Offset: 0x290 TDES Key 2 High Word Register for Channel 2 985 * --------------------------------------------------------------------------------------------------- 986 * |Bits |Field |Descriptions 987 * | :----: | :----: | :---- | 988 * |[31:0] |KEY |TDES/DES Key High/Low Word 989 * | | |The key registers for TDES/DES algorithm calculation 990 * | | |The security key for the TDES/DES accelerator is 64 bits 991 * | | |Thus, it needs two 32-bit registers to store a security key 992 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 993 * @var CRPT_T::TDES2_KEY2L 994 * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2 995 * --------------------------------------------------------------------------------------------------- 996 * |Bits |Field |Descriptions 997 * | :----: | :----: | :---- | 998 * |[31:0] |KEY |TDES/DES Key High/Low Word 999 * | | |The key registers for TDES/DES algorithm calculation 1000 * | | |The security key for the TDES/DES accelerator is 64 bits 1001 * | | |Thus, it needs two 32-bit registers to store a security key 1002 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1003 * @var CRPT_T::TDES2_KEY3H 1004 * Offset: 0x298 TDES Key 3 High Word Register for Channel 2 1005 * --------------------------------------------------------------------------------------------------- 1006 * |Bits |Field |Descriptions 1007 * | :----: | :----: | :---- | 1008 * |[31:0] |KEY |TDES/DES Key High/Low Word 1009 * | | |The key registers for TDES/DES algorithm calculation 1010 * | | |The security key for the TDES/DES accelerator is 64 bits 1011 * | | |Thus, it needs two 32-bit registers to store a security key 1012 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1013 * @var CRPT_T::TDES2_KEY3L 1014 * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2 1015 * --------------------------------------------------------------------------------------------------- 1016 * |Bits |Field |Descriptions 1017 * | :----: | :----: | :---- | 1018 * |[31:0] |KEY |TDES/DES Key High/Low Word 1019 * | | |The key registers for TDES/DES algorithm calculation 1020 * | | |The security key for the TDES/DES accelerator is 64 bits 1021 * | | |Thus, it needs two 32-bit registers to store a security key 1022 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1023 * @var CRPT_T::TDES2_IVH 1024 * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2 1025 * --------------------------------------------------------------------------------------------------- 1026 * |Bits |Field |Descriptions 1027 * | :----: | :----: | :---- | 1028 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 1029 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1030 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1031 * @var CRPT_T::TDES2_IVL 1032 * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2 1033 * --------------------------------------------------------------------------------------------------- 1034 * |Bits |Field |Descriptions 1035 * | :----: | :----: | :---- | 1036 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 1037 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1038 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1039 * @var CRPT_T::TDES2_SADDR 1040 * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2 1041 * --------------------------------------------------------------------------------------------------- 1042 * |Bits |Field |Descriptions 1043 * | :----: | :----: | :---- | 1044 * |[31:0] |SA |TDES/DES DMA Source Address 1045 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 1046 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 1047 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 1048 * | | |The start of source address should be located at word boundary 1049 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 1050 * | | |CRPT_TDESn_SA can be read and written 1051 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1052 * | | |But the value of CRPT_TDESn_SA will be updated later on 1053 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 1054 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 1055 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 1056 * @var CRPT_T::TDES2_DADDR 1057 * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2 1058 * --------------------------------------------------------------------------------------------------- 1059 * |Bits |Field |Descriptions 1060 * | :----: | :----: | :---- | 1061 * |[31:0] |DA |TDES/DES DMA Destination Address 1062 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 1063 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 1064 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 1065 * | | |The start of destination address should be located at word boundary 1066 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 1067 * | | |CRPT_TDESn_DA can be read and written 1068 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1069 * | | |But the value of CRPT_TDESn_DA will be updated later on 1070 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 1071 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 1072 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 1073 * @var CRPT_T::TDES2_CNT 1074 * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2 1075 * --------------------------------------------------------------------------------------------------- 1076 * |Bits |Field |Descriptions 1077 * | :----: | :----: | :---- | 1078 * |[31:0] |CNT |TDES/DES Byte Count 1079 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 1080 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 1081 * | | |CRPT_TDESn_CNT can be read and written 1082 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1083 * | | |But the value of CRPT_TDESn_CNT will be updated later on 1084 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 1085 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 1086 * @var CRPT_T::TDES3_KEY1H 1087 * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3 1088 * --------------------------------------------------------------------------------------------------- 1089 * |Bits |Field |Descriptions 1090 * | :----: | :----: | :---- | 1091 * |[31:0] |KEY |TDES/DES Key High/Low Word 1092 * | | |The key registers for TDES/DES algorithm calculation 1093 * | | |The security key for the TDES/DES accelerator is 64 bits 1094 * | | |Thus, it needs two 32-bit registers to store a security key 1095 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1096 * @var CRPT_T::TDES3_KEY1L 1097 * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3 1098 * --------------------------------------------------------------------------------------------------- 1099 * |Bits |Field |Descriptions 1100 * | :----: | :----: | :---- | 1101 * |[31:0] |KEY |TDES/DES Key High/Low Word 1102 * | | |The key registers for TDES/DES algorithm calculation 1103 * | | |The security key for the TDES/DES accelerator is 64 bits 1104 * | | |Thus, it needs two 32-bit registers to store a security key 1105 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1106 * @var CRPT_T::TDES3_KEY2H 1107 * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3 1108 * --------------------------------------------------------------------------------------------------- 1109 * |Bits |Field |Descriptions 1110 * | :----: | :----: | :---- | 1111 * |[31:0] |KEY |TDES/DES Key High/Low Word 1112 * | | |The key registers for TDES/DES algorithm calculation 1113 * | | |The security key for the TDES/DES accelerator is 64 bits 1114 * | | |Thus, it needs two 32-bit registers to store a security key 1115 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1116 * @var CRPT_T::TDES3_KEY2L 1117 * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3 1118 * --------------------------------------------------------------------------------------------------- 1119 * |Bits |Field |Descriptions 1120 * | :----: | :----: | :---- | 1121 * |[31:0] |KEY |TDES/DES Key High/Low Word 1122 * | | |The key registers for TDES/DES algorithm calculation 1123 * | | |The security key for the TDES/DES accelerator is 64 bits 1124 * | | |Thus, it needs two 32-bit registers to store a security key 1125 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1126 * @var CRPT_T::TDES3_KEY3H 1127 * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3 1128 * --------------------------------------------------------------------------------------------------- 1129 * |Bits |Field |Descriptions 1130 * | :----: | :----: | :---- | 1131 * |[31:0] |KEY |TDES/DES Key High/Low Word 1132 * | | |The key registers for TDES/DES algorithm calculation 1133 * | | |The security key for the TDES/DES accelerator is 64 bits 1134 * | | |Thus, it needs two 32-bit registers to store a security key 1135 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1136 * @var CRPT_T::TDES3_KEY3L 1137 * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3 1138 * --------------------------------------------------------------------------------------------------- 1139 * |Bits |Field |Descriptions 1140 * | :----: | :----: | :---- | 1141 * |[31:0] |KEY |TDES/DES Key High/Low Word 1142 * | | |The key registers for TDES/DES algorithm calculation 1143 * | | |The security key for the TDES/DES accelerator is 64 bits 1144 * | | |Thus, it needs two 32-bit registers to store a security key 1145 * | | |The register CRPT_TDESn_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register CRPT_TDESn_KEYxL is used to keep the bit [31:0]. 1146 * @var CRPT_T::TDES3_IVH 1147 * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3 1148 * --------------------------------------------------------------------------------------------------- 1149 * |Bits |Field |Descriptions 1150 * | :----: | :----: | :---- | 1151 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 1152 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1153 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1154 * @var CRPT_T::TDES3_IVL 1155 * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3 1156 * --------------------------------------------------------------------------------------------------- 1157 * |Bits |Field |Descriptions 1158 * | :----: | :----: | :---- | 1159 * |[31:0] |IV |TDES/DES Initial Vector High/Low Word 1160 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode 1161 * | | |IV is Nonce counter for TDES/DES engine in CTR mode. 1162 * @var CRPT_T::TDES3_SADDR 1163 * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3 1164 * --------------------------------------------------------------------------------------------------- 1165 * |Bits |Field |Descriptions 1166 * | :----: | :----: | :---- | 1167 * |[31:0] |SA |TDES/DES DMA Source Address 1168 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 1169 * | | |The CRPT_TDESn_SA keeps the source address of the data buffer where the source text is stored 1170 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation 1171 * | | |The start of source address should be located at word boundary 1172 * | | |In other words, bit 1 and 0 of CRPT_TDESn_SA are ignored. 1173 * | | |CRPT_TDESn_SA can be read and written 1174 * | | |Writing to CRPT_TDESn_SA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1175 * | | |But the value of CRPT_TDESn_SA will be updated later on 1176 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation. 1177 * | | |In DMA mode, software can update the next CRPT_TDESn_SA before triggering START. 1178 * | | |CRPT_TDESn_SA and CRPT_TDESn_DA can be the same in the value. 1179 * @var CRPT_T::TDES3_DADDR 1180 * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3 1181 * --------------------------------------------------------------------------------------------------- 1182 * |Bits |Field |Descriptions 1183 * | :----: | :----: | :---- | 1184 * |[31:0] |DA |TDES/DES DMA Destination Address 1185 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO 1186 * | | |The CRPT_TDESn_DA keeps the destination address of the data buffer where the engine output's text will be stored 1187 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished 1188 * | | |The start of destination address should be located at word boundary 1189 * | | |In other words, bit 1 and 0 of CRPT_TDESn_DA are ignored. 1190 * | | |CRPT_TDESn_DA can be read and written 1191 * | | |Writing to CRPT_TDESn_DA while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1192 * | | |But the value of CRPT_TDESn_DA will be updated later on 1193 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation. 1194 * | | |In DMA mode, software can update the next CRPT_TDESn_DA before triggering START. 1195 * | | |CRPT_TDESn_SAD and CRPT_TDESn_DA can be the same in the value. 1196 * @var CRPT_T::TDES3_CNT 1197 * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3 1198 * --------------------------------------------------------------------------------------------------- 1199 * |Bits |Field |Descriptions 1200 * | :----: | :----: | :---- | 1201 * |[31:0] |CNT |TDES/DES Byte Count 1202 * | | |The CRPT_TDESn_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode 1203 * | | |The CRPT_TDESn_CNT is 32-bit and the maximum of byte count is 4G bytes. 1204 * | | |CRPT_TDESn_CNT can be read and written 1205 * | | |Writing to CRPT_TDESn_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation 1206 * | | |But the value of CRPT_TDESn_CNT will be updated later on 1207 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation. 1208 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, CRPT_TDESn_CNT must be set as byte count for the last block of data before feeding in the last block of data. 1209 * @var CRPT_T::HMAC_CTL 1210 * Offset: 0x300 SHA/HMAC Control Register 1211 * --------------------------------------------------------------------------------------------------- 1212 * |Bits |Field |Descriptions 1213 * | :----: | :----: | :---- | 1214 * |[0] |START |SHA/HMAC Engine Start 1215 * | | |0 = No effect. 1216 * | | |1 = Start SHA/HMAC engine. BUSY flag will be set. 1217 * | | |This bit is always 0 when it's read back. 1218 * |[1] |STOP |SHA/HMAC Engine Stop 1219 * | | |0 = No effect. 1220 * | | |1 = Stop SHA/HMAC engine. 1221 * | | |This bit is always 0 when it's read back. 1222 * |[5] |DMALAST |SHA/HMAC Last Block 1223 * | | |This bit must be set as feeding in last byte of data. 1224 * |[7] |DMAEN |SHA/HMAC Engine DMA Enable Control 1225 * | | |0 = SHA/HMAC DMA engine Disabled. 1226 * | | |SHA/HMAC engine operates in Non-DMA mode, and gets data from the port CRPT_HMAC_DATIN. 1227 * | | |1 = SHA/HMAC DMA engine Enabled. 1228 * | | |SHA/HMAC engine operates in DMA mode, and data movement from/to the engine is done by DMA logic. 1229 * |[10:8] |OPMODE |SHA/HMAC Engine Operation Modes 1230 * | | |0x0xx: SHA160 1231 * | | |0x100: SHA256 1232 * | | |0x101: SHA224 1233 * | | |0x110: SHA512 1234 * | | |0x111: SHA384 1235 * | | |These bits can be read and written. But writing to them wouldn't take effect as BUSY is 1. 1236 * |[22] |OUTSWAP |SHA/HMAC Engine Output Data Swap 1237 * | | |0 = Keep the original order. 1238 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 1239 * |[23] |INSWAP |SHA/HMAC Engine Input Data Swap 1240 * | | |0 = Keep the original order. 1241 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}. 1242 * @var CRPT_T::HMAC_STS 1243 * Offset: 0x304 SHA/HMAC Status Flag 1244 * --------------------------------------------------------------------------------------------------- 1245 * |Bits |Field |Descriptions 1246 * | :----: | :----: | :---- | 1247 * |[0] |BUSY |SHA/HMAC Engine Busy 1248 * | | |0 = SHA/HMAC engine is idle or finished. 1249 * | | |1 = SHA/HMAC engine is busy. 1250 * |[1] |DMABUSY |SHA/HMAC Engine DMA Busy Flag 1251 * | | |0 = SHA/HMAC DMA engine is idle or finished. 1252 * | | |1 = SHA/HMAC DMA engine is busy. 1253 * |[8] |DMAERR |SHA/HMAC Engine DMA Error Flag 1254 * | | |0 = Show the SHA/HMAC engine access normal. 1255 * | | |1 = Show the SHA/HMAC engine access error. 1256 * |[16] |DATINREQ |SHA/HMAC Non-DMA Mode Data Input Request 1257 * | | |0 = No effect. 1258 * | | |1 = Request SHA/HMAC Non-DMA mode data input. 1259 * @var CRPT_T::HMAC_DGST[16] 1260 * Offset: 0x308~0x344 SHA/HMAC Digest Message 0~15 1261 * --------------------------------------------------------------------------------------------------- 1262 * |Bits |Field |Descriptions 1263 * | :----: | :----: | :---- | 1264 * |[31:0] |DGST |SHA/HMAC Digest Message Output Register 1265 * | | |For SHA-160, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST4. 1266 * | | |For SHA-224, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST6. 1267 * | | |For SHA-256, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST7. 1268 * | | |For SHA-384, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST11. 1269 * | | |For SHA-512, the digest is stored in CRPT_HMAC_DGST0 ~ CRPT_HMAC_DGST15. 1270 * @var CRPT_T::HMAC_KEYCNT 1271 * Offset: 0x348 SHA/HMAC Key Byte Count Register 1272 * --------------------------------------------------------------------------------------------------- 1273 * |Bits |Field |Descriptions 1274 * | :----: | :----: | :---- | 1275 * |[31:0] |KEYCNT |SHA/HMAC Key Byte Count 1276 * | | |The CRPT_HMAC_KEYCNT keeps the byte count of key that SHA/HMAC engine operates 1277 * | | |The register is 32-bit and the maximum byte count is 4G bytes 1278 * | | |It can be read and written. 1279 * | | |Writing to the register CRPT_HMAC_KEYCNT as the SHA/HMAC accelerator operating doesn't affect the current SHA/HMAC operation 1280 * | | |But the value of CRPT_SHA _KEYCNT will be updated later on 1281 * | | |Consequently, software can prepare the key count for the next SHA/HMAC operation. 1282 * @var CRPT_T::HMAC_SADDR 1283 * Offset: 0x34C SHA/HMAC DMA Source Address Register 1284 * --------------------------------------------------------------------------------------------------- 1285 * |Bits |Field |Descriptions 1286 * | :----: | :----: | :---- | 1287 * |[31:0] |SADDR |SHA/HMAC DMA Source Address 1288 * | | |The SHA/HMAC accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO 1289 * | | |The CRPT_HMAC_SADDR keeps the source address of the data buffer where the source text is stored 1290 * | | |Based on the source address, the SHA/HMAC accelerator can read the plain text from system memory and do SHA/HMAC operation 1291 * | | |The start of source address should be located at word boundary 1292 * | | |In other words, bit 1 and 0 of CRPT_HMAC_SADDR are ignored. 1293 * | | |CRPT_HMAC_SADDR can be read and written 1294 * | | |Writing to CRPT_HMAC_SADDR while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation 1295 * | | |But the value of CRPT_HMAC_SADDR will be updated later on 1296 * | | |Consequently, software can prepare the DMA source address for the next SHA/HMAC operation. 1297 * | | |In DMA mode, software can update the next CRPT_HMAC_SADDR before triggering START. 1298 * | | |CRPT_HMAC_SADDR and CRPT_HMAC_DADDR can be the same in the value. 1299 * @var CRPT_T::HMAC_DMACNT 1300 * Offset: 0x350 SHA/HMAC Byte Count Register 1301 * --------------------------------------------------------------------------------------------------- 1302 * |Bits |Field |Descriptions 1303 * | :----: | :----: | :---- | 1304 * |[31:0] |DMACNT |SHA/HMAC Operation Byte Count 1305 * | | |The CRPT_HMAC_DMACNT keeps the byte count of source text that is for the SHA/HMAC engine operating in DMA mode 1306 * | | |The CRPT_HMAC_DMACNT is 32-bit and the maximum of byte count is 4G bytes. 1307 * | | |CRPT_HMAC_DMACNT can be read and written 1308 * | | |Writing to CRPT_HMAC_DMACNT while the SHA/HMAC accelerator is operating doesn't affect the current SHA/HMAC operation 1309 * | | |But the value of CRPT_HMAC_DMACNT will be updated later on 1310 * | | |Consequently, software can prepare the byte count of data for the next SHA/HMAC operation. 1311 * | | |In Non-DMA mode, CRPT_HMAC_DMACNT must be set as the byte count of the last block before feeding in the last block of data. 1312 * @var CRPT_T::HMAC_DATIN 1313 * Offset: 0x354 SHA/HMAC Engine Non-DMA Mode Data Input Port Register 1314 * --------------------------------------------------------------------------------------------------- 1315 * |Bits |Field |Descriptions 1316 * | :----: | :----: | :---- | 1317 * |[31:0] |DATIN |SHA/HMAC Engine Input Port 1318 * | | |CPU feeds data to SHA/HMAC engine through this port by checking CRPT_HMAC_STS 1319 * | | |Feed data as DATINREQ is 1. 1320 * @var CRPT_T::ECC_CTL 1321 * Offset: 0x800 ECC Control Register 1322 * --------------------------------------------------------------------------------------------------- 1323 * |Bits |Field |Descriptions 1324 * | :----: | :----: | :---- | 1325 * |[0] |START |ECC Accelerator Start 1326 * | | |0 = No effect. 1327 * | | |1 = Start ECC accelerator. BUSY flag will be set. 1328 * | | |This bit is always 0 when it's read back. 1329 * | | |ECC accelerator will ignore this START signal when BUSY flag is 1. 1330 * |[1] |STOP |ECC Accelerator Stop 1331 * | | |0 = No effect. 1332 * | | |1 = Abort ECC accelerator and make it into idle state. 1333 * | | |This bit is always 0 when it's read back. 1334 * | | |Remember to clear ECC interrupt flag after stopping ECC accelerator. 1335 * |[7] |DMAEN |ECC Accelerator DMA Enable Control 1336 * | | |0 = ECC DMA engine Disabled. 1337 * | | |1 = ECC DMA engine Enabled. 1338 * | | |Only when START and DMAEN are 1, ECC DMA engine will be active 1339 * |[8] |FSEL |Field Selection 1340 * | | |0 = Binary Field (GF(2m )). 1341 * | | |1 = Prime Field (GF(p)). 1342 * |[10:9] |ECCOP |Point Operation for BF and PF 1343 * | | |00 = Point multiplication : 1344 * | | |(POINTX1, POINTY1) = SCALARK * (POINTX1, POINTY1). 1345 * | | |01 = Modulus operation : choose by MODOP (CRPT_ECC_CTL[12:11]). 1346 * | | |10 = Point addition : 1347 * | | |(POINTX1, POINTY1) = (POINTX1, POINTY1) +. 1348 * | | |(POINTX2, POINTY2) 1349 * | | |11 = Point doubling : 1350 * | | |(POINTX1, POINTY1) = 2 * (POINTX1, POINTY1). 1351 * | | |Besides above three input data, point operations still need the parameters of elliptic curve (CURVEA, CURVEB, CURVEN and CURVEM) as shown in Figure 6.27-11 1352 * |[12:11] |MODOP |Modulus Operation for PF 1353 * | | |00 = Division : 1354 * | | |POINTX1 = (POINTY1 / POINTX1) % CURVEN. 1355 * | | |01 = Multiplication : 1356 * | | |POINTX1 = (POINTX1 * POINTY1) % CURVEN. 1357 * | | |10 = Addition : 1358 * | | |POINTX1 = (POINTX1 + POINTY1) % CURVEN. 1359 * | | |11 = Subtraction : 1360 * | | |POINTX1 = (POINTX1 - POINTY1) % CURVEN. 1361 * | | |MODOP is active only when ECCOP = 01. 1362 * |[16] |LDP1 |The Control Signal of Register for the X and Y Coordinate of the First Point (POINTX1, POINTY1) 1363 * | | |0 = The register for POINTX1 and POINTY1 is not modified by DMA or user. 1364 * | | |1 = The register for POINTX1 and POINTY1 is modified by DMA or user. 1365 * |[17] |LDP2 |The Control Signal of Register for the X and Y Coordinate of the Second Point (POINTX2, POINTY2) 1366 * | | |0 = The register for POINTX2 and POINTY2 is not modified by DMA or user. 1367 * | | |1 = The register for POINTX2 and POINTY2 is modified by DMA or user. 1368 * |[18] |LDA |The Control Signal of Register for the Parameter CURVEA of Elliptic Curve 1369 * | | |0 = The register for CURVEA is not modified by DMA or user. 1370 * | | |1 = The register for CURVEA is modified by DMA or user. 1371 * |[19] |LDB |The Control Signal of Register for the Parameter CURVEB of Elliptic Curve 1372 * | | |0 = The register for CURVEB is not modified by DMA or user. 1373 * | | |1 = The register for CURVEB is modified by DMA or user. 1374 * |[20] |LDN |The Control Signal of Register for the Parameter CURVEN of Elliptic Curve 1375 * | | |0 = The register for CURVEN is not modified by DMA or user. 1376 * | | |1 = The register for CURVEN is modified by DMA or user. 1377 * |[21] |LDK |The Control Signal of Register for SCALARK 1378 * | | |0 = The register for SCALARK is not modified by DMA or user. 1379 * | | |1 = The register for SCALARK is modified by DMA or user. 1380 * |[31:22] |CURVEM |The key length of elliptic curve. 1381 * @var CRPT_T::ECC_STS 1382 * Offset: 0x804 ECC Status Register 1383 * --------------------------------------------------------------------------------------------------- 1384 * |Bits |Field |Descriptions 1385 * | :----: | :----: | :---- | 1386 * |[0] |BUSY |ECC Accelerator Busy Flag 1387 * | | |0 = The ECC accelerator is idle or finished. 1388 * | | |1 = The ECC accelerator is under processing and protects all registers. 1389 * | | |Remember to clear ECC interrupt flag after ECC accelerator finished 1390 * |[1] |DMABUSY |ECC DMA Busy Flag 1391 * | | |0 = ECC DMA is idle or finished. 1392 * | | |1 = ECC DMA is busy. 1393 * |[16] |BUSERR |ECC DMA Access Bus Error Flag 1394 * | | |0 = No error. 1395 * | | |1 = Bus error will stop DMA operation and ECC accelerator. 1396 * @var CRPT_T::ECC_X1[18] 1397 * Offset: 0x808~0x84C ECC The X-coordinate word 0~17 of the first point 1398 * --------------------------------------------------------------------------------------------------- 1399 * |Bits |Field |Descriptions 1400 * | :----: | :----: | :---- | 1401 * |[31:0] |POINTX1 |ECC the x-coordinate Value of the First Point (POINTX1) 1402 * | | |For B-163 or K-163, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 1403 * | | |For B-233 or K-233, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 1404 * | | |For B-283 or K-283, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_08 1405 * | | |For B-409 or K-409, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_12 1406 * | | |For B-571 or K-571, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_17 1407 * | | |For P-192, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_05 1408 * | | |For P-224, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_06 1409 * | | |For P-256, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_07 1410 * | | |For P-384, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_11 1411 * | | |For P-521, POINTX1 is stored in CRPT_ECC_X1_00~CRPT_ECC_X1_16 1412 * @var CRPT_T::ECC_Y1[18] 1413 * Offset: 0x850~0x894 ECC The Y-coordinate word 0~17 of the first point 1414 * --------------------------------------------------------------------------------------------------- 1415 * |Bits |Field |Descriptions 1416 * | :----: | :----: | :---- | 1417 * |[31:0] |POINTY1 |ECC the Y-coordinate Value of the First Point (POINTY1) 1418 * | | |For B-163 or K-163, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 1419 * | | |For B-233 or K-233, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 1420 * | | |For B-283 or K-283, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_08 1421 * | | |For B-409 or K-409, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_12 1422 * | | |For B-571 or K-571, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_17 1423 * | | |For P-192, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_05 1424 * | | |For P-224, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_06 1425 * | | |For P-256, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_07 1426 * | | |For P-384, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_11 1427 * | | |For P-521, POINTY1 is stored in CRPT_ECC_Y1_00~CRPT_ECC_Y1_16 1428 * @var CRPT_T::ECC_X2[18] 1429 * Offset: 0x898~0x8DC ECC The X-coordinate word 0~17 of the second point 1430 * --------------------------------------------------------------------------------------------------- 1431 * |Bits |Field |Descriptions 1432 * | :----: | :----: | :---- | 1433 * |[31:0] |POINTX2 |ECC the x-coordinate Value of the Second Point (POINTX2) 1434 * | | |For B-163 or K-163, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 1435 * | | |For B-233 or K-233, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 1436 * | | |For B-283 or K-283, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_08 1437 * | | |For B-409 or K-409, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_12 1438 * | | |For B-571 or K-571, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_17 1439 * | | |For P-192, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_05 1440 * | | |For P-224, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_06 1441 * | | |For P-256, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_07 1442 * | | |For P-384, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_11 1443 * | | |For P-521, POINTX2 is stored in CRPT_ECC_X2_00~CRPT_ECC_X2_16 1444 * @var CRPT_T::ECC_Y2[18] 1445 * Offset: 0x8E0~0x924 ECC The Y-coordinate word 0~17 of the second point 1446 * --------------------------------------------------------------------------------------------------- 1447 * |Bits |Field |Descriptions 1448 * | :----: | :----: | :---- | 1449 * |[31:0] |POINTY2 |ECC the Y-coordinate Value of the Second Point (POINTY2) 1450 * | | |For B-163 or K-163, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 1451 * | | |For B-233 or K-233, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 1452 * | | |For B-283 or K-283, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_08 1453 * | | |For B-409 or K-409, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_12 1454 * | | |For B-571 or K-571, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_17 1455 * | | |For P-192, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_05 1456 * | | |For P-224, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_06 1457 * | | |For P-256, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_07 1458 * | | |For P-384, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_11 1459 * | | |For P-521, POINTY2 is stored in CRPT_ECC_Y2_00~CRPT_ECC_Y2_16 1460 * @var CRPT_T::ECC_A[18] 1461 * Offset: 0x928~0x96C ECC The parameter CURVEA word 0~17 of elliptic curve 1462 * --------------------------------------------------------------------------------------------------- 1463 * |Bits |Field |Descriptions 1464 * | :----: | :----: | :---- | 1465 * |[31:0] |CURVEA |ECC the Parameter CURVEA Value of Elliptic Curve (CURVEA) 1466 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). 1467 * | | |For B-163 or K-163, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 1468 * | | |For B-233 or K-233, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 1469 * | | |For B-283 or K-283, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_08 1470 * | | |For B-409 or K-409, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_12 1471 * | | |For B-571 or K-571, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_17 1472 * | | |For P-192, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_05 1473 * | | |For P-224, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_06 1474 * | | |For P-256, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_07 1475 * | | |For P-384, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_11 1476 * | | |For P-521, CURVEA is stored in CRPT_ECC_A_00~CRPT_ECC_A_16 1477 * @var CRPT_T::ECC_B[18] 1478 * Offset: 0x970~0x9B4 ECC The parameter CURVEB word 0~17 of elliptic curve 1479 * --------------------------------------------------------------------------------------------------- 1480 * |Bits |Field |Descriptions 1481 * | :----: | :----: | :---- | 1482 * |[31:0] |CURVEB |ECC the Parameter CURVEB Value of Elliptic Curve (CURVEA) 1483 * | | |The formula of elliptic curve is y2=x3+CURVEA*x+CURVEB in GF(p) and y2+x*y=x3+CURVEA*x2+CURVEB in GF(2m). 1484 * | | |For B-163 or K-163, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 1485 * | | |For B-233 or K-233, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 1486 * | | |For B-283 or K-283, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_08 1487 * | | |For B-409 or K-409, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_12 1488 * | | |For B-521 or K-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_17 1489 * | | |For P-192, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_05 1490 * | | |For P-224, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_06 1491 * | | |For P-256, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_07 1492 * | | |For P-384, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_11 1493 * | | |For P-521, CURVEB is stored in CRPT_ECC_B_00~CRPT_ECC_B_16 1494 * @var CRPT_T::ECC_N[18] 1495 * Offset: 0x9B8~0x9FC ECC The parameter CURVEN word 0~17 of elliptic curve 1496 * --------------------------------------------------------------------------------------------------- 1497 * |Bits |Field |Descriptions 1498 * | :----: | :----: | :---- | 1499 * |[31:0] |CURVEN |ECC the Parameter CURVEN Value of Elliptic Curve (CURVEN) 1500 * | | |In GF(p), CURVEN is the prime p. 1501 * | | |In GF(2m), CURVEN is the irreducible polynomial. 1502 * | | |For B-163 or K-163, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 1503 * | | |For B-233 or K-233, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 1504 * | | |For B-283 or K-283, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_08 1505 * | | |For B-409 or K-409, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_12 1506 * | | |For B-571 or K-571, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_17 1507 * | | |For P-192, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_05 1508 * | | |For P-224, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_06 1509 * | | |For P-256, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_07 1510 * | | |For P-384, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_11 1511 * | | |For P-521, CURVEN is stored in CRPT_ECC_N_00~CRPT_ECC_N_16 1512 * @var CRPT_T::ECC_K[18] 1513 * Offset: 0xA00~0xA44 ECC The scalar SCALARK word 0~17 of point multiplication 1514 * --------------------------------------------------------------------------------------------------- 1515 * |Bits |Field |Descriptions 1516 * | :----: | :----: | :---- | 1517 * |[31:0] |SCALARK |ECC the Scalar SCALARK Value of Point Multiplication(SCALARK) 1518 * | | |Because the SCALARK usually stores the private key, ECC accelerator do not allow to read the register SCALARK. 1519 * | | |For B-163 or K-163, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 1520 * | | |For B-233 or K-233, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 1521 * | | |For B-283 or K-283, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_08 1522 * | | |For B-409 or K-409, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_12 1523 * | | |For B-571 or K-571, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_17 1524 * | | |For P-192, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_05 1525 * | | |For P-224, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_06 1526 * | | |For P-256, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_07 1527 * | | |For P-384, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_11 1528 * | | |For P-521, SCALARK is stored in CRPT_ECC_K_00~CRPT_ECC_K_16 1529 * @var CRPT_T::ECC_SADDR 1530 * Offset: 0xA48 ECC DMA Source Address Register 1531 * --------------------------------------------------------------------------------------------------- 1532 * |Bits |Field |Descriptions 1533 * | :----: | :----: | :---- | 1534 * @var CRPT_T::ECC_DADDR 1535 * Offset: 0xA4C ECC DMA Destination Address Register 1536 * --------------------------------------------------------------------------------------------------- 1537 * |Bits |Field |Descriptions 1538 * | :----: | :----: | :---- | 1539 * |[31:0] |DADDR |ECC DMA Destination Address 1540 * | | |The ECC accelerator supports DMA function to transfer the DATA and PARAMETER between system memory and ECC accelerator 1541 * | | |The DADDR keeps the destination address of the data buffer where output data of ECC engine will be stored 1542 * | | |Based on the destination address, the ECC accelerator can write the result data back to system memory after the ECC operation is finished 1543 * | | |The start of destination address should be located at word boundary 1544 * | | |That is, bit 1 and 0 of DADDR are ignored 1545 * | | |DADDR can be read and written 1546 * | | |In DMA mode, software must update the CRPT_ECC_DADDR before triggering START 1547 * @var CRPT_T::ECC_STARTREG 1548 * Offset: 0xA50 ECC Starting Address of Updated Registers 1549 * --------------------------------------------------------------------------------------------------- 1550 * |Bits |Field |Descriptions 1551 * | :----: | :----: | :---- | 1552 * |[31:0] |STARTREG |ECC Starting Address of Updated Registers 1553 * | | |The address of the updated registers that DMA feeds the first data or parameter to ECC engine 1554 * | | |When ECC engine is active, ECC accelerator does not allow users to modify STARTREG 1555 * | | |For example, we want to updated input data from register CRPT_ECC POINTX1 1556 * | | |Thus, the value of STARTREG is 0x808. 1557 * @var CRPT_T::ECC_WORDCNT 1558 * Offset: 0xA54 ECC DMA Word Count 1559 * --------------------------------------------------------------------------------------------------- 1560 * |Bits |Field |Descriptions 1561 * | :----: | :----: | :---- | 1562 * |[31:0] |WORDCNT |ECC DMA Word Count 1563 * | | |The CRPT_ECC_WORDCNT keeps the word count of source data that is for the required input data of ECC accelerator with various operations in DMA mode 1564 * | | |Although CRPT_ECC_WORDCNT is 32-bit, the maximum of word count in ECC accelerator is 144 words 1565 * | | |CRPT_ECC_WORDCNT can be read and written 1566 */ 1567 __IO uint32_t INTEN; /*!< [0x0000] Crypto Interrupt Enable Control Register */ 1568 __IO uint32_t INTSTS; /*!< [0x0004] Crypto Interrupt Flag */ 1569 __IO uint32_t PRNG_CTL; /*!< [0x0008] PRNG Control Register */ 1570 __O uint32_t PRNG_SEED; /*!< [0x000c] Seed for PRNG */ 1571 __I uint32_t PRNG_KEY[8]; /*!< [0x0010] ~ [0x002c] PRNG Generated Key0 ~ Key7 */ 1572 __I uint32_t RESERVE0[8]; 1573 __I uint32_t AES_FDBCK[4]; /*!< [0x0050] ~ [0x005c] AES Engine Output Feedback Data after Cryptographic Operation */ 1574 __I uint32_t TDES_FDBCKH; /*!< [0x0060] TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation */ 1575 __I uint32_t TDES_FDBCKL; /*!< [0x0064] TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation */ 1576 __I uint32_t RESERVE1[38]; 1577 __IO uint32_t AES_CTL; /*!< [0x0100] AES Control Register */ 1578 __I uint32_t AES_STS; /*!< [0x0104] AES Engine Flag */ 1579 __IO uint32_t AES_DATIN; /*!< [0x0108] AES Engine Data Input Port Register */ 1580 __I uint32_t AES_DATOUT; /*!< [0x010c] AES Engine Data Output Port Register */ 1581 __IO uint32_t AES0_KEY[8]; /*!< [0x0110] ~ [0x012c] AES Key Word 0~7 Register for Channel 0 */ 1582 __IO uint32_t AES0_IV[4]; /*!< [0x0130] ~ [0x013c] AES Initial Vector Word 0 ~ 3 Register for Channel 0 */ 1583 __IO uint32_t AES0_SADDR; /*!< [0x0140] AES DMA Source Address Register for Channel 0 */ 1584 __IO uint32_t AES0_DADDR; /*!< [0x0144] AES DMA Destination Address Register for Channel 0 */ 1585 __IO uint32_t AES0_CNT; /*!< [0x0148] AES Byte Count Register for Channel 0 */ 1586 __IO uint32_t AES1_KEY[8]; /*!< [0x014c] ~ [0x0168] AES Key Word 0~7 Register for Channel 1 */ 1587 __IO uint32_t AES1_IV[4]; /*!< [0x016c] ~ [0x0178] AES Initial Vector Word 0~3 Register for Channel 1 */ 1588 __IO uint32_t AES1_SADDR; /*!< [0x017c] AES DMA Source Address Register for Channel 1 */ 1589 __IO uint32_t AES1_DADDR; /*!< [0x0180] AES DMA Destination Address Register for Channel 1 */ 1590 __IO uint32_t AES1_CNT; /*!< [0x0184] AES Byte Count Register for Channel 1 */ 1591 __IO uint32_t AES2_KEY[8]; /*!< [0x0188] ~ [0x01a4] AES Key Word 0~7 Register for Channel 2 */ 1592 __IO uint32_t AES2_IV[4]; /*!< [0x01a8] ~ [0x01b4] AES Initial Vector Word 0~3 Register for Channel 2 */ 1593 __IO uint32_t AES2_SADDR; /*!< [0x01b8] AES DMA Source Address Register for Channel 2 */ 1594 __IO uint32_t AES2_DADDR; /*!< [0x01bc] AES DMA Destination Address Register for Channel 2 */ 1595 __IO uint32_t AES2_CNT; /*!< [0x01c0] AES Byte Count Register for Channel 2 */ 1596 __IO uint32_t AES3_KEY[8]; /*!< [0x01c4] ~ [0x01e0] AES Key Word 0~7 Register for Channel 3 */ 1597 __IO uint32_t AES3_IV[4]; /*!< [0x01e4] ~ [0x01f0] AES Initial Vector Word 0~3 Register for Channel 3 */ 1598 __IO uint32_t AES3_SADDR; /*!< [0x01f4] AES DMA Source Address Register for Channel 3 */ 1599 __IO uint32_t AES3_DADDR; /*!< [0x01f8] AES DMA Destination Address Register for Channel 3 */ 1600 __IO uint32_t AES3_CNT; /*!< [0x01fc] AES Byte Count Register for Channel 3 */ 1601 __IO uint32_t TDES_CTL; /*!< [0x0200] TDES/DES Control Register */ 1602 __I uint32_t TDES_STS; /*!< [0x0204] TDES/DES Engine Flag */ 1603 __IO uint32_t TDES0_KEY1H; /*!< [0x0208] TDES/DES Key 1 High Word Register for Channel 0 */ 1604 __IO uint32_t TDES0_KEY1L; /*!< [0x020c] TDES/DES Key 1 Low Word Register for Channel 0 */ 1605 __IO uint32_t TDES0_KEY2H; /*!< [0x0210] TDES Key 2 High Word Register for Channel 0 */ 1606 __IO uint32_t TDES0_KEY2L; /*!< [0x0214] TDES Key 2 Low Word Register for Channel 0 */ 1607 __IO uint32_t TDES0_KEY3H; /*!< [0x0218] TDES Key 3 High Word Register for Channel 0 */ 1608 __IO uint32_t TDES0_KEY3L; /*!< [0x021c] TDES Key 3 Low Word Register for Channel 0 */ 1609 __IO uint32_t TDES0_IVH; /*!< [0x0220] TDES/DES Initial Vector High Word Register for Channel 0 */ 1610 __IO uint32_t TDES0_IVL; /*!< [0x0224] TDES/DES Initial Vector Low Word Register for Channel 0 */ 1611 __IO uint32_t TDES0_SADDR; /*!< [0x0228] TDES/DES DMA Source Address Register for Channel 0 */ 1612 __IO uint32_t TDES0_DADDR; /*!< [0x022c] TDES/DES DMA Destination Address Register for Channel 0 */ 1613 __IO uint32_t TDES0_CNT; /*!< [0x0230] TDES/DES Byte Count Register for Channel 0 */ 1614 __IO uint32_t TDES_DATIN; /*!< [0x0234] TDES/DES Engine Input data Word Register */ 1615 __I uint32_t TDES_DATOUT; /*!< [0x0238] TDES/DES Engine Output data Word Register */ 1616 __I uint32_t RESERVE2[3]; 1617 __IO uint32_t TDES1_KEY1H; /*!< [0x0248] TDES/DES Key 1 High Word Register for Channel 1 */ 1618 __IO uint32_t TDES1_KEY1L; /*!< [0x024c] TDES/DES Key 1 Low Word Register for Channel 1 */ 1619 __IO uint32_t TDES1_KEY2H; /*!< [0x0250] TDES Key 2 High Word Register for Channel 1 */ 1620 __IO uint32_t TDES1_KEY2L; /*!< [0x0254] TDES Key 2 Low Word Register for Channel 1 */ 1621 __IO uint32_t TDES1_KEY3H; /*!< [0x0258] TDES Key 3 High Word Register for Channel 1 */ 1622 __IO uint32_t TDES1_KEY3L; /*!< [0x025c] TDES Key 3 Low Word Register for Channel 1 */ 1623 __IO uint32_t TDES1_IVH; /*!< [0x0260] TDES/DES Initial Vector High Word Register for Channel 1 */ 1624 __IO uint32_t TDES1_IVL; /*!< [0x0264] TDES/DES Initial Vector Low Word Register for Channel 1 */ 1625 __IO uint32_t TDES1_SADDR; /*!< [0x0268] TDES/DES DMA Source Address Register for Channel 1 */ 1626 __IO uint32_t TDES1_DADDR; /*!< [0x026c] TDES/DES DMA Destination Address Register for Channel 1 */ 1627 __IO uint32_t TDES1_CNT; /*!< [0x0270] TDES/DES Byte Count Register for Channel 1 */ 1628 __I uint32_t RESERVE3[5]; 1629 __IO uint32_t TDES2_KEY1H; /*!< [0x0288] TDES/DES Key 1 High Word Register for Channel 2 */ 1630 __IO uint32_t TDES2_KEY1L; /*!< [0x028c] TDES/DES Key 1 Low Word Register for Channel 2 */ 1631 __IO uint32_t TDES2_KEY2H; /*!< [0x0290] TDES Key 2 High Word Register for Channel 2 */ 1632 __IO uint32_t TDES2_KEY2L; /*!< [0x0294] TDES Key 2 Low Word Register for Channel 2 */ 1633 __IO uint32_t TDES2_KEY3H; /*!< [0x0298] TDES Key 3 High Word Register for Channel 2 */ 1634 __IO uint32_t TDES2_KEY3L; /*!< [0x029c] TDES Key 3 Low Word Register for Channel 2 */ 1635 __IO uint32_t TDES2_IVH; /*!< [0x02a0] TDES/DES Initial Vector High Word Register for Channel 2 */ 1636 __IO uint32_t TDES2_IVL; /*!< [0x02a4] TDES/DES Initial Vector Low Word Register for Channel 2 */ 1637 __IO uint32_t TDES2_SADDR; /*!< [0x02a8] TDES/DES DMA Source Address Register for Channel 2 */ 1638 __IO uint32_t TDES2_DADDR; /*!< [0x02ac] TDES/DES DMA Destination Address Register for Channel 2 */ 1639 __IO uint32_t TDES2_CNT; /*!< [0x02b0] TDES/DES Byte Count Register for Channel 2 */ 1640 __I uint32_t RESERVE4[5]; 1641 __IO uint32_t TDES3_KEY1H; /*!< [0x02c8] TDES/DES Key 1 High Word Register for Channel 3 */ 1642 __IO uint32_t TDES3_KEY1L; /*!< [0x02cc] TDES/DES Key 1 Low Word Register for Channel 3 */ 1643 __IO uint32_t TDES3_KEY2H; /*!< [0x02d0] TDES Key 2 High Word Register for Channel 3 */ 1644 __IO uint32_t TDES3_KEY2L; /*!< [0x02d4] TDES Key 2 Low Word Register for Channel 3 */ 1645 __IO uint32_t TDES3_KEY3H; /*!< [0x02d8] TDES Key 3 High Word Register for Channel 3 */ 1646 __IO uint32_t TDES3_KEY3L; /*!< [0x02dc] TDES Key 3 Low Word Register for Channel 3 */ 1647 __IO uint32_t TDES3_IVH; /*!< [0x02e0] TDES/DES Initial Vector High Word Register for Channel 3 */ 1648 __IO uint32_t TDES3_IVL; /*!< [0x02e4] TDES/DES Initial Vector Low Word Register for Channel 3 */ 1649 __IO uint32_t TDES3_SADDR; /*!< [0x02e8] TDES/DES DMA Source Address Register for Channel 3 */ 1650 __IO uint32_t TDES3_DADDR; /*!< [0x02ec] TDES/DES DMA Destination Address Register for Channel 3 */ 1651 __IO uint32_t TDES3_CNT; /*!< [0x02f0] TDES/DES Byte Count Register for Channel 3 */ 1652 __I uint32_t RESERVE5[3]; 1653 __IO uint32_t HMAC_CTL; /*!< [0x0300] SHA/HMAC Control Register */ 1654 __I uint32_t HMAC_STS; /*!< [0x0304] SHA/HMAC Status Flag */ 1655 __I uint32_t HMAC_DGST[16]; /*!< [0x0308] ~ [0x0344] SHA/HMAC Digest Message 0~15 */ 1656 __IO uint32_t HMAC_KEYCNT; /*!< [0x0348] SHA/HMAC Key Byte Count Register */ 1657 __IO uint32_t HMAC_SADDR; /*!< [0x034c] SHA/HMAC DMA Source Address Register */ 1658 __IO uint32_t HMAC_DMACNT; /*!< [0x0350] SHA/HMAC Byte Count Register */ 1659 __IO uint32_t HMAC_DATIN; /*!< [0x0354] SHA/HMAC Engine Non-DMA Mode Data Input Port Register */ 1660 __I uint32_t RESERVE6[298]; 1661 __IO uint32_t ECC_CTL; /*!< [0x0800] ECC Control Register */ 1662 __I uint32_t ECC_STS; /*!< [0x0804] ECC Status Register */ 1663 __IO uint32_t ECC_X1[18]; /*!< [0x0808] ~ [0x084c] ECC The X-coordinate word 0~17 of the first point */ 1664 __IO uint32_t ECC_Y1[18]; /*!< [0x0850] ~ [0x0894] ECC The Y-coordinate word 0~17 of the first point */ 1665 __IO uint32_t ECC_X2[18]; /*!< [0x0898] ~ [0x08dc] ECC The X-coordinate word 0~17 of the second point */ 1666 __IO uint32_t ECC_Y2[18]; /*!< [0x08e0] ~ [0x0924] ECC The Y-coordinate word 0~17 of the second point */ 1667 __IO uint32_t ECC_A[18]; /*!< [0x0928] ~ [0x096c] ECC The parameter CURVEA word 0~17 of elliptic curve */ 1668 __IO uint32_t ECC_B[18]; /*!< [0x0970] ~ [0x09b4] ECC The parameter CURVEB word 0~17 of elliptic curve */ 1669 __IO uint32_t ECC_N[18]; /*!< [0x09b8] ~ [0x09fc] ECC The parameter CURVEN word 0~17 of elliptic curve */ 1670 __O uint32_t ECC_K[18]; /*!< [0x0a00] ~ [0x0a44] ECC The scalar SCALARK word 0~17 of point multiplication */ 1671 __IO uint32_t ECC_SADDR; /*!< [0x0a48] ECC DMA Source Address Register */ 1672 __IO uint32_t ECC_DADDR; /*!< [0x0a4c] ECC DMA Destination Address Register */ 1673 __IO uint32_t ECC_STARTREG; /*!< [0x0a50] ECC Starting Address of Updated Registers */ 1674 __IO uint32_t ECC_WORDCNT; /*!< [0x0a54] ECC DMA Word Count */ 1675 1676 } CRPT_T; 1677 1678 /** 1679 @addtogroup CRPT_CONST CRPT Bit Field Definition 1680 Constant Definitions for CRPT Controller 1681 @{ */ 1682 1683 #define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT_T::INTEN: AESIEN Position */ 1684 #define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT_T::INTEN: AESIEN Mask */ 1685 1686 #define CRPT_INTEN_AESEIEN_Pos (1) /*!< CRPT_T::INTEN: AESEIEN Position */ 1687 #define CRPT_INTEN_AESEIEN_Msk (0x1ul << CRPT_INTEN_AESEIEN_Pos) /*!< CRPT_T::INTEN: AESEIEN Mask */ 1688 1689 #define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT_T::INTEN: TDESIEN Position */ 1690 #define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT_T::INTEN: TDESIEN Mask */ 1691 1692 #define CRPT_INTEN_TDESEIEN_Pos (9) /*!< CRPT_T::INTEN: TDESEIEN Position */ 1693 #define CRPT_INTEN_TDESEIEN_Msk (0x1ul << CRPT_INTEN_TDESEIEN_Pos) /*!< CRPT_T::INTEN: TDESEIEN Mask */ 1694 1695 #define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT_T::INTEN: PRNGIEN Position */ 1696 #define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT_T::INTEN: PRNGIEN Mask */ 1697 1698 #define CRPT_INTEN_ECCIEN_Pos (22) /*!< CRPT_T::INTEN: ECCIEN Position */ 1699 #define CRPT_INTEN_ECCIEN_Msk (0x1ul << CRPT_INTEN_ECCIEN_Pos) /*!< CRPT_T::INTEN: ECCIEN Mask */ 1700 1701 #define CRPT_INTEN_ECCEIEN_Pos (23) /*!< CRPT_T::INTEN: ECCEIEN Position */ 1702 #define CRPT_INTEN_ECCEIEN_Msk (0x1ul << CRPT_INTEN_ECCEIEN_Pos) /*!< CRPT_T::INTEN: ECCEIEN Mask */ 1703 1704 #define CRPT_INTEN_HMACIEN_Pos (24) /*!< CRPT_T::INTEN: HMACIEN Position */ 1705 #define CRPT_INTEN_HMACIEN_Msk (0x1ul << CRPT_INTEN_HMACIEN_Pos) /*!< CRPT_T::INTEN: HMACIEN Mask */ 1706 1707 #define CRPT_INTEN_HMACEIEN_Pos (25) /*!< CRPT_T::INTEN: HMACEIEN Position */ 1708 #define CRPT_INTEN_HMACEIEN_Msk (0x1ul << CRPT_INTEN_HMACEIEN_Pos) /*!< CRPT_T::INTEN: HMACEIEN Mask */ 1709 1710 #define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT_T::INTSTS: AESIF Position */ 1711 #define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT_T::INTSTS: AESIF Mask */ 1712 1713 #define CRPT_INTSTS_AESEIF_Pos (1) /*!< CRPT_T::INTSTS: AESEIF Position */ 1714 #define CRPT_INTSTS_AESEIF_Msk (0x1ul << CRPT_INTSTS_AESEIF_Pos) /*!< CRPT_T::INTSTS: AESEIF Mask */ 1715 1716 #define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT_T::INTSTS: TDESIF Position */ 1717 #define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT_T::INTSTS: TDESIF Mask */ 1718 1719 #define CRPT_INTSTS_TDESEIF_Pos (9) /*!< CRPT_T::INTSTS: TDESEIF Position */ 1720 #define CRPT_INTSTS_TDESEIF_Msk (0x1ul << CRPT_INTSTS_TDESEIF_Pos) /*!< CRPT_T::INTSTS: TDESEIF Mask */ 1721 1722 #define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT_T::INTSTS: PRNGIF Position */ 1723 #define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT_T::INTSTS: PRNGIF Mask */ 1724 1725 #define CRPT_INTSTS_ECCIF_Pos (22) /*!< CRPT_T::INTSTS: ECCIF Position */ 1726 #define CRPT_INTSTS_ECCIF_Msk (0x1ul << CRPT_INTSTS_ECCIF_Pos) /*!< CRPT_T::INTSTS: ECCIF Mask */ 1727 1728 #define CRPT_INTSTS_ECCEIF_Pos (23) /*!< CRPT_T::INTSTS: ECCEIF Position */ 1729 #define CRPT_INTSTS_ECCEIF_Msk (0x1ul << CRPT_INTSTS_ECCEIF_Pos) /*!< CRPT_T::INTSTS: ECCEIF Mask */ 1730 1731 #define CRPT_INTSTS_HMACIF_Pos (24) /*!< CRPT_T::INTSTS: HMACIF Position */ 1732 #define CRPT_INTSTS_HMACIF_Msk (0x1ul << CRPT_INTSTS_HMACIF_Pos) /*!< CRPT_T::INTSTS: HMACIF Mask */ 1733 1734 #define CRPT_INTSTS_HMACEIF_Pos (25) /*!< CRPT_T::INTSTS: HMACEIF Position */ 1735 #define CRPT_INTSTS_HMACEIF_Msk (0x1ul << CRPT_INTSTS_HMACEIF_Pos) /*!< CRPT_T::INTSTS: HMACEIF Mask */ 1736 1737 #define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT_T::PRNG_CTL: START Position */ 1738 #define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT_T::PRNG_CTL: START Mask */ 1739 1740 #define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT_T::PRNG_CTL: SEEDRLD Position */ 1741 #define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT_T::PRNG_CTL: SEEDRLD Mask */ 1742 1743 #define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT_T::PRNG_CTL: KEYSZ Position */ 1744 #define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT_T::PRNG_CTL: KEYSZ Mask */ 1745 1746 #define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT_T::PRNG_CTL: BUSY Position */ 1747 #define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT_T::PRNG_CTL: BUSY Mask */ 1748 1749 #define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT_T::PRNG_SEED: SEED Position */ 1750 #define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT_T::PRNG_SEED: SEED Mask */ 1751 1752 #define CRPT_PRNG_KEYx_KEY_Pos (0) /*!< CRPT_T::PRNG_KEY[8]: KEY Position */ 1753 #define CRPT_PRNG_KEYx_KEY_Msk (0xfffffffful << CRPT_PRNG_KEYx_KEY_Pos) /*!< CRPT_T::PRNG_KEY[8]: KEY Mask */ 1754 1755 #define CRPT_AES_FDBCKx_FDBCK_Pos (0) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Position */ 1756 #define CRPT_AES_FDBCKx_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCKx_FDBCK_Pos) /*!< CRPT_T::AES_FDBCK[4]: FDBCK Mask */ 1757 1758 #define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKH: FDBCK Position */ 1759 #define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKH: FDBCK Mask */ 1760 1761 #define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT_T::TDES_FDBCKL: FDBCK Position */ 1762 #define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT_T::TDES_FDBCKL: FDBCK Mask */ 1763 1764 #define CRPT_AES_CTL_START_Pos (0) /*!< CRPT_T::AES_CTL: START Position */ 1765 #define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT_T::AES_CTL: START Mask */ 1766 1767 #define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT_T::AES_CTL: STOP Position */ 1768 #define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT_T::AES_CTL: STOP Mask */ 1769 1770 #define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT_T::AES_CTL: KEYSZ Position */ 1771 #define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT_T::AES_CTL: KEYSZ Mask */ 1772 1773 #define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT_T::AES_CTL: DMALAST Position */ 1774 #define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT_T::AES_CTL: DMALAST Mask */ 1775 1776 #define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::AES_CTL: DMACSCAD Position */ 1777 #define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT_T::AES_CTL: DMACSCAD Mask */ 1778 1779 #define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT_T::AES_CTL: DMAEN Position */ 1780 #define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT_T::AES_CTL: DMAEN Mask */ 1781 1782 #define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT_T::AES_CTL: OPMODE Position */ 1783 #define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT_T::AES_CTL: OPMODE Mask */ 1784 1785 #define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::AES_CTL: ENCRPT Position */ 1786 #define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT_T::AES_CTL: ENCRPT Mask */ 1787 1788 #define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::AES_CTL: OUTSWAP Position */ 1789 #define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT_T::AES_CTL: OUTSWAP Mask */ 1790 1791 #define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT_T::AES_CTL: INSWAP Position */ 1792 #define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT_T::AES_CTL: INSWAP Mask */ 1793 1794 #define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::AES_CTL: CHANNEL Position */ 1795 #define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT_T::AES_CTL: CHANNEL Mask */ 1796 1797 #define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::AES_CTL: KEYUNPRT Position */ 1798 #define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::AES_CTL: KEYUNPRT Mask */ 1799 1800 #define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::AES_CTL: KEYPRT Position */ 1801 #define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT_T::AES_CTL: KEYPRT Mask */ 1802 1803 #define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT_T::AES_STS: BUSY Position */ 1804 #define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT_T::AES_STS: BUSY Mask */ 1805 1806 #define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::AES_STS: INBUFEMPTY Position */ 1807 #define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: INBUFEMPTY Mask */ 1808 1809 #define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::AES_STS: INBUFFULL Position */ 1810 #define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT_T::AES_STS: INBUFFULL Mask */ 1811 1812 #define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT_T::AES_STS: INBUFERR Position */ 1813 #define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT_T::AES_STS: INBUFERR Mask */ 1814 1815 #define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT_T::AES_STS: CNTERR Position */ 1816 #define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT_T::AES_STS: CNTERR Mask */ 1817 1818 #define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Position */ 1819 #define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::AES_STS: OUTBUFEMPTY Mask */ 1820 1821 #define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::AES_STS: OUTBUFFULL Position */ 1822 #define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::AES_STS: OUTBUFFULL Mask */ 1823 1824 #define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::AES_STS: OUTBUFERR Position */ 1825 #define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT_T::AES_STS: OUTBUFERR Mask */ 1826 1827 #define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT_T::AES_STS: BUSERR Position */ 1828 #define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT_T::AES_STS: BUSERR Mask */ 1829 1830 #define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT_T::AES_DATIN: DATIN Position */ 1831 #define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT_T::AES_DATIN: DATIN Mask */ 1832 1833 #define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::AES_DATOUT: DATOUT Position */ 1834 #define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT_T::AES_DATOUT: DATOUT Mask */ 1835 1836 #define CRPT_AES0_KEYx_KEY_Pos (0) /*!< CRPT_T::AES0_KEY[8]: KEY Position */ 1837 #define CRPT_AES0_KEYx_KEY_Msk (0xfffffffful << CRPT_AES0_KEYx_KEY_Pos) /*!< CRPT_T::AES0_KEY[8]: KEY Mask */ 1838 1839 #define CRPT_AES0_IVx_IV_Pos (0) /*!< CRPT_T::AES0_IV[4]: IV Position */ 1840 #define CRPT_AES0_IVx_IV_Msk (0xfffffffful << CRPT_AES0_IVx_IV_Pos) /*!< CRPT_T::AES0_IV[4]: IV Mask */ 1841 1842 #define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES0_SADDR: SADDR Position */ 1843 #define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT_T::AES0_SADDR: SADDR Mask */ 1844 1845 #define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES0_DADDR: DADDR Position */ 1846 #define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT_T::AES0_DADDR: DADDR Mask */ 1847 1848 #define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT_T::AES0_CNT: CNT Position */ 1849 #define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT_T::AES0_CNT: CNT Mask */ 1850 1851 #define CRPT_AES1_KEYx_KEY_Pos (0) /*!< CRPT_T::AES1_KEY[8]: KEY Position */ 1852 #define CRPT_AES1_KEYx_KEY_Msk (0xfffffffful << CRPT_AES1_KEYx_KEY_Pos) /*!< CRPT_T::AES1_KEY[8]: KEY Mask */ 1853 1854 #define CRPT_AES1_IVx_IV_Pos (0) /*!< CRPT_T::AES1_IV[4]: IV Position */ 1855 #define CRPT_AES1_IVx_IV_Msk (0xfffffffful << CRPT_AES1_IVx_IV_Pos) /*!< CRPT_T::AES1_IV[4]: IV Mask */ 1856 1857 #define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES1_SADDR: SADDR Position */ 1858 #define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT_T::AES1_SADDR: SADDR Mask */ 1859 1860 #define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES1_DADDR: DADDR Position */ 1861 #define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT_T::AES1_DADDR: DADDR Mask */ 1862 1863 #define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT_T::AES1_CNT: CNT Position */ 1864 #define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT_T::AES1_CNT: CNT Mask */ 1865 1866 #define CRPT_AES2_KEYx_KEY_Pos (0) /*!< CRPT_T::AES2_KEYx: KEY Position */ 1867 #define CRPT_AES2_KEYx_KEY_Msk (0xfffffffful << CRPT_AES2_KEYx_KEY_Pos) /*!< CRPT_T::AES2_KEYx: KEY Mask */ 1868 1869 #define CRPT_AES2_IVx_IV_Pos (0) /*!< CRPT_T::AES2_IVx: IV Position */ 1870 #define CRPT_AES2_IVx_IV_Msk (0xfffffffful << CRPT_AES2_IVx_IV_Pos) /*!< CRPT_T::AES2_IVx: IV Mask */ 1871 1872 #define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES2_SADDR: SADDR Position */ 1873 #define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT_T::AES2_SADDR: SADDR Mask */ 1874 1875 #define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES2_DADDR: DADDR Position */ 1876 #define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT_T::AES2_DADDR: DADDR Mask */ 1877 1878 #define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT_T::AES2_CNT: CNT Position */ 1879 #define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT_T::AES2_CNT: CNT Mask */ 1880 1881 #define CRPT_AES3_KEYx_KEY_Pos (0) /*!< CRPT_T::AES3_KEY[8]: KEY Position */ 1882 #define CRPT_AES3_KEYx_KEY_Msk (0xfffffffful << CRPT_AES3_KEYx_KEY_Pos) /*!< CRPT_T::AES3_KEY[8]: KEY Mask */ 1883 1884 #define CRPT_AES3_IVx_IV_Pos (0) /*!< CRPT_T::AES3_IV[4]: IV Position */ 1885 #define CRPT_AES3_IVx_IV_Msk (0xfffffffful << CRPT_AES3_IVx_IV_Pos) /*!< CRPT_T::AES3_IV[4]: IV Mask */ 1886 1887 #define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::AES3_SADDR: SADDR Position */ 1888 #define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT_T::AES3_SADDR: SADDR Mask */ 1889 1890 #define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::AES3_DADDR: DADDR Position */ 1891 #define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT_T::AES3_DADDR: DADDR Mask */ 1892 1893 #define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT_T::AES3_CNT: CNT Position */ 1894 #define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT_T::AES3_CNT: CNT Mask */ 1895 1896 #define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT_T::TDES_CTL: START Position */ 1897 #define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT_T::TDES_CTL: START Mask */ 1898 1899 #define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT_T::TDES_CTL: STOP Position */ 1900 #define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT_T::TDES_CTL: STOP Mask */ 1901 1902 #define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT_T::TDES_CTL: TMODE Position */ 1903 #define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT_T::TDES_CTL: TMODE Mask */ 1904 1905 #define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT_T::TDES_CTL: 3KEYS Position */ 1906 #define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT_T::TDES_CTL: 3KEYS Mask */ 1907 1908 #define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT_T::TDES_CTL: DMALAST Position */ 1909 #define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT_T::TDES_CTL: DMALAST Mask */ 1910 1911 #define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT_T::TDES_CTL: DMACSCAD Position */ 1912 #define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT_T::TDES_CTL: DMACSCAD Mask */ 1913 1914 #define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT_T::TDES_CTL: DMAEN Position */ 1915 #define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT_T::TDES_CTL: DMAEN Mask */ 1916 1917 #define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT_T::TDES_CTL: OPMODE Position */ 1918 #define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT_T::TDES_CTL: OPMODE Mask */ 1919 1920 #define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT_T::TDES_CTL: ENCRPT Position */ 1921 #define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT_T::TDES_CTL: ENCRPT Mask */ 1922 1923 #define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT_T::TDES_CTL: BLKSWAP Position */ 1924 #define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT_T::TDES_CTL: BLKSWAP Mask */ 1925 1926 #define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::TDES_CTL: OUTSWAP Position */ 1927 #define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT_T::TDES_CTL: OUTSWAP Mask */ 1928 1929 #define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT_T::TDES_CTL: INSWAP Position */ 1930 #define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT_T::TDES_CTL: INSWAP Mask */ 1931 1932 #define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT_T::TDES_CTL: CHANNEL Position */ 1933 #define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT_T::TDES_CTL: CHANNEL Mask */ 1934 1935 #define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT_T::TDES_CTL: KEYUNPRT Position */ 1936 #define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYUNPRT Mask */ 1937 1938 #define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT_T::TDES_CTL: KEYPRT Position */ 1939 #define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT_T::TDES_CTL: KEYPRT Mask */ 1940 1941 #define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT_T::TDES_STS: BUSY Position */ 1942 #define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT_T::TDES_STS: BUSY Mask */ 1943 1944 #define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT_T::TDES_STS: INBUFEMPTY Position */ 1945 #define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: INBUFEMPTY Mask */ 1946 1947 #define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT_T::TDES_STS: INBUFFULL Position */ 1948 #define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT_T::TDES_STS: INBUFFULL Mask */ 1949 1950 #define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT_T::TDES_STS: INBUFERR Position */ 1951 #define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT_T::TDES_STS: INBUFERR Mask */ 1952 1953 #define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Position */ 1954 #define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT_T::TDES_STS: OUTBUFEMPTY Mask */ 1955 1956 #define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT_T::TDES_STS: OUTBUFFULL Position */ 1957 #define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT_T::TDES_STS: OUTBUFFULL Mask */ 1958 1959 #define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT_T::TDES_STS: OUTBUFERR Position */ 1960 #define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT_T::TDES_STS: OUTBUFERR Mask */ 1961 1962 #define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT_T::TDES_STS: BUSERR Position */ 1963 #define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT_T::TDES_STS: BUSERR Mask */ 1964 1965 #define CRPT_TDES0_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxH: KEY Position */ 1966 #define CRPT_TDES0_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxH_KEY_Pos) /*!< CRPT_T::TDES0_KEYxH: KEY Mask */ 1967 1968 #define CRPT_TDES0_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES0_KEYxL: KEY Position */ 1969 #define CRPT_TDES0_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES0_KEYxL_KEY_Pos) /*!< CRPT_T::TDES0_KEYxL: KEY Mask */ 1970 1971 #define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT_T::TDES0_IVH: IV Position */ 1972 #define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT_T::TDES0_IVH: IV Mask */ 1973 1974 #define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT_T::TDES0_IVL: IV Position */ 1975 #define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT_T::TDES0_IVL: IV Mask */ 1976 1977 #define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES0_SADDR: SADDR Position */ 1978 #define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT_T::TDES0_SADDR: SADDR Mask */ 1979 1980 #define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES0_DADDR: DADDR Position */ 1981 #define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT_T::TDES0_DADDR: DADDR Mask */ 1982 1983 #define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT_T::TDES0_CNT: CNT Position */ 1984 #define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT_T::TDES0_CNT: CNT Mask */ 1985 1986 #define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT_T::TDES_DATIN: DATIN Position */ 1987 #define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT_T::TDES_DATIN: DATIN Mask */ 1988 1989 #define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT_T::TDES_DATOUT: DATOUT Position */ 1990 #define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT_T::TDES_DATOUT: DATOUT Mask */ 1991 1992 #define CRPT_TDES1_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxH: KEY Position */ 1993 #define CRPT_TDES1_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES1_KEYxH_KEY_Pos) /*!< CRPT_T::TDES1_KEYxH: KEY Mask */ 1994 1995 #define CRPT_TDES1_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES1_KEYxL: KEY Position */ 1996 #define CRPT_TDES1_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT_T::TDES1_KEYxL: KEY Mask */ 1997 1998 #define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT_T::TDES1_IVH: IV Position */ 1999 #define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT_T::TDES1_IVH: IV Mask */ 2000 2001 #define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT_T::TDES1_IVL: IV Position */ 2002 #define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT_T::TDES1_IVL: IV Mask */ 2003 2004 #define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES1_SADDR: SADDR Position */ 2005 #define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT_T::TDES1_SADDR: SADDR Mask */ 2006 2007 #define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES1_DADDR: DADDR Position */ 2008 #define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT_T::TDES1_DADDR: DADDR Mask */ 2009 2010 #define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT_T::TDES1_CNT: CNT Position */ 2011 #define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT_T::TDES1_CNT: CNT Mask */ 2012 2013 #define CRPT_TDES2_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxH: KEY Position */ 2014 #define CRPT_TDES2_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxH_KEY_Pos) /*!< CRPT_T::TDES2_KEYxH: KEY Mask */ 2015 2016 #define CRPT_TDES2_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES2_KEYxL: KEY Position */ 2017 #define CRPT_TDES2_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES2_KEYxL_KEY_Pos) /*!< CRPT_T::TDES2_KEYxL: KEY Mask */ 2018 2019 #define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT_T::TDES2_IVH: IV Position */ 2020 #define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT_T::TDES2_IVH: IV Mask */ 2021 2022 #define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT_T::TDES2_IVL: IV Position */ 2023 #define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT_T::TDES2_IVL: IV Mask */ 2024 2025 #define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES2_SADDR: SADDR Position */ 2026 #define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT_T::TDES2_SADDR: SADDR Mask */ 2027 2028 #define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES2_DADDR: DADDR Position */ 2029 #define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT_T::TDES2_DADDR: DADDR Mask */ 2030 2031 #define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT_T::TDES2_CNT: CNT Position */ 2032 #define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT_T::TDES2_CNT: CNT Mask */ 2033 2034 #define CRPT_TDES3_KEYxH_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxH: KEY Position */ 2035 #define CRPT_TDES3_KEYxH_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxH_KEY_Pos) /*!< CRPT_T::TDES3_KEYxH: KEY Mask */ 2036 2037 #define CRPT_TDES3_KEYxL_KEY_Pos (0) /*!< CRPT_T::TDES3_KEYxL: KEY Position */ 2038 #define CRPT_TDES3_KEYxL_KEY_Msk (0xfffffffful << CRPT_TDES3_KEYxL_KEY_Pos) /*!< CRPT_T::TDES3_KEYxL: KEY Mask */ 2039 2040 #define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT_T::TDES3_IVH: IV Position */ 2041 #define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT_T::TDES3_IVH: IV Mask */ 2042 2043 #define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT_T::TDES3_IVL: IV Position */ 2044 #define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT_T::TDES3_IVL: IV Mask */ 2045 2046 #define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT_T::TDES3_SADDR: SADDR Position */ 2047 #define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT_T::TDES3_SADDR: SADDR Mask */ 2048 2049 #define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT_T::TDES3_DADDR: DADDR Position */ 2050 #define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT_T::TDES3_DADDR: DADDR Mask */ 2051 2052 #define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT_T::TDES3_CNT: CNT Position */ 2053 #define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT_T::TDES3_CNT: CNT Mask */ 2054 2055 #define CRPT_HMAC_CTL_START_Pos (0) /*!< CRPT_T::HMAC_CTL: START Position */ 2056 #define CRPT_HMAC_CTL_START_Msk (0x1ul << CRPT_HMAC_CTL_START_Pos) /*!< CRPT_T::HMAC_CTL: START Mask */ 2057 2058 #define CRPT_HMAC_CTL_STOP_Pos (1) /*!< CRPT_T::HMAC_CTL: STOP Position */ 2059 #define CRPT_HMAC_CTL_STOP_Msk (0x1ul << CRPT_HMAC_CTL_STOP_Pos) /*!< CRPT_T::HMAC_CTL: STOP Mask */ 2060 2061 #define CRPT_HMAC_CTL_DMALAST_Pos (5) /*!< CRPT_T::HMAC_CTL: DMALAST Position */ 2062 #define CRPT_HMAC_CTL_DMALAST_Msk (0x1ul << CRPT_HMAC_CTL_DMALAST_Pos) /*!< CRPT_T::HMAC_CTL: DMALAST Mask */ 2063 2064 #define CRPT_HMAC_CTL_DMAEN_Pos (7) /*!< CRPT_T::HMAC_CTL: DMAEN Position */ 2065 #define CRPT_HMAC_CTL_DMAEN_Msk (0x1ul << CRPT_HMAC_CTL_DMAEN_Pos) /*!< CRPT_T::HMAC_CTL: DMAEN Mask */ 2066 2067 #define CRPT_HMAC_CTL_OPMODE_Pos (8) /*!< CRPT_T::HMAC_CTL: OPMODE Position */ 2068 #define CRPT_HMAC_CTL_OPMODE_Msk (0x7ul << CRPT_HMAC_CTL_OPMODE_Pos) /*!< CRPT_T::HMAC_CTL: OPMODE Mask */ 2069 2070 #define CRPT_HMAC_CTL_OUTSWAP_Pos (22) /*!< CRPT_T::HMAC_CTL: OUTSWAP Position */ 2071 #define CRPT_HMAC_CTL_OUTSWAP_Msk (0x1ul << CRPT_HMAC_CTL_OUTSWAP_Pos) /*!< CRPT_T::HMAC_CTL: OUTSWAP Mask */ 2072 2073 #define CRPT_HMAC_CTL_INSWAP_Pos (23) /*!< CRPT_T::HMAC_CTL: INSWAP Position */ 2074 #define CRPT_HMAC_CTL_INSWAP_Msk (0x1ul << CRPT_HMAC_CTL_INSWAP_Pos) /*!< CRPT_T::HMAC_CTL: INSWAP Mask */ 2075 2076 #define CRPT_HMAC_STS_BUSY_Pos (0) /*!< CRPT_T::HMAC_STS: BUSY Position */ 2077 #define CRPT_HMAC_STS_BUSY_Msk (0x1ul << CRPT_HMAC_STS_BUSY_Pos) /*!< CRPT_T::HMAC_STS: BUSY Mask */ 2078 2079 #define CRPT_HMAC_STS_DMABUSY_Pos (1) /*!< CRPT_T::HMAC_STS: DMABUSY Position */ 2080 #define CRPT_HMAC_STS_DMABUSY_Msk (0x1ul << CRPT_HMAC_STS_DMABUSY_Pos) /*!< CRPT_T::HMAC_STS: DMABUSY Mask */ 2081 2082 #define CRPT_HMAC_STS_DMAERR_Pos (8) /*!< CRPT_T::HMAC_STS: DMAERR Position */ 2083 #define CRPT_HMAC_STS_DMAERR_Msk (0x1ul << CRPT_HMAC_STS_DMAERR_Pos) /*!< CRPT_T::HMAC_STS: DMAERR Mask */ 2084 2085 #define CRPT_HMAC_STS_DATINREQ_Pos (16) /*!< CRPT_T::HMAC_STS: DATINREQ Position */ 2086 #define CRPT_HMAC_STS_DATINREQ_Msk (0x1ul << CRPT_HMAC_STS_DATINREQ_Pos) /*!< CRPT_T::HMAC_STS: DATINREQ Mask */ 2087 2088 #define CRPT_HMAC_DGSTx_DGST_Pos (0) /*!< CRPT_T::HMAC_DGSTx: DGST Position */ 2089 #define CRPT_HMAC_DGSTx_DGST_Msk (0xfffffffful << CRPT_HMAC_DGSTx_DGST_Pos) /*!< CRPT_T::HMAC_DGSTx: DGST Mask */ 2090 2091 #define CRPT_HMAC_KEYCNT_KEYCNT_Pos (0) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Position */ 2092 #define CRPT_HMAC_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_HMAC_KEYCNT_KEYCNT_Pos) /*!< CRPT_T::HMAC_KEYCNT: KEYCNT Mask */ 2093 2094 #define CRPT_HMAC_SADDR_SADDR_Pos (0) /*!< CRPT_T::HMAC_SADDR: SADDR Position */ 2095 #define CRPT_HMAC_SADDR_SADDR_Msk (0xfffffffful << CRPT_HMAC_SADDR_SADDR_Pos) /*!< CRPT_T::HMAC_SADDR: SADDR Mask */ 2096 2097 #define CRPT_HMAC_DMACNT_DMACNT_Pos (0) /*!< CRPT_T::HMAC_DMACNT: DMACNT Position */ 2098 #define CRPT_HMAC_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_HMAC_DMACNT_DMACNT_Pos) /*!< CRPT_T::HMAC_DMACNT: DMACNT Mask */ 2099 2100 #define CRPT_HMAC_DATIN_DATIN_Pos (0) /*!< CRPT_T::HMAC_DATIN: DATIN Position */ 2101 #define CRPT_HMAC_DATIN_DATIN_Msk (0xfffffffful << CRPT_HMAC_DATIN_DATIN_Pos) /*!< CRPT_T::HMAC_DATIN: DATIN Mask */ 2102 2103 #define CRPT_ECC_CTL_START_Pos (0) /*!< CRPT_T::ECC_CTL: START Position */ 2104 #define CRPT_ECC_CTL_START_Msk (0x1ul << CRPT_ECC_CTL_START_Pos) /*!< CRPT_T::ECC_CTL: START Mask */ 2105 2106 #define CRPT_ECC_CTL_STOP_Pos (1) /*!< CRPT_T::ECC_CTL: STOP Position */ 2107 #define CRPT_ECC_CTL_STOP_Msk (0x1ul << CRPT_ECC_CTL_STOP_Pos) /*!< CRPT_T::ECC_CTL: STOP Mask */ 2108 2109 #define CRPT_ECC_CTL_DMAEN_Pos (7) /*!< CRPT_T::ECC_CTL: DMAEN Position */ 2110 #define CRPT_ECC_CTL_DMAEN_Msk (0x1ul << CRPT_ECC_CTL_DMAEN_Pos) /*!< CRPT_T::ECC_CTL: DMAEN Mask */ 2111 2112 #define CRPT_ECC_CTL_FSEL_Pos (8) /*!< CRPT_T::ECC_CTL: FSEL Position */ 2113 #define CRPT_ECC_CTL_FSEL_Msk (0x1ul << CRPT_ECC_CTL_FSEL_Pos) /*!< CRPT_T::ECC_CTL: FSEL Mask */ 2114 2115 #define CRPT_ECC_CTL_ECCOP_Pos (9) /*!< CRPT_T::ECC_CTL: ECCOP Position */ 2116 #define CRPT_ECC_CTL_ECCOP_Msk (0x3ul << CRPT_ECC_CTL_ECCOP_Pos) /*!< CRPT_T::ECC_CTL: ECCOP Mask */ 2117 2118 #define CRPT_ECC_CTL_MODOP_Pos (11) /*!< CRPT_T::ECC_CTL: MODOP Position */ 2119 #define CRPT_ECC_CTL_MODOP_Msk (0x3ul << CRPT_ECC_CTL_MODOP_Pos) /*!< CRPT_T::ECC_CTL: MODOP Mask */ 2120 2121 #define CRPT_ECC_CTL_LDP1_Pos (16) /*!< CRPT_T::ECC_CTL: LDP1 Position */ 2122 #define CRPT_ECC_CTL_LDP1_Msk (0x1ul << CRPT_ECC_CTL_LDP1_Pos) /*!< CRPT_T::ECC_CTL: LDP1 Mask */ 2123 2124 #define CRPT_ECC_CTL_LDP2_Pos (17) /*!< CRPT_T::ECC_CTL: LDP2 Position */ 2125 #define CRPT_ECC_CTL_LDP2_Msk (0x1ul << CRPT_ECC_CTL_LDP2_Pos) /*!< CRPT_T::ECC_CTL: LDP2 Mask */ 2126 2127 #define CRPT_ECC_CTL_LDA_Pos (18) /*!< CRPT_T::ECC_CTL: LDA Position */ 2128 #define CRPT_ECC_CTL_LDA_Msk (0x1ul << CRPT_ECC_CTL_LDA_Pos) /*!< CRPT_T::ECC_CTL: LDA Mask */ 2129 2130 #define CRPT_ECC_CTL_LDB_Pos (19) /*!< CRPT_T::ECC_CTL: LDB Position */ 2131 #define CRPT_ECC_CTL_LDB_Msk (0x1ul << CRPT_ECC_CTL_LDB_Pos) /*!< CRPT_T::ECC_CTL: LDB Mask */ 2132 2133 #define CRPT_ECC_CTL_LDN_Pos (20) /*!< CRPT_T::ECC_CTL: LDN Position */ 2134 #define CRPT_ECC_CTL_LDN_Msk (0x1ul << CRPT_ECC_CTL_LDN_Pos) /*!< CRPT_T::ECC_CTL: LDN Mask */ 2135 2136 #define CRPT_ECC_CTL_LDK_Pos (21) /*!< CRPT_T::ECC_CTL: LDK Position */ 2137 #define CRPT_ECC_CTL_LDK_Msk (0x1ul << CRPT_ECC_CTL_LDK_Pos) /*!< CRPT_T::ECC_CTL: LDK Mask */ 2138 2139 #define CRPT_ECC_CTL_CURVEM_Pos (22) /*!< CRPT_T::ECC_CTL: CURVEM Position */ 2140 #define CRPT_ECC_CTL_CURVEM_Msk (0x3fful << CRPT_ECC_CTL_CURVEM_Pos) /*!< CRPT_T::ECC_CTL: CURVEM Mask */ 2141 2142 #define CRPT_ECC_STS_BUSY_Pos (0) /*!< CRPT_T::ECC_STS: BUSY Position */ 2143 #define CRPT_ECC_STS_BUSY_Msk (0x1ul << CRPT_ECC_STS_BUSY_Pos) /*!< CRPT_T::ECC_STS: BUSY Mask */ 2144 2145 #define CRPT_ECC_STS_DMABUSY_Pos (1) /*!< CRPT_T::ECC_STS: DMABUSY Position */ 2146 #define CRPT_ECC_STS_DMABUSY_Msk (0x1ul << CRPT_ECC_STS_DMABUSY_Pos) /*!< CRPT_T::ECC_STS: DMABUSY Mask */ 2147 2148 #define CRPT_ECC_STS_BUSERR_Pos (16) /*!< CRPT_T::ECC_STS: BUSERR Position */ 2149 #define CRPT_ECC_STS_BUSERR_Msk (0x1ul << CRPT_ECC_STS_BUSERR_Pos) /*!< CRPT_T::ECC_STS: BUSERR Mask */ 2150 2151 #define CRPT_ECC_X1_POINTX1_Pos (0) /*!< CRPT_T::ECC_X1: POINTX1 Position */ 2152 #define CRPT_ECC_X1_POINTX1_Msk (0xfffffffful << CRPT_ECC_X1_POINTX1_Pos) /*!< CRPT_T::ECC_X1: POINTX1 Mask */ 2153 2154 #define CRPT_ECC_Y1_POINTY1_Pos (0) /*!< CRPT_T::ECC_Y1: POINTY1 Position */ 2155 #define CRPT_ECC_Y1_POINTY1_Msk (0xfffffffful << CRPT_ECC_Y1_POINTY1_Pos) /*!< CRPT_T::ECC_Y1: POINTY1 Mask */ 2156 2157 #define CRPT_ECC_X2_POINTX2_Pos (0) /*!< CRPT_T::ECC_X2: POINTX2 Position */ 2158 #define CRPT_ECC_X2_POINTX2_Msk (0xfffffffful << CRPT_ECC_X2_POINTX2_Pos) /*!< CRPT_T::ECC_X2: POINTX2 Mask */ 2159 2160 #define CRPT_ECC_Y2_POINTY2_Pos (0) /*!< CRPT_T::ECC_Y2: POINTY2 Position */ 2161 #define CRPT_ECC_Y2_POINTY2_Msk (0xfffffffful << CRPT_ECC_Y2_POINTY2_Pos) /*!< CRPT_T::ECC_Y2: POINTY2 Mask */ 2162 2163 #define CRPT_ECC_A_CURVEA_Pos (0) /*!< CRPT_T::ECC_A: CURVEA Position */ 2164 #define CRPT_ECC_A_CURVEA_Msk (0xfffffffful << CRPT_ECC_A_CURVEA_Pos) /*!< CRPT_T::ECC_A: CURVEA Mask */ 2165 2166 #define CRPT_ECC_B_CURVEB_Pos (0) /*!< CRPT_T::ECC_B: CURVEB Position */ 2167 #define CRPT_ECC_B_CURVEB_Msk (0xfffffffful << CRPT_ECC_B_CURVEB_Pos) /*!< CRPT_T::ECC_B: CURVEB Mask */ 2168 2169 #define CRPT_ECC_N_CURVEN_Pos (0) /*!< CRPT_T::ECC_N: CURVEN Position */ 2170 #define CRPT_ECC_N_CURVEN_Msk (0xfffffffful << CRPT_ECC_N_CURVEN_Pos) /*!< CRPT_T::ECC_N: CURVEN Mask */ 2171 2172 #define CRPT_ECC_K_SCALARK_Pos (0) /*!< CRPT_T::ECC_K: SCALARK Position */ 2173 #define CRPT_ECC_K_SCALARK_Msk (0xfffffffful << CRPT_ECC_K_SCALARK_Pos) /*!< CRPT_T::ECC_K: SCALARK Mask */ 2174 2175 #define CRPT_ECC_DADDR_DADDR_Pos (0) /*!< CRPT_T::ECC_DADDR: DADDR Position */ 2176 #define CRPT_ECC_DADDR_DADDR_Msk (0xfffffffful << CRPT_ECC_DADDR_DADDR_Pos) /*!< CRPT_T::ECC_DADDR: DADDR Mask */ 2177 2178 #define CRPT_ECC_STARTREG_STARTREG_Pos (0) /*!< CRPT_T::ECC_STARTREG: STARTREG Position*/ 2179 #define CRPT_ECC_STARTREG_STARTREG_Msk (0xfffffffful << CRPT_ECC_STARTREG_STARTREG_Pos) /*!< CRPT_T::ECC_STARTREG: STARTREG Mask */ 2180 2181 #define CRPT_ECC_WORDCNT_WORDCNT_Pos (0) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Position */ 2182 #define CRPT_ECC_WORDCNT_WORDCNT_Msk (0xfffffffful << CRPT_ECC_WORDCNT_WORDCNT_Pos) /*!< CRPT_T::ECC_WORDCNT: WORDCNT Mask */ 2183 2184 /**@}*/ /* CRPT_CONST */ 2185 /**@}*/ /* end of CRPT register group */ 2186 /**@}*/ /* end of REGISTER group */ 2187 2188 2189 #endif /* __CRPT_REG_H__ */ 2190
