1 /**************************************************************************//** 2 * @file can_reg.h 3 * @version V1.00 4 * @brief CAN register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CAN_REG_H__ 10 #define __CAN_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 19 /*---------------------- Controller Area Network Controller -------------------------*/ 20 /** 21 @addtogroup CAN Controller Area Network Controller(CAN) 22 Memory Mapped Structure for CAN Controller 23 @{ 24 */ 25 26 27 typedef struct 28 { 29 30 31 32 /** 33 * @var CAN_IF_T::CREQ 34 * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers 35 * --------------------------------------------------------------------------------------------------- 36 * |Bits |Field |Descriptions 37 * | :----: | :----: | :---- | 38 * |[5:0] |MessageNumber|Message Number 39 * | | |0x01-0x20: Valid Message Number, the Message Object in the Message 40 * | | |RAM is selected for data transfer. 41 * | | |0x00: Not a valid Message Number, interpreted as 0x20. 42 * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F. 43 * |[15] |Busy |Busy Flag 44 * | | |0 = Read/write action has finished. 45 * | | |1 = Writing to the IFn Command Request Register is in progress. 46 * | | |This bit can only be read by the software. 47 * @var CAN_IF_T::CMASK 48 * Offset: 0x24, 0x84 IFn Command Mask Register 49 * --------------------------------------------------------------------------------------------------- 50 * |Bits |Field |Descriptions 51 * | :----: | :----: | :---- | 52 * |[0] |DAT_B |Access Data Bytes [7:4] 53 * | | |Write Operation: 54 * | | |0 = Data Bytes [7:4] unchanged. 55 * | | |1 = Transfer Data Bytes [7:4] to Message Object. 56 * | | |Read Operation: 57 * | | |0 = Data Bytes [7:4] unchanged. 58 * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register. 59 * |[1] |DAT_A |Access Data Bytes [3:0] 60 * | | |Write Operation: 61 * | | |0 = Data Bytes [3:0] unchanged. 62 * | | |1 = Transfer Data Bytes [3:0] to Message Object. 63 * | | |Read Operation: 64 * | | |0 = Data Bytes [3:0] unchanged. 65 * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register. 66 * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation 67 * | | |0 = TxRqst bit unchanged. 68 * | | |1 = Set TxRqst bit. 69 * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored. 70 * | | |Access New Data Bit when Read Operation. 71 * | | |0 = NewDat bit remains unchanged. 72 * | | |1 = Clear NewDat bit in the Message Object. 73 * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. 74 * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits. 75 * |[3] |ClrIntPnd |Clear Interrupt Pending Bit 76 * | | |Write Operation: 77 * | | |When writing to a Message Object, this bit is ignored. 78 * | | |Read Operation: 79 * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged. 80 * | | |1 = Clear IntPnd bit in the Message Object. 81 * |[4] |Control |Control Access Control Bits 82 * | | |Write Operation: 83 * | | |0 = Control Bits unchanged. 84 * | | |1 = Transfer Control Bits to Message Object. 85 * | | |Read Operation: 86 * | | |0 = Control Bits unchanged. 87 * | | |1 = Transfer Control Bits to IFn Message Buffer Register. 88 * |[5] |Arb |Access Arbitration Bits 89 * | | |Write Operation: 90 * | | |0 = Arbitration bits unchanged. 91 * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object. 92 * | | |Read Operation: 93 * | | |0 = Arbitration bits unchanged. 94 * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register. 95 * |[6] |Mask |Access Mask Bits 96 * | | |Write Operation: 97 * | | |0 = Mask bits unchanged. 98 * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object. 99 * | | |Read Operation: 100 * | | |0 = Mask bits unchanged. 101 * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register. 102 * |[7] |WR_RD |Write / Read Mode 103 * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers. 104 * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register. 105 * @var CAN_IF_T::MASK1 106 * Offset: 0x28, 0x88 IFn Mask 1 Register 107 * --------------------------------------------------------------------------------------------------- 108 * |Bits |Field |Descriptions 109 * | :----: | :----: | :---- | 110 * |[15:0] |Msk[15:0] |Identifier Mask 15-0 111 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. 112 * | | |1 = The corresponding identifier bit is used for acceptance filtering. 113 * @var CAN_IF_T::MASK2 114 * Offset: 0x2C, 0x8C IFn Mask 2 Register 115 * --------------------------------------------------------------------------------------------------- 116 * |Bits |Field |Descriptions 117 * | :----: | :----: | :---- | 118 * |[12:0] |Msk[28:16]|Identifier Mask 28-16 119 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering. 120 * | | |1 = The corresponding identifier bit is used for acceptance filtering. 121 * |[14] |MDir |Mask Message Direction 122 * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering. 123 * | | |1 = The message direction bit (Dir) is used for acceptance filtering. 124 * |[15] |MXtd |Mask Extended Identifier 125 * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering. 126 * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering. 127 * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]). 128 * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered. 129 * @var CAN_IF_T::ARB1 130 * Offset: 0x30, 0x90 IFn Arbitration 1 Register 131 * --------------------------------------------------------------------------------------------------- 132 * |Bits |Field |Descriptions 133 * | :----: | :----: | :---- | 134 * |[15:0] |ID[15:0] |Message Identifier 15-0 135 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame"). 136 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame") 137 * @var CAN_IF_T::ARB2 138 * Offset: 0x34, 0x94 IFn Arbitration 2 Register 139 * --------------------------------------------------------------------------------------------------- 140 * |Bits |Field |Descriptions 141 * | :----: | :----: | :---- | 142 * |[12:0] |ID[28:16] |Message Identifier 28-16 143 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame"). 144 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame") 145 * |[13] |Dir |Message Direction 146 * | | |0 = Direction is receive. 147 * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted. 148 * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object. 149 * | | |1 = Direction is transmit. 150 * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame. 151 * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one). 152 * |[14] |Xtd |Extended Identifier 153 * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object. 154 * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object. 155 * |[15] |MsgVal |Message Valid 156 * | | |0 = The Message Object is ignored by the Message Handler. 157 * | | |1 = The Message Object is configured and should be considered by the Message Handler. 158 * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]). 159 * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required. 160 * @var CAN_IF_T::MCON 161 * Offset: 0x38, 0x98 IFn Message Control Register 162 * --------------------------------------------------------------------------------------------------- 163 * |Bits |Field |Descriptions 164 * | :----: | :----: | :---- | 165 * |[3:0] |DLC |Data Length Code 166 * | | |0-8: Data Frame has 0-8 data bytes. 167 * | | |9-15: Data Frame has 8 data bytes 168 * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. 169 * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message. 170 * | | |Data 0: 1st data byte of a CAN Data Frame 171 * | | |Data 1: 2nd data byte of a CAN Data Frame 172 * | | |Data 2: 3rd data byte of a CAN Data Frame 173 * | | |Data 3: 4th data byte of a CAN Data Frame 174 * | | |Data 4: 5th data byte of a CAN Data Frame 175 * | | |Data 5: 6th data byte of a CAN Data Frame 176 * | | |Data 6: 7th data byte of a CAN Data Frame 177 * | | |Data 7 : 8th data byte of a CAN Data Frame 178 * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last. 179 * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object. 180 * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values. 181 * |[7] |EoB |End Of Buffer 182 * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer. 183 * | | |1 = Single Message Object or last Message Object of a FIFO Buffer. 184 * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer. 185 * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one. 186 * |[8] |TxRqst |Transmit Request 187 * | | |0 = This Message Object is not waiting for transmission. 188 * | | |1 = The transmission of this Message Object is requested and is not yet done. 189 * |[9] |RmtEn |Remote Enable Control 190 * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged. 191 * | | |1 = At the reception of a Remote Frame, TxRqst is set. 192 * |[10] |RxIE |Receive Interrupt Enable Control 193 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame. 194 * | | |1 = IntPnd will be set after a successful reception of a frame. 195 * |[11] |TxIE |Transmit Interrupt Enable Control 196 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame. 197 * | | |1 = IntPnd will be set after a successful transmission of a frame. 198 * |[12] |UMask |Use Acceptance Mask 199 * | | |0 = Mask ignored. 200 * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering. 201 * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one. 202 * |[13] |IntPnd |Interrupt Pending 203 * | | |0 = This message object is not the source of an interrupt. 204 * | | |1 = This message object is the source of an interrupt. 205 * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority. 206 * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive). 207 * | | |0 = No message lost since last time this bit was reset by the CPU. 208 * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message. 209 * |[15] |NewDat |New Data 210 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software. 211 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. 212 * @var CAN_IF_T::DAT_A1 213 * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) 214 * --------------------------------------------------------------------------------------------------- 215 * |Bits |Field |Descriptions 216 * | :----: | :----: | :---- | 217 * |[7:0] |Data0 |Data Byte 0 218 * | | |1st data byte of a CAN Data Frame 219 * |[15:8] |Data1 |Data Byte 1 220 * | | |2nd data byte of a CAN Data Frame 221 * @var CAN_IF_T::DAT_A2 222 * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) 223 * --------------------------------------------------------------------------------------------------- 224 * |Bits |Field |Descriptions 225 * | :----: | :----: | :---- | 226 * |[7:0] |Data2 |Data Byte 2 227 * | | |3rd data byte of CAN Data Frame 228 * |[15:8] |Data3 |Data Byte 3 229 * | | |4th data byte of CAN Data Frame 230 * @var CAN_IF_T::DAT_B1 231 * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) 232 * --------------------------------------------------------------------------------------------------- 233 * |Bits |Field |Descriptions 234 * | :----: | :----: | :---- | 235 * |[7:0] |Data4 |Data Byte 4 236 * | | |5th data byte of CAN Data Frame 237 * |[15:8] |Data5 |Data Byte 5 238 * | | |6th data byte of CAN Data Frame 239 * @var CAN_IF_T::DAT_B2 240 * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) 241 * --------------------------------------------------------------------------------------------------- 242 * |Bits |Field |Descriptions 243 * | :----: | :----: | :---- | 244 * |[7:0] |Data6 |Data Byte 6 245 * | | |7th data byte of CAN Data Frame. 246 * |[15:8] |Data7 |Data Byte 7 247 * | | |8th data byte of CAN Data Frame. 248 */ 249 250 __IO uint32_t CREQ; /* Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers */ 251 __IO uint32_t CMASK; /* Offset: 0x24, 0x84 IFn Command Mask Register */ 252 __IO uint32_t MASK1; /* Offset: 0x28, 0x88 IFn Mask 1 Register */ 253 __IO uint32_t MASK2; /* Offset: 0x2C, 0x8C IFn Mask 2 Register */ 254 __IO uint32_t ARB1; /* Offset: 0x30, 0x90 IFn Arbitration 1 Register */ 255 __IO uint32_t ARB2; /* Offset: 0x34, 0x94 IFn Arbitration 2 Register */ 256 __IO uint32_t MCON; /* Offset: 0x38, 0x98 IFn Message Control Register */ 257 __IO uint32_t DAT_A1; /* Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3) */ 258 __IO uint32_t DAT_A2; /* Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3) */ 259 __IO uint32_t DAT_B1; /* Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3) */ 260 __IO uint32_t DAT_B2; /* Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3) */ 261 __I uint32_t RESERVE0[13]; 262 263 } CAN_IF_T; 264 265 266 267 268 typedef struct 269 { 270 271 272 273 /** 274 * @var CAN_T::CON 275 * Offset: 0x00 Control Register 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[0] |Init |Init Initialization 280 * | | |0 = Normal Operation. 281 * | | |1 = Initialization is started. 282 * |[1] |IE |Module Interrupt Enable Control 283 * | | |0 = Disabled. 284 * | | |1 = Enabled. 285 * |[2] |SIE |Status Change Interrupt Enable Control 286 * | | |0 = Disabled - No Status Change Interrupt will be generated. 287 * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected. 288 * |[3] |EIE |Error Interrupt Enable Control 289 * | | |0 = Disabled - No Error Status Interrupt will be generated. 290 * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt. 291 * |[5] |DAR |Automatic Re-Transmission Disable Control 292 * | | |0 = Automatic Retransmission of disturbed messages enabled. 293 * | | |1 = Automatic Retransmission disabled. 294 * |[6] |CCE |Configuration Change Enable Control 295 * | | |0 = No write access to the Bit Timing Register. 296 * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1). 297 * |[7] |Test |Test Mode Enable Control 298 * | | |0 = Normal Operation. 299 * | | |1 = Test Mode. 300 * @var CAN_T::STATUS 301 * Offset: 0x04 Status Register 302 * --------------------------------------------------------------------------------------------------- 303 * |Bits |Field |Descriptions 304 * | :----: | :----: | :---- | 305 * |[2:0] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus) 306 * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus. 307 * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error. 308 * | | |The unused code '7' may be written by the CPU to check for updates. 309 * | | |The following table describes the error code. 310 * |[3] |TxOK |Transmitted A Message Successfully 311 * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted. 312 * | | |This bit is never reset by the CAN Core. 313 * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. 314 * |[4] |RxOK |Received A Message Successfully 315 * | | |0 = No message has been successfully received since this bit was last reset by the CPU. 316 * | | |This bit is never reset by the CAN Core. 317 * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering). 318 * |[5] |EPass |Error Passive (Read Only) 319 * | | |0 = The CAN Core is error active. 320 * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification. 321 * |[6] |EWarn |Error Warning Status (Read Only) 322 * | | |0 = Both error counters are below the error warning limit of 96. 323 * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96. 324 * |[7] |BOff |Bus-Off Status (Read Only) 325 * | | |0 = The CAN module is not in bus-off state. 326 * | | |1 = The CAN module is in bus-off state. 327 * @var CAN_T::ERR 328 * Offset: 0x08 Error Counter Register 329 * --------------------------------------------------------------------------------------------------- 330 * |Bits |Field |Descriptions 331 * | :----: | :----: | :---- | 332 * |[7:0] |TEC |Transmit Error Counter 333 * | | |Actual state of the Transmit Error Counter. Values between 0 and 255. 334 * |[14:8] |REC |Receive Error Counter 335 * | | |Actual state of the Receive Error Counter. Values between 0 and 127. 336 * |[15] |RP |Receive Error Passive 337 * | | |0 = The Receive Error Counter is below the error passive level. 338 * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification. 339 * @var CAN_T::BTIME 340 * Offset: 0x0C Bit Timing Register 341 * --------------------------------------------------------------------------------------------------- 342 * |Bits |Field |Descriptions 343 * | :----: | :----: | :---- | 344 * |[5:0] |BRP |Baud Rate Prescaler 345 * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta. 346 * | | |The bit time is built up from a multiple of this quanta. 347 * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ]. 348 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 349 * |[7:6] |SJW |(Re)Synchronization Jump Width 350 * | | |0x0-0x3: Valid programmed values are [0 ... 3]. 351 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 352 * |[11:8] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg 353 * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15]. 354 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used. 355 * |[14:12] |TSeg2 |Time Segment After Sample Point 356 * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7]. 357 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used. 358 * @var CAN_T::IIDR 359 * Offset: 0x10 Interrupt Identifier Register 360 * --------------------------------------------------------------------------------------------------- 361 * |Bits |Field |Descriptions 362 * | :----: | :----: | :---- | 363 * |[15:0] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt) 364 * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order. 365 * | | |An interrupt remains pending until the application software has cleared it. 366 * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active. 367 * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset. 368 * | | |The Status Interrupt has the highest priority. 369 * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number. 370 * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]). 371 * | | |The Status Interrupt is cleared by reading the Status Register. 372 * @var CAN_T::TEST 373 * Offset: 0x14 Test Register (Register Map Note 1) 374 * --------------------------------------------------------------------------------------------------- 375 * |Bits |Field |Descriptions 376 * | :----: | :----: | :---- | 377 * |[1:0] |Res |Reserved 378 * | | |There are reserved bits. 379 * | | |These bits are always read as '0' and must always be written with '0'. 380 * |[2] |Basic |Basic Mode 381 * | | |0 = Basic Mode disabled. 382 * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. 383 * |[3] |Silent |Silent Mode 384 * | | |0 = Normal operation. 385 * | | |1 = The module is in Silent Mode. 386 * |[4] |LBack |Loop Back Mode Enable Control 387 * | | |0 = Loop Back Mode is disabled. 388 * | | |1 = Loop Back Mode is enabled. 389 * |[6:5] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin 390 * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core. 391 * | | |01 = Sample Point can be monitored at CAN_TX pin. 392 * | | |10 = CAN_TX pin drives a dominant ('0') value. 393 * | | |11 = CAN_TX pin drives a recessive ('1') value. 394 * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only) 395 * | | |0 = The CAN bus is dominant (CAN_RX = '0'). 396 * | | |1 = The CAN bus is recessive (CAN_RX = '1'). 397 * @var CAN_T::BRPE 398 * Offset: 0x18 Baud Rate Prescaler Extension Register 399 * --------------------------------------------------------------------------------------------------- 400 * |Bits |Field |Descriptions 401 * | :----: | :----: | :---- | 402 * |[3:0] |BRPE |BRPE: Baud Rate Prescaler Extension 403 * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023. 404 * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used. 405 * @var CAN_T::IF 406 * Offset: 0x20~0xFC CAN Interface Registers 407 * --------------------------------------------------------------------------------------------------- 408 * CAN interface structure. Refer to \ref CAN_IF_T for detail information. 409 * 410 * @var CAN_T::TXREQ1 411 * Offset: 0x100 Transmission Request Register 1 412 * --------------------------------------------------------------------------------------------------- 413 * |Bits |Field |Descriptions 414 * | :----: | :----: | :---- | 415 * |[15:0] |TxRqst[16:1]|Transmission Request Bits 16-1 (Of All Message Objects) 416 * | | |0 = This Message Object is not waiting for transmission. 417 * | | |1 = The transmission of this Message Object is requested and is not yet done. 418 * | | |These bits are read only. 419 * @var CAN_T::TXREQ2 420 * Offset: 0x104 Transmission Request Register 2 421 * --------------------------------------------------------------------------------------------------- 422 * |Bits |Field |Descriptions 423 * | :----: | :----: | :---- | 424 * |[15:0] |TxRqst[32:17]|Transmission Request Bits 32-17 (Of All Message Objects) 425 * | | |0 = This Message Object is not waiting for transmission. 426 * | | |1 = The transmission of this Message Object is requested and is not yet done. 427 * | | |These bits are read only. 428 * @var CAN_T::NDAT1 429 * Offset: 0x120 New Data Register 1 430 * --------------------------------------------------------------------------------------------------- 431 * |Bits |Field |Descriptions 432 * | :----: | :----: | :---- | 433 * |[15:0] |NewData[16:1]|New Data Bits 16-1 (Of All Message Objects) 434 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. 435 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. 436 * @var CAN_T::NDAT2 437 * Offset: 0x124 New Data Register 2 438 * --------------------------------------------------------------------------------------------------- 439 * |Bits |Field |Descriptions 440 * | :----: | :----: | :---- | 441 * |[15:0] |NewData[32:17]|New Data Bits 32-17 (Of All Message Objects) 442 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software. 443 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object. 444 * @var CAN_T::IPND1 445 * Offset: 0x140 Interrupt Pending Register 1 446 * --------------------------------------------------------------------------------------------------- 447 * |Bits |Field |Descriptions 448 * | :----: | :----: | :---- | 449 * |[15:0] |IntPnd[16:1]|Interrupt Pending Bits 16-1 (Of All Message Objects) 450 * | | |0 = This message object is not the source of an interrupt. 451 * | | |1 = This message object is the source of an interrupt. 452 * @var CAN_T::IPND2 453 * Offset: 0x144 Interrupt Pending Register 2 454 * --------------------------------------------------------------------------------------------------- 455 * |Bits |Field |Descriptions 456 * | :----: | :----: | :---- | 457 * |[15:0] |IntPnd[32:17]|Interrupt Pending Bits 32-17(Of All Message Objects) 458 * | | |0 = This message object is not the source of an interrupt. 459 * | | |1 = This message object is the source of an interrupt. 460 * @var CAN_T::MVLD1 461 * Offset: 0x160 Message Valid Register 1 462 * --------------------------------------------------------------------------------------------------- 463 * |Bits |Field |Descriptions 464 * | :----: | :----: | :---- | 465 * |[15:0] |MsgVal[16:1]|Message Valid Bits 16-1 (Of All Message Objects) (Read Only) 466 * | | |0 = This Message Object is ignored by the Message Handler. 467 * | | |1 = This Message Object is configured and should be considered by the Message Handler. 468 * | | |Ex. 469 * | | |CAN_MVLD1[0] means Message object No.1 is valid or not. 470 * | | |If CAN_MVLD1[0] is set, message object No.1 is configured. 471 * @var CAN_T::MVLD2 472 * Offset: 0x164 Message Valid Register 2 473 * --------------------------------------------------------------------------------------------------- 474 * |Bits |Field |Descriptions 475 * | :----: | :----: | :---- | 476 * |[15:0] |MsgVal[32:17]|Message Valid Bits 32-17 (Of All Message Objects) (Read Only) 477 * | | |0 = This Message Object is ignored by the Message Handler. 478 * | | |1 = This Message Object is configured and should be considered by the Message Handler. 479 * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not. 480 * | | |If CAN_MVLD2[15] is set, message object No.32 is configured. 481 * @var CAN_T::WU_EN 482 * Offset: 0x168 Wake-up Enable Register 483 * --------------------------------------------------------------------------------------------------- 484 * |Bits |Field |Descriptions 485 * | :----: | :----: | :---- | 486 * |[0] |WAKUP_EN |Wake-Up Enable Control 487 * | | |0 = The wake-up function Disabled. 488 * | | |1 = The wake-up function Enabled. 489 * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin. 490 * @var CAN_T::WU_STATUS 491 * Offset: 0x16C Wake-up Status Register 492 * --------------------------------------------------------------------------------------------------- 493 * |Bits |Field |Descriptions 494 * | :----: | :----: | :---- | 495 * |[0] |WAKUP_STS |Wake-Up Status 496 * | | |0 = No wake-up event occurred. 497 * | | |1 = Wake-up event occurred. 498 * | | |Note: This bit can be cleared by writing '0'. 499 */ 500 501 __IO uint32_t CON; /* Offset: 0x00 Control Register */ 502 __IO uint32_t STATUS; /* Offset: 0x04 Status Register */ 503 __I uint32_t ERR; /* Offset: 0x08 Error Counter Register */ 504 __IO uint32_t BTIME; /* Offset: 0x0C Bit Timing Register */ 505 __I uint32_t IIDR; /* Offset: 0x10 Interrupt Identifier Register */ 506 __IO uint32_t TEST; /* Offset: 0x14 Test Register (Register Map Note 1) */ 507 __IO uint32_t BRPE; /* Offset: 0x18 Baud Rate Prescaler Extension Register */ 508 __I uint32_t RESERVE0[1]; 509 __IO CAN_IF_T IF[2]; /* Offset: 0x20~0xFC CAN Interface Registers */ 510 __I uint32_t RESERVE1[8]; 511 __I uint32_t TXREQ1; /* Offset: 0x100 Transmission Request Register 1 */ 512 __I uint32_t TXREQ2; /* Offset: 0x104 Transmission Request Register 2 */ 513 __I uint32_t RESERVE3[6]; 514 __I uint32_t NDAT1; /* Offset: 0x120 New Data Register 1 */ 515 __I uint32_t NDAT2; /* Offset: 0x124 New Data Register 2 */ 516 __I uint32_t RESERVE4[6]; 517 __I uint32_t IPND1; /* Offset: 0x140 Interrupt Pending Register 1 */ 518 __I uint32_t IPND2; /* Offset: 0x144 Interrupt Pending Register 2 */ 519 __I uint32_t RESERVE5[6]; 520 __I uint32_t MVLD1; /* Offset: 0x160 Message Valid Register 1 */ 521 __I uint32_t MVLD2; /* Offset: 0x164 Message Valid Register 2 */ 522 __IO uint32_t WU_EN; /* Offset: 0x168 Wake-up Enable Register */ 523 __IO uint32_t WU_STATUS; /* Offset: 0x16C Wake-up Status Register */ 524 525 } CAN_T; 526 527 528 529 /** 530 @addtogroup CAN_CONST CAN Bit Field Definition 531 Constant Definitions for CAN Controller 532 @{ 533 */ 534 /* CAN CON Bit Field Definitions */ 535 #define CAN_CON_TEST_Pos 7 /*!< CAN_T::CON: TEST Position */ 536 #define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) /*!< CAN_T::CON: TEST Mask */ 537 538 #define CAN_CON_CCE_Pos 6 /*!< CAN_T::CON: CCE Position */ 539 #define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) /*!< CAN_T::CON: CCE Mask */ 540 541 #define CAN_CON_DAR_Pos 5 /*!< CAN_T::CON: DAR Position */ 542 #define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) /*!< CAN_T::CON: DAR Mask */ 543 544 #define CAN_CON_EIE_Pos 3 /*!< CAN_T::CON: EIE Position */ 545 #define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) /*!< CAN_T::CON: EIE Mask */ 546 547 #define CAN_CON_SIE_Pos 2 /*!< CAN_T::CON: SIE Position */ 548 #define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) /*!< CAN_T::CON: SIE Mask */ 549 550 #define CAN_CON_IE_Pos 1 /*!< CAN_T::CON: IE Position */ 551 #define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) /*!< CAN_T::CON: IE Mask */ 552 553 #define CAN_CON_INIT_Pos 0 /*!< CAN_T::CON: INIT Position */ 554 #define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) /*!< CAN_T::CON: INIT Mask */ 555 556 /* CAN STATUS Bit Field Definitions */ 557 #define CAN_STATUS_BOFF_Pos 7 /*!< CAN_T::STATUS: BOFF Position */ 558 #define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) /*!< CAN_T::STATUS: BOFF Mask */ 559 560 #define CAN_STATUS_EWARN_Pos 6 /*!< CAN_T::STATUS: EWARN Position */ 561 #define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) /*!< CAN_T::STATUS: EWARN Mask */ 562 563 #define CAN_STATUS_EPASS_Pos 5 /*!< CAN_T::STATUS: EPASS Position */ 564 #define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) /*!< CAN_T::STATUS: EPASS Mask */ 565 566 #define CAN_STATUS_RXOK_Pos 4 /*!< CAN_T::STATUS: RXOK Position */ 567 #define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) /*!< CAN_T::STATUS: RXOK Mask */ 568 569 #define CAN_STATUS_TXOK_Pos 3 /*!< CAN_T::STATUS: TXOK Position */ 570 #define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) /*!< CAN_T::STATUS: TXOK Mask */ 571 572 #define CAN_STATUS_LEC_Pos 0 /*!< CAN_T::STATUS: LEC Position */ 573 #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) /*!< CAN_T::STATUS: LEC Mask */ 574 575 /* CAN ERR Bit Field Definitions */ 576 #define CAN_ERR_RP_Pos 15 /*!< CAN_T::ERR: RP Position */ 577 #define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) /*!< CAN_T::ERR: RP Mask */ 578 579 #define CAN_ERR_REC_Pos 8 /*!< CAN_T::ERR: REC Position */ 580 #define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN_T::ERR: REC Mask */ 581 582 #define CAN_ERR_TEC_Pos 0 /*!< CAN_T::ERR: TEC Position */ 583 #define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN_T::ERR: TEC Mask */ 584 585 /* CAN BTIME Bit Field Definitions */ 586 #define CAN_BTIME_TSEG2_Pos 12 /*!< CAN_T::BTIME: TSEG2 Position */ 587 #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN_T::BTIME: TSEG2 Mask */ 588 589 #define CAN_BTIME_TSEG1_Pos 8 /*!< CAN_T::BTIME: TSEG1 Position */ 590 #define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN_T::BTIME: TSEG1 Mask */ 591 592 #define CAN_BTIME_SJW_Pos 6 /*!< CAN_T::BTIME: SJW Position */ 593 #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN_T::BTIME: SJW Mask */ 594 595 #define CAN_BTIME_BRP_Pos 0 /*!< CAN_T::BTIME: BRP Position */ 596 #define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN_T::BTIME: BRP Mask */ 597 598 /* CAN IIDR Bit Field Definitions */ 599 #define CAN_IIDR_INTID_Pos 0 /*!< CAN_T::IIDR: INTID Position */ 600 #define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN_T::IIDR: INTID Mask */ 601 602 /* CAN TEST Bit Field Definitions */ 603 #define CAN_TEST_RX_Pos 7 /*!< CAN_T::TEST: RX Position */ 604 #define CAN_TEST_RX_Msk (0x1ul << CAN_TEST_RX_Pos) /*!< CAN_T::TEST: RX Mask */ 605 606 #define CAN_TEST_TX_Pos 5 /*!< CAN_T::TEST: TX Position */ 607 #define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN_T::TEST: TX Mask */ 608 609 #define CAN_TEST_LBACK_Pos 4 /*!< CAN_T::TEST: LBACK Position */ 610 #define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) /*!< CAN_T::TEST: LBACK Mask */ 611 612 #define CAN_TEST_SILENT_Pos 3 /*!< CAN_T::TEST: Silent Position */ 613 #define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) /*!< CAN_T::TEST: Silent Mask */ 614 615 #define CAN_TEST_BASIC_Pos 2 /*!< CAN_T::TEST: Basic Position */ 616 #define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) /*!< CAN_T::TEST: Basic Mask */ 617 618 /* CAN BPRE Bit Field Definitions */ 619 #define CAN_BRPE_BRPE_Pos 0 /*!< CAN_T::BRPE: BRPE Position */ 620 #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN_T::BRPE: BRPE Mask */ 621 622 /* CAN IFn_CREQ Bit Field Definitions */ 623 #define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN_IF_T::CREQ: BUSY Position */ 624 #define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN_IF_T::CREQ: BUSY Mask */ 625 626 #define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN_IF_T::CREQ: MSGNUM Position */ 627 #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN_IF_T::CREQ: MSGNUM Mask */ 628 629 /* CAN IFn_CMASK Bit Field Definitions */ 630 #define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN_IF_T::CMASK: WRRD Position */ 631 #define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN_IF_T::CMASK: WRRD Mask */ 632 633 #define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN_IF_T::CMASK: MASK Position */ 634 #define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN_IF_T::CMASK: MASK Mask */ 635 636 #define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN_IF_T::CMASK: ARB Position */ 637 #define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN_IF_T::CMASK: ARB Mask */ 638 639 #define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN_IF_T::CMASK: CONTROL Position */ 640 #define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN_IF_T::CMASK: CONTROL Mask */ 641 642 #define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN_IF_T::CMASK: CLRINTPND Position */ 643 #define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN_IF_T::CMASK: CLRINTPND Mask */ 644 645 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Position */ 646 #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN_IF_T::CMASK: TXRQSTNEWDAT Mask */ 647 648 #define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN_IF_T::CMASK: DATAA Position */ 649 #define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN_IF_T::CMASK: DATAA Mask */ 650 651 #define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN_IF_T::CMASK: DATAB Position */ 652 #define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN_IF_T::CMASK: DATAB Mask */ 653 654 /* CAN IFn_MASK1 Bit Field Definitions */ 655 #define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN_IF_T::MASK1: MSK Position */ 656 #define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN_IF_T::MASK1: MSK Mask */ 657 658 /* CAN IFn_MASK2 Bit Field Definitions */ 659 #define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN_IF_T::MASK2: MXTD Position */ 660 #define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN_IF_T::MASK2: MXTD Mask */ 661 662 #define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN_IF_T::MASK2: MDIR Position */ 663 #define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN_IF_T::MASK2: MDIR Mask */ 664 665 #define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN_IF_T::MASK2: MSK Position */ 666 #define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN_IF_T::MASK2: MSK Mask */ 667 668 /* CAN IFn_ARB1 Bit Field Definitions */ 669 #define CAN_IF_ARB1_ID_Pos 0 /*!< CAN_IF_T::ARB1: ID Position */ 670 #define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN_IF_T::ARB1: ID Mask */ 671 672 /* CAN IFn_ARB2 Bit Field Definitions */ 673 #define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN_IF_T::ARB2: MSGVAL Position */ 674 #define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN_IF_T::ARB2: MSGVAL Mask */ 675 676 #define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN_IF_T::ARB2: XTD Position */ 677 #define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN_IF_T::ARB2: XTD Mask */ 678 679 #define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN_IF_T::ARB2: DIR Position */ 680 #define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN_IF_T::ARB2: DIR Mask */ 681 682 #define CAN_IF_ARB2_ID_Pos 0 /*!< CAN_IF_T::ARB2: ID Position */ 683 #define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN_IF_T::ARB2: ID Mask */ 684 685 /* CAN IFn_MCON Bit Field Definitions */ 686 #define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN_IF_T::MCON: NEWDAT Position */ 687 #define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN_IF_T::MCON: NEWDAT Mask */ 688 689 #define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN_IF_T::MCON: MSGLST Position */ 690 #define CAN_IF_MCON_MSGLST_Msk (0x1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN_IF_T::MCON: MSGLST Mask */ 691 692 #define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN_IF_T::MCON: INTPND Position */ 693 #define CAN_IF_MCON_INTPND_Msk (0x1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN_IF_T::MCON: INTPND Mask */ 694 695 #define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN_IF_T::MCON: UMASK Position */ 696 #define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN_IF_T::MCON: UMASK Mask */ 697 698 #define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN_IF_T::MCON: TXIE Position */ 699 #define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN_IF_T::MCON: TXIE Mask */ 700 701 #define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN_IF_T::MCON: RXIE Position */ 702 #define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN_IF_T::MCON: RXIE Mask */ 703 704 #define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN_IF_T::MCON: RMTEN Position */ 705 #define CAN_IF_MCON_RMTEN_Msk (0x1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN_IF_T::MCON: RMTEN Mask */ 706 707 #define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN_IF_T::MCON: TXRQST Position */ 708 #define CAN_IF_MCON_TXRQST_Msk (0x1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN_IF_T::MCON: TXRQST Mask */ 709 710 #define CAN_IF_MCON_EOB_Pos 7 /*!< CAN_IF_T::MCON: EOB Position */ 711 #define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN_IF_T::MCON: EOB Mask */ 712 713 #define CAN_IF_MCON_DLC_Pos 0 /*!< CAN_IF_T::MCON: DLC Position */ 714 #define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN_IF_T::MCON: DLC Mask */ 715 716 /* CAN IFn_DATA_A1 Bit Field Definitions */ 717 #define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN_IF_T::DATAA1: DATA1 Position */ 718 #define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN_IF_T::DATAA1: DATA1 Mask */ 719 720 #define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN_IF_T::DATAA1: DATA0 Position */ 721 #define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN_IF_T::DATAA1: DATA0 Mask */ 722 723 /* CAN IFn_DATA_A2 Bit Field Definitions */ 724 #define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN_IF_T::DATAA1: DATA3 Position */ 725 #define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN_IF_T::DATAA1: DATA3 Mask */ 726 727 #define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN_IF_T::DATAA1: DATA2 Position */ 728 #define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN_IF_T::DATAA1: DATA2 Mask */ 729 730 /* CAN IFn_DATA_B1 Bit Field Definitions */ 731 #define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN_IF_T::DATAB1: DATA5 Position */ 732 #define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN_IF_T::DATAB1: DATA5 Mask */ 733 734 #define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN_IF_T::DATAB1: DATA4 Position */ 735 #define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN_IF_T::DATAB1: DATA4 Mask */ 736 737 /* CAN IFn_DATA_B2 Bit Field Definitions */ 738 #define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN_IF_T::DATAB2: DATA7 Position */ 739 #define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN_IF_T::DATAB2: DATA7 Mask */ 740 741 #define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN_IF_T::DATAB2: DATA6 Position */ 742 #define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN_IF_T::DATAB2: DATA6 Mask */ 743 744 /* CAN IFn_TXRQST1 Bit Field Definitions */ 745 #define CAN_TXRQST1_TXRQST_Pos 0 /*!< CAN_T::TXRQST1: TXRQST Position */ 746 #define CAN_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_TXRQST1_TXRQST_Pos) /*!< CAN_T::TXRQST1: TXRQST Mask */ 747 748 /* CAN IFn_TXRQST2 Bit Field Definitions */ 749 #define CAN_TXRQST2_TXRQST_Pos 0 /*!< CAN_T::TXRQST2: TXRQST Position */ 750 #define CAN_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_TXRQST2_TXRQST_Pos) /*!< CAN_T::TXRQST2: TXRQST Mask */ 751 752 /* CAN IFn_NDAT1 Bit Field Definitions */ 753 #define CAN_NDAT1_NEWDATA_Pos 0 /*!< CAN_T::NDAT1: NEWDATA Position */ 754 #define CAN_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_NDAT1_NEWDATA_Pos) /*!< CAN_T::NDAT1: NEWDATA Mask */ 755 756 /* CAN IFn_NDAT2 Bit Field Definitions */ 757 #define CAN_NDAT2_NEWDATA_Pos 0 /*!< CAN_T::NDAT2: NEWDATA Position */ 758 #define CAN_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_NDAT2_NEWDATA_Pos) /*!< CAN_T::NDAT2: NEWDATA Mask */ 759 760 /* CAN IFn_IPND1 Bit Field Definitions */ 761 #define CAN_IPND1_INTPND_Pos 0 /*!< CAN_T::IPND1: INTPND Position */ 762 #define CAN_IPND1_INTPND_Msk (0xFFFFul << CAN_IPND1_INTPND_Pos) /*!< CAN_T::IPND1: INTPND Mask */ 763 764 /* CAN IFn_IPND2 Bit Field Definitions */ 765 #define CAN_IPND2_INTPND_Pos 0 /*!< CAN_T::IPND2: INTPND Position */ 766 #define CAN_IPND2_INTPND_Msk (0xFFFFul << CAN_IPND2_INTPND_Pos) /*!< CAN_T::IPND2: INTPND Mask */ 767 768 /* CAN IFn_MVLD1 Bit Field Definitions */ 769 #define CAN_MVLD1_MSGVAL_Pos 0 /*!< CAN_T::MVLD1: MSGVAL Position */ 770 #define CAN_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_MVLD1_MSGVAL_Pos) /*!< CAN_T::MVLD1: MSGVAL Mask */ 771 772 /* CAN IFn_MVLD2 Bit Field Definitions */ 773 #define CAN_MVLD2_MSGVAL_Pos 0 /*!< CAN_T::MVLD2: MSGVAL Position */ 774 #define CAN_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_MVLD2_MSGVAL_Pos) /*!< CAN_T::MVLD2: MSGVAL Mask */ 775 776 /* CAN WUEN Bit Field Definitions */ 777 #define CAN_WU_EN_WAKUP_EN_Pos 0 /*!< CAN_T::WU_EN: WAKUP_EN Position */ 778 #define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) /*!< CAN_T::WU_EN: WAKUP_EN Mask */ 779 780 /* CAN WUSTATUS Bit Field Definitions */ 781 #define CAN_WU_STATUS_WAKUP_STS_Pos 0 /*!< CAN_T::WU_STATUS: WAKUP_STS Position */ 782 #define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) /*!< CAN_T::WU_STATUS: WAKUP_STS Mask */ 783 784 785 /**@}*/ /* CAN_CONST */ 786 /**@}*/ /* end of CAN register group */ 787 /**@}*/ /* end of REGISTER group */ 788 789 790 #endif /* __CAN_REG_H__ */ 791
