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Searched refs:uartlcr_h (Results 1 – 4 of 4) sorted by relevance

/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_s1/Native_Driver/
Duart_pl011_drv.c47 volatile uint32_t uartlcr_h; member
185 p_uart->uartlcr_h |= UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_enable_fifo()
190 p_uart->uartlcr_h &= ~UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_disable_fifo()
195 return (bool)(p_uart->uartlcr_h & UART_PL011_UARTLCR_H_FEN_MASK); in _uart_pl011_is_fifo_enabled()
230 p_uart->uartlcr_h = p_uart->uartlcr_h; in _uart_pl011_set_baudrate()
240 uint32_t ctrl_reg = p_uart->uartlcr_h & ~(UART_PL011_FORMAT_MASK); in _uart_pl011_set_format()
247 p_uart->uartlcr_h = ctrl_reg | word_len | parity | stop_bits; in _uart_pl011_set_format()
314 p_uart->uartlcr_h |= (mask); in _uart_pl011_set_lcr_h_bit()
331 p_uart->uartlcr_h &= ~(mask); in _uart_pl011_clear_lcr_h_bit()
352 p_uart->uartlcr_h = UART_PL011_LCR_H_REG_RESET_VALUE; in _uart_pl011_reset_regs()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/native_drivers/
Duart_pl011_drv.c47 volatile uint32_t uartlcr_h; member
185 p_uart->uartlcr_h |= UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_enable_fifo()
190 p_uart->uartlcr_h &= ~UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_disable_fifo()
195 return (bool)(p_uart->uartlcr_h & UART_PL011_UARTLCR_H_FEN_MASK); in _uart_pl011_is_fifo_enabled()
230 p_uart->uartlcr_h = p_uart->uartlcr_h; in _uart_pl011_set_baudrate()
240 uint32_t ctrl_reg = p_uart->uartlcr_h & ~(UART_PL011_FORMAT_MASK); in _uart_pl011_set_format()
247 p_uart->uartlcr_h = ctrl_reg | word_len | parity | stop_bits; in _uart_pl011_set_format()
314 p_uart->uartlcr_h |= (mask); in _uart_pl011_set_lcr_h_bit()
331 p_uart->uartlcr_h &= ~(mask); in _uart_pl011_clear_lcr_h_bit()
352 p_uart->uartlcr_h = UART_PL011_LCR_H_REG_RESET_VALUE; in _uart_pl011_reset_regs()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_b1/Native_Driver/
Duart_pl011_drv.c47 volatile uint32_t uartlcr_h; member
185 p_uart->uartlcr_h |= UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_enable_fifo()
190 p_uart->uartlcr_h &= ~UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_disable_fifo()
195 return (bool)(p_uart->uartlcr_h & UART_PL011_UARTLCR_H_FEN_MASK); in _uart_pl011_is_fifo_enabled()
230 p_uart->uartlcr_h = p_uart->uartlcr_h; in _uart_pl011_set_baudrate()
240 uint32_t ctrl_reg = p_uart->uartlcr_h & ~(UART_PL011_FORMAT_MASK); in _uart_pl011_set_format()
247 p_uart->uartlcr_h = ctrl_reg | word_len | parity | stop_bits; in _uart_pl011_set_format()
314 p_uart->uartlcr_h |= (mask); in _uart_pl011_set_lcr_h_bit()
331 p_uart->uartlcr_h &= ~(mask); in _uart_pl011_clear_lcr_h_bit()
352 p_uart->uartlcr_h = UART_PL011_LCR_H_REG_RESET_VALUE; in _uart_pl011_reset_regs()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/corstone1000/Native_Driver/
Duart_pl011_drv.c47 volatile uint32_t uartlcr_h; member
185 p_uart->uartlcr_h |= UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_enable_fifo()
190 p_uart->uartlcr_h &= ~UART_PL011_UARTLCR_H_FEN_MASK; in _uart_pl011_disable_fifo()
195 return (bool)(p_uart->uartlcr_h & UART_PL011_UARTLCR_H_FEN_MASK); in _uart_pl011_is_fifo_enabled()
230 p_uart->uartlcr_h = p_uart->uartlcr_h; in _uart_pl011_set_baudrate()
240 uint32_t ctrl_reg = p_uart->uartlcr_h & ~(UART_PL011_FORMAT_MASK); in _uart_pl011_set_format()
247 p_uart->uartlcr_h = ctrl_reg | word_len | parity | stop_bits; in _uart_pl011_set_format()
314 p_uart->uartlcr_h |= (mask); in _uart_pl011_set_lcr_h_bit()
331 p_uart->uartlcr_h &= ~(mask); in _uart_pl011_clear_lcr_h_bit()
352 p_uart->uartlcr_h = UART_PL011_LCR_H_REG_RESET_VALUE; in _uart_pl011_reset_regs()