1 /* 2 * Copyright (c) 2013-2017 ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 * $Date: 2. Feb 2017 19 * $Revision: V2.3 20 * 21 * Project: USART (Universal Synchronous Asynchronous Receiver Transmitter) 22 * Driver definitions 23 */ 24 25 /* History: 26 * Version 2.3 27 * ARM_USART_STATUS and ARM_USART_MODEM_STATUS made volatile 28 * Version 2.2 29 * Corrected ARM_USART_CPOL_Pos and ARM_USART_CPHA_Pos definitions 30 * Version 2.1 31 * Removed optional argument parameter from Signal Event 32 * Version 2.0 33 * New simplified driver: 34 * complexity moved to upper layer (especially data handling) 35 * more unified API for different communication interfaces 36 * renamed driver UART -> USART (Asynchronous & Synchronous) 37 * Added modes: 38 * Synchronous 39 * Single-wire 40 * IrDA 41 * Smart Card 42 * Changed prefix ARM_DRV -> ARM_DRIVER 43 * Version 1.10 44 * Namespace prefix ARM_ added 45 * Version 1.01 46 * Added events: 47 * ARM_UART_EVENT_TX_EMPTY, ARM_UART_EVENT_RX_TIMEOUT 48 * ARM_UART_EVENT_TX_THRESHOLD, ARM_UART_EVENT_RX_THRESHOLD 49 * Added functions: SetTxThreshold, SetRxThreshold 50 * Added "rx_timeout_event" to capabilities 51 * Version 1.00 52 * Initial release 53 */ 54 55 #ifndef DRIVER_USART_H_ 56 #define DRIVER_USART_H_ 57 58 #ifdef __cplusplus 59 extern "C" 60 { 61 #endif 62 63 #include "Driver_Common.h" 64 65 #define ARM_USART_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,3) /* API version */ 66 67 68 /****** USART Control Codes *****/ 69 70 #define ARM_USART_CONTROL_Pos 0 71 #define ARM_USART_CONTROL_Msk (0xFFUL << ARM_USART_CONTROL_Pos) 72 73 /*----- USART Control Codes: Mode -----*/ 74 #define ARM_USART_MODE_ASYNCHRONOUS (0x01UL << ARM_USART_CONTROL_Pos) ///< UART (Asynchronous); arg = Baudrate 75 #define ARM_USART_MODE_SYNCHRONOUS_MASTER (0x02UL << ARM_USART_CONTROL_Pos) ///< Synchronous Master (generates clock signal); arg = Baudrate 76 #define ARM_USART_MODE_SYNCHRONOUS_SLAVE (0x03UL << ARM_USART_CONTROL_Pos) ///< Synchronous Slave (external clock signal) 77 #define ARM_USART_MODE_SINGLE_WIRE (0x04UL << ARM_USART_CONTROL_Pos) ///< UART Single-wire (half-duplex); arg = Baudrate 78 #define ARM_USART_MODE_IRDA (0x05UL << ARM_USART_CONTROL_Pos) ///< UART IrDA; arg = Baudrate 79 #define ARM_USART_MODE_SMART_CARD (0x06UL << ARM_USART_CONTROL_Pos) ///< UART Smart Card; arg = Baudrate 80 81 /*----- USART Control Codes: Mode Parameters: Data Bits -----*/ 82 #define ARM_USART_DATA_BITS_Pos 8 83 #define ARM_USART_DATA_BITS_Msk (7UL << ARM_USART_DATA_BITS_Pos) 84 #define ARM_USART_DATA_BITS_5 (5UL << ARM_USART_DATA_BITS_Pos) ///< 5 Data bits 85 #define ARM_USART_DATA_BITS_6 (6UL << ARM_USART_DATA_BITS_Pos) ///< 6 Data bit 86 #define ARM_USART_DATA_BITS_7 (7UL << ARM_USART_DATA_BITS_Pos) ///< 7 Data bits 87 #define ARM_USART_DATA_BITS_8 (0UL << ARM_USART_DATA_BITS_Pos) ///< 8 Data bits (default) 88 #define ARM_USART_DATA_BITS_9 (1UL << ARM_USART_DATA_BITS_Pos) ///< 9 Data bits 89 90 /*----- USART Control Codes: Mode Parameters: Parity -----*/ 91 #define ARM_USART_PARITY_Pos 12 92 #define ARM_USART_PARITY_Msk (3UL << ARM_USART_PARITY_Pos) 93 #define ARM_USART_PARITY_NONE (0UL << ARM_USART_PARITY_Pos) ///< No Parity (default) 94 #define ARM_USART_PARITY_EVEN (1UL << ARM_USART_PARITY_Pos) ///< Even Parity 95 #define ARM_USART_PARITY_ODD (2UL << ARM_USART_PARITY_Pos) ///< Odd Parity 96 97 /*----- USART Control Codes: Mode Parameters: Stop Bits -----*/ 98 #define ARM_USART_STOP_BITS_Pos 14 99 #define ARM_USART_STOP_BITS_Msk (3UL << ARM_USART_STOP_BITS_Pos) 100 #define ARM_USART_STOP_BITS_1 (0UL << ARM_USART_STOP_BITS_Pos) ///< 1 Stop bit (default) 101 #define ARM_USART_STOP_BITS_2 (1UL << ARM_USART_STOP_BITS_Pos) ///< 2 Stop bits 102 #define ARM_USART_STOP_BITS_1_5 (2UL << ARM_USART_STOP_BITS_Pos) ///< 1.5 Stop bits 103 #define ARM_USART_STOP_BITS_0_5 (3UL << ARM_USART_STOP_BITS_Pos) ///< 0.5 Stop bits 104 105 /*----- USART Control Codes: Mode Parameters: Flow Control -----*/ 106 #define ARM_USART_FLOW_CONTROL_Pos 16 107 #define ARM_USART_FLOW_CONTROL_Msk (3UL << ARM_USART_FLOW_CONTROL_Pos) 108 #define ARM_USART_FLOW_CONTROL_NONE (0UL << ARM_USART_FLOW_CONTROL_Pos) ///< No Flow Control (default) 109 #define ARM_USART_FLOW_CONTROL_RTS (1UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS Flow Control 110 #define ARM_USART_FLOW_CONTROL_CTS (2UL << ARM_USART_FLOW_CONTROL_Pos) ///< CTS Flow Control 111 #define ARM_USART_FLOW_CONTROL_RTS_CTS (3UL << ARM_USART_FLOW_CONTROL_Pos) ///< RTS/CTS Flow Control 112 113 /*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/ 114 #define ARM_USART_CPOL_Pos 18 115 #define ARM_USART_CPOL_Msk (1UL << ARM_USART_CPOL_Pos) 116 #define ARM_USART_CPOL0 (0UL << ARM_USART_CPOL_Pos) ///< CPOL = 0 (default) 117 #define ARM_USART_CPOL1 (1UL << ARM_USART_CPOL_Pos) ///< CPOL = 1 118 119 /*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/ 120 #define ARM_USART_CPHA_Pos 19 121 #define ARM_USART_CPHA_Msk (1UL << ARM_USART_CPHA_Pos) 122 #define ARM_USART_CPHA0 (0UL << ARM_USART_CPHA_Pos) ///< CPHA = 0 (default) 123 #define ARM_USART_CPHA1 (1UL << ARM_USART_CPHA_Pos) ///< CPHA = 1 124 125 126 /*----- USART Control Codes: Miscellaneous Controls -----*/ 127 #define ARM_USART_SET_DEFAULT_TX_VALUE (0x10UL << ARM_USART_CONTROL_Pos) ///< Set default Transmit value (Synchronous Receive only); arg = value 128 #define ARM_USART_SET_IRDA_PULSE (0x11UL << ARM_USART_CONTROL_Pos) ///< Set IrDA Pulse in ns; arg: 0=3/16 of bit period 129 #define ARM_USART_SET_SMART_CARD_GUARD_TIME (0x12UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Guard Time; arg = number of bit periods 130 #define ARM_USART_SET_SMART_CARD_CLOCK (0x13UL << ARM_USART_CONTROL_Pos) ///< Set Smart Card Clock in Hz; arg: 0=Clock not generated 131 #define ARM_USART_CONTROL_SMART_CARD_NACK (0x14UL << ARM_USART_CONTROL_Pos) ///< Smart Card NACK generation; arg: 0=disabled, 1=enabled 132 #define ARM_USART_CONTROL_TX (0x15UL << ARM_USART_CONTROL_Pos) ///< Transmitter; arg: 0=disabled, 1=enabled 133 #define ARM_USART_CONTROL_RX (0x16UL << ARM_USART_CONTROL_Pos) ///< Receiver; arg: 0=disabled, 1=enabled 134 #define ARM_USART_CONTROL_BREAK (0x17UL << ARM_USART_CONTROL_Pos) ///< Continuous Break transmission; arg: 0=disabled, 1=enabled 135 #define ARM_USART_ABORT_SEND (0x18UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Send 136 #define ARM_USART_ABORT_RECEIVE (0x19UL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Receive 137 #define ARM_USART_ABORT_TRANSFER (0x1AUL << ARM_USART_CONTROL_Pos) ///< Abort \ref ARM_USART_Transfer 138 139 140 141 /****** USART specific error codes *****/ 142 #define ARM_USART_ERROR_MODE (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< Specified Mode not supported 143 #define ARM_USART_ERROR_BAUDRATE (ARM_DRIVER_ERROR_SPECIFIC - 2) ///< Specified baudrate not supported 144 #define ARM_USART_ERROR_DATA_BITS (ARM_DRIVER_ERROR_SPECIFIC - 3) ///< Specified number of Data bits not supported 145 #define ARM_USART_ERROR_PARITY (ARM_DRIVER_ERROR_SPECIFIC - 4) ///< Specified Parity not supported 146 #define ARM_USART_ERROR_STOP_BITS (ARM_DRIVER_ERROR_SPECIFIC - 5) ///< Specified number of Stop bits not supported 147 #define ARM_USART_ERROR_FLOW_CONTROL (ARM_DRIVER_ERROR_SPECIFIC - 6) ///< Specified Flow Control not supported 148 #define ARM_USART_ERROR_CPOL (ARM_DRIVER_ERROR_SPECIFIC - 7) ///< Specified Clock Polarity not supported 149 #define ARM_USART_ERROR_CPHA (ARM_DRIVER_ERROR_SPECIFIC - 8) ///< Specified Clock Phase not supported 150 151 152 /** 153 \brief USART Status 154 */ 155 typedef volatile struct _ARM_USART_STATUS { 156 uint32_t tx_busy : 1; ///< Transmitter busy flag 157 uint32_t rx_busy : 1; ///< Receiver busy flag 158 uint32_t tx_underflow : 1; ///< Transmit data underflow detected (cleared on start of next send operation) 159 uint32_t rx_overflow : 1; ///< Receive data overflow detected (cleared on start of next receive operation) 160 uint32_t rx_break : 1; ///< Break detected on receive (cleared on start of next receive operation) 161 uint32_t rx_framing_error : 1; ///< Framing error detected on receive (cleared on start of next receive operation) 162 uint32_t rx_parity_error : 1; ///< Parity error detected on receive (cleared on start of next receive operation) 163 uint32_t reserved : 25; 164 } ARM_USART_STATUS; 165 166 /** 167 \brief USART Modem Control 168 */ 169 typedef enum _ARM_USART_MODEM_CONTROL { 170 ARM_USART_RTS_CLEAR, ///< Deactivate RTS 171 ARM_USART_RTS_SET, ///< Activate RTS 172 ARM_USART_DTR_CLEAR, ///< Deactivate DTR 173 ARM_USART_DTR_SET ///< Activate DTR 174 } ARM_USART_MODEM_CONTROL; 175 176 /** 177 \brief USART Modem Status 178 */ 179 typedef volatile struct _ARM_USART_MODEM_STATUS { 180 uint32_t cts : 1; ///< CTS state: 1=Active, 0=Inactive 181 uint32_t dsr : 1; ///< DSR state: 1=Active, 0=Inactive 182 uint32_t dcd : 1; ///< DCD state: 1=Active, 0=Inactive 183 uint32_t ri : 1; ///< RI state: 1=Active, 0=Inactive 184 uint32_t reserved : 28; 185 } ARM_USART_MODEM_STATUS; 186 187 188 /****** USART Event *****/ 189 #define ARM_USART_EVENT_SEND_COMPLETE (1UL << 0) ///< Send completed; however USART may still transmit data 190 #define ARM_USART_EVENT_RECEIVE_COMPLETE (1UL << 1) ///< Receive completed 191 #define ARM_USART_EVENT_TRANSFER_COMPLETE (1UL << 2) ///< Transfer completed 192 #define ARM_USART_EVENT_TX_COMPLETE (1UL << 3) ///< Transmit completed (optional) 193 #define ARM_USART_EVENT_TX_UNDERFLOW (1UL << 4) ///< Transmit data not available (Synchronous Slave) 194 #define ARM_USART_EVENT_RX_OVERFLOW (1UL << 5) ///< Receive data overflow 195 #define ARM_USART_EVENT_RX_TIMEOUT (1UL << 6) ///< Receive character timeout (optional) 196 #define ARM_USART_EVENT_RX_BREAK (1UL << 7) ///< Break detected on receive 197 #define ARM_USART_EVENT_RX_FRAMING_ERROR (1UL << 8) ///< Framing error detected on receive 198 #define ARM_USART_EVENT_RX_PARITY_ERROR (1UL << 9) ///< Parity error detected on receive 199 #define ARM_USART_EVENT_CTS (1UL << 10) ///< CTS state changed (optional) 200 #define ARM_USART_EVENT_DSR (1UL << 11) ///< DSR state changed (optional) 201 #define ARM_USART_EVENT_DCD (1UL << 12) ///< DCD state changed (optional) 202 #define ARM_USART_EVENT_RI (1UL << 13) ///< RI state changed (optional) 203 204 205 // Function documentation 206 /** 207 \fn ARM_DRIVER_VERSION ARM_USART_GetVersion (void) 208 \brief Get driver version. 209 \return \ref ARM_DRIVER_VERSION 210 211 \fn ARM_USART_CAPABILITIES ARM_USART_GetCapabilities (void) 212 \brief Get driver capabilities 213 \return \ref ARM_USART_CAPABILITIES 214 215 \fn int32_t ARM_USART_Initialize (ARM_USART_SignalEvent_t cb_event) 216 \brief Initialize USART Interface. 217 \param[in] cb_event Pointer to \ref ARM_USART_SignalEvent 218 \return \ref execution_status 219 220 \fn int32_t ARM_USART_Uninitialize (void) 221 \brief De-initialize USART Interface. 222 \return \ref execution_status 223 224 \fn int32_t ARM_USART_PowerControl (ARM_POWER_STATE state) 225 \brief Control USART Interface Power. 226 \param[in] state Power state 227 \return \ref execution_status 228 229 \fn int32_t ARM_USART_Send (const void *data, uint32_t num) 230 \brief Start sending data to USART transmitter. 231 \param[in] data Pointer to buffer with data to send to USART transmitter 232 \param[in] num Number of data items to send 233 \return \ref execution_status 234 235 \fn int32_t ARM_USART_Receive (void *data, uint32_t num) 236 \brief Start receiving data from USART receiver. 237 \param[out] data Pointer to buffer for data to receive from USART receiver 238 \param[in] num Number of data items to receive 239 \return \ref execution_status 240 241 \fn int32_t ARM_USART_Transfer (const void *data_out, 242 void *data_in, 243 uint32_t num) 244 \brief Start sending/receiving data to/from USART transmitter/receiver. 245 \param[in] data_out Pointer to buffer with data to send to USART transmitter 246 \param[out] data_in Pointer to buffer for data to receive from USART receiver 247 \param[in] num Number of data items to transfer 248 \return \ref execution_status 249 250 \fn uint32_t ARM_USART_GetTxCount (void) 251 \brief Get transmitted data count. 252 \return number of data items transmitted 253 254 \fn uint32_t ARM_USART_GetRxCount (void) 255 \brief Get received data count. 256 \return number of data items received 257 258 \fn int32_t ARM_USART_Control (uint32_t control, uint32_t arg) 259 \brief Control USART Interface. 260 \param[in] control Operation 261 \param[in] arg Argument of operation (optional) 262 \return common \ref execution_status and driver specific \ref usart_execution_status 263 264 \fn ARM_USART_STATUS ARM_USART_GetStatus (void) 265 \brief Get USART status. 266 \return USART status \ref ARM_USART_STATUS 267 268 \fn int32_t ARM_USART_SetModemControl (ARM_USART_MODEM_CONTROL control) 269 \brief Set USART Modem Control line state. 270 \param[in] control \ref ARM_USART_MODEM_CONTROL 271 \return \ref execution_status 272 273 \fn ARM_USART_MODEM_STATUS ARM_USART_GetModemStatus (void) 274 \brief Get USART Modem Status lines state. 275 \return modem status \ref ARM_USART_MODEM_STATUS 276 277 \fn void ARM_USART_SignalEvent (uint32_t event) 278 \brief Signal USART Events. 279 \param[in] event \ref USART_events notification mask 280 \return none 281 */ 282 283 typedef void (*ARM_USART_SignalEvent_t) (uint32_t event); ///< Pointer to \ref ARM_USART_SignalEvent : Signal USART Event. 284 285 286 /** 287 \brief USART Device Driver Capabilities. 288 */ 289 typedef struct _ARM_USART_CAPABILITIES { 290 uint32_t asynchronous : 1; ///< supports UART (Asynchronous) mode 291 uint32_t synchronous_master : 1; ///< supports Synchronous Master mode 292 uint32_t synchronous_slave : 1; ///< supports Synchronous Slave mode 293 uint32_t single_wire : 1; ///< supports UART Single-wire mode 294 uint32_t irda : 1; ///< supports UART IrDA mode 295 uint32_t smart_card : 1; ///< supports UART Smart Card mode 296 uint32_t smart_card_clock : 1; ///< Smart Card Clock generator available 297 uint32_t flow_control_rts : 1; ///< RTS Flow Control available 298 uint32_t flow_control_cts : 1; ///< CTS Flow Control available 299 uint32_t event_tx_complete : 1; ///< Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE 300 uint32_t event_rx_timeout : 1; ///< Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT 301 uint32_t rts : 1; ///< RTS Line: 0=not available, 1=available 302 uint32_t cts : 1; ///< CTS Line: 0=not available, 1=available 303 uint32_t dtr : 1; ///< DTR Line: 0=not available, 1=available 304 uint32_t dsr : 1; ///< DSR Line: 0=not available, 1=available 305 uint32_t dcd : 1; ///< DCD Line: 0=not available, 1=available 306 uint32_t ri : 1; ///< RI Line: 0=not available, 1=available 307 uint32_t event_cts : 1; ///< Signal CTS change event: \ref ARM_USART_EVENT_CTS 308 uint32_t event_dsr : 1; ///< Signal DSR change event: \ref ARM_USART_EVENT_DSR 309 uint32_t event_dcd : 1; ///< Signal DCD change event: \ref ARM_USART_EVENT_DCD 310 uint32_t event_ri : 1; ///< Signal RI change event: \ref ARM_USART_EVENT_RI 311 uint32_t reserved : 11; ///< Reserved (must be zero) 312 } ARM_USART_CAPABILITIES; 313 314 315 /** 316 \brief Access structure of the USART Driver. 317 */ 318 typedef struct _ARM_DRIVER_USART { 319 ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_USART_GetVersion : Get driver version. 320 ARM_USART_CAPABILITIES (*GetCapabilities) (void); ///< Pointer to \ref ARM_USART_GetCapabilities : Get driver capabilities. 321 int32_t (*Initialize) (ARM_USART_SignalEvent_t cb_event); ///< Pointer to \ref ARM_USART_Initialize : Initialize USART Interface. 322 int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_USART_Uninitialize : De-initialize USART Interface. 323 int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_USART_PowerControl : Control USART Interface Power. 324 int32_t (*Send) (const void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Send : Start sending data to USART transmitter. 325 int32_t (*Receive) ( void *data, uint32_t num); ///< Pointer to \ref ARM_USART_Receive : Start receiving data from USART receiver. 326 int32_t (*Transfer) (const void *data_out, 327 void *data_in, 328 uint32_t num); ///< Pointer to \ref ARM_USART_Transfer : Start sending/receiving data to/from USART. 329 uint32_t (*GetTxCount) (void); ///< Pointer to \ref ARM_USART_GetTxCount : Get transmitted data count. 330 uint32_t (*GetRxCount) (void); ///< Pointer to \ref ARM_USART_GetRxCount : Get received data count. 331 int32_t (*Control) (uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_USART_Control : Control USART Interface. 332 ARM_USART_STATUS (*GetStatus) (void); ///< Pointer to \ref ARM_USART_GetStatus : Get USART status. 333 int32_t (*SetModemControl) (ARM_USART_MODEM_CONTROL control); ///< Pointer to \ref ARM_USART_SetModemControl : Set USART Modem Control line state. 334 ARM_USART_MODEM_STATUS (*GetModemStatus) (void); ///< Pointer to \ref ARM_USART_GetModemStatus : Get USART Modem Status lines state. 335 } const ARM_DRIVER_USART; 336 337 #ifdef __cplusplus 338 } 339 #endif 340 341 #endif /* DRIVER_USART_H_ */ 342
