Home
last modified time | relevance | path

Searched refs:bit (Results 1 – 25 of 39) sorted by relevance

12

/trusted-firmware-m-3.4.0/docs/platform/cypress/psoc64/libs/core-lib/
DREADME.md14 * `CY_LO8`: Gets the lower 8 bits of a 16-bit value
15 * `CY_HI8`: Gets the upper 8 bits of a 16-bit value
16 * `CY_LO16`: Gets the lower 16 bits of a 32-bit value
17 * `CY_HI16`: Gets the upper 16 bits of a 32-bit value
18 * `CY_SWAP_ENDIAN16`: Swaps the byte ordering of a 16-bit value
19 * `CY_SWAP_ENDIAN32`: Swaps the byte ordering of a 32-bit value
20 * `CY_SWAP_ENDIAN64`: Swaps the byte ordering of a 64-bit value
21 * `CY_GET_REG8`: Reads the 8-bit value from the specified address
22 * `CY_SET_REG8`: Writes an 8-bit value to the specified address
23 * `CY_GET_REG16`: Reads the 16-bit value from the specified address
[all …]
DRELEASE.md10 * CY_LO8: Gets the lower 8 bits of a 16-bit value
11 * CY_HI8: Gets the upper 8 bits of a 16-bit value
12 * CY_LO16: Gets the lower 16 bits of a 32-bit value
13 * CY_HI16: Gets the upper 16 bits of a 32-bit value
14 * CY_SWAP_ENDIAN16: Swaps the byte ordering of a 16-bit value
15 * CY_SWAP_ENDIAN32: Swaps the byte ordering of a 32-bit value
16 * CY_SWAP_ENDIAN64: Swaps the byte ordering of a 64-bit value
17 * CY_GET_REG8: Reads the 8-bit value from the specified address
18 * CY_SET_REG8: Writes an 8-bit value to the specified address
19 * CY_GET_REG16: Reads the 16-bit value from the specified address
[all …]
/trusted-firmware-m-3.4.0/lib/ext/cryptocell-312-runtime/utils/src/cc3x_boot_cert/examples/enabler_cert/
Dsb_enabler_dbg_cert_rma.cfg16 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
17 # Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is s…
18 #debug-mask[x-y] = The additional DCU lock by the OEM. 128 bit mask in 4*32 bits hex format (…
20 …ory HBK field for verification of the public key: 0 = 128bit HBK0; 1 = 128bit HBK1; 2 = 256bit HB…
Dx509_sb_enabler_dbg_cert_rma.cfg16 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
17 # Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is s…
18 #debug-mask[x-y] = The additional DCU lock by the OEM. 128 bit mask in 4*32 bits hex format (…
20 …ory HBK field for verification of the public key: 0 = 128bit HBK0; 1 = 128bit HBK1; 2 = 256bit HB…
Dsb_enabler_dbg_cert.cfg16 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
17 # Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is s…
18 #debug-mask[x-y] = The additional DCU lock by the OEM. 128 bit mask in 4*32 bits hex format (…
20 …ory HBK field for verification of the public key: 0 = 128bit HBK0; 1 = 128bit HBK1; 2 = 256bit HB…
Dsb_enabler_dbg_cert_rma_no_pwd.cfg16 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
17 # Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is s…
18 #debug-mask[x-y] = The additional DCU lock by the OEM. 128 bit mask in 4*32 bits hex format (…
20 …ory HBK field for verification of the public key: 0 = 128bit HBK0; 1 = 128bit HBK1; 2 = 256bit HB…
Dx509_sb_enabler_dbg_cert.cfg16 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
17 # Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is s…
18 #debug-mask[x-y] = The additional DCU lock by the OEM. 128 bit mask in 4*32 bits hex format (…
20 …ory HBK field for verification of the public key: 0 = 128bit HBK0; 1 = 128bit HBK1; 2 = 256bit HB…
Dsb_enabler_dbg_cert_no_pwd.cfg16 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
17 # Cannot be defined together with rma-mode. If bit 0 in debug-mask[0-31] is s…
18 #debug-mask[x-y] = The additional DCU lock by the OEM. 128 bit mask in 4*32 bits hex format (…
20 …ory HBK field for verification of the public key: 0 = 128bit HBK0; 1 = 128bit HBK1; 2 = 256bit HB…
/trusted-firmware-m-3.4.0/docs/technical_references/design_docs/
Dstateless_rot_service.rst41 * - bit 31
43 * - bit 30
44 - stateless handle indicator bit, always 1
45 * - bit 29 - bit 16
47 * - bit 15 - bit 8
49 * - bit 7 - bit 0
53 ``psa_call()``, an indicator bit is set in the handle indicate the type of the
56 indicator bit is always 0.
Dtfm_its_service.rst164 The ITS APIs identify assets with 64-bit UIDs, to which the ITS service must
165 append the 32-bit client ID of the calling partition for access control. The
166 existing filesystem uses 32-bit file IDs to identify files, so some mapping
179 - Modify the filesystem to take (at least) 96-bit file IDs, in the form of a
190 metadata entry would be increased by 64-bits and the 96-bit fids would need to
204 The ITS APIs provide a 32-bit ``create_flags`` parameter, which contains bit
221 To implement the second option, a 32-bit ``flag`` field would be added to the
Dtfm_its_512_flash.rst58 - Currently power-failure is detected by software by incrementing an 8-bit
/trusted-firmware-m-3.4.0/lib/ext/cryptocell-312-runtime/utils/src/cc3x_boot_cert/examples/key_cert/
Dsb_key_cert.cfg13 …eld for verification of the public key: 0 = 128bit ICV key (HBK0); 1 = 128bit OEM key (HBK1); 2 =…
Dsb_key_cert_hbk0.cfg13 …eld for verification of the public key: 0 = 128bit ICV key (HBK0); 1 = 128bit OEM key (HBK1); 2 =…
Dsb_key_cert_hbk1.cfg13 …eld for verification of the public key: 0 = 128bit ICV key (HBK0); 1 = 128bit OEM key (HBK1); 2 =…
/trusted-firmware-m-3.4.0/platform/ext/target/nuvoton/m2351/bsp/Library/StdDriver/src/
Dretarget.c291 uint8_t idx, bit; in ProcessHardFault() local
445 bit = idx & 0x1f; in ProcessHardFault()
447 s = (SCU->PNSSET[idx] >> bit) & 1ul; in ProcessHardFault()
456 bit = idx & 0x1f; in ProcessHardFault()
458 s = (SCU->PNSSET[idx] >> bit) & 1ul; in ProcessHardFault()
477 bit = idx & 0x1f; in ProcessHardFault()
479 s = (SCU->PNSSET[idx] >> bit) & 1ul; in ProcessHardFault()
/trusted-firmware-m-3.4.0/lib/ext/cryptocell-312-runtime/utils/src/cc3x_boot_cert/examples/developer_cert/
Dsb_developer_dbg_cert.cfg14 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
15 # If bit 0 in debug-mask[0-31] is set, the HW keys reset in debug mode is not…
Dsb_developer_dbg_cert_no_pwd.cfg14 #debug-mask[x-y] = The DCU mask allowed by the OEM. 128 bit mask in 4*32 bits hex format (e.g.…
15 # If bit 0 in debug-mask[0-31] is set, the HW keys reset in debug mode is not…
/trusted-firmware-m-3.4.0/lib/ext/cryptocell-312-runtime/codesafe/src/crypto_api/ffcdh/
Dcc_ffcdh_local.h63 #define FFCDH_OFFS_TO_VAL(bit, offset) ((bit) << (offset)) argument
/trusted-firmware-m-3.4.0/docs/platform/stm/common/stm32u5xx/
Dreadme.rst52 - Stop = 1 bit
/trusted-firmware-m-3.4.0/docs/platform/stm/common/stm32l5xx/
Dreadme.rst58 - Stop = 1 bit
/trusted-firmware-m-3.4.0/docs/security/security_advisories/
Dsvc_caller_sp_fetching_vulnerability.rst34 handler code relies on the 'SPSEL' bit in 'EXC_RETURN' to get the caller stack
57 stack pointer register by checking both the PE mode and SPSEL bit. The handler
/trusted-firmware-m-3.4.0/
Dtoolchain_IARARM.cmake29 # This variable name is a bit of a misnomer. The file it is set to is included
/trusted-firmware-m-3.4.0/docs/integration_guide/platform/
Dplatform_provisioning.rst77 (Where a bit cannot transition from a 1 to a 0), such as physical OTP memory,
/trusted-firmware-m-3.4.0/lib/ext/cryptocell-312-runtime/codesafe/src/crypto_api/pki/rsa/
Drsa_genkey.c480 uint32_t bit; in PkaRsaKgX931LucasPrimeTest() local
504 bit = PkaGetBitFromPkaReg( rK, lenId, i, rT); in PkaRsaKgX931LucasPrimeTest()
506 if (bit != 0) { in PkaRsaKgX931LucasPrimeTest()
/trusted-firmware-m-3.4.0/lib/ext/t_cose/
DREADME.md179 These are approximate numbers for 64-bit x86 code optimized for size
206 heap memory. This will vary quite a bit by crypto library. Some may use malloc. Some may

12