1 /**************************************************************************//** 2 * @file sys.h 3 * @version V3 4 * @brief M2354 series System Manager (SYS) driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 ******************************************************************************/ 9 #ifndef __SYS_H__ 10 #define __SYS_H__ 11 12 13 #ifdef __cplusplus 14 extern "C" 15 { 16 #endif 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup SYS_Driver SYS Driver 23 @{ 24 */ 25 26 /** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants 27 @{ 28 */ 29 30 /*---------------------------------------------------------------------------------------------------------*/ 31 /* Module Reset Control Resister constant definitions. */ 32 /*---------------------------------------------------------------------------------------------------------*/ 33 #define PDMA0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA0RST_Pos) /*!< PDMA0 reset is one of the SYS_ResetModule parameter */ 34 #define EBI_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_EBIRST_Pos) /*!< EBI reset is one of the SYS_ResetModule parameter */ 35 #define USBH_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_USBHRST_Pos) /*!< USBH reset is one of the SYS_ResetModule parameter */ 36 #define SDH0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_SDH0RST_Pos) /*!< SDH0 reset is one of the SYS_ResetModule parameter */ 37 #define CRC_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRCRST_Pos) /*!< CRC reset is one of the SYS_ResetModule parameter */ 38 #define CRPT_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRPTRST_Pos) /*!< CRPT reset is one of the SYS_ResetModule parameter */ 39 #define KS_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_KSRST_Pos) /*!< KS reset is one of the SYS_ResetModule parameter */ 40 #define PDMA1_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA1RST_Pos) /*!< PDMA1 reset is one of the SYS_ResetModule parameter */ 41 42 #define GPIO_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_GPIORST_Pos) /*!< GPIO reset is one of the SYS_ResetModule parameter */ 43 #define TMR0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR0RST_Pos) /*!< TMR0 reset is one of the SYS_ResetModule parameter */ 44 #define TMR1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR1RST_Pos) /*!< TMR1 reset is one of the SYS_ResetModule parameter */ 45 #define TMR2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR2RST_Pos) /*!< TMR2 reset is one of the SYS_ResetModule parameter */ 46 #define TMR3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR3RST_Pos) /*!< TMR3 reset is one of the SYS_ResetModule parameter */ 47 #define TMR4_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR4RST_Pos) /*!< TMR4 reset is one of the SYS_ResetModule parameter */ 48 #define TMR5_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_TMR5RST_Pos) /*!< TMR5 reset is one of the SYS_ResetModule parameter */ 49 50 #define ACMP01_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_ACMP01RST_Pos) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */ 51 #define I2C0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C0RST_Pos) /*!< I2C0 reset is one of the SYS_ResetModule parameter */ 52 #define I2C1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C1RST_Pos) /*!< I2C1 reset is one of the SYS_ResetModule parameter */ 53 #define I2C2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C2RST_Pos) /*!< I2C2 reset is one of the SYS_ResetModule parameter */ 54 #define QSPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_QSPI0RST_Pos) /*!< QSPI0 reset is one of the SYS_ResetModule parameter */ 55 #define SPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI0RST_Pos) /*!< SPI0 reset is one of the SYS_ResetModule parameter */ 56 #define SPI1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI1RST_Pos) /*!< SPI1 reset is one of the SYS_ResetModule parameter */ 57 #define SPI2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI2RST_Pos) /*!< SPI2 reset is one of the SYS_ResetModule parameter */ 58 #define UART0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART0RST_Pos) /*!< UART0 reset is one of the SYS_ResetModule parameter */ 59 #define UART1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART1RST_Pos) /*!< UART1 reset is one of the SYS_ResetModule parameter */ 60 #define UART2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART2RST_Pos) /*!< UART2 reset is one of the SYS_ResetModule parameter */ 61 #define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */ 62 #define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */ 63 #define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */ 64 #define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */ 65 #define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */ 66 #define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */ 67 #define EADC_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_EADCRST_Pos) /*!< EADC reset is one of the SYS_ResetModule parameter */ 68 #define I2S0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2S0RST_Pos) /*!< I2S0 reset is one of the SYS_ResetModule parameter */ 69 #define LCD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_LCDRST_Pos) /*!< LCD reset is one of the SYS_ResetModule parameter */ 70 #define TRNG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TRNGRST_Pos) /*!< TRNG reset is one of the SYS_ResetModule parameter */ 71 72 #define SC0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC0RST_Pos) /*!< SC0 reset is one of the SYS_ResetModule parameter */ 73 #define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */ 74 #define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */ 75 #define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */ 76 #define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */ 77 #define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */ 78 #define DAC_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_DACRST_Pos) /*!< DAC reset is one of the SYS_ResetModule parameter */ 79 #define EPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM0RST_Pos) /*!< EPWM0 reset is one of the SYS_ResetModule parameter */ 80 #define EPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM1RST_Pos) /*!< EPWM1 reset is one of the SYS_ResetModule parameter */ 81 #define BPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM0RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */ 82 #define BPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM1RST_Pos) /*!< BPWM1 reset is one of the SYS_ResetModule parameter */ 83 #define QEI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI0RST_Pos) /*!< QEI0 reset is one of the SYS_ResetModule parameter */ 84 #define QEI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI1RST_Pos) /*!< QEI1 reset is one of the SYS_ResetModule parameter */ 85 #define ECAP0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP0RST_Pos) /*!< ECAP0 reset is one of the SYS_ResetModule parameter */ 86 #define ECAP1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP1RST_Pos) /*!< ECAP1 reset is one of the SYS_ResetModule parameter */ 87 88 89 /*---------------------------------------------------------------------------------------------------------*/ 90 /* Brown Out Detector Threshold Voltage Selection constant definitions. */ 91 /*---------------------------------------------------------------------------------------------------------*/ 92 #define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */ 93 #define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */ 94 #define SYS_BODCTL_BODVL_3_0V (7UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.0V */ 95 #define SYS_BODCTL_BODVL_2_8V (6UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.8V */ 96 #define SYS_BODCTL_BODVL_2_6V (5UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.6V */ 97 #define SYS_BODCTL_BODVL_2_4V (4UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.4V */ 98 #define SYS_BODCTL_BODVL_2_2V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */ 99 #define SYS_BODCTL_BODVL_2_0V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.0V */ 100 #define SYS_BODCTL_BODVL_1_8V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.8V */ 101 #define SYS_BODCTL_BODVL_1_6V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 1.6V */ 102 103 104 /*---------------------------------------------------------------------------------------------------------*/ 105 /* VREFCTL constant definitions. (Write-Protection Register) */ 106 /*---------------------------------------------------------------------------------------------------------*/ 107 #define SYS_VREFCTL_VREF_PIN (0x0UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = Vref pin */ 108 #define SYS_VREFCTL_VREF_1_6V (0x3UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 1.6V */ 109 #define SYS_VREFCTL_VREF_2_0V (0x7UL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.0V */ 110 #define SYS_VREFCTL_VREF_2_5V (0xBUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 2.5V */ 111 #define SYS_VREFCTL_VREF_3_0V (0xFUL<<SYS_VREFCTL_VREFCTL_Pos) /*!< Vref = 3.0V */ 112 113 114 /*---------------------------------------------------------------------------------------------------------*/ 115 /* USBPHY constant definitions. (Write-Protection Register) */ 116 /*---------------------------------------------------------------------------------------------------------*/ 117 #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */ 118 #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */ 119 #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */ 120 #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */ 121 122 123 /*---------------------------------------------------------------------------------------------------------*/ 124 /* PLCTL constant definitions. (Write-Protection Register) */ 125 /*---------------------------------------------------------------------------------------------------------*/ 126 #define SYS_PLCTL_PLSEL_PL0 (0x0UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 0. Supports system clock up to 96MHz. */ 127 #define SYS_PLCTL_PLSEL_PL1 (0x1UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 1. Supports system clock up to 84MHz. */ 128 #define SYS_PLCTL_PLSEL_PL2 (0x2UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 2. Supports system clock up to 48MHz. */ 129 #define SYS_PLCTL_PLSEL_PL3 (0x3UL<<SYS_PLCTL_PLSEL_Pos) /*!< Set power level to power level 3. Supports system clock up to 4MHz. */ 130 #define SYS_PLCTL_MVRS_LDO (0x0UL<<SYS_PLCTL_MVRS_Pos) /*!< Set main voltage regulator type to LDO */ 131 #define SYS_PLCTL_MVRS_DCDC (0x1UL<<SYS_PLCTL_MVRS_Pos) /*!< Set main voltage regulator type to DCDC */ 132 133 134 /*---------------------------------------------------------------------------------------------------------*/ 135 /* PLSTS constant definitions. (Write-Protection Register) */ 136 /*---------------------------------------------------------------------------------------------------------*/ 137 #define SYS_PLSTS_PLSTATUS_PL0 (0x0UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 0. Supports system clock up to 96MHz. */ 138 #define SYS_PLSTS_PLSTATUS_PL1 (0x1UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 1. Supports system clock up to 84MHz. */ 139 #define SYS_PLSTS_PLSTATUS_PL2 (0x2UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 2. Supports system clock up to 48MHz. */ 140 #define SYS_PLSTS_PLSTATUS_PL3 (0x3UL<<SYS_PLSTS_PLSTATUS_Pos) /*!< Power level is power level 3. Supports system clock up to 4MHz. */ 141 #define SYS_PLSTS_CURMVR_LDO (0x0UL<<SYS_PLSTS_CURMVR_Pos) /*!< Main voltage regulator type is LDO */ 142 #define SYS_PLSTS_CURMVR_DCDC (0x1UL<<SYS_PLSTS_CURMVR_Pos) /*!< Main voltage regulator type is DCDC */ 143 144 145 /*---------------------------------------------------------------------------------------------------------*/ 146 /* SRAMPC0 constant definitions. (Write-Protection Register) */ 147 /*---------------------------------------------------------------------------------------------------------*/ 148 #define SYS_SRAMPC0_SRAM_NORMAL 0x0UL /*!< Select SRAM power mode to normal mode */ 149 #define SYS_SRAMPC0_SRAM_RETENTION 0x1UL /*!< Select SRAM power mode to retention mode */ 150 #define SYS_SRAMPC0_SRAM_POWER_SHUT_DOWN 0x2UL /*!< Select SRAM power mode to power shut down mode */ 151 152 /*---------------------------------------------------------------------------------------------------------*/ 153 /* SRAMPPC1 constant definitions. (Write-Protection Register) */ 154 /*---------------------------------------------------------------------------------------------------------*/ 155 #define SYS_SRAMPC1_SRAM_NORMAL 0x80000000UL /*!< Select SRAM power mode to normal mode */ 156 #define SYS_SRAMPC1_SRAM_RETENTION 0x80000001UL /*!< Select SRAM power mode to retention mode */ 157 #define SYS_SRAMPC1_SRAM_POWER_SHUT_DOWN 0x80000002UL /*!< Select SRAM power mode to power shut down mode */ 158 159 /*---------------------------------------------------------------------------------------------------------*/ 160 /* Multi-Function constant definitions. */ 161 /*---------------------------------------------------------------------------------------------------------*/ 162 163 /* How to use below #define? 164 165 Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial function, 166 user can issue following command to achieve it. 167 168 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk)) | SYS_GPA_MFPL_PA0MFP_UART0_RXD; 169 SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA1MFP_Msk)) | SYS_GPA_MFPL_PA1MFP_UART0_TXD; 170 */ 171 172 173 /* PA.0 MFP */ 174 #define SYS_GPA_MFPL_PA0MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for GPIO */ 175 #define SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 (0x3UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for QSPI0_MOSI0 */ 176 #define SYS_GPA_MFPL_PA0MFP_SPI0_MOSI (0x4UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SPI0_MOSI */ 177 #define SYS_GPA_MFPL_PA0MFP_LCD_COM6 (0x5UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for LCD_COM6 */ 178 #define SYS_GPA_MFPL_PA0MFP_LCD_SEG14 (0x5UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for LCD_SEG14 */ 179 #define SYS_GPA_MFPL_PA0MFP_SC0_CLK (0x6UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for SC0_CLK */ 180 #define SYS_GPA_MFPL_PA0MFP_UART0_RXD (0x7UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART0_RXD */ 181 #define SYS_GPA_MFPL_PA0MFP_UART1_nRTS (0x8UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for UART1_nRTS */ 182 #define SYS_GPA_MFPL_PA0MFP_I2C2_SDA (0x9UL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for I2C2_SDA */ 183 #define SYS_GPA_MFPL_PA0MFP_LCD_SEG24 (0xBUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for LCD_SEG24 */ 184 #define SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 (0xCUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for BPWM0_CH0 */ 185 #define SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 (0xDUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for EPWM0_CH5 */ 186 #define SYS_GPA_MFPL_PA0MFP_DAC0_ST (0xFUL<<SYS_GPA_MFPL_PA0MFP_Pos) /*!< GPA_MFPL PA0 setting for DAC0_ST */ 187 188 /* PA.1 MFP */ 189 #define SYS_GPA_MFPL_PA1MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for GPIO */ 190 #define SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 (0x3UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for QSPI0_MISO0 */ 191 #define SYS_GPA_MFPL_PA1MFP_SPI0_MISO (0x4UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SPI0_MISO */ 192 #define SYS_GPA_MFPL_PA1MFP_LCD_COM7 (0x5UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for LCD_COM7 */ 193 #define SYS_GPA_MFPL_PA1MFP_LCD_SEG13 (0x5UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for LCD_SEG13 */ 194 #define SYS_GPA_MFPL_PA1MFP_SC0_DAT (0x6UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for SC0_DAT */ 195 #define SYS_GPA_MFPL_PA1MFP_UART0_TXD (0x7UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART0_TXD */ 196 #define SYS_GPA_MFPL_PA1MFP_UART1_nCTS (0x8UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for UART1_nCTS */ 197 #define SYS_GPA_MFPL_PA1MFP_I2C2_SCL (0x9UL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for I2C2_SCL */ 198 #define SYS_GPA_MFPL_PA1MFP_LCD_SEG25 (0xBUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for LCD_SEG25 */ 199 #define SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 (0xCUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for BPWM0_CH1 */ 200 #define SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 (0xDUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for EPWM0_CH4 */ 201 #define SYS_GPA_MFPL_PA1MFP_DAC1_ST (0xFUL<<SYS_GPA_MFPL_PA1MFP_Pos) /*!< GPA_MFPL PA1 setting for DAC1_ST */ 202 203 /* PA.2 MFP */ 204 #define SYS_GPA_MFPL_PA2MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for GPIO */ 205 #define SYS_GPA_MFPL_PA2MFP_QSPI0_CLK (0x3UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for QSPI0_CLK */ 206 #define SYS_GPA_MFPL_PA2MFP_SPI0_CLK (0x4UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SPI0_CLK */ 207 #define SYS_GPA_MFPL_PA2MFP_LCD_SEG3 (0x5UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for LCD_SEG3 */ 208 #define SYS_GPA_MFPL_PA2MFP_SC0_RST (0x6UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for SC0_RST */ 209 #define SYS_GPA_MFPL_PA2MFP_UART4_RXD (0x7UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART4_RXD */ 210 #define SYS_GPA_MFPL_PA2MFP_UART1_RXD (0x8UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for UART1_RXD */ 211 #define SYS_GPA_MFPL_PA2MFP_I2C1_SDA (0x9UL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C1_SDA */ 212 #define SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS (0xAUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for I2C0_SMBSUS */ 213 #define SYS_GPA_MFPL_PA2MFP_LCD_SEG26 (0xBUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for LCD_SEG26 */ 214 #define SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 (0xCUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for BPWM0_CH2 */ 215 #define SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 (0xDUL<<SYS_GPA_MFPL_PA2MFP_Pos) /*!< GPA_MFPL PA2 setting for EPWM0_CH3 */ 216 217 /* PA.3 MFP */ 218 #define SYS_GPA_MFPL_PA3MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for GPIO */ 219 #define SYS_GPA_MFPL_PA3MFP_QSPI0_SS (0x3UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for QSPI0_SS */ 220 #define SYS_GPA_MFPL_PA3MFP_SPI0_SS (0x4UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SPI0_SS */ 221 #define SYS_GPA_MFPL_PA3MFP_LCD_SEG4 (0x5UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for LCD_SEG4 */ 222 #define SYS_GPA_MFPL_PA3MFP_SC0_PWR (0x6UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for SC0_PWR */ 223 #define SYS_GPA_MFPL_PA3MFP_UART4_TXD (0x7UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART4_TXD */ 224 #define SYS_GPA_MFPL_PA3MFP_UART1_TXD (0x8UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for UART1_TXD */ 225 #define SYS_GPA_MFPL_PA3MFP_I2C1_SCL (0x9UL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C1_SCL */ 226 #define SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL (0xAUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for I2C0_SMBAL */ 227 #define SYS_GPA_MFPL_PA3MFP_LCD_SEG27 (0xBUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for LCD_SEG27 */ 228 #define SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 (0xCUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for BPWM0_CH3 */ 229 #define SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 (0xDUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EPWM0_CH2 */ 230 #define SYS_GPA_MFPL_PA3MFP_QEI0_B (0xEUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for QEI0_B */ 231 #define SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1 (0xFUL<<SYS_GPA_MFPL_PA3MFP_Pos) /*!< GPA_MFPL PA3 setting for EPWM1_BRAKE1 */ 232 233 /* PA.4 MFP */ 234 #define SYS_GPA_MFPL_PA4MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for GPIO */ 235 #define SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 (0x3UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QSPI0_MOSI1 */ 236 #define SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK (0x4UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SPI0_I2SMCLK */ 237 #define SYS_GPA_MFPL_PA4MFP_LCD_SEG5 (0x5UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for LCD_SEG5 */ 238 #define SYS_GPA_MFPL_PA4MFP_SC0_nCD (0x6UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for SC0_nCD */ 239 #define SYS_GPA_MFPL_PA4MFP_UART0_nRTS (0x7UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART0_nRTS */ 240 #define SYS_GPA_MFPL_PA4MFP_UART5_RXD (0x8UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART5_RXD */ 241 #define SYS_GPA_MFPL_PA4MFP_I2C0_SDA (0x9UL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for I2C0_SDA */ 242 #define SYS_GPA_MFPL_PA4MFP_CAN0_RXD (0xAUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for CAN0_RXD */ 243 #define SYS_GPA_MFPL_PA4MFP_UART0_RXD (0xBUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for UART0_RXD */ 244 #define SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 (0xCUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for BPWM0_CH4 */ 245 #define SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 (0xDUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for EPWM0_CH1 */ 246 #define SYS_GPA_MFPL_PA4MFP_QEI0_A (0xEUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for QEI0_A */ 247 #define SYS_GPA_MFPL_PA4MFP_LCD_SEG28 (0xFUL<<SYS_GPA_MFPL_PA4MFP_Pos) /*!< GPA_MFPL PA4 setting for LCD_SEG28 */ 248 249 /* PA.5 MFP */ 250 #define SYS_GPA_MFPL_PA5MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for GPIO */ 251 #define SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 (0x3UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QSPI0_MISO1 */ 252 #define SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK (0x4UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SPI1_I2SMCLK */ 253 #define SYS_GPA_MFPL_PA5MFP_LCD_SEG6 (0x5UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for LCD_SEG6 */ 254 #define SYS_GPA_MFPL_PA5MFP_SC2_nCD (0x6UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for SC2_nCD */ 255 #define SYS_GPA_MFPL_PA5MFP_UART0_nCTS (0x7UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART0_nCTS */ 256 #define SYS_GPA_MFPL_PA5MFP_UART5_TXD (0x8UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART5_TXD */ 257 #define SYS_GPA_MFPL_PA5MFP_I2C0_SCL (0x9UL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for I2C0_SCL */ 258 #define SYS_GPA_MFPL_PA5MFP_CAN0_TXD (0xAUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for CAN0_TXD */ 259 #define SYS_GPA_MFPL_PA5MFP_UART0_TXD (0xBUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for UART0_TXD */ 260 #define SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 (0xCUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for BPWM0_CH5 */ 261 #define SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 (0xDUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for EPWM0_CH0 */ 262 #define SYS_GPA_MFPL_PA5MFP_QEI0_INDEX (0xEUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for QEI0_INDEX */ 263 #define SYS_GPA_MFPL_PA5MFP_LCD_SEG29 (0xFUL<<SYS_GPA_MFPL_PA5MFP_Pos) /*!< GPA_MFPL PA5 setting for LCD_SEG29 */ 264 265 /* PA.6 MFP */ 266 #define SYS_GPA_MFPL_PA6MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for GPIO */ 267 #define SYS_GPA_MFPL_PA6MFP_EBI_AD6 (0x2UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EBI_AD6 */ 268 #define SYS_GPA_MFPL_PA6MFP_SPI1_SS (0x4UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SPI1_SS */ 269 #define SYS_GPA_MFPL_PA6MFP_SC2_CLK (0x6UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for SC2_CLK */ 270 #define SYS_GPA_MFPL_PA6MFP_UART0_RXD (0x7UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for UART0_RXD */ 271 #define SYS_GPA_MFPL_PA6MFP_I2C1_SDA (0x8UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for I2C1_SDA */ 272 #define SYS_GPA_MFPL_PA6MFP_LCD_SEG7 (0x9UL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for LCD_SEG7 */ 273 #define SYS_GPA_MFPL_PA6MFP_TM5 (0xAUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for TM5 */ 274 #define SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 (0xBUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for EPWM1_CH5 */ 275 #define SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 (0xCUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for BPWM1_CH3 */ 276 #define SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT (0xDUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for ACMP1_WLAT */ 277 #define SYS_GPA_MFPL_PA6MFP_TM3 (0xEUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for TM3 */ 278 #define SYS_GPA_MFPL_PA6MFP_INT0 (0xFUL<<SYS_GPA_MFPL_PA6MFP_Pos) /*!< GPA_MFPL PA6 setting for INT0 */ 279 280 /* PA.7 MFP */ 281 #define SYS_GPA_MFPL_PA7MFP_GPIO (0x0UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for GPIO */ 282 #define SYS_GPA_MFPL_PA7MFP_EBI_AD7 (0x2UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EBI_AD7 */ 283 #define SYS_GPA_MFPL_PA7MFP_SPI1_CLK (0x4UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SPI1_CLK */ 284 #define SYS_GPA_MFPL_PA7MFP_SC2_DAT (0x6UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for SC2_DAT */ 285 #define SYS_GPA_MFPL_PA7MFP_UART0_TXD (0x7UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for UART0_TXD */ 286 #define SYS_GPA_MFPL_PA7MFP_I2C1_SCL (0x8UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for I2C1_SCL */ 287 #define SYS_GPA_MFPL_PA7MFP_LCD_SEG8 (0x9UL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for LCD_SEG8 */ 288 #define SYS_GPA_MFPL_PA7MFP_TM4 (0xAUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for TM4 */ 289 #define SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 (0xBUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for EPWM1_CH4 */ 290 #define SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 (0xCUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for BPWM1_CH2 */ 291 #define SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT (0xDUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for ACMP0_WLAT */ 292 #define SYS_GPA_MFPL_PA7MFP_TM2 (0xEUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for TM2 */ 293 #define SYS_GPA_MFPL_PA7MFP_INT1 (0xFUL<<SYS_GPA_MFPL_PA7MFP_Pos) /*!< GPA_MFPL PA7 setting for INT1 */ 294 295 /* PA.8 MFP */ 296 #define SYS_GPA_MFPH_PA8MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for GPIO */ 297 #define SYS_GPA_MFPH_PA8MFP_EBI_ALE (0x2UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for EBI_ALE */ 298 #define SYS_GPA_MFPH_PA8MFP_SC2_CLK (0x3UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SC2_CLK */ 299 #define SYS_GPA_MFPH_PA8MFP_SPI2_MOSI (0x4UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for SPI2_MOSI */ 300 #define SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 (0x6UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for USCI0_CTL1 */ 301 #define SYS_GPA_MFPH_PA8MFP_UART1_RXD (0x7UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for UART1_RXD */ 302 #define SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 (0x9UL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for BPWM0_CH3 */ 303 #define SYS_GPA_MFPH_PA8MFP_QEI1_B (0xAUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for QEI1_B */ 304 #define SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 (0xBUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for ECAP0_IC2 */ 305 #define SYS_GPA_MFPH_PA8MFP_TM5_EXT (0xCUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for TM5_EXT */ 306 #define SYS_GPA_MFPH_PA8MFP_TM3_EXT (0xDUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for TM3_EXT */ 307 #define SYS_GPA_MFPH_PA8MFP_LCD_SEG11 (0xEUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for LCD_SEG11 */ 308 #define SYS_GPA_MFPH_PA8MFP_INT4 (0xFUL<<SYS_GPA_MFPH_PA8MFP_Pos) /*!< GPA_MFPH PA8 setting for INT4 */ 309 310 /* PA.9 MFP */ 311 #define SYS_GPA_MFPH_PA9MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for GPIO */ 312 #define SYS_GPA_MFPH_PA9MFP_EBI_MCLK (0x2UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for EBI_MCLK */ 313 #define SYS_GPA_MFPH_PA9MFP_SC2_DAT (0x3UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SC2_DAT */ 314 #define SYS_GPA_MFPH_PA9MFP_SPI2_MISO (0x4UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for SPI2_MISO */ 315 #define SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 (0x6UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for USCI0_DAT1 */ 316 #define SYS_GPA_MFPH_PA9MFP_UART1_TXD (0x7UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for UART1_TXD */ 317 #define SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 (0x9UL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for BPWM0_CH2 */ 318 #define SYS_GPA_MFPH_PA9MFP_QEI1_A (0xAUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for QEI1_A */ 319 #define SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 (0xBUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for ECAP0_IC1 */ 320 #define SYS_GPA_MFPH_PA9MFP_TM4_EXT (0xCUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for TM4_EXT */ 321 #define SYS_GPA_MFPH_PA9MFP_TM2_EXT (0xDUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for TM2_EXT */ 322 #define SYS_GPA_MFPH_PA9MFP_LCD_SEG12 (0xEUL<<SYS_GPA_MFPH_PA9MFP_Pos) /*!< GPA_MFPH PA9 setting for LCD_SEG12 */ 323 324 /* PA.10 MFP */ 325 #define SYS_GPA_MFPH_PA10MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for GPIO */ 326 #define SYS_GPA_MFPH_PA10MFP_ACMP1_P0 (0x1UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for ACMP1_P0 */ 327 #define SYS_GPA_MFPH_PA10MFP_EBI_nWR (0x2UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for EBI_nWR */ 328 #define SYS_GPA_MFPH_PA10MFP_SC2_RST (0x3UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for SC2_RST */ 329 #define SYS_GPA_MFPH_PA10MFP_SPI2_CLK (0x4UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for SPI2_CLK */ 330 #define SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 (0x6UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for USCI0_DAT0 */ 331 #define SYS_GPA_MFPH_PA10MFP_I2C2_SDA (0x7UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for I2C2_SDA */ 332 #define SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 (0x9UL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for BPWM0_CH1 */ 333 #define SYS_GPA_MFPH_PA10MFP_QEI1_INDEX (0xAUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for QEI1_INDEX */ 334 #define SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 (0xBUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for ECAP0_IC0 */ 335 #define SYS_GPA_MFPH_PA10MFP_TM1_EXT (0xDUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for TM1_EXT */ 336 #define SYS_GPA_MFPH_PA10MFP_DAC0_ST (0xEUL<<SYS_GPA_MFPH_PA10MFP_Pos) /*!< GPA_MFPH PA10 setting for DAC0_ST */ 337 338 /* PA.11 MFP */ 339 #define SYS_GPA_MFPH_PA11MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for GPIO */ 340 #define SYS_GPA_MFPH_PA11MFP_ACMP0_P0 (0x1UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for ACMP0_P0 */ 341 #define SYS_GPA_MFPH_PA11MFP_EBI_nRD (0x2UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for EBI_nRD */ 342 #define SYS_GPA_MFPH_PA11MFP_SC2_PWR (0x3UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for SC2_PWR */ 343 #define SYS_GPA_MFPH_PA11MFP_SPI2_SS (0x4UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for SPI2_SS */ 344 #define SYS_GPA_MFPH_PA11MFP_USCI0_CLK (0x6UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for USCI0_CLK */ 345 #define SYS_GPA_MFPH_PA11MFP_I2C2_SCL (0x7UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for I2C2_SCL */ 346 #define SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 (0x9UL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for BPWM0_CH0 */ 347 #define SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT (0xAUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for EPWM0_SYNC_OUT */ 348 #define SYS_GPA_MFPH_PA11MFP_TM0_EXT (0xDUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for TM0_EXT */ 349 #define SYS_GPA_MFPH_PA11MFP_DAC1_ST (0xEUL<<SYS_GPA_MFPH_PA11MFP_Pos) /*!< GPA_MFPH PA11 setting for DAC1_ST */ 350 351 /* PA.12 MFP */ 352 #define SYS_GPA_MFPH_PA12MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for GPIO */ 353 #define SYS_GPA_MFPH_PA12MFP_I2S0_BCLK (0x2UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for I2S0_BCLK */ 354 #define SYS_GPA_MFPH_PA12MFP_UART4_TXD (0x3UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for UART4_TXD */ 355 #define SYS_GPA_MFPH_PA12MFP_I2C1_SCL (0x4UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for I2C1_SCL */ 356 #define SYS_GPA_MFPH_PA12MFP_SPI2_SS (0x5UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SPI2_SS */ 357 #define SYS_GPA_MFPH_PA12MFP_CAN0_TXD (0x6UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for CAN0_TXD */ 358 #define SYS_GPA_MFPH_PA12MFP_SC2_PWR (0x7UL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for SC2_PWR */ 359 #define SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 (0xBUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for BPWM1_CH2 */ 360 #define SYS_GPA_MFPH_PA12MFP_QEI1_INDEX (0xCUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for QEI1_INDEX */ 361 #define SYS_GPA_MFPH_PA12MFP_USB_VBUS (0xEUL<<SYS_GPA_MFPH_PA12MFP_Pos) /*!< GPA_MFPH PA12 setting for USB_VBUS */ 362 363 /* PA.13 MFP */ 364 #define SYS_GPA_MFPH_PA13MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for GPIO */ 365 #define SYS_GPA_MFPH_PA13MFP_I2S0_MCLK (0x2UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for I2S0_MCLK */ 366 #define SYS_GPA_MFPH_PA13MFP_UART4_RXD (0x3UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for UART4_RXD */ 367 #define SYS_GPA_MFPH_PA13MFP_I2C1_SDA (0x4UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for I2C1_SDA */ 368 #define SYS_GPA_MFPH_PA13MFP_SPI2_CLK (0x5UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for SPI2_CLK */ 369 #define SYS_GPA_MFPH_PA13MFP_CAN0_RXD (0x6UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for CAN0_RXD */ 370 #define SYS_GPA_MFPH_PA13MFP_SC2_RST (0x7UL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for SC2_RST */ 371 #define SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 (0xBUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for BPWM1_CH3 */ 372 #define SYS_GPA_MFPH_PA13MFP_QEI1_A (0xCUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for QEI1_A */ 373 #define SYS_GPA_MFPH_PA13MFP_USB_D_N (0xEUL<<SYS_GPA_MFPH_PA13MFP_Pos) /*!< GPA_MFPH PA13 setting for USB_D_N */ 374 375 /* PA.14 MFP */ 376 #define SYS_GPA_MFPH_PA14MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for GPIO */ 377 #define SYS_GPA_MFPH_PA14MFP_I2S0_DI (0x2UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for I2S0_DI */ 378 #define SYS_GPA_MFPH_PA14MFP_UART0_TXD (0x3UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for UART0_TXD */ 379 #define SYS_GPA_MFPH_PA14MFP_SPI2_MISO (0x5UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for SPI2_MISO */ 380 #define SYS_GPA_MFPH_PA14MFP_I2C2_SCL (0x6UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for I2C2_SCL */ 381 #define SYS_GPA_MFPH_PA14MFP_SC2_DAT (0x7UL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for SC2_DAT */ 382 #define SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 (0xBUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for BPWM1_CH4 */ 383 #define SYS_GPA_MFPH_PA14MFP_QEI1_B (0xCUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for QEI1_B */ 384 #define SYS_GPA_MFPH_PA14MFP_USB_D_P (0xEUL<<SYS_GPA_MFPH_PA14MFP_Pos) /*!< GPA_MFPH PA14 setting for USB_D_P */ 385 386 /* PA.15 MFP */ 387 #define SYS_GPA_MFPH_PA15MFP_GPIO (0x0UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for GPIO */ 388 #define SYS_GPA_MFPH_PA15MFP_I2S0_DO (0x2UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2S0_DO */ 389 #define SYS_GPA_MFPH_PA15MFP_UART0_RXD (0x3UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for UART0_RXD */ 390 #define SYS_GPA_MFPH_PA15MFP_SPI2_MOSI (0x5UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for SPI2_MOSI */ 391 #define SYS_GPA_MFPH_PA15MFP_I2C2_SDA (0x6UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for I2C2_SDA */ 392 #define SYS_GPA_MFPH_PA15MFP_SC2_CLK (0x7UL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for SC2_CLK */ 393 #define SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 (0xBUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for BPWM1_CH5 */ 394 #define SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN (0xCUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for EPWM0_SYNC_IN */ 395 #define SYS_GPA_MFPH_PA15MFP_USB_OTG_ID (0xEUL<<SYS_GPA_MFPH_PA15MFP_Pos) /*!< GPA_MFPH PA15 setting for USB_OTG_ID */ 396 397 /* PB.0 MFP */ 398 #define SYS_GPB_MFPL_PB0MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for GPIO */ 399 #define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x1UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC0_CH0 */ 400 #define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x2UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_ADR9 */ 401 #define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x3UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SD0_CMD */ 402 #define SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK (0x4UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI2_I2SMCLK */ 403 #define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x7UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD */ 404 #define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x8UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK */ 405 #define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x9UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C1_SDA */ 406 #define SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 (0xBUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM0_CH5 */ 407 #define SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 (0xCUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM1_CH5 */ 408 #define SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 (0xDUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EPWM0_BRAKE1 */ 409 #define SYS_GPB_MFPL_PB0MFP_QSPI0_MOSI1 (0xFUL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for QSPI0_MOSI1 */ 410 411 /* PB.1 MFP */ 412 #define SYS_GPB_MFPL_PB1MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for GPIO */ 413 #define SYS_GPB_MFPL_PB1MFP_EADC0_CH1 (0x1UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EADC0_CH1 */ 414 #define SYS_GPB_MFPL_PB1MFP_EBI_ADR8 (0x2UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EBI_ADR8 */ 415 #define SYS_GPB_MFPL_PB1MFP_SD0_CLK (0x3UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SD0_CLK */ 416 #define SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK (0x5UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI1_I2SMCLK */ 417 #define SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK (0x6UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for SPI3_I2SMCLK */ 418 #define SYS_GPB_MFPL_PB1MFP_UART2_TXD (0x7UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for UART2_TXD */ 419 #define SYS_GPB_MFPL_PB1MFP_USCI1_CLK (0x8UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for USCI1_CLK */ 420 #define SYS_GPB_MFPL_PB1MFP_I2C1_SCL (0x9UL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2C1_SCL */ 421 #define SYS_GPB_MFPL_PB1MFP_I2S0_LRCK (0xAUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for I2S0_LRCK */ 422 #define SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 (0xBUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM0_CH4 */ 423 #define SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 (0xCUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM1_CH4 */ 424 #define SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 (0xDUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for EPWM0_BRAKE0 */ 425 #define SYS_GPB_MFPL_PB1MFP_QSPI0_MISO1 (0xFUL<<SYS_GPB_MFPL_PB1MFP_Pos) /*!< GPB_MFPL PB1 setting for QSPI0_MISO1 */ 426 427 /* PB.2 MFP */ 428 #define SYS_GPB_MFPL_PB2MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for GPIO */ 429 #define SYS_GPB_MFPL_PB2MFP_ACMP0_P1 (0x1UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for ACMP0_P1 */ 430 #define SYS_GPB_MFPL_PB2MFP_EADC0_CH2 (0x1UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EADC0_CH2 */ 431 #define SYS_GPB_MFPL_PB2MFP_EBI_ADR3 (0x2UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EBI_ADR3 */ 432 #define SYS_GPB_MFPL_PB2MFP_SD0_DAT0 (0x3UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SD0_DAT0 */ 433 #define SYS_GPB_MFPL_PB2MFP_SPI1_SS (0x5UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SPI1_SS */ 434 #define SYS_GPB_MFPL_PB2MFP_UART1_RXD (0x6UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART1_RXD */ 435 #define SYS_GPB_MFPL_PB2MFP_UART5_nCTS (0x7UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for UART5_nCTS */ 436 #define SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 (0x8UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for USCI1_DAT0 */ 437 #define SYS_GPB_MFPL_PB2MFP_SC0_PWR (0x9UL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for SC0_PWR */ 438 #define SYS_GPB_MFPL_PB2MFP_I2S0_DO (0xAUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for I2S0_DO */ 439 #define SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 (0xBUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for EPWM0_CH3 */ 440 #define SYS_GPB_MFPL_PB2MFP_I2C1_SDA (0xCUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for I2C1_SDA */ 441 #define SYS_GPB_MFPL_PB2MFP_TM5 (0xDUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for TM5 */ 442 #define SYS_GPB_MFPL_PB2MFP_TM3 (0xEUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for TM3 */ 443 #define SYS_GPB_MFPL_PB2MFP_INT3 (0xFUL<<SYS_GPB_MFPL_PB2MFP_Pos) /*!< GPB_MFPL PB2 setting for INT3 */ 444 445 /* PB.3 MFP */ 446 #define SYS_GPB_MFPL_PB3MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for GPIO */ 447 #define SYS_GPB_MFPL_PB3MFP_ACMP0_N (0x1UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for ACMP0_N */ 448 #define SYS_GPB_MFPL_PB3MFP_EADC0_CH3 (0x1UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EADC0_CH3 */ 449 #define SYS_GPB_MFPL_PB3MFP_EBI_ADR2 (0x2UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EBI_ADR2 */ 450 #define SYS_GPB_MFPL_PB3MFP_SD0_DAT1 (0x3UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SD0_DAT1 */ 451 #define SYS_GPB_MFPL_PB3MFP_SPI1_CLK (0x5UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SPI1_CLK */ 452 #define SYS_GPB_MFPL_PB3MFP_UART1_TXD (0x6UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART1_TXD */ 453 #define SYS_GPB_MFPL_PB3MFP_UART5_nRTS (0x7UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for UART5_nRTS */ 454 #define SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 (0x8UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for USCI1_DAT1 */ 455 #define SYS_GPB_MFPL_PB3MFP_SC0_RST (0x9UL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for SC0_RST */ 456 #define SYS_GPB_MFPL_PB3MFP_I2S0_DI (0xAUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for I2S0_DI */ 457 #define SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 (0xBUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for EPWM0_CH2 */ 458 #define SYS_GPB_MFPL_PB3MFP_I2C1_SCL (0xCUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for I2C1_SCL */ 459 #define SYS_GPB_MFPL_PB3MFP_TM4 (0xDUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for TM4 */ 460 #define SYS_GPB_MFPL_PB3MFP_TM2 (0xEUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for TM2 */ 461 #define SYS_GPB_MFPL_PB3MFP_INT2 (0xFUL<<SYS_GPB_MFPL_PB3MFP_Pos) /*!< GPB_MFPL PB3 setting for INT2 */ 462 463 /* PB.4 MFP */ 464 #define SYS_GPB_MFPL_PB4MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for GPIO */ 465 #define SYS_GPB_MFPL_PB4MFP_ACMP1_P1 (0x1UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for ACMP1_P1 */ 466 #define SYS_GPB_MFPL_PB4MFP_EADC0_CH4 (0x1UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EADC0_CH4 */ 467 #define SYS_GPB_MFPL_PB4MFP_EBI_ADR1 (0x2UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EBI_ADR1 */ 468 #define SYS_GPB_MFPL_PB4MFP_SD0_DAT2 (0x3UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SD0_DAT2 */ 469 #define SYS_GPB_MFPL_PB4MFP_SPI1_MOSI (0x5UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SPI1_MOSI */ 470 #define SYS_GPB_MFPL_PB4MFP_I2C0_SDA (0x6UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for I2C0_SDA */ 471 #define SYS_GPB_MFPL_PB4MFP_UART5_RXD (0x7UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART5_RXD */ 472 #define SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 (0x8UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for USCI1_CTL1 */ 473 #define SYS_GPB_MFPL_PB4MFP_SC0_DAT (0x9UL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for SC0_DAT */ 474 #define SYS_GPB_MFPL_PB4MFP_I2S0_MCLK (0xAUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for I2S0_MCLK */ 475 #define SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 (0xBUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for EPWM0_CH1 */ 476 #define SYS_GPB_MFPL_PB4MFP_UART2_RXD (0xCUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for UART2_RXD */ 477 #define SYS_GPB_MFPL_PB4MFP_TM1 (0xEUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for TM1 */ 478 #define SYS_GPB_MFPL_PB4MFP_INT1 (0xFUL<<SYS_GPB_MFPL_PB4MFP_Pos) /*!< GPB_MFPL PB4 setting for INT1 */ 479 480 /* PB.5 MFP */ 481 #define SYS_GPB_MFPL_PB5MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for GPIO */ 482 #define SYS_GPB_MFPL_PB5MFP_ACMP1_N (0x1UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for ACMP1_N */ 483 #define SYS_GPB_MFPL_PB5MFP_EADC0_CH5 (0x1UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EADC0_CH5 */ 484 #define SYS_GPB_MFPL_PB5MFP_EBI_ADR0 (0x2UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EBI_ADR0 */ 485 #define SYS_GPB_MFPL_PB5MFP_SD0_DAT3 (0x3UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SD0_DAT3 */ 486 #define SYS_GPB_MFPL_PB5MFP_SPI1_MISO (0x5UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SPI1_MISO */ 487 #define SYS_GPB_MFPL_PB5MFP_I2C0_SCL (0x6UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for I2C0_SCL */ 488 #define SYS_GPB_MFPL_PB5MFP_UART5_TXD (0x7UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART5_TXD */ 489 #define SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 (0x8UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for USCI1_CTL0 */ 490 #define SYS_GPB_MFPL_PB5MFP_SC0_CLK (0x9UL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for SC0_CLK */ 491 #define SYS_GPB_MFPL_PB5MFP_I2S0_BCLK (0xAUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for I2S0_BCLK */ 492 #define SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 (0xBUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for EPWM0_CH0 */ 493 #define SYS_GPB_MFPL_PB5MFP_UART2_TXD (0xCUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for UART2_TXD */ 494 #define SYS_GPB_MFPL_PB5MFP_TM0 (0xEUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for TM0 */ 495 #define SYS_GPB_MFPL_PB5MFP_INT0 (0xFUL<<SYS_GPB_MFPL_PB5MFP_Pos) /*!< GPB_MFPL PB5 setting for INT0 */ 496 497 /* PB.6 MFP */ 498 #define SYS_GPB_MFPL_PB6MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for GPIO */ 499 #define SYS_GPB_MFPL_PB6MFP_EADC0_CH6 (0x1UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EADC0_CH6 */ 500 #define SYS_GPB_MFPL_PB6MFP_EBI_nWRH (0x2UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nWRH */ 501 #define SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 (0x4UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for USCI1_DAT1 */ 502 #define SYS_GPB_MFPL_PB6MFP_UART1_RXD (0x6UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for UART1_RXD */ 503 #define SYS_GPB_MFPL_PB6MFP_EBI_nCS1 (0x8UL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EBI_nCS1 */ 504 #define SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 (0xAUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for BPWM1_CH5 */ 505 #define SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 (0xBUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_BRAKE1 */ 506 #define SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 (0xCUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for EPWM1_CH5 */ 507 #define SYS_GPB_MFPL_PB6MFP_INT4 (0xDUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for INT4 */ 508 #define SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN (0xEUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for USB_VBUS_EN */ 509 #define SYS_GPB_MFPL_PB6MFP_ACMP1_O (0xFUL<<SYS_GPB_MFPL_PB6MFP_Pos) /*!< GPB_MFPL PB6 setting for ACMP1_O */ 510 511 /* PB.7 MFP */ 512 #define SYS_GPB_MFPL_PB7MFP_GPIO (0x0UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for GPIO */ 513 #define SYS_GPB_MFPL_PB7MFP_EADC0_CH7 (0x1UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EADC0_CH7 */ 514 #define SYS_GPB_MFPL_PB7MFP_EBI_nWRL (0x2UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nWRL */ 515 #define SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 (0x4UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for USCI1_DAT0 */ 516 #define SYS_GPB_MFPL_PB7MFP_UART1_TXD (0x6UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for UART1_TXD */ 517 #define SYS_GPB_MFPL_PB7MFP_EBI_nCS0 (0x8UL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EBI_nCS0 */ 518 #define SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 (0xAUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for BPWM1_CH4 */ 519 #define SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 (0xBUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_BRAKE0 */ 520 #define SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 (0xCUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for EPWM1_CH4 */ 521 #define SYS_GPB_MFPL_PB7MFP_INT5 (0xDUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for INT5 */ 522 #define SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST (0xEUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for USB_VBUS_ST */ 523 #define SYS_GPB_MFPL_PB7MFP_ACMP0_O (0xFUL<<SYS_GPB_MFPL_PB7MFP_Pos) /*!< GPB_MFPL PB7 setting for ACMP0_O */ 524 525 /* PB.8 MFP */ 526 #define SYS_GPB_MFPH_PB8MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for GPIO */ 527 #define SYS_GPB_MFPH_PB8MFP_EADC0_CH8 (0x1UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EADC0_CH8 */ 528 #define SYS_GPB_MFPH_PB8MFP_EBI_ADR19 (0x2UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for EBI_ADR19 */ 529 #define SYS_GPB_MFPH_PB8MFP_USCI1_CLK (0x4UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for USCI1_CLK */ 530 #define SYS_GPB_MFPH_PB8MFP_UART0_RXD (0x5UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART0_RXD */ 531 #define SYS_GPB_MFPH_PB8MFP_UART1_nRTS (0x6UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for UART1_nRTS */ 532 #define SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS (0x7UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for I2C1_SMBSUS */ 533 #define SYS_GPB_MFPH_PB8MFP_I2C0_SDA (0x9UL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for I2C0_SDA */ 534 #define SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 (0xAUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for BPWM1_CH3 */ 535 #define SYS_GPB_MFPH_PB8MFP_SPI3_MOSI (0xBUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for SPI3_MOSI */ 536 #define SYS_GPB_MFPH_PB8MFP_INT6 (0xDUL<<SYS_GPB_MFPH_PB8MFP_Pos) /*!< GPB_MFPH PB8 setting for INT6 */ 537 538 /* PB.9 MFP */ 539 #define SYS_GPB_MFPH_PB9MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for GPIO */ 540 #define SYS_GPB_MFPH_PB9MFP_EADC0_CH9 (0x1UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EADC0_CH9 */ 541 #define SYS_GPB_MFPH_PB9MFP_EBI_ADR18 (0x2UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for EBI_ADR18 */ 542 #define SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 (0x4UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for USCI1_CTL1 */ 543 #define SYS_GPB_MFPH_PB9MFP_UART0_TXD (0x5UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART0_TXD */ 544 #define SYS_GPB_MFPH_PB9MFP_UART1_nCTS (0x6UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for UART1_nCTS */ 545 #define SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL (0x7UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for I2C1_SMBAL */ 546 #define SYS_GPB_MFPH_PB9MFP_I2C0_SCL (0x9UL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for I2C0_SCL */ 547 #define SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 (0xAUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for BPWM1_CH2 */ 548 #define SYS_GPB_MFPH_PB9MFP_SPI3_MISO (0xBUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for SPI3_MISO */ 549 #define SYS_GPB_MFPH_PB9MFP_INT7 (0xDUL<<SYS_GPB_MFPH_PB9MFP_Pos) /*!< GPB_MFPH PB9 setting for INT7 */ 550 551 /* PB.10 MFP */ 552 #define SYS_GPB_MFPH_PB10MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for GPIO */ 553 #define SYS_GPB_MFPH_PB10MFP_EADC0_CH10 (0x1UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for EADC0_CH10 */ 554 #define SYS_GPB_MFPH_PB10MFP_EBI_ADR17 (0x2UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for EBI_ADR17 */ 555 #define SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 (0x4UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for USCI1_CTL0 */ 556 #define SYS_GPB_MFPH_PB10MFP_UART0_nRTS (0x5UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for UART0_nRTS */ 557 #define SYS_GPB_MFPH_PB10MFP_UART4_RXD (0x6UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for UART4_RXD */ 558 #define SYS_GPB_MFPH_PB10MFP_I2C1_SDA (0x7UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for I2C1_SDA */ 559 #define SYS_GPB_MFPH_PB10MFP_CAN0_RXD (0x8UL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for CAN0_RXD */ 560 #define SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 (0xAUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for BPWM1_CH1 */ 561 #define SYS_GPB_MFPH_PB10MFP_SPI3_SS (0xBUL<<SYS_GPB_MFPH_PB10MFP_Pos) /*!< GPB_MFPH PB10 setting for SPI3_SS */ 562 563 /* PB.11 MFP */ 564 #define SYS_GPB_MFPH_PB11MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for GPIO */ 565 #define SYS_GPB_MFPH_PB11MFP_EADC0_CH11 (0x1UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for EADC0_CH11 */ 566 #define SYS_GPB_MFPH_PB11MFP_EBI_ADR16 (0x2UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for EBI_ADR16 */ 567 #define SYS_GPB_MFPH_PB11MFP_UART0_nCTS (0x5UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for UART0_nCTS */ 568 #define SYS_GPB_MFPH_PB11MFP_UART4_TXD (0x6UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for UART4_TXD */ 569 #define SYS_GPB_MFPH_PB11MFP_I2C1_SCL (0x7UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for I2C1_SCL */ 570 #define SYS_GPB_MFPH_PB11MFP_CAN0_TXD (0x8UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for CAN0_TXD */ 571 #define SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK (0x9UL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for SPI0_I2SMCLK */ 572 #define SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 (0xAUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for BPWM1_CH0 */ 573 #define SYS_GPB_MFPH_PB11MFP_SPI3_CLK (0xBUL<<SYS_GPB_MFPH_PB11MFP_Pos) /*!< GPB_MFPH PB11 setting for SPI3_CLK */ 574 575 /* PB.12 MFP */ 576 #define SYS_GPB_MFPH_PB12MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for GPIO */ 577 #define SYS_GPB_MFPH_PB12MFP_ACMP0_P2 (0x1UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for ACMP0_P2 */ 578 #define SYS_GPB_MFPH_PB12MFP_ACMP1_P2 (0x1UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for ACMP1_P2 */ 579 #define SYS_GPB_MFPH_PB12MFP_DAC0_OUT (0x1UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for DAC0_OUT */ 580 #define SYS_GPB_MFPH_PB12MFP_EADC0_CH12 (0x1UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for EADC0_CH12 */ 581 #define SYS_GPB_MFPH_PB12MFP_EBI_AD15 (0x2UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for EBI_AD15 */ 582 #define SYS_GPB_MFPH_PB12MFP_SC1_CLK (0x3UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for SC1_CLK */ 583 #define SYS_GPB_MFPH_PB12MFP_SPI0_MOSI (0x4UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for SPI0_MOSI */ 584 #define SYS_GPB_MFPH_PB12MFP_USCI0_CLK (0x5UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for USCI0_CLK */ 585 #define SYS_GPB_MFPH_PB12MFP_UART0_RXD (0x6UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for UART0_RXD */ 586 #define SYS_GPB_MFPH_PB12MFP_UART3_nCTS (0x7UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for UART3_nCTS */ 587 #define SYS_GPB_MFPH_PB12MFP_I2C2_SDA (0x8UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for I2C2_SDA */ 588 #define SYS_GPB_MFPH_PB12MFP_SD0_nCD (0x9UL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for SD0_nCD */ 589 #define SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 (0xBUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for EPWM1_CH3 */ 590 #define SYS_GPB_MFPH_PB12MFP_TM3_EXT (0xDUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for TM3_EXT */ 591 #define SYS_GPB_MFPH_PB12MFP_TM5_EXT (0xEUL<<SYS_GPB_MFPH_PB12MFP_Pos) /*!< GPB_MFPH PB12 setting for TM5_EXT */ 592 593 /* PB.13 MFP */ 594 #define SYS_GPB_MFPH_PB13MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for GPIO */ 595 #define SYS_GPB_MFPH_PB13MFP_ACMP0_P3 (0x1UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for ACMP0_P3 */ 596 #define SYS_GPB_MFPH_PB13MFP_ACMP1_P3 (0x1UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for ACMP1_P3 */ 597 #define SYS_GPB_MFPH_PB13MFP_DAC1_OUT (0x1UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for DAC1_OUT */ 598 #define SYS_GPB_MFPH_PB13MFP_EADC0_CH13 (0x1UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EADC0_CH13 */ 599 #define SYS_GPB_MFPH_PB13MFP_EBI_AD14 (0x2UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EBI_AD14 */ 600 #define SYS_GPB_MFPH_PB13MFP_SC1_DAT (0x3UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for SC1_DAT */ 601 #define SYS_GPB_MFPH_PB13MFP_SPI0_MISO (0x4UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for SPI0_MISO */ 602 #define SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 (0x5UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for USCI0_DAT0 */ 603 #define SYS_GPB_MFPH_PB13MFP_UART0_TXD (0x6UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for UART0_TXD */ 604 #define SYS_GPB_MFPH_PB13MFP_UART3_nRTS (0x7UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for UART3_nRTS */ 605 #define SYS_GPB_MFPH_PB13MFP_I2C2_SCL (0x8UL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for I2C2_SCL */ 606 #define SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 (0xBUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for EPWM1_CH2 */ 607 #define SYS_GPB_MFPH_PB13MFP_TM2_EXT (0xDUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for TM2_EXT */ 608 #define SYS_GPB_MFPH_PB13MFP_TM4_EXT (0xEUL<<SYS_GPB_MFPH_PB13MFP_Pos) /*!< GPB_MFPH PB13 setting for TM4_EXT */ 609 610 /* PB.14 MFP */ 611 #define SYS_GPB_MFPH_PB14MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for GPIO */ 612 #define SYS_GPB_MFPH_PB14MFP_EADC0_CH14 (0x1UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EADC0_CH14 */ 613 #define SYS_GPB_MFPH_PB14MFP_EBI_AD13 (0x2UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EBI_AD13 */ 614 #define SYS_GPB_MFPH_PB14MFP_SC1_RST (0x3UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for SC1_RST */ 615 #define SYS_GPB_MFPH_PB14MFP_SPI0_CLK (0x4UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for SPI0_CLK */ 616 #define SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 (0x5UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for USCI0_DAT1 */ 617 #define SYS_GPB_MFPH_PB14MFP_UART0_nRTS (0x6UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for UART0_nRTS */ 618 #define SYS_GPB_MFPH_PB14MFP_UART3_RXD (0x7UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for UART3_RXD */ 619 #define SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS (0x8UL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for I2C2_SMBSUS */ 620 #define SYS_GPB_MFPH_PB14MFP_EPWM0_BRAKE1 (0xAUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EPWM0_BRAKE1 */ 621 #define SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 (0xBUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for EPWM1_CH1 */ 622 #define SYS_GPB_MFPH_PB14MFP_TM1_EXT (0xDUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for TM1_EXT */ 623 #define SYS_GPB_MFPH_PB14MFP_CLKO (0xEUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for CLKO */ 624 #define SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST (0xFUL<<SYS_GPB_MFPH_PB14MFP_Pos) /*!< GPB_MFPH PB14 setting for USB_VBUS_ST */ 625 626 /* PB.15 MFP */ 627 #define SYS_GPB_MFPH_PB15MFP_GPIO (0x0UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for GPIO */ 628 #define SYS_GPB_MFPH_PB15MFP_EADC0_CH15 (0x1UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EADC0_CH15 */ 629 #define SYS_GPB_MFPH_PB15MFP_EBI_AD12 (0x2UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EBI_AD12 */ 630 #define SYS_GPB_MFPH_PB15MFP_SC1_PWR (0x3UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for SC1_PWR */ 631 #define SYS_GPB_MFPH_PB15MFP_SPI0_SS (0x4UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for SPI0_SS */ 632 #define SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 (0x5UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for USCI0_CTL1 */ 633 #define SYS_GPB_MFPH_PB15MFP_UART0_nCTS (0x6UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for UART0_nCTS */ 634 #define SYS_GPB_MFPH_PB15MFP_UART3_TXD (0x7UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for UART3_TXD */ 635 #define SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL (0x8UL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for I2C2_SMBAL */ 636 #define SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 (0xBUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for EPWM1_CH0 */ 637 #define SYS_GPB_MFPH_PB15MFP_TM0_EXT (0xDUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for TM0_EXT */ 638 #define SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN (0xEUL<<SYS_GPB_MFPH_PB15MFP_Pos) /*!< GPB_MFPH PB15 setting for USB_VBUS_EN */ 639 640 /* PC.0 MFP */ 641 #define SYS_GPC_MFPL_PC0MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for GPIO */ 642 #define SYS_GPC_MFPL_PC0MFP_EBI_AD0 (0x2UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EBI_AD0 */ 643 #define SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 (0x4UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for QSPI0_MOSI0 */ 644 #define SYS_GPC_MFPL_PC0MFP_SC1_CLK (0x5UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SC1_CLK */ 645 #define SYS_GPC_MFPL_PC0MFP_I2S0_LRCK (0x6UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2S0_LRCK */ 646 #define SYS_GPC_MFPL_PC0MFP_SPI1_SS (0x7UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI1_SS */ 647 #define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x8UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_RXD */ 648 #define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x9UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2C0_SDA */ 649 #define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0xCUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EPWM1_CH5 */ 650 #define SYS_GPC_MFPL_PC0MFP_LCD_COM0 (0xDUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for LCD_COM0 */ 651 #define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0xEUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for ACMP1_O */ 652 653 /* PC.1 MFP */ 654 #define SYS_GPC_MFPL_PC1MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for GPIO */ 655 #define SYS_GPC_MFPL_PC1MFP_EBI_AD1 (0x2UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EBI_AD1 */ 656 #define SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 (0x4UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for QSPI0_MISO0 */ 657 #define SYS_GPC_MFPL_PC1MFP_SC1_DAT (0x5UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SC1_DAT */ 658 #define SYS_GPC_MFPL_PC1MFP_I2S0_DO (0x6UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2S0_DO */ 659 #define SYS_GPC_MFPL_PC1MFP_SPI1_CLK (0x7UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SPI1_CLK */ 660 #define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x8UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_TXD */ 661 #define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x9UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2C0_SCL */ 662 #define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0xCUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EPWM1_CH4 */ 663 #define SYS_GPC_MFPL_PC1MFP_LCD_COM1 (0xDUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for LCD_COM1 */ 664 #define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0xEUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ACMP0_O */ 665 #define SYS_GPC_MFPL_PC1MFP_EADC0_ST (0xFUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EADC0_ST */ 666 667 /* PC.2 MFP */ 668 #define SYS_GPC_MFPL_PC2MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for GPIO */ 669 #define SYS_GPC_MFPL_PC2MFP_EBI_AD2 (0x2UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EBI_AD2 */ 670 #define SYS_GPC_MFPL_PC2MFP_QSPI0_CLK (0x4UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for QSPI0_CLK */ 671 #define SYS_GPC_MFPL_PC2MFP_SC1_RST (0x5UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SC1_RST */ 672 #define SYS_GPC_MFPL_PC2MFP_I2S0_DI (0x6UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2S0_DI */ 673 #define SYS_GPC_MFPL_PC2MFP_SPI1_MOSI (0x7UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI1_MOSI */ 674 #define SYS_GPC_MFPL_PC2MFP_UART2_nCTS (0x8UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART2_nCTS */ 675 #define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x9UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS */ 676 #define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0xBUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART3_RXD */ 677 #define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0xCUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EPWM1_CH3 */ 678 #define SYS_GPC_MFPL_PC2MFP_LCD_COM2 (0xFUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for LCD_COM2 */ 679 680 /* PC.3 MFP */ 681 #define SYS_GPC_MFPL_PC3MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO */ 682 #define SYS_GPC_MFPL_PC3MFP_EBI_AD3 (0x2UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EBI_AD3 */ 683 #define SYS_GPC_MFPL_PC3MFP_QSPI0_SS (0x4UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for QSPI0_SS */ 684 #define SYS_GPC_MFPL_PC3MFP_SC1_PWR (0x5UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SC1_PWR */ 685 #define SYS_GPC_MFPL_PC3MFP_I2S0_MCLK (0x6UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2S0_MCLK */ 686 #define SYS_GPC_MFPL_PC3MFP_SPI1_MISO (0x7UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI1_MISO */ 687 #define SYS_GPC_MFPL_PC3MFP_UART2_nRTS (0x8UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART2_nRTS */ 688 #define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x9UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2C0_SMBAL */ 689 #define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0xBUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART3_TXD */ 690 #define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0xCUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EPWM1_CH2 */ 691 #define SYS_GPC_MFPL_PC3MFP_LCD_COM3 (0xFUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for LCD_COM3 */ 692 693 /* PC.4 MFP */ 694 #define SYS_GPC_MFPL_PC4MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO */ 695 #define SYS_GPC_MFPL_PC4MFP_EBI_AD4 (0x2UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EBI_AD4 */ 696 #define SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 (0x4UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for QSPI0_MOSI1 */ 697 #define SYS_GPC_MFPL_PC4MFP_SC1_nCD (0x5UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SC1_nCD */ 698 #define SYS_GPC_MFPL_PC4MFP_I2S0_BCLK (0x6UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2S0_BCLK */ 699 #define SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK (0x7UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for SPI1_I2SMCLK */ 700 #define SYS_GPC_MFPL_PC4MFP_UART2_RXD (0x8UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART2_RXD */ 701 #define SYS_GPC_MFPL_PC4MFP_I2C1_SDA (0x9UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for I2C1_SDA */ 702 #define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0xAUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for CAN0_RXD */ 703 #define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0xBUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART4_RXD */ 704 #define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0xCUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EPWM1_CH1 */ 705 #define SYS_GPC_MFPL_PC4MFP_LCD_SEG16 (0xEUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for LCD_SEG16 */ 706 #define SYS_GPC_MFPL_PC4MFP_LCD_COM4 (0xFUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for LCD_COM4 */ 707 #define SYS_GPC_MFPL_PC4MFP_LCD_SEG43 (0xFUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for LCD_SEG43 */ 708 709 /* PC.5 MFP */ 710 #define SYS_GPC_MFPL_PC5MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO */ 711 #define SYS_GPC_MFPL_PC5MFP_EBI_AD5 (0x2UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EBI_AD5 */ 712 #define SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 (0x4UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for QSPI0_MISO1 */ 713 #define SYS_GPC_MFPL_PC5MFP_UART2_TXD (0x8UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART2_TXD */ 714 #define SYS_GPC_MFPL_PC5MFP_I2C1_SCL (0x9UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for I2C1_SCL */ 715 #define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0xAUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for CAN0_TXD */ 716 #define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0xBUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART4_TXD */ 717 #define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0xCUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EPWM1_CH0 */ 718 #define SYS_GPC_MFPL_PC5MFP_LCD_SEG15 (0xEUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for LCD_SEG15 */ 719 #define SYS_GPC_MFPL_PC5MFP_LCD_COM5 (0xFUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for LCD_COM5 */ 720 #define SYS_GPC_MFPL_PC5MFP_LCD_SEG42 (0xFUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for LCD_SEG42 */ 721 722 /* PC.6 MFP */ 723 #define SYS_GPC_MFPL_PC6MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO */ 724 #define SYS_GPC_MFPL_PC6MFP_EBI_AD8 (0x2UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EBI_AD8 */ 725 #define SYS_GPC_MFPL_PC6MFP_SPI1_MOSI (0x4UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SPI1_MOSI */ 726 #define SYS_GPC_MFPL_PC6MFP_UART4_RXD (0x5UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART4_RXD */ 727 #define SYS_GPC_MFPL_PC6MFP_SC2_RST (0x6UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for SC2_RST */ 728 #define SYS_GPC_MFPL_PC6MFP_UART0_nRTS (0x7UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for UART0_nRTS */ 729 #define SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS (0x8UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for I2C1_SMBSUS */ 730 #define SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 (0xBUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for EPWM1_CH3 */ 731 #define SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 (0xCUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for BPWM1_CH1 */ 732 #define SYS_GPC_MFPL_PC6MFP_LCD_SEG9 (0xDUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for LCD_SEG9 */ 733 #define SYS_GPC_MFPL_PC6MFP_TM1 (0xEUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for TM1 */ 734 #define SYS_GPC_MFPL_PC6MFP_INT2 (0xFUL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for INT2 */ 735 736 /* PC.7 MFP */ 737 #define SYS_GPC_MFPL_PC7MFP_GPIO (0x0UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for GPIO */ 738 #define SYS_GPC_MFPL_PC7MFP_EBI_AD9 (0x2UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EBI_AD9 */ 739 #define SYS_GPC_MFPL_PC7MFP_SPI1_MISO (0x4UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SPI1_MISO */ 740 #define SYS_GPC_MFPL_PC7MFP_UART4_TXD (0x5UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART4_TXD */ 741 #define SYS_GPC_MFPL_PC7MFP_SC2_PWR (0x6UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for SC2_PWR */ 742 #define SYS_GPC_MFPL_PC7MFP_UART0_nCTS (0x7UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for UART0_nCTS */ 743 #define SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL (0x8UL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for I2C1_SMBAL */ 744 #define SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 (0xBUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for EPWM1_CH2 */ 745 #define SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 (0xCUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for BPWM1_CH0 */ 746 #define SYS_GPC_MFPL_PC7MFP_LCD_SEG10 (0xDUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for LCD_SEG10 */ 747 #define SYS_GPC_MFPL_PC7MFP_TM0 (0xEUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for TM0 */ 748 #define SYS_GPC_MFPL_PC7MFP_INT3 (0xFUL<<SYS_GPC_MFPL_PC7MFP_Pos) /*!< GPC_MFPL PC7 setting for INT3 */ 749 750 /* PC.8 MFP */ 751 #define SYS_GPC_MFPH_PC8MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for GPIO */ 752 #define SYS_GPC_MFPH_PC8MFP_EBI_ADR16 (0x2UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EBI_ADR16 */ 753 #define SYS_GPC_MFPH_PC8MFP_I2C0_SDA (0x4UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for I2C0_SDA */ 754 #define SYS_GPC_MFPH_PC8MFP_UART4_nCTS (0x5UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART4_nCTS */ 755 #define SYS_GPC_MFPH_PC8MFP_UART1_RXD (0x8UL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for UART1_RXD */ 756 #define SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 (0xBUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for EPWM1_CH1 */ 757 #define SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 (0xCUL<<SYS_GPC_MFPH_PC8MFP_Pos) /*!< GPC_MFPH PC8 setting for BPWM1_CH4 */ 758 759 /* PC.9 MFP */ 760 #define SYS_GPC_MFPH_PC9MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for GPIO */ 761 #define SYS_GPC_MFPH_PC9MFP_EBI_ADR7 (0x2UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EBI_ADR7 */ 762 #define SYS_GPC_MFPH_PC9MFP_SPI3_SS (0x6UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for SPI3_SS */ 763 #define SYS_GPC_MFPH_PC9MFP_UART3_RXD (0x7UL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for UART3_RXD */ 764 #define SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 (0xCUL<<SYS_GPC_MFPH_PC9MFP_Pos) /*!< GPC_MFPH PC9 setting for EPWM1_CH3 */ 765 766 /* PC.10 MFP */ 767 #define SYS_GPC_MFPH_PC10MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for GPIO */ 768 #define SYS_GPC_MFPH_PC10MFP_EBI_ADR6 (0x2UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for EBI_ADR6 */ 769 #define SYS_GPC_MFPH_PC10MFP_SPI3_CLK (0x6UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for SPI3_CLK */ 770 #define SYS_GPC_MFPH_PC10MFP_UART3_TXD (0x7UL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for UART3_TXD */ 771 #define SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 (0xBUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for ECAP1_IC0 */ 772 #define SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 (0xCUL<<SYS_GPC_MFPH_PC10MFP_Pos) /*!< GPC_MFPH PC10 setting for EPWM1_CH2 */ 773 774 /* PC.11 MFP */ 775 #define SYS_GPC_MFPH_PC11MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for GPIO */ 776 #define SYS_GPC_MFPH_PC11MFP_EBI_ADR5 (0x2UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for EBI_ADR5 */ 777 #define SYS_GPC_MFPH_PC11MFP_UART0_RXD (0x3UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for UART0_RXD */ 778 #define SYS_GPC_MFPH_PC11MFP_I2C0_SDA (0x4UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for I2C0_SDA */ 779 #define SYS_GPC_MFPH_PC11MFP_SPI3_MOSI (0x6UL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for SPI3_MOSI */ 780 #define SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 (0xBUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for ECAP1_IC1 */ 781 #define SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 (0xCUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for EPWM1_CH1 */ 782 #define SYS_GPC_MFPH_PC11MFP_ACMP1_O (0xEUL<<SYS_GPC_MFPH_PC11MFP_Pos) /*!< GPC_MFPH PC11 setting for ACMP1_O */ 783 784 /* PC.12 MFP */ 785 #define SYS_GPC_MFPH_PC12MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for GPIO */ 786 #define SYS_GPC_MFPH_PC12MFP_EBI_ADR4 (0x2UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for EBI_ADR4 */ 787 #define SYS_GPC_MFPH_PC12MFP_UART0_TXD (0x3UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for UART0_TXD */ 788 #define SYS_GPC_MFPH_PC12MFP_I2C0_SCL (0x4UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for I2C0_SCL */ 789 #define SYS_GPC_MFPH_PC12MFP_SPI3_MISO (0x6UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SPI3_MISO */ 790 #define SYS_GPC_MFPH_PC12MFP_SC0_nCD (0x9UL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for SC0_nCD */ 791 #define SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 (0xBUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for ECAP1_IC2 */ 792 #define SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 (0xCUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for EPWM1_CH0 */ 793 #define SYS_GPC_MFPH_PC12MFP_ACMP0_O (0xEUL<<SYS_GPC_MFPH_PC12MFP_Pos) /*!< GPC_MFPH PC12 setting for ACMP0_O */ 794 795 /* PC.13 MFP */ 796 #define SYS_GPC_MFPH_PC13MFP_GPIO (0x0UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for GPIO */ 797 #define SYS_GPC_MFPH_PC13MFP_EBI_ADR10 (0x2UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for EBI_ADR10 */ 798 #define SYS_GPC_MFPH_PC13MFP_SC2_nCD (0x3UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SC2_nCD */ 799 #define SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK (0x4UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for SPI2_I2SMCLK */ 800 #define SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 (0x6UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for USCI0_CTL0 */ 801 #define SYS_GPC_MFPH_PC13MFP_UART2_TXD (0x7UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for UART2_TXD */ 802 #define SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 (0x9UL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for BPWM0_CH4 */ 803 #define SYS_GPC_MFPH_PC13MFP_CLKO (0xDUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for CLKO */ 804 #define SYS_GPC_MFPH_PC13MFP_EADC0_ST (0xEUL<<SYS_GPC_MFPH_PC13MFP_Pos) /*!< GPC_MFPH PC13 setting for EADC0_ST */ 805 806 /* PD.0 MFP */ 807 #define SYS_GPD_MFPL_PD0MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for GPIO */ 808 #define SYS_GPD_MFPL_PD0MFP_EBI_AD13 (0x2UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for EBI_AD13 */ 809 #define SYS_GPD_MFPL_PD0MFP_USCI0_CLK (0x3UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for USCI0_CLK */ 810 #define SYS_GPD_MFPL_PD0MFP_SPI0_MOSI (0x4UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SPI0_MOSI */ 811 #define SYS_GPD_MFPL_PD0MFP_UART3_RXD (0x5UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for UART3_RXD */ 812 #define SYS_GPD_MFPL_PD0MFP_I2C2_SDA (0x6UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for I2C2_SDA */ 813 #define SYS_GPD_MFPL_PD0MFP_SC2_CLK (0x7UL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for SC2_CLK */ 814 #define SYS_GPD_MFPL_PD0MFP_TM2 (0xEUL<<SYS_GPD_MFPL_PD0MFP_Pos) /*!< GPD_MFPL PD0 setting for TM2 */ 815 816 /* PD.1 MFP */ 817 #define SYS_GPD_MFPL_PD1MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for GPIO */ 818 #define SYS_GPD_MFPL_PD1MFP_EBI_AD12 (0x2UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for EBI_AD12 */ 819 #define SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 (0x3UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for USCI0_DAT0 */ 820 #define SYS_GPD_MFPL_PD1MFP_SPI0_MISO (0x4UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SPI0_MISO */ 821 #define SYS_GPD_MFPL_PD1MFP_UART3_TXD (0x5UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for UART3_TXD */ 822 #define SYS_GPD_MFPL_PD1MFP_I2C2_SCL (0x6UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for I2C2_SCL */ 823 #define SYS_GPD_MFPL_PD1MFP_SC2_DAT (0x7UL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for SC2_DAT */ 824 #define SYS_GPD_MFPL_PD1MFP_LCD_SEG0 (0xFUL<<SYS_GPD_MFPL_PD1MFP_Pos) /*!< GPD_MFPL PD1 setting for LCD_SEG0 */ 825 826 /* PD.2 MFP */ 827 #define SYS_GPD_MFPL_PD2MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for GPIO */ 828 #define SYS_GPD_MFPL_PD2MFP_EBI_AD11 (0x2UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for EBI_AD11 */ 829 #define SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 (0x3UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for USCI0_DAT1 */ 830 #define SYS_GPD_MFPL_PD2MFP_SPI0_CLK (0x4UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SPI0_CLK */ 831 #define SYS_GPD_MFPL_PD2MFP_UART3_nCTS (0x5UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART3_nCTS */ 832 #define SYS_GPD_MFPL_PD2MFP_SC2_RST (0x7UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for SC2_RST */ 833 #define SYS_GPD_MFPL_PD2MFP_UART0_RXD (0x9UL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for UART0_RXD */ 834 #define SYS_GPD_MFPL_PD2MFP_LCD_SEG1 (0xFUL<<SYS_GPD_MFPL_PD2MFP_Pos) /*!< GPD_MFPL PD2 setting for LCD_SEG1 */ 835 836 /* PD.3 MFP */ 837 #define SYS_GPD_MFPL_PD3MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for GPIO */ 838 #define SYS_GPD_MFPL_PD3MFP_EBI_AD10 (0x2UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for EBI_AD10 */ 839 #define SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 (0x3UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI0_CTL1 */ 840 #define SYS_GPD_MFPL_PD3MFP_SPI0_SS (0x4UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SPI0_SS */ 841 #define SYS_GPD_MFPL_PD3MFP_UART3_nRTS (0x5UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART3_nRTS */ 842 #define SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 (0x6UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for USCI1_CTL0 */ 843 #define SYS_GPD_MFPL_PD3MFP_SC2_PWR (0x7UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC2_PWR */ 844 #define SYS_GPD_MFPL_PD3MFP_SC1_nCD (0x8UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for SC1_nCD */ 845 #define SYS_GPD_MFPL_PD3MFP_UART0_TXD (0x9UL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for UART0_TXD */ 846 #define SYS_GPD_MFPL_PD3MFP_LCD_SEG2 (0xFUL<<SYS_GPD_MFPL_PD3MFP_Pos) /*!< GPD_MFPL PD3 setting for LCD_SEG2 */ 847 848 /* PD.4 MFP */ 849 #define SYS_GPD_MFPL_PD4MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for GPIO */ 850 #define SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 (0x3UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI0_CTL0 */ 851 #define SYS_GPD_MFPL_PD4MFP_I2C1_SDA (0x4UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for I2C1_SDA */ 852 #define SYS_GPD_MFPL_PD4MFP_SPI1_SS (0x5UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SPI1_SS */ 853 #define SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 (0x6UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USCI1_CTL1 */ 854 #define SYS_GPD_MFPL_PD4MFP_SC1_CLK (0x8UL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for SC1_CLK */ 855 #define SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST (0xEUL<<SYS_GPD_MFPL_PD4MFP_Pos) /*!< GPD_MFPL PD4 setting for USB_VBUS_ST */ 856 857 /* PD.5 MFP */ 858 #define SYS_GPD_MFPL_PD5MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for GPIO */ 859 #define SYS_GPD_MFPL_PD5MFP_I2C1_SCL (0x4UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for I2C1_SCL */ 860 #define SYS_GPD_MFPL_PD5MFP_SPI1_CLK (0x5UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SPI1_CLK */ 861 #define SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 (0x6UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for USCI1_DAT0 */ 862 #define SYS_GPD_MFPL_PD5MFP_SC1_DAT (0x8UL<<SYS_GPD_MFPL_PD5MFP_Pos) /*!< GPD_MFPL PD5 setting for SC1_DAT */ 863 864 /* PD.6 MFP */ 865 #define SYS_GPD_MFPL_PD6MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for GPIO */ 866 #define SYS_GPD_MFPL_PD6MFP_UART1_RXD (0x3UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for UART1_RXD */ 867 #define SYS_GPD_MFPL_PD6MFP_I2C0_SDA (0x4UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for I2C0_SDA */ 868 #define SYS_GPD_MFPL_PD6MFP_SPI1_MOSI (0x5UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SPI1_MOSI */ 869 #define SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 (0x6UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for USCI1_DAT1 */ 870 #define SYS_GPD_MFPL_PD6MFP_SC1_RST (0x8UL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for SC1_RST */ 871 #define SYS_GPD_MFPL_PD6MFP_LCD_SEG13 (0xFUL<<SYS_GPD_MFPL_PD6MFP_Pos) /*!< GPD_MFPL PD6 setting for LCD_SEG13 */ 872 873 /* PD.7 MFP */ 874 #define SYS_GPD_MFPL_PD7MFP_GPIO (0x0UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for GPIO */ 875 #define SYS_GPD_MFPL_PD7MFP_UART1_TXD (0x3UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for UART1_TXD */ 876 #define SYS_GPD_MFPL_PD7MFP_I2C0_SCL (0x4UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for I2C0_SCL */ 877 #define SYS_GPD_MFPL_PD7MFP_SPI1_MISO (0x5UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SPI1_MISO */ 878 #define SYS_GPD_MFPL_PD7MFP_USCI1_CLK (0x6UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for USCI1_CLK */ 879 #define SYS_GPD_MFPL_PD7MFP_SC1_PWR (0x8UL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for SC1_PWR */ 880 #define SYS_GPD_MFPL_PD7MFP_LCD_SEG14 (0xFUL<<SYS_GPD_MFPL_PD7MFP_Pos) /*!< GPD_MFPL PD7 setting for LCD_SEG14 */ 881 882 /* PD.8 MFP */ 883 #define SYS_GPD_MFPH_PD8MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for GPIO */ 884 #define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x2UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_AD6 */ 885 #define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x3UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for I2C2_SDA */ 886 #define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x4UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for UART2_nRTS */ 887 #define SYS_GPD_MFPH_PD8MFP_LCD_COM6 (0xFUL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for LCD_COM6 */ 888 #define SYS_GPD_MFPH_PD8MFP_LCD_SEG41 (0xFUL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for LCD_SEG41 */ 889 890 /* PD.9 MFP */ 891 #define SYS_GPD_MFPH_PD9MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO */ 892 #define SYS_GPD_MFPH_PD9MFP_EBI_AD7 (0x2UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for EBI_AD7 */ 893 #define SYS_GPD_MFPH_PD9MFP_I2C2_SCL (0x3UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for I2C2_SCL */ 894 #define SYS_GPD_MFPH_PD9MFP_UART2_nCTS (0x4UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for UART2_nCTS */ 895 #define SYS_GPD_MFPH_PD9MFP_LCD_COM7 (0xFUL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for LCD_COM7 */ 896 #define SYS_GPD_MFPH_PD9MFP_LCD_SEG40 (0xFUL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for LCD_SEG40 */ 897 898 /* PD.10 MFP */ 899 #define SYS_GPD_MFPH_PD10MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for GPIO */ 900 #define SYS_GPD_MFPH_PD10MFP_EBI_nCS2 (0x2UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for EBI_nCS2 */ 901 #define SYS_GPD_MFPH_PD10MFP_UART1_RXD (0x3UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for UART1_RXD */ 902 #define SYS_GPD_MFPH_PD10MFP_CAN0_RXD (0x4UL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for CAN0_RXD */ 903 #define SYS_GPD_MFPH_PD10MFP_QEI0_B (0xAUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for QEI0_B */ 904 #define SYS_GPD_MFPH_PD10MFP_INT7 (0xFUL<<SYS_GPD_MFPH_PD10MFP_Pos) /*!< GPD_MFPH PD10 setting for INT7 */ 905 906 /* PD.11 MFP */ 907 #define SYS_GPD_MFPH_PD11MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for GPIO */ 908 #define SYS_GPD_MFPH_PD11MFP_EBI_nCS1 (0x2UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for EBI_nCS1 */ 909 #define SYS_GPD_MFPH_PD11MFP_UART1_TXD (0x3UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for UART1_TXD */ 910 #define SYS_GPD_MFPH_PD11MFP_CAN0_TXD (0x4UL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for CAN0_TXD */ 911 #define SYS_GPD_MFPH_PD11MFP_QEI0_A (0xAUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for QEI0_A */ 912 #define SYS_GPD_MFPH_PD11MFP_INT6 (0xFUL<<SYS_GPD_MFPH_PD11MFP_Pos) /*!< GPD_MFPH PD11 setting for INT6 */ 913 914 /* PD.12 MFP */ 915 #define SYS_GPD_MFPH_PD12MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for GPIO */ 916 #define SYS_GPD_MFPH_PD12MFP_EBI_nCS0 (0x2UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for EBI_nCS0 */ 917 #define SYS_GPD_MFPH_PD12MFP_UART2_RXD (0x7UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for UART2_RXD */ 918 #define SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 (0x9UL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for BPWM0_CH5 */ 919 #define SYS_GPD_MFPH_PD12MFP_QEI0_INDEX (0xAUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for QEI0_INDEX */ 920 #define SYS_GPD_MFPH_PD12MFP_CLKO (0xDUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for CLKO */ 921 #define SYS_GPD_MFPH_PD12MFP_EADC0_ST (0xEUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for EADC0_ST */ 922 #define SYS_GPD_MFPH_PD12MFP_INT5 (0xFUL<<SYS_GPD_MFPH_PD12MFP_Pos) /*!< GPD_MFPH PD12 setting for INT5 */ 923 924 /* PD.14 MFP */ 925 #define SYS_GPD_MFPH_PD14MFP_GPIO (0x0UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for GPIO */ 926 #define SYS_GPD_MFPH_PD14MFP_EBI_nCS0 (0x2UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for EBI_nCS0 */ 927 #define SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK (0x3UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for SPI3_I2SMCLK */ 928 #define SYS_GPD_MFPH_PD14MFP_SC1_nCD (0x4UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for SC1_nCD */ 929 #define SYS_GPD_MFPH_PD14MFP_USCI0_CTL0 (0x5UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for USCI0_CTL0 */ 930 #define SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK (0x6UL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for SPI0_I2SMCLK */ 931 #define SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 (0xBUL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for EPWM0_CH4 */ 932 #define SYS_GPD_MFPH_PD14MFP_LCD_SEG0 (0xFUL<<SYS_GPD_MFPH_PD14MFP_Pos) /*!< GPD_MFPH PD14 setting for LCD_SEG0 */ 933 934 /* PE.0 MFP */ 935 #define SYS_GPE_MFPL_PE0MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for GPIO */ 936 #define SYS_GPE_MFPL_PE0MFP_EBI_AD11 (0x2UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for EBI_AD11 */ 937 #define SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 (0x3UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for QSPI0_MOSI0 */ 938 #define SYS_GPE_MFPL_PE0MFP_SC2_CLK (0x4UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SC2_CLK */ 939 #define SYS_GPE_MFPL_PE0MFP_I2S0_MCLK (0x5UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2S0_MCLK */ 940 #define SYS_GPE_MFPL_PE0MFP_SPI1_MOSI (0x6UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for SPI1_MOSI */ 941 #define SYS_GPE_MFPL_PE0MFP_UART3_RXD (0x7UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART3_RXD */ 942 #define SYS_GPE_MFPL_PE0MFP_I2C1_SDA (0x8UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for I2C1_SDA */ 943 #define SYS_GPE_MFPL_PE0MFP_UART4_nRTS (0x9UL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for UART4_nRTS */ 944 #define SYS_GPE_MFPL_PE0MFP_LCD_SEG5 (0xFUL<<SYS_GPE_MFPL_PE0MFP_Pos) /*!< GPE_MFPL PE0 setting for LCD_SEG5 */ 945 946 /* PE.1 MFP */ 947 #define SYS_GPE_MFPL_PE1MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for GPIO */ 948 #define SYS_GPE_MFPL_PE1MFP_EBI_AD10 (0x2UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for EBI_AD10 */ 949 #define SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 (0x3UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for QSPI0_MISO0 */ 950 #define SYS_GPE_MFPL_PE1MFP_SC2_DAT (0x4UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SC2_DAT */ 951 #define SYS_GPE_MFPL_PE1MFP_I2S0_BCLK (0x5UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2S0_BCLK */ 952 #define SYS_GPE_MFPL_PE1MFP_SPI1_MISO (0x6UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for SPI1_MISO */ 953 #define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x7UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART3_TXD */ 954 #define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x8UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2C1_SCL */ 955 #define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x9UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART4_nCTS */ 956 #define SYS_GPE_MFPL_PE1MFP_LCD_SEG6 (0xFUL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for LCD_SEG6 */ 957 958 /* PE.2 MFP */ 959 #define SYS_GPE_MFPL_PE2MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO */ 960 #define SYS_GPE_MFPL_PE2MFP_EBI_ALE (0x2UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EBI_ALE */ 961 #define SYS_GPE_MFPL_PE2MFP_SD0_DAT0 (0x3UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SD0_DAT0 */ 962 #define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x5UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI3_MOSI */ 963 #define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x6UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SC0_CLK */ 964 #define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x7UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for USCI0_CLK */ 965 #define SYS_GPE_MFPL_PE2MFP_QEI0_B (0xBUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for QEI0_B */ 966 #define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0xCUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EPWM0_CH5 */ 967 #define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0xDUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for BPWM0_CH0 */ 968 #define SYS_GPE_MFPL_PE2MFP_LCD_SEG7 (0xFUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for LCD_SEG7 */ 969 970 /* PE.3 MFP */ 971 #define SYS_GPE_MFPL_PE3MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for GPIO */ 972 #define SYS_GPE_MFPL_PE3MFP_EBI_MCLK (0x2UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EBI_MCLK */ 973 #define SYS_GPE_MFPL_PE3MFP_SD0_DAT1 (0x3UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SD0_DAT1 */ 974 #define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x5UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI3_MISO */ 975 #define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x6UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SC0_DAT */ 976 #define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x7UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for USCI0_DAT0 */ 977 #define SYS_GPE_MFPL_PE3MFP_QEI0_A (0xBUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for QEI0_A */ 978 #define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0xCUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EPWM0_CH4 */ 979 #define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0xDUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for BPWM0_CH1 */ 980 #define SYS_GPE_MFPL_PE3MFP_LCD_SEG8 (0xFUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for LCD_SEG8 */ 981 982 /* PE.4 MFP */ 983 #define SYS_GPE_MFPL_PE4MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for GPIO */ 984 #define SYS_GPE_MFPL_PE4MFP_EBI_nWR (0x2UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EBI_nWR */ 985 #define SYS_GPE_MFPL_PE4MFP_SD0_DAT2 (0x3UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SD0_DAT2 */ 986 #define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x5UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI3_CLK */ 987 #define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x6UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_RST */ 988 #define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x7UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for USCI0_DAT1 */ 989 #define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0xBUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for QEI0_INDEX */ 990 #define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0xCUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EPWM0_CH3 */ 991 #define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0xDUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for BPWM0_CH2 */ 992 #define SYS_GPE_MFPL_PE4MFP_LCD_SEG9 (0xFUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for LCD_SEG9 */ 993 994 /* PE.5 MFP */ 995 #define SYS_GPE_MFPL_PE5MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for GPIO */ 996 #define SYS_GPE_MFPL_PE5MFP_EBI_nRD (0x2UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EBI_nRD */ 997 #define SYS_GPE_MFPL_PE5MFP_SD0_DAT3 (0x3UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SD0_DAT3 */ 998 #define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x5UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI3_SS */ 999 #define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x6UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_PWR */ 1000 #define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x7UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for USCI0_CTL1 */ 1001 #define SYS_GPE_MFPL_PE5MFP_QEI1_B (0xBUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for QEI1_B */ 1002 #define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0xCUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EPWM0_CH2 */ 1003 #define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0xDUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for BPWM0_CH3 */ 1004 #define SYS_GPE_MFPL_PE5MFP_LCD_SEG10 (0xFUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for LCD_SEG10 */ 1005 1006 /* PE.6 MFP */ 1007 #define SYS_GPE_MFPL_PE6MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for GPIO */ 1008 #define SYS_GPE_MFPL_PE6MFP_SD0_CLK (0x3UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SD0_CLK */ 1009 #define SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK (0x5UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SPI3_I2SMCLK */ 1010 #define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x6UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SC0_nCD */ 1011 #define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x7UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for USCI0_CTL0 */ 1012 #define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x8UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for UART5_RXD */ 1013 #define SYS_GPE_MFPL_PE6MFP_QEI1_A (0xBUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for QEI1_A */ 1014 #define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0xCUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for EPWM0_CH1 */ 1015 #define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0xDUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for BPWM0_CH4 */ 1016 #define SYS_GPE_MFPL_PE6MFP_LCD_SEG11 (0xFUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for LCD_SEG11 */ 1017 1018 /* PE.7 MFP */ 1019 #define SYS_GPE_MFPL_PE7MFP_GPIO (0x0UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO */ 1020 #define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x3UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SD0_CMD */ 1021 #define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x8UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for UART5_TXD */ 1022 #define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0xBUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for QEI1_INDEX */ 1023 #define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0xCUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for EPWM0_CH0 */ 1024 #define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0xDUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for BPWM0_CH5 */ 1025 #define SYS_GPE_MFPL_PE7MFP_LCD_SEG12 (0xFUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for LCD_SEG12 */ 1026 1027 /* PE.8 MFP */ 1028 #define SYS_GPE_MFPH_PE8MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for GPIO */ 1029 #define SYS_GPE_MFPH_PE8MFP_EBI_ADR10 (0x2UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EBI_ADR10 */ 1030 #define SYS_GPE_MFPH_PE8MFP_I2S0_BCLK (0x4UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for I2S0_BCLK */ 1031 #define SYS_GPE_MFPH_PE8MFP_SPI2_CLK (0x5UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for SPI2_CLK */ 1032 #define SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 (0x6UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for USCI1_CTL1 */ 1033 #define SYS_GPE_MFPH_PE8MFP_UART2_TXD (0x7UL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for UART2_TXD */ 1034 #define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0xAUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_CH0 */ 1035 #define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0xBUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0 */ 1036 #define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0xCUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ECAP0_IC0 */ 1037 #define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 (0xEUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for TRACE_DATA3 */ 1038 #define SYS_GPE_MFPH_PE8MFP_LCD_SEG32 (0xFUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for LCD_SEG32 */ 1039 1040 /* PE.9 MFP */ 1041 #define SYS_GPE_MFPH_PE9MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO */ 1042 #define SYS_GPE_MFPH_PE9MFP_EBI_ADR11 (0x2UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EBI_ADR11 */ 1043 #define SYS_GPE_MFPH_PE9MFP_I2S0_MCLK (0x4UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for I2S0_MCLK */ 1044 #define SYS_GPE_MFPH_PE9MFP_SPI2_MISO (0x5UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for SPI2_MISO */ 1045 #define SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 (0x6UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for USCI1_CTL0 */ 1046 #define SYS_GPE_MFPH_PE9MFP_UART2_RXD (0x7UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for UART2_RXD */ 1047 #define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0xAUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_CH1 */ 1048 #define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0xBUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1 */ 1049 #define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0xCUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ECAP0_IC1 */ 1050 #define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 (0xEUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for TRACE_DATA2 */ 1051 #define SYS_GPE_MFPH_PE9MFP_LCD_SEG31 (0xFUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for LCD_SEG31 */ 1052 1053 /* PE.10 MFP */ 1054 #define SYS_GPE_MFPH_PE10MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for GPIO */ 1055 #define SYS_GPE_MFPH_PE10MFP_EBI_ADR12 (0x2UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for EBI_ADR12 */ 1056 #define SYS_GPE_MFPH_PE10MFP_I2S0_DI (0x4UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for I2S0_DI */ 1057 #define SYS_GPE_MFPH_PE10MFP_SPI2_MOSI (0x5UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for SPI2_MOSI */ 1058 #define SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 (0x6UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for USCI1_DAT0 */ 1059 #define SYS_GPE_MFPH_PE10MFP_UART3_TXD (0x7UL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for UART3_TXD */ 1060 #define SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 (0xAUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for EPWM0_CH2 */ 1061 #define SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 (0xBUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for EPWM1_BRAKE0 */ 1062 #define SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 (0xCUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for ECAP0_IC2 */ 1063 #define SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 (0xEUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for TRACE_DATA1 */ 1064 #define SYS_GPE_MFPH_PE10MFP_LCD_SEG30 (0xFUL<<SYS_GPE_MFPH_PE10MFP_Pos) /*!< GPE_MFPH PE10 setting for LCD_SEG30 */ 1065 1066 /* PE.11 MFP */ 1067 #define SYS_GPE_MFPH_PE11MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for GPIO */ 1068 #define SYS_GPE_MFPH_PE11MFP_EBI_ADR13 (0x2UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for EBI_ADR13 */ 1069 #define SYS_GPE_MFPH_PE11MFP_I2S0_DO (0x4UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for I2S0_DO */ 1070 #define SYS_GPE_MFPH_PE11MFP_SPI2_SS (0x5UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for SPI2_SS */ 1071 #define SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 (0x6UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for USCI1_DAT1 */ 1072 #define SYS_GPE_MFPH_PE11MFP_UART3_RXD (0x7UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART3_RXD */ 1073 #define SYS_GPE_MFPH_PE11MFP_UART1_nCTS (0x8UL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for UART1_nCTS */ 1074 #define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0xAUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for EPWM0_CH3 */ 1075 #define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0xBUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1 */ 1076 #define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0xDUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for ECAP1_IC2 */ 1077 #define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 (0xEUL<<SYS_GPE_MFPH_PE11MFP_Pos) /*!< GPE_MFPH PE11 setting for TRACE_DATA0 */ 1078 1079 /* PE.12 MFP */ 1080 #define SYS_GPE_MFPH_PE12MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for GPIO */ 1081 #define SYS_GPE_MFPH_PE12MFP_EBI_ADR14 (0x2UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for EBI_ADR14 */ 1082 #define SYS_GPE_MFPH_PE12MFP_I2S0_LRCK (0x4UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for I2S0_LRCK */ 1083 #define SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK (0x5UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for SPI2_I2SMCLK */ 1084 #define SYS_GPE_MFPH_PE12MFP_USCI1_CLK (0x6UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for USCI1_CLK */ 1085 #define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x8UL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for UART1_nRTS */ 1086 #define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0xAUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for EPWM0_CH4 */ 1087 #define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0xDUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for ECAP1_IC1 */ 1088 #define SYS_GPE_MFPH_PE12MFP_TRACE_CLK (0xEUL<<SYS_GPE_MFPH_PE12MFP_Pos) /*!< GPE_MFPH PE12 setting for TRACE_CLK */ 1089 1090 /* PE.13 MFP */ 1091 #define SYS_GPE_MFPH_PE13MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for GPIO */ 1092 #define SYS_GPE_MFPH_PE13MFP_EBI_ADR15 (0x2UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for EBI_ADR15 */ 1093 #define SYS_GPE_MFPH_PE13MFP_I2C0_SCL (0x4UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for I2C0_SCL */ 1094 #define SYS_GPE_MFPH_PE13MFP_UART4_nRTS (0x5UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for UART4_nRTS */ 1095 #define SYS_GPE_MFPH_PE13MFP_UART1_TXD (0x8UL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for UART1_TXD */ 1096 #define SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 (0xAUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for EPWM0_CH5 */ 1097 #define SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 (0xBUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for EPWM1_CH0 */ 1098 #define SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 (0xCUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for BPWM1_CH5 */ 1099 #define SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 (0xDUL<<SYS_GPE_MFPH_PE13MFP_Pos) /*!< GPE_MFPH PE13 setting for ECAP1_IC0 */ 1100 1101 /* PE.14 MFP */ 1102 #define SYS_GPE_MFPH_PE14MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for GPIO */ 1103 #define SYS_GPE_MFPH_PE14MFP_EBI_AD8 (0x2UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for EBI_AD8 */ 1104 #define SYS_GPE_MFPH_PE14MFP_UART2_TXD (0x3UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for UART2_TXD */ 1105 #define SYS_GPE_MFPH_PE14MFP_CAN0_TXD (0x4UL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for CAN0_TXD */ 1106 #define SYS_GPE_MFPH_PE14MFP_LCD_SEG23 (0xFUL<<SYS_GPE_MFPH_PE14MFP_Pos) /*!< GPE_MFPH PE14 setting for LCD_SEG23 */ 1107 1108 /* PE.15 MFP */ 1109 #define SYS_GPE_MFPH_PE15MFP_GPIO (0x0UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for GPIO */ 1110 #define SYS_GPE_MFPH_PE15MFP_EBI_AD9 (0x2UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for EBI_AD9 */ 1111 #define SYS_GPE_MFPH_PE15MFP_UART2_RXD (0x3UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for UART2_RXD */ 1112 #define SYS_GPE_MFPH_PE15MFP_CAN0_RXD (0x4UL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for CAN0_RXD */ 1113 #define SYS_GPE_MFPH_PE15MFP_LCD_SEG22 (0xFUL<<SYS_GPE_MFPH_PE15MFP_Pos) /*!< GPE_MFPH PE15 setting for LCD_SEG22 */ 1114 1115 /* PF.0 MFP */ 1116 #define SYS_GPF_MFPL_PF0MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for GPIO */ 1117 #define SYS_GPF_MFPL_PF0MFP_UART1_TXD (0x2UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART1_TXD */ 1118 #define SYS_GPF_MFPL_PF0MFP_I2C1_SCL (0x3UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for I2C1_SCL */ 1119 #define SYS_GPF_MFPL_PF0MFP_UART0_TXD (0x4UL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for UART0_TXD */ 1120 #define SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 (0xCUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for BPWM1_CH0 */ 1121 #define SYS_GPF_MFPL_PF0MFP_ICE_DAT (0xEUL<<SYS_GPF_MFPL_PF0MFP_Pos) /*!< GPF_MFPL PF0 setting for ICE_DAT */ 1122 1123 /* PF.1 MFP */ 1124 #define SYS_GPF_MFPL_PF1MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for GPIO */ 1125 #define SYS_GPF_MFPL_PF1MFP_UART1_RXD (0x2UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for UART1_RXD */ 1126 #define SYS_GPF_MFPL_PF1MFP_I2C1_SDA (0x3UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for I2C1_SDA */ 1127 #define SYS_GPF_MFPL_PF1MFP_UART0_RXD (0x4UL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for UART0_RXD */ 1128 #define SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 (0xCUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for BPWM1_CH1 */ 1129 #define SYS_GPF_MFPL_PF1MFP_ICE_CLK (0xEUL<<SYS_GPF_MFPL_PF1MFP_Pos) /*!< GPF_MFPL PF1 setting for ICE_CLK */ 1130 1131 /* PF.2 MFP */ 1132 #define SYS_GPF_MFPL_PF2MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for GPIO */ 1133 #define SYS_GPF_MFPL_PF2MFP_EBI_nCS1 (0x2UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for EBI_nCS1 */ 1134 #define SYS_GPF_MFPL_PF2MFP_UART0_RXD (0x3UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for UART0_RXD */ 1135 #define SYS_GPF_MFPL_PF2MFP_I2C0_SDA (0x4UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for I2C0_SDA */ 1136 #define SYS_GPF_MFPL_PF2MFP_QSPI0_CLK (0x5UL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for QSPI0_CLK */ 1137 #define SYS_GPF_MFPL_PF2MFP_XT1_OUT (0xAUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for XT1_OUT */ 1138 #define SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 (0xBUL<<SYS_GPF_MFPL_PF2MFP_Pos) /*!< GPF_MFPL PF2 setting for BPWM1_CH1 */ 1139 1140 /* PF.3 MFP */ 1141 #define SYS_GPF_MFPL_PF3MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for GPIO */ 1142 #define SYS_GPF_MFPL_PF3MFP_EBI_nCS0 (0x2UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for EBI_nCS0 */ 1143 #define SYS_GPF_MFPL_PF3MFP_UART0_TXD (0x3UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for UART0_TXD */ 1144 #define SYS_GPF_MFPL_PF3MFP_I2C0_SCL (0x4UL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for I2C0_SCL */ 1145 #define SYS_GPF_MFPL_PF3MFP_XT1_IN (0xAUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for XT1_IN */ 1146 #define SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 (0xBUL<<SYS_GPF_MFPL_PF3MFP_Pos) /*!< GPF_MFPL PF3 setting for BPWM1_CH0 */ 1147 1148 /* PF.4 MFP */ 1149 #define SYS_GPF_MFPL_PF4MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for GPIO */ 1150 #define SYS_GPF_MFPL_PF4MFP_UART2_TXD (0x2UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_TXD */ 1151 #define SYS_GPF_MFPL_PF4MFP_UART2_nRTS (0x4UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for UART2_nRTS */ 1152 #define SYS_GPF_MFPL_PF4MFP_EPWM0_CH1 (0x7UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for EPWM0_CH1 */ 1153 #define SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 (0x8UL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for BPWM0_CH5 */ 1154 #define SYS_GPF_MFPL_PF4MFP_X32_OUT (0xAUL<<SYS_GPF_MFPL_PF4MFP_Pos) /*!< GPF_MFPL PF4 setting for X32_OUT */ 1155 1156 /* PF.5 MFP */ 1157 #define SYS_GPF_MFPL_PF5MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for GPIO */ 1158 #define SYS_GPF_MFPL_PF5MFP_UART2_RXD (0x2UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_RXD */ 1159 #define SYS_GPF_MFPL_PF5MFP_UART2_nCTS (0x4UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for UART2_nCTS */ 1160 #define SYS_GPF_MFPL_PF5MFP_EPWM0_CH0 (0x7UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EPWM0_CH0 */ 1161 #define SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 (0x8UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for BPWM0_CH4 */ 1162 #define SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT (0x9UL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EPWM0_SYNC_OUT */ 1163 #define SYS_GPF_MFPL_PF5MFP_X32_IN (0xAUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for X32_IN */ 1164 #define SYS_GPF_MFPL_PF5MFP_EADC0_ST (0xBUL<<SYS_GPF_MFPL_PF5MFP_Pos) /*!< GPF_MFPL PF5 setting for EADC0_ST */ 1165 1166 /* PF.6 MFP */ 1167 #define SYS_GPF_MFPL_PF6MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for GPIO */ 1168 #define SYS_GPF_MFPL_PF6MFP_EBI_ADR19 (0x2UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_ADR19 */ 1169 #define SYS_GPF_MFPL_PF6MFP_SC0_CLK (0x3UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SC0_CLK */ 1170 #define SYS_GPF_MFPL_PF6MFP_I2S0_LRCK (0x4UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for I2S0_LRCK */ 1171 #define SYS_GPF_MFPL_PF6MFP_SPI0_MOSI (0x5UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SPI0_MOSI */ 1172 #define SYS_GPF_MFPL_PF6MFP_UART4_RXD (0x6UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for UART4_RXD */ 1173 #define SYS_GPF_MFPL_PF6MFP_EBI_nCS0 (0x7UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for EBI_nCS0 */ 1174 #define SYS_GPF_MFPL_PF6MFP_SPI3_I2SMCLK (0x9UL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for SPI3_I2SMCLK */ 1175 #define SYS_GPF_MFPL_PF6MFP_TAMPER0 (0xAUL<<SYS_GPF_MFPL_PF6MFP_Pos) /*!< GPF_MFPL PF6 setting for TAMPER0 */ 1176 1177 /* PF.7 MFP */ 1178 #define SYS_GPF_MFPL_PF7MFP_GPIO (0x0UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for GPIO */ 1179 #define SYS_GPF_MFPL_PF7MFP_EBI_ADR18 (0x2UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for EBI_ADR18 */ 1180 #define SYS_GPF_MFPL_PF7MFP_SC0_DAT (0x3UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SC0_DAT */ 1181 #define SYS_GPF_MFPL_PF7MFP_I2S0_DO (0x4UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for I2S0_DO */ 1182 #define SYS_GPF_MFPL_PF7MFP_SPI0_MISO (0x5UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for SPI0_MISO */ 1183 #define SYS_GPF_MFPL_PF7MFP_UART4_TXD (0x6UL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for UART4_TXD */ 1184 #define SYS_GPF_MFPL_PF7MFP_TAMPER1 (0xAUL<<SYS_GPF_MFPL_PF7MFP_Pos) /*!< GPF_MFPL PF7 setting for TAMPER1 */ 1185 1186 /* PF.8 MFP */ 1187 #define SYS_GPF_MFPH_PF8MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for GPIO */ 1188 #define SYS_GPF_MFPH_PF8MFP_EBI_ADR17 (0x2UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for EBI_ADR17 */ 1189 #define SYS_GPF_MFPH_PF8MFP_SC0_RST (0x3UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SC0_RST */ 1190 #define SYS_GPF_MFPH_PF8MFP_I2S0_DI (0x4UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for I2S0_DI */ 1191 #define SYS_GPF_MFPH_PF8MFP_SPI0_CLK (0x5UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for SPI0_CLK */ 1192 #define SYS_GPF_MFPH_PF8MFP_UART5_nCTS (0x6UL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for UART5_nCTS */ 1193 #define SYS_GPF_MFPH_PF8MFP_TAMPER2 (0xAUL<<SYS_GPF_MFPH_PF8MFP_Pos) /*!< GPF_MFPH PF8 setting for TAMPER2 */ 1194 1195 /* PF.9 MFP */ 1196 #define SYS_GPF_MFPH_PF9MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for GPIO */ 1197 #define SYS_GPF_MFPH_PF9MFP_EBI_ADR16 (0x2UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for EBI_ADR16 */ 1198 #define SYS_GPF_MFPH_PF9MFP_SC0_PWR (0x3UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for SC0_PWR */ 1199 #define SYS_GPF_MFPH_PF9MFP_I2S0_MCLK (0x4UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for I2S0_MCLK */ 1200 #define SYS_GPF_MFPH_PF9MFP_SPI0_SS (0x5UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for SPI0_SS */ 1201 #define SYS_GPF_MFPH_PF9MFP_UART5_nRTS (0x6UL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for UART5_nRTS */ 1202 #define SYS_GPF_MFPH_PF9MFP_TAMPER3 (0xAUL<<SYS_GPF_MFPH_PF9MFP_Pos) /*!< GPF_MFPH PF9 setting for TAMPER3 */ 1203 1204 /* PF.10 MFP */ 1205 #define SYS_GPF_MFPH_PF10MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for GPIO */ 1206 #define SYS_GPF_MFPH_PF10MFP_EBI_ADR15 (0x2UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for EBI_ADR15 */ 1207 #define SYS_GPF_MFPH_PF10MFP_SC0_nCD (0x3UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for SC0_nCD */ 1208 #define SYS_GPF_MFPH_PF10MFP_I2S0_BCLK (0x4UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for I2S0_BCLK */ 1209 #define SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK (0x5UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for SPI0_I2SMCLK */ 1210 #define SYS_GPF_MFPH_PF10MFP_UART5_RXD (0x6UL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for UART5_RXD */ 1211 #define SYS_GPF_MFPH_PF10MFP_TAMPER4 (0xAUL<<SYS_GPF_MFPH_PF10MFP_Pos) /*!< GPF_MFPH PF10 setting for TAMPER4 */ 1212 1213 /* PF.11 MFP */ 1214 #define SYS_GPF_MFPH_PF11MFP_GPIO (0x0UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for GPIO */ 1215 #define SYS_GPF_MFPH_PF11MFP_EBI_ADR14 (0x2UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for EBI_ADR14 */ 1216 #define SYS_GPF_MFPH_PF11MFP_SPI2_MOSI (0x3UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for SPI2_MOSI */ 1217 #define SYS_GPF_MFPH_PF11MFP_UART5_TXD (0x6UL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for UART5_TXD */ 1218 #define SYS_GPF_MFPH_PF11MFP_TAMPER5 (0xAUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for TAMPER5 */ 1219 #define SYS_GPF_MFPH_PF11MFP_TM5 (0xCUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for TM5 */ 1220 #define SYS_GPF_MFPH_PF11MFP_TM3 (0xDUL<<SYS_GPF_MFPH_PF11MFP_Pos) /*!< GPF_MFPH PF11 setting for TM3 */ 1221 1222 /* PG.2 MFP */ 1223 #define SYS_GPG_MFPL_PG2MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for GPIO */ 1224 #define SYS_GPG_MFPL_PG2MFP_EBI_ADR11 (0x2UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for EBI_ADR11 */ 1225 #define SYS_GPG_MFPL_PG2MFP_SPI2_SS (0x3UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for SPI2_SS */ 1226 #define SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL (0x4UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C0_SMBAL */ 1227 #define SYS_GPG_MFPL_PG2MFP_I2C1_SCL (0x5UL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for I2C1_SCL */ 1228 #define SYS_GPG_MFPL_PG2MFP_TM0 (0xDUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for TM0 */ 1229 #define SYS_GPG_MFPL_PG2MFP_LCD_SEG39 (0xFUL<<SYS_GPG_MFPL_PG2MFP_Pos) /*!< GPG_MFPL PG2 setting for LCD_SEG39 */ 1230 1231 /* PG.3 MFP */ 1232 #define SYS_GPG_MFPL_PG3MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for GPIO */ 1233 #define SYS_GPG_MFPL_PG3MFP_EBI_ADR12 (0x2UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for EBI_ADR12 */ 1234 #define SYS_GPG_MFPL_PG3MFP_SPI2_CLK (0x3UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for SPI2_CLK */ 1235 #define SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS (0x4UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C0_SMBSUS */ 1236 #define SYS_GPG_MFPL_PG3MFP_I2C1_SDA (0x5UL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for I2C1_SDA */ 1237 #define SYS_GPG_MFPL_PG3MFP_TM1 (0xDUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for TM1 */ 1238 #define SYS_GPG_MFPL_PG3MFP_LCD_SEG38 (0xFUL<<SYS_GPG_MFPL_PG3MFP_Pos) /*!< GPG_MFPL PG3 setting for LCD_SEG38 */ 1239 1240 /* PG.4 MFP */ 1241 #define SYS_GPG_MFPL_PG4MFP_GPIO (0x0UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for GPIO */ 1242 #define SYS_GPG_MFPL_PG4MFP_EBI_ADR13 (0x2UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for EBI_ADR13 */ 1243 #define SYS_GPG_MFPL_PG4MFP_SPI2_MISO (0x3UL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for SPI2_MISO */ 1244 #define SYS_GPG_MFPL_PG4MFP_TM4 (0xCUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for TM4 */ 1245 #define SYS_GPG_MFPL_PG4MFP_TM2 (0xDUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for TM2 */ 1246 #define SYS_GPG_MFPL_PG4MFP_LCD_SEG37 (0xFUL<<SYS_GPG_MFPL_PG4MFP_Pos) /*!< GPG_MFPL PG4 setting for LCD_SEG37 */ 1247 1248 /* PG.9 MFP */ 1249 #define SYS_GPG_MFPH_PG9MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO */ 1250 #define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x2UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for EBI_AD0 */ 1251 #define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0xCUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for BPWM0_CH5 */ 1252 #define SYS_GPG_MFPH_PG9MFP_LCD_SEG21 (0xFUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for LCD_SEG21 */ 1253 1254 /* PG.10 MFP */ 1255 #define SYS_GPG_MFPH_PG10MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for GPIO */ 1256 #define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x2UL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for EBI_AD1 */ 1257 #define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0xCUL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for BPWM0_CH4 */ 1258 #define SYS_GPG_MFPH_PG10MFP_LCD_SEG20 (0xFUL<<SYS_GPG_MFPH_PG10MFP_Pos) /*!< GPG_MFPH PG10 setting for LCD_SEG20 */ 1259 1260 /* PG.11 MFP */ 1261 #define SYS_GPG_MFPH_PG11MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for GPIO */ 1262 #define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x2UL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for EBI_AD2 */ 1263 #define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0xCUL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for BPWM0_CH3 */ 1264 #define SYS_GPG_MFPH_PG11MFP_LCD_SEG19 (0xFUL<<SYS_GPG_MFPH_PG11MFP_Pos) /*!< GPG_MFPH PG11 setting for LCD_SEG19 */ 1265 1266 /* PG.12 MFP */ 1267 #define SYS_GPG_MFPH_PG12MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for GPIO */ 1268 #define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x2UL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for EBI_AD3 */ 1269 #define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0xCUL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for BPWM0_CH2 */ 1270 #define SYS_GPG_MFPH_PG12MFP_LCD_SEG18 (0xFUL<<SYS_GPG_MFPH_PG12MFP_Pos) /*!< GPG_MFPH PG12 setting for LCD_SEG18 */ 1271 1272 /* PG.13 MFP */ 1273 #define SYS_GPG_MFPH_PG13MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for GPIO */ 1274 #define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x2UL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for EBI_AD4 */ 1275 #define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0xCUL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for BPWM0_CH1 */ 1276 #define SYS_GPG_MFPH_PG13MFP_LCD_SEG17 (0xFUL<<SYS_GPG_MFPH_PG13MFP_Pos) /*!< GPG_MFPH PG13 setting for LCD_SEG17 */ 1277 1278 /* PG.14 MFP */ 1279 #define SYS_GPG_MFPH_PG14MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for GPIO */ 1280 #define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x2UL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for EBI_AD5 */ 1281 #define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0xCUL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for BPWM0_CH0 */ 1282 #define SYS_GPG_MFPH_PG14MFP_LCD_SEG16 (0xFUL<<SYS_GPG_MFPH_PG14MFP_Pos) /*!< GPG_MFPH PG14 setting for LCD_SEG16 */ 1283 1284 /* PG.15 MFP */ 1285 #define SYS_GPG_MFPH_PG15MFP_GPIO (0x0UL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for GPIO */ 1286 #define SYS_GPG_MFPH_PG15MFP_LCD_SEG15 (0xDUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for LCD_SEG15 */ 1287 #define SYS_GPG_MFPH_PG15MFP_CLKO (0xEUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for CLKO */ 1288 #define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0xFUL<<SYS_GPG_MFPH_PG15MFP_Pos) /*!< GPG_MFPH PG15 setting for EADC0_ST */ 1289 1290 /* PH.4 MFP */ 1291 #define SYS_GPH_MFPL_PH4MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for GPIO */ 1292 #define SYS_GPH_MFPL_PH4MFP_EBI_ADR3 (0x2UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for EBI_ADR3 */ 1293 #define SYS_GPH_MFPL_PH4MFP_SPI1_MISO (0x3UL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for SPI1_MISO */ 1294 #define SYS_GPH_MFPL_PH4MFP_LCD_SEG36 (0xFUL<<SYS_GPH_MFPL_PH4MFP_Pos) /*!< GPH_MFPL PH4 setting for LCD_SEG36 */ 1295 1296 /* PH.5 MFP */ 1297 #define SYS_GPH_MFPL_PH5MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for GPIO */ 1298 #define SYS_GPH_MFPL_PH5MFP_EBI_ADR2 (0x2UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for EBI_ADR2 */ 1299 #define SYS_GPH_MFPL_PH5MFP_SPI1_MOSI (0x3UL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for SPI1_MOSI */ 1300 #define SYS_GPH_MFPL_PH5MFP_LCD_SEG35 (0xFUL<<SYS_GPH_MFPL_PH5MFP_Pos) /*!< GPH_MFPL PH5 setting for LCD_SEG35 */ 1301 1302 /* PH.6 MFP */ 1303 #define SYS_GPH_MFPL_PH6MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for GPIO */ 1304 #define SYS_GPH_MFPL_PH6MFP_EBI_ADR1 (0x2UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for EBI_ADR1 */ 1305 #define SYS_GPH_MFPL_PH6MFP_SPI1_CLK (0x3UL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for SPI1_CLK */ 1306 #define SYS_GPH_MFPL_PH6MFP_LCD_SEG34 (0xFUL<<SYS_GPH_MFPL_PH6MFP_Pos) /*!< GPH_MFPL PH6 setting for LCD_SEG34 */ 1307 1308 /* PH.7 MFP */ 1309 #define SYS_GPH_MFPL_PH7MFP_GPIO (0x0UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for GPIO */ 1310 #define SYS_GPH_MFPL_PH7MFP_EBI_ADR0 (0x2UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for EBI_ADR0 */ 1311 #define SYS_GPH_MFPL_PH7MFP_SPI1_SS (0x3UL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for SPI1_SS */ 1312 #define SYS_GPH_MFPL_PH7MFP_LCD_SEG33 (0xFUL<<SYS_GPH_MFPL_PH7MFP_Pos) /*!< GPH_MFPL PH7 setting for LCD_SEG33 */ 1313 1314 /* PH.8 MFP */ 1315 #define SYS_GPH_MFPH_PH8MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for GPIO */ 1316 #define SYS_GPH_MFPH_PH8MFP_EBI_AD12 (0x2UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for EBI_AD12 */ 1317 #define SYS_GPH_MFPH_PH8MFP_QSPI0_CLK (0x3UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for QSPI0_CLK */ 1318 #define SYS_GPH_MFPH_PH8MFP_SC2_PWR (0x4UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SC2_PWR */ 1319 #define SYS_GPH_MFPH_PH8MFP_I2S0_DI (0x5UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2S0_DI */ 1320 #define SYS_GPH_MFPH_PH8MFP_SPI1_CLK (0x6UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for SPI1_CLK */ 1321 #define SYS_GPH_MFPH_PH8MFP_UART3_nRTS (0x7UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART3_nRTS */ 1322 #define SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL (0x8UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2C1_SMBAL */ 1323 #define SYS_GPH_MFPH_PH8MFP_I2C2_SCL (0x9UL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for I2C2_SCL */ 1324 #define SYS_GPH_MFPH_PH8MFP_UART1_TXD (0xAUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for UART1_TXD */ 1325 #define SYS_GPH_MFPH_PH8MFP_LCD_SEG4 (0xFUL<<SYS_GPH_MFPH_PH8MFP_Pos) /*!< GPH_MFPH PH8 setting for LCD_SEG4 */ 1326 1327 /* PH.9 MFP */ 1328 #define SYS_GPH_MFPH_PH9MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for GPIO */ 1329 #define SYS_GPH_MFPH_PH9MFP_EBI_AD13 (0x2UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for EBI_AD13 */ 1330 #define SYS_GPH_MFPH_PH9MFP_QSPI0_SS (0x3UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for QSPI0_SS */ 1331 #define SYS_GPH_MFPH_PH9MFP_SC2_RST (0x4UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SC2_RST */ 1332 #define SYS_GPH_MFPH_PH9MFP_I2S0_DO (0x5UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2S0_DO */ 1333 #define SYS_GPH_MFPH_PH9MFP_SPI1_SS (0x6UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for SPI1_SS */ 1334 #define SYS_GPH_MFPH_PH9MFP_UART3_nCTS (0x7UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART3_nCTS */ 1335 #define SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS (0x8UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2C1_SMBSUS */ 1336 #define SYS_GPH_MFPH_PH9MFP_I2C2_SDA (0x9UL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for I2C2_SDA */ 1337 #define SYS_GPH_MFPH_PH9MFP_UART1_RXD (0xAUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for UART1_RXD */ 1338 #define SYS_GPH_MFPH_PH9MFP_LCD_SEG3 (0xFUL<<SYS_GPH_MFPH_PH9MFP_Pos) /*!< GPH_MFPH PH9 setting for LCD_SEG3 */ 1339 1340 /* PH.10 MFP */ 1341 #define SYS_GPH_MFPH_PH10MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for GPIO */ 1342 #define SYS_GPH_MFPH_PH10MFP_EBI_AD14 (0x2UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for EBI_AD14 */ 1343 #define SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 (0x3UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for QSPI0_MISO1 */ 1344 #define SYS_GPH_MFPH_PH10MFP_SC2_nCD (0x4UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for SC2_nCD */ 1345 #define SYS_GPH_MFPH_PH10MFP_I2S0_LRCK (0x5UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for I2S0_LRCK */ 1346 #define SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK (0x6UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for SPI1_I2SMCLK */ 1347 #define SYS_GPH_MFPH_PH10MFP_UART4_TXD (0x7UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for UART4_TXD */ 1348 #define SYS_GPH_MFPH_PH10MFP_UART0_TXD (0x8UL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for UART0_TXD */ 1349 #define SYS_GPH_MFPH_PH10MFP_LCD_SEG2 (0xFUL<<SYS_GPH_MFPH_PH10MFP_Pos) /*!< GPH_MFPH PH10 setting for LCD_SEG2 */ 1350 1351 /* PH.11 MFP */ 1352 #define SYS_GPH_MFPH_PH11MFP_GPIO (0x0UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for GPIO */ 1353 #define SYS_GPH_MFPH_PH11MFP_EBI_AD15 (0x2UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for EBI_AD15 */ 1354 #define SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 (0x3UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for QSPI0_MOSI1 */ 1355 #define SYS_GPH_MFPH_PH11MFP_UART4_RXD (0x7UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for UART4_RXD */ 1356 #define SYS_GPH_MFPH_PH11MFP_UART0_RXD (0x8UL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for UART0_RXD */ 1357 #define SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 (0xBUL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for EPWM0_CH5 */ 1358 #define SYS_GPH_MFPH_PH11MFP_LCD_SEG1 (0xFUL<<SYS_GPH_MFPH_PH11MFP_Pos) /*!< GPH_MFPH PH11 setting for LCD_SEG1 */ 1359 1360 1361 /*---------------------------------------------------------------------------------------------------------*/ 1362 /* Multi-Function setting constant definitions abbreviation. */ 1363 /*---------------------------------------------------------------------------------------------------------*/ 1364 1365 #define ACMP0_N_PB3 SYS_GPB_MFPL_PB3MFP_ACMP0_N /*!< GPB_MFPL PB3 setting for ACMP0_N*/ 1366 #define ACMP0_O_PB7 SYS_GPB_MFPL_PB7MFP_ACMP0_O /*!< GPB_MFPL PB7 setting for ACMP0_O*/ 1367 #define ACMP0_O_PC1 SYS_GPC_MFPL_PC1MFP_ACMP0_O /*!< GPC_MFPL PC1 setting for ACMP0_O*/ 1368 #define ACMP0_O_PC12 SYS_GPC_MFPH_PC12MFP_ACMP0_O /*!< GPC_MFPH PC12 setting for ACMP0_O*/ 1369 #define ACMP0_P0_PA11 SYS_GPA_MFPH_PA11MFP_ACMP0_P0 /*!< GPA_MFPH PA11 setting for ACMP0_P0*/ 1370 #define ACMP0_P1_PB2 SYS_GPB_MFPL_PB2MFP_ACMP0_P1 /*!< GPB_MFPL PB2 setting for ACMP0_P1*/ 1371 #define ACMP0_P2_PB12 SYS_GPB_MFPH_PB12MFP_ACMP0_P2 /*!< GPB_MFPH PB12 setting for ACMP0_P2*/ 1372 #define ACMP0_P3_PB13 SYS_GPB_MFPH_PB13MFP_ACMP0_P3 /*!< GPB_MFPH PB13 setting for ACMP0_P3*/ 1373 #define ACMP0_WLAT_PA7 SYS_GPA_MFPL_PA7MFP_ACMP0_WLAT /*!< GPA_MFPL PA7 setting for ACMP0_WLAT*/ 1374 #define ACMP1_N_PB5 SYS_GPB_MFPL_PB5MFP_ACMP1_N /*!< GPB_MFPL PB5 setting for ACMP1_N*/ 1375 #define ACMP1_O_PB6 SYS_GPB_MFPL_PB6MFP_ACMP1_O /*!< GPB_MFPL PB6 setting for ACMP1_O*/ 1376 #define ACMP1_O_PC11 SYS_GPC_MFPH_PC11MFP_ACMP1_O /*!< GPC_MFPH PC11 setting for ACMP1_O*/ 1377 #define ACMP1_O_PC0 SYS_GPC_MFPL_PC0MFP_ACMP1_O /*!< GPC_MFPL PC0 setting for ACMP1_O*/ 1378 #define ACMP1_P0_PA10 SYS_GPA_MFPH_PA10MFP_ACMP1_P0 /*!< GPA_MFPH PA10 setting for ACMP1_P0*/ 1379 #define ACMP1_P1_PB4 SYS_GPB_MFPL_PB4MFP_ACMP1_P1 /*!< GPB_MFPL PB4 setting for ACMP1_P1*/ 1380 #define ACMP1_P2_PB12 SYS_GPB_MFPH_PB12MFP_ACMP1_P2 /*!< GPB_MFPH PB12 setting for ACMP1_P2*/ 1381 #define ACMP1_P3_PB13 SYS_GPB_MFPH_PB13MFP_ACMP1_P3 /*!< GPB_MFPH PB13 setting for ACMP1_P3*/ 1382 #define ACMP1_WLAT_PA6 SYS_GPA_MFPL_PA6MFP_ACMP1_WLAT /*!< GPA_MFPL PA6 setting for ACMP1_WLAT*/ 1383 #define BPWM0_CH0_PA0 SYS_GPA_MFPL_PA0MFP_BPWM0_CH0 /*!< GPA_MFPL PA0 setting for BPWM0_CH0*/ 1384 #define BPWM0_CH0_PA11 SYS_GPA_MFPH_PA11MFP_BPWM0_CH0 /*!< GPA_MFPH PA11 setting for BPWM0_CH0*/ 1385 #define BPWM0_CH0_PE2 SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 /*!< GPE_MFPL PE2 setting for BPWM0_CH0*/ 1386 #define BPWM0_CH0_PG14 SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 /*!< GPG_MFPH PG14 setting for BPWM0_CH0*/ 1387 #define BPWM0_CH1_PA1 SYS_GPA_MFPL_PA1MFP_BPWM0_CH1 /*!< GPA_MFPL PA1 setting for BPWM0_CH1*/ 1388 #define BPWM0_CH1_PE3 SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 /*!< GPE_MFPL PE3 setting for BPWM0_CH1*/ 1389 #define BPWM0_CH1_PG13 SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 /*!< GPG_MFPH PG13 setting for BPWM0_CH1*/ 1390 #define BPWM0_CH1_PA10 SYS_GPA_MFPH_PA10MFP_BPWM0_CH1 /*!< GPA_MFPH PA10 setting for BPWM0_CH1*/ 1391 #define BPWM0_CH2_PE4 SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 /*!< GPE_MFPL PE4 setting for BPWM0_CH2*/ 1392 #define BPWM0_CH2_PG12 SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 /*!< GPG_MFPH PG12 setting for BPWM0_CH2*/ 1393 #define BPWM0_CH2_PA2 SYS_GPA_MFPL_PA2MFP_BPWM0_CH2 /*!< GPA_MFPL PA2 setting for BPWM0_CH2*/ 1394 #define BPWM0_CH2_PA9 SYS_GPA_MFPH_PA9MFP_BPWM0_CH2 /*!< GPA_MFPH PA9 setting for BPWM0_CH2*/ 1395 #define BPWM0_CH3_PG11 SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 /*!< GPG_MFPH PG11 setting for BPWM0_CH3*/ 1396 #define BPWM0_CH3_PA3 SYS_GPA_MFPL_PA3MFP_BPWM0_CH3 /*!< GPA_MFPL PA3 setting for BPWM0_CH3*/ 1397 #define BPWM0_CH3_PA8 SYS_GPA_MFPH_PA8MFP_BPWM0_CH3 /*!< GPA_MFPH PA8 setting for BPWM0_CH3*/ 1398 #define BPWM0_CH3_PE5 SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 /*!< GPE_MFPL PE5 setting for BPWM0_CH3*/ 1399 #define BPWM0_CH4_PG10 SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 /*!< GPG_MFPH PG10 setting for BPWM0_CH4*/ 1400 #define BPWM0_CH4_PA4 SYS_GPA_MFPL_PA4MFP_BPWM0_CH4 /*!< GPA_MFPL PA4 setting for BPWM0_CH4*/ 1401 #define BPWM0_CH4_PC13 SYS_GPC_MFPH_PC13MFP_BPWM0_CH4 /*!< GPC_MFPH PC13 setting for BPWM0_CH4*/ 1402 #define BPWM0_CH4_PE6 SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 /*!< GPE_MFPL PE6 setting for BPWM0_CH4*/ 1403 #define BPWM0_CH4_PF5 SYS_GPF_MFPL_PF5MFP_BPWM0_CH4 /*!< GPF_MFPL PF5 setting for BPWM0_CH4*/ 1404 #define BPWM0_CH5_PA5 SYS_GPA_MFPL_PA5MFP_BPWM0_CH5 /*!< GPA_MFPL PA5 setting for BPWM0_CH5*/ 1405 #define BPWM0_CH5_PE7 SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 /*!< GPE_MFPL PE7 setting for BPWM0_CH5*/ 1406 #define BPWM0_CH5_PF4 SYS_GPF_MFPL_PF4MFP_BPWM0_CH5 /*!< GPF_MFPL PF4 setting for BPWM0_CH5*/ 1407 #define BPWM0_CH5_PD12 SYS_GPD_MFPH_PD12MFP_BPWM0_CH5 /*!< GPD_MFPH PD12 setting for BPWM0_CH5*/ 1408 #define BPWM0_CH5_PG9 SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 /*!< GPG_MFPH PG9 setting for BPWM0_CH5*/ 1409 #define BPWM1_CH0_PB11 SYS_GPB_MFPH_PB11MFP_BPWM1_CH0 /*!< GPB_MFPH PB11 setting for BPWM1_CH0*/ 1410 #define BPWM1_CH0_PC7 SYS_GPC_MFPL_PC7MFP_BPWM1_CH0 /*!< GPC_MFPL PC7 setting for BPWM1_CH0*/ 1411 #define BPWM1_CH0_PF0 SYS_GPF_MFPL_PF0MFP_BPWM1_CH0 /*!< GPF_MFPL PF0 setting for BPWM1_CH0*/ 1412 #define BPWM1_CH0_PF3 SYS_GPF_MFPL_PF3MFP_BPWM1_CH0 /*!< GPF_MFPL PF3 setting for BPWM1_CH0*/ 1413 #define BPWM1_CH1_PC6 SYS_GPC_MFPL_PC6MFP_BPWM1_CH1 /*!< GPC_MFPL PC6 setting for BPWM1_CH1*/ 1414 #define BPWM1_CH1_PF1 SYS_GPF_MFPL_PF1MFP_BPWM1_CH1 /*!< GPF_MFPL PF1 setting for BPWM1_CH1*/ 1415 #define BPWM1_CH1_PF2 SYS_GPF_MFPL_PF2MFP_BPWM1_CH1 /*!< GPF_MFPL PF2 setting for BPWM1_CH1*/ 1416 #define BPWM1_CH1_PB10 SYS_GPB_MFPH_PB10MFP_BPWM1_CH1 /*!< GPB_MFPH PB10 setting for BPWM1_CH1*/ 1417 #define BPWM1_CH2_PB9 SYS_GPB_MFPH_PB9MFP_BPWM1_CH2 /*!< GPB_MFPH PB9 setting for BPWM1_CH2*/ 1418 #define BPWM1_CH2_PA7 SYS_GPA_MFPL_PA7MFP_BPWM1_CH2 /*!< GPA_MFPL PA7 setting for BPWM1_CH2*/ 1419 #define BPWM1_CH2_PA12 SYS_GPA_MFPH_PA12MFP_BPWM1_CH2 /*!< GPA_MFPH PA12 setting for BPWM1_CH2*/ 1420 #define BPWM1_CH3_PA6 SYS_GPA_MFPL_PA6MFP_BPWM1_CH3 /*!< GPA_MFPL PA6 setting for BPWM1_CH3*/ 1421 #define BPWM1_CH3_PA13 SYS_GPA_MFPH_PA13MFP_BPWM1_CH3 /*!< GPA_MFPH PA13 setting for BPWM1_CH3*/ 1422 #define BPWM1_CH3_PB8 SYS_GPB_MFPH_PB8MFP_BPWM1_CH3 /*!< GPB_MFPH PB8 setting for BPWM1_CH3*/ 1423 #define BPWM1_CH4_PA14 SYS_GPA_MFPH_PA14MFP_BPWM1_CH4 /*!< GPA_MFPH PA14 setting for BPWM1_CH4*/ 1424 #define BPWM1_CH4_PC8 SYS_GPC_MFPH_PC8MFP_BPWM1_CH4 /*!< GPC_MFPH PC8 setting for BPWM1_CH4*/ 1425 #define BPWM1_CH4_PB7 SYS_GPB_MFPL_PB7MFP_BPWM1_CH4 /*!< GPB_MFPL PB7 setting for BPWM1_CH4*/ 1426 #define BPWM1_CH5_PA15 SYS_GPA_MFPH_PA15MFP_BPWM1_CH5 /*!< GPA_MFPH PA15 setting for BPWM1_CH5*/ 1427 #define BPWM1_CH5_PB6 SYS_GPB_MFPL_PB6MFP_BPWM1_CH5 /*!< GPB_MFPL PB6 setting for BPWM1_CH5*/ 1428 #define BPWM1_CH5_PE13 SYS_GPE_MFPH_PE13MFP_BPWM1_CH5 /*!< GPE_MFPH PE13 setting for BPWM1_CH5*/ 1429 #define CAN0_RXD_PA13 SYS_GPA_MFPH_PA13MFP_CAN0_RXD /*!< GPA_MFPH PA13 setting for CAN0_RXD*/ 1430 #define CAN0_RXD_PD10 SYS_GPD_MFPH_PD10MFP_CAN0_RXD /*!< GPD_MFPH PD10 setting for CAN0_RXD*/ 1431 #define CAN0_RXD_PA4 SYS_GPA_MFPL_PA4MFP_CAN0_RXD /*!< GPA_MFPL PA4 setting for CAN0_RXD*/ 1432 #define CAN0_RXD_PC4 SYS_GPC_MFPL_PC4MFP_CAN0_RXD /*!< GPC_MFPL PC4 setting for CAN0_RXD*/ 1433 #define CAN0_RXD_PB10 SYS_GPB_MFPH_PB10MFP_CAN0_RXD /*!< GPB_MFPH PB10 setting for CAN0_RXD*/ 1434 #define CAN0_RXD_PE15 SYS_GPE_MFPH_PE15MFP_CAN0_RXD /*!< GPE_MFPH PE15 setting for CAN0_RXD*/ 1435 #define CAN0_TXD_PD11 SYS_GPD_MFPH_PD11MFP_CAN0_TXD /*!< GPD_MFPH PD11 setting for CAN0_TXD*/ 1436 #define CAN0_TXD_PC5 SYS_GPC_MFPL_PC5MFP_CAN0_TXD /*!< GPC_MFPL PC5 setting for CAN0_TXD*/ 1437 #define CAN0_TXD_PB11 SYS_GPB_MFPH_PB11MFP_CAN0_TXD /*!< GPB_MFPH PB11 setting for CAN0_TXD*/ 1438 #define CAN0_TXD_PA12 SYS_GPA_MFPH_PA12MFP_CAN0_TXD /*!< GPA_MFPH PA12 setting for CAN0_TXD*/ 1439 #define CAN0_TXD_PE14 SYS_GPE_MFPH_PE14MFP_CAN0_TXD /*!< GPE_MFPH PE14 setting for CAN0_TXD*/ 1440 #define CAN0_TXD_PA5 SYS_GPA_MFPL_PA5MFP_CAN0_TXD /*!< GPA_MFPL PA5 setting for CAN0_TXD*/ 1441 #define CLKO_PC13 SYS_GPC_MFPH_PC13MFP_CLKO /*!< GPC_MFPH PC13 setting for CLKO*/ 1442 #define CLKO_PB14 SYS_GPB_MFPH_PB14MFP_CLKO /*!< GPB_MFPH PB14 setting for CLKO*/ 1443 #define CLKO_PD12 SYS_GPD_MFPH_PD12MFP_CLKO /*!< GPD_MFPH PD12 setting for CLKO*/ 1444 #define CLKO_PG15 SYS_GPG_MFPH_PG15MFP_CLKO /*!< GPG_MFPH PG15 setting for CLKO*/ 1445 #define DAC0_OUT_PB12 SYS_GPB_MFPH_PB12MFP_DAC0_OUT /*!< GPB_MFPH PB12 setting for DAC0_OUT*/ 1446 #define DAC0_OUT_PB12 SYS_GPB_MFPH_PB12MFP_DAC0_OUT /*!< GPB_MFPH PB12 setting for DAC0_OUT*/ 1447 #define DAC0_ST_PA0 SYS_GPA_MFPL_PA0MFP_DAC0_ST /*!< GPA_MFPL PA0 setting for DAC0_ST*/ 1448 #define DAC0_ST_PA10 SYS_GPA_MFPH_PA10MFP_DAC0_ST /*!< GPA_MFPH PA10 setting for DAC0_ST*/ 1449 #define DAC1_OUT_PB13 SYS_GPB_MFPH_PB13MFP_DAC1_OUT /*!< GPB_MFPH PB13 setting for DAC1_OUT*/ 1450 #define DAC1_OUT_PB13 SYS_GPB_MFPH_PB13MFP_DAC1_OUT /*!< GPB_MFPH PB13 setting for DAC1_OUT*/ 1451 #define DAC1_ST_PA1 SYS_GPA_MFPL_PA1MFP_DAC1_ST /*!< GPA_MFPL PA1 setting for DAC1_ST*/ 1452 #define DAC1_ST_PA11 SYS_GPA_MFPH_PA11MFP_DAC1_ST /*!< GPA_MFPH PA11 setting for DAC1_ST*/ 1453 #define EADC0_CH0_PB0 SYS_GPB_MFPL_PB0MFP_EADC0_CH0 /*!< GPB_MFPL PB0 setting for EADC0_CH0*/ 1454 #define EADC0_CH1_PB1 SYS_GPB_MFPL_PB1MFP_EADC0_CH1 /*!< GPB_MFPL PB1 setting for EADC0_CH1*/ 1455 #define EADC0_CH10_PB10 SYS_GPB_MFPH_PB10MFP_EADC0_CH10 /*!< GPB_MFPH PB10 setting for EADC0_CH10*/ 1456 #define EADC0_CH11_PB11 SYS_GPB_MFPH_PB11MFP_EADC0_CH11 /*!< GPB_MFPH PB11 setting for EADC0_CH11*/ 1457 #define EADC0_CH12_PB12 SYS_GPB_MFPH_PB12MFP_EADC0_CH12 /*!< GPB_MFPH PB12 setting for EADC0_CH12*/ 1458 #define EADC0_CH13_PB13 SYS_GPB_MFPH_PB13MFP_EADC0_CH13 /*!< GPB_MFPH PB13 setting for EADC0_CH13*/ 1459 #define EADC0_CH14_PB14 SYS_GPB_MFPH_PB14MFP_EADC0_CH14 /*!< GPB_MFPH PB14 setting for EADC0_CH14*/ 1460 #define EADC0_CH15_PB15 SYS_GPB_MFPH_PB15MFP_EADC0_CH15 /*!< GPB_MFPH PB15 setting for EADC0_CH15*/ 1461 #define EADC0_CH15_PD10 SYS_GPD_MFPH_PD10MFP_EADC0_CH15 /*!< GPD_MFPH PD10 setting for EADC0_CH15*/ 1462 #define EADC0_CH2_PB2 SYS_GPB_MFPL_PB2MFP_EADC0_CH2 /*!< GPB_MFPL PB2 setting for EADC0_CH2*/ 1463 #define EADC0_CH3_PB3 SYS_GPB_MFPL_PB3MFP_EADC0_CH3 /*!< GPB_MFPL PB3 setting for EADC0_CH3*/ 1464 #define EADC0_CH4_PB4 SYS_GPB_MFPL_PB4MFP_EADC0_CH4 /*!< GPB_MFPL PB4 setting for EADC0_CH4*/ 1465 #define EADC0_CH5_PB5 SYS_GPB_MFPL_PB5MFP_EADC0_CH5 /*!< GPB_MFPL PB5 setting for EADC0_CH5*/ 1466 #define EADC0_CH6_PB6 SYS_GPB_MFPL_PB6MFP_EADC0_CH6 /*!< GPB_MFPL PB6 setting for EADC0_CH6*/ 1467 #define EADC0_CH7_PB7 SYS_GPB_MFPL_PB7MFP_EADC0_CH7 /*!< GPB_MFPL PB7 setting for EADC0_CH7*/ 1468 #define EADC0_CH8_PB8 SYS_GPB_MFPH_PB8MFP_EADC0_CH8 /*!< GPB_MFPH PB8 setting for EADC0_CH8*/ 1469 #define EADC0_CH9_PB9 SYS_GPB_MFPH_PB9MFP_EADC0_CH9 /*!< GPB_MFPH PB9 setting for EADC0_CH9*/ 1470 #define EADC0_ST_PF5 SYS_GPF_MFPL_PF5MFP_EADC0_ST /*!< GPF_MFPL PF5 setting for EADC0_ST*/ 1471 #define EADC0_ST_PC13 SYS_GPC_MFPH_PC13MFP_EADC0_ST /*!< GPC_MFPH PC13 setting for EADC0_ST*/ 1472 #define EADC0_ST_PC1 SYS_GPC_MFPL_PC1MFP_EADC0_ST /*!< GPC_MFPL PC1 setting for EADC0_ST*/ 1473 #define EADC0_ST_PD12 SYS_GPD_MFPH_PD12MFP_EADC0_ST /*!< GPD_MFPH PD12 setting for EADC0_ST*/ 1474 #define EADC0_ST_PG15 SYS_GPG_MFPH_PG15MFP_EADC0_ST /*!< GPG_MFPH PG15 setting for EADC0_ST*/ 1475 #define EBI_AD0_PC0 SYS_GPC_MFPL_PC0MFP_EBI_AD0 /*!< GPC_MFPL PC0 setting for EBI_AD0*/ 1476 #define EBI_AD0_PG9 SYS_GPG_MFPH_PG9MFP_EBI_AD0 /*!< GPG_MFPH PG9 setting for EBI_AD0*/ 1477 #define EBI_AD1_PG10 SYS_GPG_MFPH_PG10MFP_EBI_AD1 /*!< GPG_MFPH PG10 setting for EBI_AD1*/ 1478 #define EBI_AD1_PC1 SYS_GPC_MFPL_PC1MFP_EBI_AD1 /*!< GPC_MFPL PC1 setting for EBI_AD1*/ 1479 #define EBI_AD10_PE1 SYS_GPE_MFPL_PE1MFP_EBI_AD10 /*!< GPE_MFPL PE1 setting for EBI_AD10*/ 1480 #define EBI_AD10_PD3 SYS_GPD_MFPL_PD3MFP_EBI_AD10 /*!< GPD_MFPL PD3 setting for EBI_AD10*/ 1481 #define EBI_AD10_PD13 SYS_GPD_MFPH_PD13MFP_EBI_AD10 /*!< GPD_MFPH PD13 setting for EBI_AD10*/ 1482 #define EBI_AD11_PE0 SYS_GPE_MFPL_PE0MFP_EBI_AD11 /*!< GPE_MFPL PE0 setting for EBI_AD11*/ 1483 #define EBI_AD11_PD2 SYS_GPD_MFPL_PD2MFP_EBI_AD11 /*!< GPD_MFPL PD2 setting for EBI_AD11*/ 1484 #define EBI_AD12_PD1 SYS_GPD_MFPL_PD1MFP_EBI_AD12 /*!< GPD_MFPL PD1 setting for EBI_AD12*/ 1485 #define EBI_AD12_PB15 SYS_GPB_MFPH_PB15MFP_EBI_AD12 /*!< GPB_MFPH PB15 setting for EBI_AD12*/ 1486 #define EBI_AD12_PH8 SYS_GPH_MFPH_PH8MFP_EBI_AD12 /*!< GPH_MFPH PH8 setting for EBI_AD12*/ 1487 #define EBI_AD13_PD0 SYS_GPD_MFPL_PD0MFP_EBI_AD13 /*!< GPD_MFPL PD0 setting for EBI_AD13*/ 1488 #define EBI_AD13_PB14 SYS_GPB_MFPH_PB14MFP_EBI_AD13 /*!< GPB_MFPH PB14 setting for EBI_AD13*/ 1489 #define EBI_AD13_PH9 SYS_GPH_MFPH_PH9MFP_EBI_AD13 /*!< GPH_MFPH PH9 setting for EBI_AD13*/ 1490 #define EBI_AD14_PB13 SYS_GPB_MFPH_PB13MFP_EBI_AD14 /*!< GPB_MFPH PB13 setting for EBI_AD14*/ 1491 #define EBI_AD14_PH10 SYS_GPH_MFPH_PH10MFP_EBI_AD14 /*!< GPH_MFPH PH10 setting for EBI_AD14*/ 1492 #define EBI_AD15_PB12 SYS_GPB_MFPH_PB12MFP_EBI_AD15 /*!< GPB_MFPH PB12 setting for EBI_AD15*/ 1493 #define EBI_AD15_PH11 SYS_GPH_MFPH_PH11MFP_EBI_AD15 /*!< GPH_MFPH PH11 setting for EBI_AD15*/ 1494 #define EBI_AD2_PC2 SYS_GPC_MFPL_PC2MFP_EBI_AD2 /*!< GPC_MFPL PC2 setting for EBI_AD2*/ 1495 #define EBI_AD2_PG11 SYS_GPG_MFPH_PG11MFP_EBI_AD2 /*!< GPG_MFPH PG11 setting for EBI_AD2*/ 1496 #define EBI_AD3_PG12 SYS_GPG_MFPH_PG12MFP_EBI_AD3 /*!< GPG_MFPH PG12 setting for EBI_AD3*/ 1497 #define EBI_AD3_PC3 SYS_GPC_MFPL_PC3MFP_EBI_AD3 /*!< GPC_MFPL PC3 setting for EBI_AD3*/ 1498 #define EBI_AD4_PC4 SYS_GPC_MFPL_PC4MFP_EBI_AD4 /*!< GPC_MFPL PC4 setting for EBI_AD4*/ 1499 #define EBI_AD4_PG13 SYS_GPG_MFPH_PG13MFP_EBI_AD4 /*!< GPG_MFPH PG13 setting for EBI_AD4*/ 1500 #define EBI_AD5_PG14 SYS_GPG_MFPH_PG14MFP_EBI_AD5 /*!< GPG_MFPH PG14 setting for EBI_AD5*/ 1501 #define EBI_AD5_PC5 SYS_GPC_MFPL_PC5MFP_EBI_AD5 /*!< GPC_MFPL PC5 setting for EBI_AD5*/ 1502 #define EBI_AD6_PD8 SYS_GPD_MFPH_PD8MFP_EBI_AD6 /*!< GPD_MFPH PD8 setting for EBI_AD6*/ 1503 #define EBI_AD6_PA6 SYS_GPA_MFPL_PA6MFP_EBI_AD6 /*!< GPA_MFPL PA6 setting for EBI_AD6*/ 1504 #define EBI_AD7_PD9 SYS_GPD_MFPH_PD9MFP_EBI_AD7 /*!< GPD_MFPH PD9 setting for EBI_AD7*/ 1505 #define EBI_AD7_PA7 SYS_GPA_MFPL_PA7MFP_EBI_AD7 /*!< GPA_MFPL PA7 setting for EBI_AD7*/ 1506 #define EBI_AD8_PE14 SYS_GPE_MFPH_PE14MFP_EBI_AD8 /*!< GPE_MFPH PE14 setting for EBI_AD8*/ 1507 #define EBI_AD8_PC6 SYS_GPC_MFPL_PC6MFP_EBI_AD8 /*!< GPC_MFPL PC6 setting for EBI_AD8*/ 1508 #define EBI_AD9_PC7 SYS_GPC_MFPL_PC7MFP_EBI_AD9 /*!< GPC_MFPL PC7 setting for EBI_AD9*/ 1509 #define EBI_AD9_PE15 SYS_GPE_MFPH_PE15MFP_EBI_AD9 /*!< GPE_MFPH PE15 setting for EBI_AD9*/ 1510 #define EBI_ADR0_PB5 SYS_GPB_MFPL_PB5MFP_EBI_ADR0 /*!< GPB_MFPL PB5 setting for EBI_ADR0*/ 1511 #define EBI_ADR0_PH7 SYS_GPH_MFPL_PH7MFP_EBI_ADR0 /*!< GPH_MFPL PH7 setting for EBI_ADR0*/ 1512 #define EBI_ADR1_PH6 SYS_GPH_MFPL_PH6MFP_EBI_ADR1 /*!< GPH_MFPL PH6 setting for EBI_ADR1*/ 1513 #define EBI_ADR1_PB4 SYS_GPB_MFPL_PB4MFP_EBI_ADR1 /*!< GPB_MFPL PB4 setting for EBI_ADR1*/ 1514 #define EBI_ADR10_PC13 SYS_GPC_MFPH_PC13MFP_EBI_ADR10 /*!< GPC_MFPH PC13 setting for EBI_ADR10*/ 1515 #define EBI_ADR10_PE8 SYS_GPE_MFPH_PE8MFP_EBI_ADR10 /*!< GPE_MFPH PE8 setting for EBI_ADR10*/ 1516 #define EBI_ADR11_PE9 SYS_GPE_MFPH_PE9MFP_EBI_ADR11 /*!< GPE_MFPH PE9 setting for EBI_ADR11*/ 1517 #define EBI_ADR11_PG2 SYS_GPG_MFPL_PG2MFP_EBI_ADR11 /*!< GPG_MFPL PG2 setting for EBI_ADR11*/ 1518 #define EBI_ADR12_PE10 SYS_GPE_MFPH_PE10MFP_EBI_ADR12 /*!< GPE_MFPH PE10 setting for EBI_ADR12*/ 1519 #define EBI_ADR12_PG3 SYS_GPG_MFPL_PG3MFP_EBI_ADR12 /*!< GPG_MFPL PG3 setting for EBI_ADR12*/ 1520 #define EBI_ADR13_PE11 SYS_GPE_MFPH_PE11MFP_EBI_ADR13 /*!< GPE_MFPH PE11 setting for EBI_ADR13*/ 1521 #define EBI_ADR13_PG4 SYS_GPG_MFPL_PG4MFP_EBI_ADR13 /*!< GPG_MFPL PG4 setting for EBI_ADR13*/ 1522 #define EBI_ADR14_PF11 SYS_GPF_MFPH_PF11MFP_EBI_ADR14 /*!< GPF_MFPH PF11 setting for EBI_ADR14*/ 1523 #define EBI_ADR14_PE12 SYS_GPE_MFPH_PE12MFP_EBI_ADR14 /*!< GPE_MFPH PE12 setting for EBI_ADR14*/ 1524 #define EBI_ADR15_PE13 SYS_GPE_MFPH_PE13MFP_EBI_ADR15 /*!< GPE_MFPH PE13 setting for EBI_ADR15*/ 1525 #define EBI_ADR15_PF10 SYS_GPF_MFPH_PF10MFP_EBI_ADR15 /*!< GPF_MFPH PF10 setting for EBI_ADR15*/ 1526 #define EBI_ADR16_PC8 SYS_GPC_MFPH_PC8MFP_EBI_ADR16 /*!< GPC_MFPH PC8 setting for EBI_ADR16*/ 1527 #define EBI_ADR16_PF9 SYS_GPF_MFPH_PF9MFP_EBI_ADR16 /*!< GPF_MFPH PF9 setting for EBI_ADR16*/ 1528 #define EBI_ADR16_PB11 SYS_GPB_MFPH_PB11MFP_EBI_ADR16 /*!< GPB_MFPH PB11 setting for EBI_ADR16*/ 1529 #define EBI_ADR17_PB10 SYS_GPB_MFPH_PB10MFP_EBI_ADR17 /*!< GPB_MFPH PB10 setting for EBI_ADR17*/ 1530 #define EBI_ADR17_PF8 SYS_GPF_MFPH_PF8MFP_EBI_ADR17 /*!< GPF_MFPH PF8 setting for EBI_ADR17*/ 1531 #define EBI_ADR18_PF7 SYS_GPF_MFPL_PF7MFP_EBI_ADR18 /*!< GPF_MFPL PF7 setting for EBI_ADR18*/ 1532 #define EBI_ADR18_PB9 SYS_GPB_MFPH_PB9MFP_EBI_ADR18 /*!< GPB_MFPH PB9 setting for EBI_ADR18*/ 1533 #define EBI_ADR19_PB8 SYS_GPB_MFPH_PB8MFP_EBI_ADR19 /*!< GPB_MFPH PB8 setting for EBI_ADR19*/ 1534 #define EBI_ADR19_PF6 SYS_GPF_MFPL_PF6MFP_EBI_ADR19 /*!< GPF_MFPL PF6 setting for EBI_ADR19*/ 1535 #define EBI_ADR2_PB3 SYS_GPB_MFPL_PB3MFP_EBI_ADR2 /*!< GPB_MFPL PB3 setting for EBI_ADR2*/ 1536 #define EBI_ADR2_PH5 SYS_GPH_MFPL_PH5MFP_EBI_ADR2 /*!< GPH_MFPL PH5 setting for EBI_ADR2*/ 1537 #define EBI_ADR3_PH4 SYS_GPH_MFPL_PH4MFP_EBI_ADR3 /*!< GPH_MFPL PH4 setting for EBI_ADR3*/ 1538 #define EBI_ADR3_PB2 SYS_GPB_MFPL_PB2MFP_EBI_ADR3 /*!< GPB_MFPL PB2 setting for EBI_ADR3*/ 1539 #define EBI_ADR4_PC12 SYS_GPC_MFPH_PC12MFP_EBI_ADR4 /*!< GPC_MFPH PC12 setting for EBI_ADR4*/ 1540 #define EBI_ADR5_PC11 SYS_GPC_MFPH_PC11MFP_EBI_ADR5 /*!< GPC_MFPH PC11 setting for EBI_ADR5*/ 1541 #define EBI_ADR6_PC10 SYS_GPC_MFPH_PC10MFP_EBI_ADR6 /*!< GPC_MFPH PC10 setting for EBI_ADR6*/ 1542 #define EBI_ADR7_PC9 SYS_GPC_MFPH_PC9MFP_EBI_ADR7 /*!< GPC_MFPH PC9 setting for EBI_ADR7*/ 1543 #define EBI_ADR8_PB1 SYS_GPB_MFPL_PB1MFP_EBI_ADR8 /*!< GPB_MFPL PB1 setting for EBI_ADR8*/ 1544 #define EBI_ADR9_PB0 SYS_GPB_MFPL_PB0MFP_EBI_ADR9 /*!< GPB_MFPL PB0 setting for EBI_ADR9*/ 1545 #define EBI_ALE_PE2 SYS_GPE_MFPL_PE2MFP_EBI_ALE /*!< GPE_MFPL PE2 setting for EBI_ALE*/ 1546 #define EBI_ALE_PA8 SYS_GPA_MFPH_PA8MFP_EBI_ALE /*!< GPA_MFPH PA8 setting for EBI_ALE*/ 1547 #define EBI_MCLK_PA9 SYS_GPA_MFPH_PA9MFP_EBI_MCLK /*!< GPA_MFPH PA9 setting for EBI_MCLK*/ 1548 #define EBI_MCLK_PE3 SYS_GPE_MFPL_PE3MFP_EBI_MCLK /*!< GPE_MFPL PE3 setting for EBI_MCLK*/ 1549 #define EBI_nCS0_PD12 SYS_GPD_MFPH_PD12MFP_EBI_nCS0 /*!< GPD_MFPH PD12 setting for EBI_nCS0*/ 1550 #define EBI_nCS0_PD14 SYS_GPD_MFPH_PD14MFP_EBI_nCS0 /*!< GPD_MFPH PD14 setting for EBI_nCS0*/ 1551 #define EBI_nCS0_PF3 SYS_GPF_MFPL_PF3MFP_EBI_nCS0 /*!< GPF_MFPL PF3 setting for EBI_nCS0*/ 1552 #define EBI_nCS0_PB7 SYS_GPB_MFPL_PB7MFP_EBI_nCS0 /*!< GPB_MFPL PB7 setting for EBI_nCS0*/ 1553 #define EBI_nCS0_PF6 SYS_GPF_MFPL_PF6MFP_EBI_nCS0 /*!< GPF_MFPL PF6 setting for EBI_nCS0*/ 1554 #define EBI_nCS1_PF2 SYS_GPF_MFPL_PF2MFP_EBI_nCS1 /*!< GPF_MFPL PF2 setting for EBI_nCS1*/ 1555 #define EBI_nCS1_PB6 SYS_GPB_MFPL_PB6MFP_EBI_nCS1 /*!< GPB_MFPL PB6 setting for EBI_nCS1*/ 1556 #define EBI_nCS1_PD11 SYS_GPD_MFPH_PD11MFP_EBI_nCS1 /*!< GPD_MFPH PD11 setting for EBI_nCS1*/ 1557 #define EBI_nCS2_PD10 SYS_GPD_MFPH_PD10MFP_EBI_nCS2 /*!< GPD_MFPH PD10 setting for EBI_nCS2*/ 1558 #define EBI_nRD_PE5 SYS_GPE_MFPL_PE5MFP_EBI_nRD /*!< GPE_MFPL PE5 setting for EBI_nRD*/ 1559 #define EBI_nRD_PA11 SYS_GPA_MFPH_PA11MFP_EBI_nRD /*!< GPA_MFPH PA11 setting for EBI_nRD*/ 1560 #define EBI_nWR_PE4 SYS_GPE_MFPL_PE4MFP_EBI_nWR /*!< GPE_MFPL PE4 setting for EBI_nWR*/ 1561 #define EBI_nWR_PA10 SYS_GPA_MFPH_PA10MFP_EBI_nWR /*!< GPA_MFPH PA10 setting for EBI_nWR*/ 1562 #define EBI_nWRH_PB6 SYS_GPB_MFPL_PB6MFP_EBI_nWRH /*!< GPB_MFPL PB6 setting for EBI_nWRH*/ 1563 #define EBI_nWRL_PB7 SYS_GPB_MFPL_PB7MFP_EBI_nWRL /*!< GPB_MFPL PB7 setting for EBI_nWRL*/ 1564 #define ECAP0_IC0_PE8 SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 /*!< GPE_MFPH PE8 setting for ECAP0_IC0*/ 1565 #define ECAP0_IC0_PA10 SYS_GPA_MFPH_PA10MFP_ECAP0_IC0 /*!< GPA_MFPH PA10 setting for ECAP0_IC0*/ 1566 #define ECAP0_IC1_PA9 SYS_GPA_MFPH_PA9MFP_ECAP0_IC1 /*!< GPA_MFPH PA9 setting for ECAP0_IC1*/ 1567 #define ECAP0_IC1_PE9 SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 /*!< GPE_MFPH PE9 setting for ECAP0_IC1*/ 1568 #define ECAP0_IC2_PE10 SYS_GPE_MFPH_PE10MFP_ECAP0_IC2 /*!< GPE_MFPH PE10 setting for ECAP0_IC2*/ 1569 #define ECAP0_IC2_PA8 SYS_GPA_MFPH_PA8MFP_ECAP0_IC2 /*!< GPA_MFPH PA8 setting for ECAP0_IC2*/ 1570 #define ECAP1_IC0_PE13 SYS_GPE_MFPH_PE13MFP_ECAP1_IC0 /*!< GPE_MFPH PE13 setting for ECAP1_IC0*/ 1571 #define ECAP1_IC0_PC10 SYS_GPC_MFPH_PC10MFP_ECAP1_IC0 /*!< GPC_MFPH PC10 setting for ECAP1_IC0*/ 1572 #define ECAP1_IC1_PC11 SYS_GPC_MFPH_PC11MFP_ECAP1_IC1 /*!< GPC_MFPH PC11 setting for ECAP1_IC1*/ 1573 #define ECAP1_IC1_PE12 SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 /*!< GPE_MFPH PE12 setting for ECAP1_IC1*/ 1574 #define ECAP1_IC2_PC12 SYS_GPC_MFPH_PC12MFP_ECAP1_IC2 /*!< GPC_MFPH PC12 setting for ECAP1_IC2*/ 1575 #define ECAP1_IC2_PE11 SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 /*!< GPE_MFPH PE11 setting for ECAP1_IC2*/ 1576 #define EPWM0_BRAKE0_PE8 SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0*/ 1577 #define EPWM0_BRAKE0_PB1 SYS_GPB_MFPL_PB1MFP_EPWM0_BRAKE0 /*!< GPB_MFPL PB1 setting for EPWM0_BRAKE0*/ 1578 #define EPWM0_BRAKE1_PB14 SYS_GPB_MFPH_PB14MFP_EPWM0_BRAKE1 /*!< GPB_MFPH PB14 setting for EPWM0_BRAKE1*/ 1579 #define EPWM0_BRAKE1_PE9 SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1*/ 1580 #define EPWM0_BRAKE1_PB0 SYS_GPB_MFPL_PB0MFP_EPWM0_BRAKE1 /*!< GPB_MFPL PB0 setting for EPWM0_BRAKE1*/ 1581 #define EPWM0_CH0_PF5 SYS_GPF_MFPL_PF5MFP_EPWM0_CH0 /*!< GPF_MFPL PF5 setting for EPWM0_CH0*/ 1582 #define EPWM0_CH0_PA5 SYS_GPA_MFPL_PA5MFP_EPWM0_CH0 /*!< GPA_MFPL PA5 setting for EPWM0_CH0*/ 1583 #define EPWM0_CH0_PB5 SYS_GPB_MFPL_PB5MFP_EPWM0_CH0 /*!< GPB_MFPL PB5 setting for EPWM0_CH0*/ 1584 #define EPWM0_CH0_PE8 SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 /*!< GPE_MFPH PE8 setting for EPWM0_CH0*/ 1585 #define EPWM0_CH0_PE7 SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 /*!< GPE_MFPL PE7 setting for EPWM0_CH0*/ 1586 #define EPWM0_CH1_PA4 SYS_GPA_MFPL_PA4MFP_EPWM0_CH1 /*!< GPA_MFPL PA4 setting for EPWM0_CH1*/ 1587 #define EPWM0_CH1_PE9 SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 /*!< GPE_MFPH PE9 setting for EPWM0_CH1*/ 1588 #define EPWM0_CH1_PE6 SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 /*!< GPE_MFPL PE6 setting for EPWM0_CH1*/ 1589 #define EPWM0_CH1_PF4 SYS_GPF_MFPL_PF4MFP_EPWM0_CH1 /*!< GPF_MFPL PF4 setting for EPWM0_CH1*/ 1590 #define EPWM0_CH1_PB4 SYS_GPB_MFPL_PB4MFP_EPWM0_CH1 /*!< GPB_MFPL PB4 setting for EPWM0_CH1*/ 1591 #define EPWM0_CH2_PE10 SYS_GPE_MFPH_PE10MFP_EPWM0_CH2 /*!< GPE_MFPH PE10 setting for EPWM0_CH2*/ 1592 #define EPWM0_CH2_PE5 SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 /*!< GPE_MFPL PE5 setting for EPWM0_CH2*/ 1593 #define EPWM0_CH2_PA3 SYS_GPA_MFPL_PA3MFP_EPWM0_CH2 /*!< GPA_MFPL PA3 setting for EPWM0_CH2*/ 1594 #define EPWM0_CH2_PB3 SYS_GPB_MFPL_PB3MFP_EPWM0_CH2 /*!< GPB_MFPL PB3 setting for EPWM0_CH2*/ 1595 #define EPWM0_CH3_PA2 SYS_GPA_MFPL_PA2MFP_EPWM0_CH3 /*!< GPA_MFPL PA2 setting for EPWM0_CH3*/ 1596 #define EPWM0_CH3_PB2 SYS_GPB_MFPL_PB2MFP_EPWM0_CH3 /*!< GPB_MFPL PB2 setting for EPWM0_CH3*/ 1597 #define EPWM0_CH3_PE11 SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 /*!< GPE_MFPH PE11 setting for EPWM0_CH3*/ 1598 #define EPWM0_CH3_PE4 SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 /*!< GPE_MFPL PE4 setting for EPWM0_CH3*/ 1599 #define EPWM0_CH4_PE3 SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 /*!< GPE_MFPL PE3 setting for EPWM0_CH4*/ 1600 #define EPWM0_CH4_PD14 SYS_GPD_MFPH_PD14MFP_EPWM0_CH4 /*!< GPD_MFPH PD14 setting for EPWM0_CH4*/ 1601 #define EPWM0_CH4_PA1 SYS_GPA_MFPL_PA1MFP_EPWM0_CH4 /*!< GPA_MFPL PA1 setting for EPWM0_CH4*/ 1602 #define EPWM0_CH4_PE12 SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 /*!< GPE_MFPH PE12 setting for EPWM0_CH4*/ 1603 #define EPWM0_CH4_PB1 SYS_GPB_MFPL_PB1MFP_EPWM0_CH4 /*!< GPB_MFPL PB1 setting for EPWM0_CH4*/ 1604 #define EPWM0_CH5_PA0 SYS_GPA_MFPL_PA0MFP_EPWM0_CH5 /*!< GPA_MFPL PA0 setting for EPWM0_CH5*/ 1605 #define EPWM0_CH5_PB0 SYS_GPB_MFPL_PB0MFP_EPWM0_CH5 /*!< GPB_MFPL PB0 setting for EPWM0_CH5*/ 1606 #define EPWM0_CH5_PE13 SYS_GPE_MFPH_PE13MFP_EPWM0_CH5 /*!< GPE_MFPH PE13 setting for EPWM0_CH5*/ 1607 #define EPWM0_CH5_PE2 SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 /*!< GPE_MFPL PE2 setting for EPWM0_CH5*/ 1608 #define EPWM0_CH5_PH11 SYS_GPH_MFPH_PH11MFP_EPWM0_CH5 /*!< GPH_MFPH PH11 setting for EPWM0_CH5*/ 1609 #define EPWM0_SYNC_IN_PA15 SYS_GPA_MFPH_PA15MFP_EPWM0_SYNC_IN /*!< GPA_MFPH PA15 setting for EPWM0_SYNC_IN*/ 1610 #define EPWM0_SYNC_OUT_PA11 SYS_GPA_MFPH_PA11MFP_EPWM0_SYNC_OUT /*!< GPA_MFPH PA11 setting for EPWM0_SYNC_OUT*/ 1611 #define EPWM0_SYNC_OUT_PF5 SYS_GPF_MFPL_PF5MFP_EPWM0_SYNC_OUT /*!< GPF_MFPL PF5 setting for EPWM0_SYNC_OUT*/ 1612 #define EPWM1_BRAKE0_PB7 SYS_GPB_MFPL_PB7MFP_EPWM1_BRAKE0 /*!< GPB_MFPL PB7 setting for EPWM1_BRAKE0*/ 1613 #define EPWM1_BRAKE0_PE10 SYS_GPE_MFPH_PE10MFP_EPWM1_BRAKE0 /*!< GPE_MFPH PE10 setting for EPWM1_BRAKE0*/ 1614 #define EPWM1_BRAKE1_PB6 SYS_GPB_MFPL_PB6MFP_EPWM1_BRAKE1 /*!< GPB_MFPL PB6 setting for EPWM1_BRAKE1*/ 1615 #define EPWM1_BRAKE1_PA3 SYS_GPA_MFPL_PA3MFP_EPWM1_BRAKE1 /*!< GPA_MFPL PA3 setting for EPWM1_BRAKE1*/ 1616 #define EPWM1_BRAKE1_PE11 SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 /*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1*/ 1617 #define EPWM1_CH0_PE13 SYS_GPE_MFPH_PE13MFP_EPWM1_CH0 /*!< GPE_MFPH PE13 setting for EPWM1_CH0*/ 1618 #define EPWM1_CH0_PC12 SYS_GPC_MFPH_PC12MFP_EPWM1_CH0 /*!< GPC_MFPH PC12 setting for EPWM1_CH0*/ 1619 #define EPWM1_CH0_PB15 SYS_GPB_MFPH_PB15MFP_EPWM1_CH0 /*!< GPB_MFPH PB15 setting for EPWM1_CH0*/ 1620 #define EPWM1_CH0_PC5 SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 /*!< GPC_MFPL PC5 setting for EPWM1_CH0*/ 1621 #define EPWM1_CH1_PC8 SYS_GPC_MFPH_PC8MFP_EPWM1_CH1 /*!< GPC_MFPH PC8 setting for EPWM1_CH1*/ 1622 #define EPWM1_CH1_PC11 SYS_GPC_MFPH_PC11MFP_EPWM1_CH1 /*!< GPC_MFPH PC11 setting for EPWM1_CH1*/ 1623 #define EPWM1_CH1_PB14 SYS_GPB_MFPH_PB14MFP_EPWM1_CH1 /*!< GPB_MFPH PB14 setting for EPWM1_CH1*/ 1624 #define EPWM1_CH1_PC4 SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 /*!< GPC_MFPL PC4 setting for EPWM1_CH1*/ 1625 #define EPWM1_CH2_PC7 SYS_GPC_MFPL_PC7MFP_EPWM1_CH2 /*!< GPC_MFPL PC7 setting for EPWM1_CH2*/ 1626 #define EPWM1_CH2_PC3 SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 /*!< GPC_MFPL PC3 setting for EPWM1_CH2*/ 1627 #define EPWM1_CH2_PC10 SYS_GPC_MFPH_PC10MFP_EPWM1_CH2 /*!< GPC_MFPH PC10 setting for EPWM1_CH2*/ 1628 #define EPWM1_CH2_PB13 SYS_GPB_MFPH_PB13MFP_EPWM1_CH2 /*!< GPB_MFPH PB13 setting for EPWM1_CH2*/ 1629 #define EPWM1_CH3_PC6 SYS_GPC_MFPL_PC6MFP_EPWM1_CH3 /*!< GPC_MFPL PC6 setting for EPWM1_CH3*/ 1630 #define EPWM1_CH3_PC2 SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 /*!< GPC_MFPL PC2 setting for EPWM1_CH3*/ 1631 #define EPWM1_CH3_PB12 SYS_GPB_MFPH_PB12MFP_EPWM1_CH3 /*!< GPB_MFPH PB12 setting for EPWM1_CH3*/ 1632 #define EPWM1_CH3_PC9 SYS_GPC_MFPH_PC9MFP_EPWM1_CH3 /*!< GPC_MFPH PC9 setting for EPWM1_CH3*/ 1633 #define EPWM1_CH4_PC1 SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 /*!< GPC_MFPL PC1 setting for EPWM1_CH4*/ 1634 #define EPWM1_CH4_PB1 SYS_GPB_MFPL_PB1MFP_EPWM1_CH4 /*!< GPB_MFPL PB1 setting for EPWM1_CH4*/ 1635 #define EPWM1_CH4_PB7 SYS_GPB_MFPL_PB7MFP_EPWM1_CH4 /*!< GPB_MFPL PB7 setting for EPWM1_CH4*/ 1636 #define EPWM1_CH4_PA7 SYS_GPA_MFPL_PA7MFP_EPWM1_CH4 /*!< GPA_MFPL PA7 setting for EPWM1_CH4*/ 1637 #define EPWM1_CH5_PB6 SYS_GPB_MFPL_PB6MFP_EPWM1_CH5 /*!< GPB_MFPL PB6 setting for EPWM1_CH5*/ 1638 #define EPWM1_CH5_PC0 SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 /*!< GPC_MFPL PC0 setting for EPWM1_CH5*/ 1639 #define EPWM1_CH5_PB0 SYS_GPB_MFPL_PB0MFP_EPWM1_CH5 /*!< GPB_MFPL PB0 setting for EPWM1_CH5*/ 1640 #define EPWM1_CH5_PA6 SYS_GPA_MFPL_PA6MFP_EPWM1_CH5 /*!< GPA_MFPL PA6 setting for EPWM1_CH5*/ 1641 #define I2C0_SCL_PE13 SYS_GPE_MFPH_PE13MFP_I2C0_SCL /*!< GPE_MFPH PE13 setting for I2C0_SCL*/ 1642 #define I2C0_SCL_PB9 SYS_GPB_MFPH_PB9MFP_I2C0_SCL /*!< GPB_MFPH PB9 setting for I2C0_SCL*/ 1643 #define I2C0_SCL_PD7 SYS_GPD_MFPL_PD7MFP_I2C0_SCL /*!< GPD_MFPL PD7 setting for I2C0_SCL*/ 1644 #define I2C0_SCL_PA5 SYS_GPA_MFPL_PA5MFP_I2C0_SCL /*!< GPA_MFPL PA5 setting for I2C0_SCL*/ 1645 #define I2C0_SCL_PB5 SYS_GPB_MFPL_PB5MFP_I2C0_SCL /*!< GPB_MFPL PB5 setting for I2C0_SCL*/ 1646 #define I2C0_SCL_PC1 SYS_GPC_MFPL_PC1MFP_I2C0_SCL /*!< GPC_MFPL PC1 setting for I2C0_SCL*/ 1647 #define I2C0_SCL_PC12 SYS_GPC_MFPH_PC12MFP_I2C0_SCL /*!< GPC_MFPH PC12 setting for I2C0_SCL*/ 1648 #define I2C0_SCL_PF3 SYS_GPF_MFPL_PF3MFP_I2C0_SCL /*!< GPF_MFPL PF3 setting for I2C0_SCL*/ 1649 #define I2C0_SDA_PB4 SYS_GPB_MFPL_PB4MFP_I2C0_SDA /*!< GPB_MFPL PB4 setting for I2C0_SDA*/ 1650 #define I2C0_SDA_PD6 SYS_GPD_MFPL_PD6MFP_I2C0_SDA /*!< GPD_MFPL PD6 setting for I2C0_SDA*/ 1651 #define I2C0_SDA_PB8 SYS_GPB_MFPH_PB8MFP_I2C0_SDA /*!< GPB_MFPH PB8 setting for I2C0_SDA*/ 1652 #define I2C0_SDA_PC11 SYS_GPC_MFPH_PC11MFP_I2C0_SDA /*!< GPC_MFPH PC11 setting for I2C0_SDA*/ 1653 #define I2C0_SDA_PF2 SYS_GPF_MFPL_PF2MFP_I2C0_SDA /*!< GPF_MFPL PF2 setting for I2C0_SDA*/ 1654 #define I2C0_SDA_PC0 SYS_GPC_MFPL_PC0MFP_I2C0_SDA /*!< GPC_MFPL PC0 setting for I2C0_SDA*/ 1655 #define I2C0_SDA_PC8 SYS_GPC_MFPH_PC8MFP_I2C0_SDA /*!< GPC_MFPH PC8 setting for I2C0_SDA*/ 1656 #define I2C0_SDA_PA4 SYS_GPA_MFPL_PA4MFP_I2C0_SDA /*!< GPA_MFPL PA4 setting for I2C0_SDA*/ 1657 #define I2C0_SMBAL_PA3 SYS_GPA_MFPL_PA3MFP_I2C0_SMBAL /*!< GPA_MFPL PA3 setting for I2C0_SMBAL*/ 1658 #define I2C0_SMBAL_PG2 SYS_GPG_MFPL_PG2MFP_I2C0_SMBAL /*!< GPG_MFPL PG2 setting for I2C0_SMBAL*/ 1659 #define I2C0_SMBAL_PC3 SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL /*!< GPC_MFPL PC3 setting for I2C0_SMBAL*/ 1660 #define I2C0_SMBSUS_PA2 SYS_GPA_MFPL_PA2MFP_I2C0_SMBSUS /*!< GPA_MFPL PA2 setting for I2C0_SMBSUS*/ 1661 #define I2C0_SMBSUS_PC2 SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS*/ 1662 #define I2C0_SMBSUS_PG3 SYS_GPG_MFPL_PG3MFP_I2C0_SMBSUS /*!< GPG_MFPL PG3 setting for I2C0_SMBSUS*/ 1663 #define I2C1_SCL_PB1 SYS_GPB_MFPL_PB1MFP_I2C1_SCL /*!< GPB_MFPL PB1 setting for I2C1_SCL*/ 1664 #define I2C1_SCL_PE1 SYS_GPE_MFPL_PE1MFP_I2C1_SCL /*!< GPE_MFPL PE1 setting for I2C1_SCL*/ 1665 #define I2C1_SCL_PF0 SYS_GPF_MFPL_PF0MFP_I2C1_SCL /*!< GPF_MFPL PF0 setting for I2C1_SCL*/ 1666 #define I2C1_SCL_PA12 SYS_GPA_MFPH_PA12MFP_I2C1_SCL /*!< GPA_MFPH PA12 setting for I2C1_SCL*/ 1667 #define I2C1_SCL_PA7 SYS_GPA_MFPL_PA7MFP_I2C1_SCL /*!< GPA_MFPL PA7 setting for I2C1_SCL*/ 1668 #define I2C1_SCL_PB11 SYS_GPB_MFPH_PB11MFP_I2C1_SCL /*!< GPB_MFPH PB11 setting for I2C1_SCL*/ 1669 #define I2C1_SCL_PG2 SYS_GPG_MFPL_PG2MFP_I2C1_SCL /*!< GPG_MFPL PG2 setting for I2C1_SCL*/ 1670 #define I2C1_SCL_PA3 SYS_GPA_MFPL_PA3MFP_I2C1_SCL /*!< GPA_MFPL PA3 setting for I2C1_SCL*/ 1671 #define I2C1_SCL_PC5 SYS_GPC_MFPL_PC5MFP_I2C1_SCL /*!< GPC_MFPL PC5 setting for I2C1_SCL*/ 1672 #define I2C1_SCL_PD5 SYS_GPD_MFPL_PD5MFP_I2C1_SCL /*!< GPD_MFPL PD5 setting for I2C1_SCL*/ 1673 #define I2C1_SCL_PB3 SYS_GPB_MFPL_PB3MFP_I2C1_SCL /*!< GPB_MFPL PB3 setting for I2C1_SCL*/ 1674 #define I2C1_SDA_PA2 SYS_GPA_MFPL_PA2MFP_I2C1_SDA /*!< GPA_MFPL PA2 setting for I2C1_SDA*/ 1675 #define I2C1_SDA_PB10 SYS_GPB_MFPH_PB10MFP_I2C1_SDA /*!< GPB_MFPH PB10 setting for I2C1_SDA*/ 1676 #define I2C1_SDA_PF1 SYS_GPF_MFPL_PF1MFP_I2C1_SDA /*!< GPF_MFPL PF1 setting for I2C1_SDA*/ 1677 #define I2C1_SDA_PB2 SYS_GPB_MFPL_PB2MFP_I2C1_SDA /*!< GPB_MFPL PB2 setting for I2C1_SDA*/ 1678 #define I2C1_SDA_PD4 SYS_GPD_MFPL_PD4MFP_I2C1_SDA /*!< GPD_MFPL PD4 setting for I2C1_SDA*/ 1679 #define I2C1_SDA_PA13 SYS_GPA_MFPH_PA13MFP_I2C1_SDA /*!< GPA_MFPH PA13 setting for I2C1_SDA*/ 1680 #define I2C1_SDA_PA6 SYS_GPA_MFPL_PA6MFP_I2C1_SDA /*!< GPA_MFPL PA6 setting for I2C1_SDA*/ 1681 #define I2C1_SDA_PE0 SYS_GPE_MFPL_PE0MFP_I2C1_SDA /*!< GPE_MFPL PE0 setting for I2C1_SDA*/ 1682 #define I2C1_SDA_PG3 SYS_GPG_MFPL_PG3MFP_I2C1_SDA /*!< GPG_MFPL PG3 setting for I2C1_SDA*/ 1683 #define I2C1_SDA_PC4 SYS_GPC_MFPL_PC4MFP_I2C1_SDA /*!< GPC_MFPL PC4 setting for I2C1_SDA*/ 1684 #define I2C1_SDA_PB0 SYS_GPB_MFPL_PB0MFP_I2C1_SDA /*!< GPB_MFPL PB0 setting for I2C1_SDA*/ 1685 #define I2C1_SMBAL_PB9 SYS_GPB_MFPH_PB9MFP_I2C1_SMBAL /*!< GPB_MFPH PB9 setting for I2C1_SMBAL*/ 1686 #define I2C1_SMBAL_PH8 SYS_GPH_MFPH_PH8MFP_I2C1_SMBAL /*!< GPH_MFPH PH8 setting for I2C1_SMBAL*/ 1687 #define I2C1_SMBAL_PC7 SYS_GPC_MFPL_PC7MFP_I2C1_SMBAL /*!< GPC_MFPL PC7 setting for I2C1_SMBAL*/ 1688 #define I2C1_SMBSUS_PC6 SYS_GPC_MFPL_PC6MFP_I2C1_SMBSUS /*!< GPC_MFPL PC6 setting for I2C1_SMBSUS*/ 1689 #define I2C1_SMBSUS_PB8 SYS_GPB_MFPH_PB8MFP_I2C1_SMBSUS /*!< GPB_MFPH PB8 setting for I2C1_SMBSUS*/ 1690 #define I2C1_SMBSUS_PH9 SYS_GPH_MFPH_PH9MFP_I2C1_SMBSUS /*!< GPH_MFPH PH9 setting for I2C1_SMBSUS*/ 1691 #define I2C2_SCL_PA14 SYS_GPA_MFPH_PA14MFP_I2C2_SCL /*!< GPA_MFPH PA14 setting for I2C2_SCL*/ 1692 #define I2C2_SCL_PH8 SYS_GPH_MFPH_PH8MFP_I2C2_SCL /*!< GPH_MFPH PH8 setting for I2C2_SCL*/ 1693 #define I2C2_SCL_PA11 SYS_GPA_MFPH_PA11MFP_I2C2_SCL /*!< GPA_MFPH PA11 setting for I2C2_SCL*/ 1694 #define I2C2_SCL_PB13 SYS_GPB_MFPH_PB13MFP_I2C2_SCL /*!< GPB_MFPH PB13 setting for I2C2_SCL*/ 1695 #define I2C2_SCL_PD9 SYS_GPD_MFPH_PD9MFP_I2C2_SCL /*!< GPD_MFPH PD9 setting for I2C2_SCL*/ 1696 #define I2C2_SCL_PA1 SYS_GPA_MFPL_PA1MFP_I2C2_SCL /*!< GPA_MFPL PA1 setting for I2C2_SCL*/ 1697 #define I2C2_SCL_PD1 SYS_GPD_MFPL_PD1MFP_I2C2_SCL /*!< GPD_MFPL PD1 setting for I2C2_SCL*/ 1698 #define I2C2_SDA_PD8 SYS_GPD_MFPH_PD8MFP_I2C2_SDA /*!< GPD_MFPH PD8 setting for I2C2_SDA*/ 1699 #define I2C2_SDA_PD0 SYS_GPD_MFPL_PD0MFP_I2C2_SDA /*!< GPD_MFPL PD0 setting for I2C2_SDA*/ 1700 #define I2C2_SDA_PA15 SYS_GPA_MFPH_PA15MFP_I2C2_SDA /*!< GPA_MFPH PA15 setting for I2C2_SDA*/ 1701 #define I2C2_SDA_PH9 SYS_GPH_MFPH_PH9MFP_I2C2_SDA /*!< GPH_MFPH PH9 setting for I2C2_SDA*/ 1702 #define I2C2_SDA_PA10 SYS_GPA_MFPH_PA10MFP_I2C2_SDA /*!< GPA_MFPH PA10 setting for I2C2_SDA*/ 1703 #define I2C2_SDA_PA0 SYS_GPA_MFPL_PA0MFP_I2C2_SDA /*!< GPA_MFPL PA0 setting for I2C2_SDA*/ 1704 #define I2C2_SDA_PB12 SYS_GPB_MFPH_PB12MFP_I2C2_SDA /*!< GPB_MFPH PB12 setting for I2C2_SDA*/ 1705 #define I2C2_SMBAL_PB15 SYS_GPB_MFPH_PB15MFP_I2C2_SMBAL /*!< GPB_MFPH PB15 setting for I2C2_SMBAL*/ 1706 #define I2C2_SMBSUS_PB14 SYS_GPB_MFPH_PB14MFP_I2C2_SMBSUS /*!< GPB_MFPH PB14 setting for I2C2_SMBSUS*/ 1707 #define I2S0_BCLK_PF10 SYS_GPF_MFPH_PF10MFP_I2S0_BCLK /*!< GPF_MFPH PF10 setting for I2S0_BCLK*/ 1708 #define I2S0_BCLK_PB5 SYS_GPB_MFPL_PB5MFP_I2S0_BCLK /*!< GPB_MFPL PB5 setting for I2S0_BCLK*/ 1709 #define I2S0_BCLK_PE1 SYS_GPE_MFPL_PE1MFP_I2S0_BCLK /*!< GPE_MFPL PE1 setting for I2S0_BCLK*/ 1710 #define I2S0_BCLK_PA12 SYS_GPA_MFPH_PA12MFP_I2S0_BCLK /*!< GPA_MFPH PA12 setting for I2S0_BCLK*/ 1711 #define I2S0_BCLK_PC4 SYS_GPC_MFPL_PC4MFP_I2S0_BCLK /*!< GPC_MFPL PC4 setting for I2S0_BCLK*/ 1712 #define I2S0_BCLK_PE8 SYS_GPE_MFPH_PE8MFP_I2S0_BCLK /*!< GPE_MFPH PE8 setting for I2S0_BCLK*/ 1713 #define I2S0_DI_PC2 SYS_GPC_MFPL_PC2MFP_I2S0_DI /*!< GPC_MFPL PC2 setting for I2S0_DI*/ 1714 #define I2S0_DI_PE10 SYS_GPE_MFPH_PE10MFP_I2S0_DI /*!< GPE_MFPH PE10 setting for I2S0_DI*/ 1715 #define I2S0_DI_PF8 SYS_GPF_MFPH_PF8MFP_I2S0_DI /*!< GPF_MFPH PF8 setting for I2S0_DI*/ 1716 #define I2S0_DI_PH8 SYS_GPH_MFPH_PH8MFP_I2S0_DI /*!< GPH_MFPH PH8 setting for I2S0_DI*/ 1717 #define I2S0_DI_PB3 SYS_GPB_MFPL_PB3MFP_I2S0_DI /*!< GPB_MFPL PB3 setting for I2S0_DI*/ 1718 #define I2S0_DI_PA14 SYS_GPA_MFPH_PA14MFP_I2S0_DI /*!< GPA_MFPH PA14 setting for I2S0_DI*/ 1719 #define I2S0_DO_PH9 SYS_GPH_MFPH_PH9MFP_I2S0_DO /*!< GPH_MFPH PH9 setting for I2S0_DO*/ 1720 #define I2S0_DO_PC1 SYS_GPC_MFPL_PC1MFP_I2S0_DO /*!< GPC_MFPL PC1 setting for I2S0_DO*/ 1721 #define I2S0_DO_PA15 SYS_GPA_MFPH_PA15MFP_I2S0_DO /*!< GPA_MFPH PA15 setting for I2S0_DO*/ 1722 #define I2S0_DO_PB2 SYS_GPB_MFPL_PB2MFP_I2S0_DO /*!< GPB_MFPL PB2 setting for I2S0_DO*/ 1723 #define I2S0_DO_PF7 SYS_GPF_MFPL_PF7MFP_I2S0_DO /*!< GPF_MFPL PF7 setting for I2S0_DO*/ 1724 #define I2S0_DO_PE11 SYS_GPE_MFPH_PE11MFP_I2S0_DO /*!< GPE_MFPH PE11 setting for I2S0_DO*/ 1725 #define I2S0_LRCK_PC0 SYS_GPC_MFPL_PC0MFP_I2S0_LRCK /*!< GPC_MFPL PC0 setting for I2S0_LRCK*/ 1726 #define I2S0_LRCK_PB1 SYS_GPB_MFPL_PB1MFP_I2S0_LRCK /*!< GPB_MFPL PB1 setting for I2S0_LRCK*/ 1727 #define I2S0_LRCK_PH10 SYS_GPH_MFPH_PH10MFP_I2S0_LRCK /*!< GPH_MFPH PH10 setting for I2S0_LRCK*/ 1728 #define I2S0_LRCK_PF6 SYS_GPF_MFPL_PF6MFP_I2S0_LRCK /*!< GPF_MFPL PF6 setting for I2S0_LRCK*/ 1729 #define I2S0_LRCK_PE12 SYS_GPE_MFPH_PE12MFP_I2S0_LRCK /*!< GPE_MFPH PE12 setting for I2S0_LRCK*/ 1730 #define I2S0_MCLK_PC3 SYS_GPC_MFPL_PC3MFP_I2S0_MCLK /*!< GPC_MFPL PC3 setting for I2S0_MCLK*/ 1731 #define I2S0_MCLK_PF9 SYS_GPF_MFPH_PF9MFP_I2S0_MCLK /*!< GPF_MFPH PF9 setting for I2S0_MCLK*/ 1732 #define I2S0_MCLK_PE0 SYS_GPE_MFPL_PE0MFP_I2S0_MCLK /*!< GPE_MFPL PE0 setting for I2S0_MCLK*/ 1733 #define I2S0_MCLK_PB4 SYS_GPB_MFPL_PB4MFP_I2S0_MCLK /*!< GPB_MFPL PB4 setting for I2S0_MCLK*/ 1734 #define I2S0_MCLK_PA13 SYS_GPA_MFPH_PA13MFP_I2S0_MCLK /*!< GPA_MFPH PA13 setting for I2S0_MCLK*/ 1735 #define I2S0_MCLK_PE9 SYS_GPE_MFPH_PE9MFP_I2S0_MCLK /*!< GPE_MFPH PE9 setting for I2S0_MCLK*/ 1736 #define ICE_CLK_PF1 SYS_GPF_MFPL_PF1MFP_ICE_CLK /*!< GPF_MFPL PF1 setting for ICE_CLK*/ 1737 #define ICE_DAT_PF0 SYS_GPF_MFPL_PF0MFP_ICE_DAT /*!< GPF_MFPL PF0 setting for ICE_DAT*/ 1738 #define INT0_PA6 SYS_GPA_MFPL_PA6MFP_INT0 /*!< GPA_MFPL PA6 setting for INT0*/ 1739 #define INT0_PB5 SYS_GPB_MFPL_PB5MFP_INT0 /*!< GPB_MFPL PB5 setting for INT0*/ 1740 #define INT1_PB4 SYS_GPB_MFPL_PB4MFP_INT1 /*!< GPB_MFPL PB4 setting for INT1*/ 1741 #define INT1_PA7 SYS_GPA_MFPL_PA7MFP_INT1 /*!< GPA_MFPL PA7 setting for INT1*/ 1742 #define INT2_PB3 SYS_GPB_MFPL_PB3MFP_INT2 /*!< GPB_MFPL PB3 setting for INT2*/ 1743 #define INT2_PC6 SYS_GPC_MFPL_PC6MFP_INT2 /*!< GPC_MFPL PC6 setting for INT2*/ 1744 #define INT3_PB2 SYS_GPB_MFPL_PB2MFP_INT3 /*!< GPB_MFPL PB2 setting for INT3*/ 1745 #define INT3_PC7 SYS_GPC_MFPL_PC7MFP_INT3 /*!< GPC_MFPL PC7 setting for INT3*/ 1746 #define INT4_PA8 SYS_GPA_MFPH_PA8MFP_INT4 /*!< GPA_MFPH PA8 setting for INT4*/ 1747 #define INT4_PB6 SYS_GPB_MFPL_PB6MFP_INT4 /*!< GPB_MFPL PB6 setting for INT4*/ 1748 #define INT5_PB7 SYS_GPB_MFPL_PB7MFP_INT5 /*!< GPB_MFPL PB7 setting for INT5*/ 1749 #define INT5_PD12 SYS_GPD_MFPH_PD12MFP_INT5 /*!< GPD_MFPH PD12 setting for INT5*/ 1750 #define INT6_PD11 SYS_GPD_MFPH_PD11MFP_INT6 /*!< GPD_MFPH PD11 setting for INT6*/ 1751 #define INT6_PB8 SYS_GPB_MFPH_PB8MFP_INT6 /*!< GPB_MFPH PB8 setting for INT6*/ 1752 #define INT7_PB9 SYS_GPB_MFPH_PB9MFP_INT7 /*!< GPB_MFPH PB9 setting for INT7*/ 1753 #define INT7_PD10 SYS_GPD_MFPH_PD10MFP_INT7 /*!< GPD_MFPH PD10 setting for INT7*/ 1754 #define LCD_COM0_PC0 SYS_GPC_MFPL_PC0MFP_LCD_COM0 /*!< GPC_MFPL PC0 setting for LCD_COM0*/ 1755 #define LCD_COM1_PC1 SYS_GPC_MFPL_PC1MFP_LCD_COM1 /*!< GPC_MFPL PC1 setting for LCD_COM1*/ 1756 #define LCD_COM2_PC2 SYS_GPC_MFPL_PC2MFP_LCD_COM2 /*!< GPC_MFPL PC2 setting for LCD_COM2*/ 1757 #define LCD_COM3_PC3 SYS_GPC_MFPL_PC3MFP_LCD_COM3 /*!< GPC_MFPL PC3 setting for LCD_COM3*/ 1758 #define LCD_COM4_PC4 SYS_GPC_MFPL_PC4MFP_LCD_COM4 /*!< GPC_MFPL PC4 setting for LCD_COM4*/ 1759 #define LCD_COM5_PC5 SYS_GPC_MFPL_PC5MFP_LCD_COM5 /*!< GPC_MFPL PC5 setting for LCD_COM5*/ 1760 #define LCD_COM6_PA0 SYS_GPA_MFPL_PA0MFP_LCD_COM6 /*!< GPA_MFPL PA0 setting for LCD_COM6*/ 1761 #define LCD_COM6_PD8 SYS_GPD_MFPH_PD8MFP_LCD_COM6 /*!< GPD_MFPH PD8 setting for LCD_COM6*/ 1762 #define LCD_COM7_PA1 SYS_GPA_MFPL_PA1MFP_LCD_COM7 /*!< GPA_MFPL PA1 setting for LCD_COM7*/ 1763 #define LCD_COM7_PD9 SYS_GPD_MFPH_PD9MFP_LCD_COM7 /*!< GPD_MFPH PD9 setting for LCD_COM7*/ 1764 #define LCD_SEG0_PD14 SYS_GPD_MFPH_PD14MFP_LCD_SEG0 /*!< GPD_MFPH PD14 setting for LCD_SEG0*/ 1765 #define LCD_SEG0_PD1 SYS_GPD_MFPL_PD1MFP_LCD_SEG0 /*!< GPD_MFPL PD1 setting for LCD_SEG0*/ 1766 #define LCD_SEG1_PD2 SYS_GPD_MFPL_PD2MFP_LCD_SEG1 /*!< GPD_MFPL PD2 setting for LCD_SEG1*/ 1767 #define LCD_SEG1_PH11 SYS_GPH_MFPH_PH11MFP_LCD_SEG1 /*!< GPH_MFPH PH11 setting for LCD_SEG1*/ 1768 #define LCD_SEG10_PC7 SYS_GPC_MFPL_PC7MFP_LCD_SEG10 /*!< GPC_MFPL PC7 setting for LCD_SEG10*/ 1769 #define LCD_SEG10_PE5 SYS_GPE_MFPL_PE5MFP_LCD_SEG10 /*!< GPE_MFPL PE5 setting for LCD_SEG10*/ 1770 #define LCD_SEG11_PA8 SYS_GPA_MFPH_PA8MFP_LCD_SEG11 /*!< GPA_MFPH PA8 setting for LCD_SEG11*/ 1771 #define LCD_SEG11_PE6 SYS_GPE_MFPL_PE6MFP_LCD_SEG11 /*!< GPE_MFPL PE6 setting for LCD_SEG11*/ 1772 #define LCD_SEG12_PA9 SYS_GPA_MFPH_PA9MFP_LCD_SEG12 /*!< GPA_MFPH PA9 setting for LCD_SEG12*/ 1773 #define LCD_SEG12_PE7 SYS_GPE_MFPL_PE7MFP_LCD_SEG12 /*!< GPE_MFPL PE7 setting for LCD_SEG12*/ 1774 #define LCD_SEG13_PD6 SYS_GPD_MFPL_PD6MFP_LCD_SEG13 /*!< GPD_MFPL PD6 setting for LCD_SEG13*/ 1775 #define LCD_SEG13_PA1 SYS_GPA_MFPL_PA1MFP_LCD_SEG13 /*!< GPA_MFPL PA1 setting for LCD_SEG13*/ 1776 #define LCD_SEG14_PD7 SYS_GPD_MFPL_PD7MFP_LCD_SEG14 /*!< GPD_MFPL PD7 setting for LCD_SEG14*/ 1777 #define LCD_SEG14_PA0 SYS_GPA_MFPL_PA0MFP_LCD_SEG14 /*!< GPA_MFPL PA0 setting for LCD_SEG14*/ 1778 #define LCD_SEG15_PG15 SYS_GPG_MFPH_PG15MFP_LCD_SEG15 /*!< GPG_MFPH PG15 setting for LCD_SEG15*/ 1779 #define LCD_SEG16_PG14 SYS_GPG_MFPH_PG14MFP_LCD_SEG16 /*!< GPG_MFPH PG14 setting for LCD_SEG16*/ 1780 #define LCD_SEG17_PG13 SYS_GPG_MFPH_PG13MFP_LCD_SEG17 /*!< GPG_MFPH PG13 setting for LCD_SEG17*/ 1781 #define LCD_SEG18_PG12 SYS_GPG_MFPH_PG12MFP_LCD_SEG18 /*!< GPG_MFPH PG12 setting for LCD_SEG18*/ 1782 #define LCD_SEG19_PG11 SYS_GPG_MFPH_PG11MFP_LCD_SEG19 /*!< GPG_MFPH PG11 setting for LCD_SEG19*/ 1783 #define LCD_SEG2_PH10 SYS_GPH_MFPH_PH10MFP_LCD_SEG2 /*!< GPH_MFPH PH10 setting for LCD_SEG2*/ 1784 #define LCD_SEG2_PD3 SYS_GPD_MFPL_PD3MFP_LCD_SEG2 /*!< GPD_MFPL PD3 setting for LCD_SEG2*/ 1785 #define LCD_SEG20_PG10 SYS_GPG_MFPH_PG10MFP_LCD_SEG20 /*!< GPG_MFPH PG10 setting for LCD_SEG20*/ 1786 #define LCD_SEG21_PG9 SYS_GPG_MFPH_PG9MFP_LCD_SEG21 /*!< GPG_MFPH PG9 setting for LCD_SEG21*/ 1787 #define LCD_SEG22_PE15 SYS_GPE_MFPH_PE15MFP_LCD_SEG22 /*!< GPE_MFPH PE15 setting for LCD_SEG22*/ 1788 #define LCD_SEG23_PE14 SYS_GPE_MFPH_PE14MFP_LCD_SEG23 /*!< GPE_MFPH PE14 setting for LCD_SEG23*/ 1789 #define LCD_SEG24_PA0 SYS_GPA_MFPL_PA0MFP_LCD_SEG24 /*!< GPA_MFPL PA0 setting for LCD_SEG24*/ 1790 #define LCD_SEG25_PA1 SYS_GPA_MFPL_PA1MFP_LCD_SEG25 /*!< GPA_MFPL PA1 setting for LCD_SEG25*/ 1791 #define LCD_SEG26_PA2 SYS_GPA_MFPL_PA2MFP_LCD_SEG26 /*!< GPA_MFPL PA2 setting for LCD_SEG26*/ 1792 #define LCD_SEG27_PA3 SYS_GPA_MFPL_PA3MFP_LCD_SEG27 /*!< GPA_MFPL PA3 setting for LCD_SEG27*/ 1793 #define LCD_SEG28_PA4 SYS_GPA_MFPL_PA4MFP_LCD_SEG28 /*!< GPA_MFPL PA4 setting for LCD_SEG28*/ 1794 #define LCD_SEG29_PA5 SYS_GPA_MFPL_PA5MFP_LCD_SEG29 /*!< GPA_MFPL PA5 setting for LCD_SEG29*/ 1795 #define LCD_SEG3_PA2 SYS_GPA_MFPL_PA2MFP_LCD_SEG3 /*!< GPA_MFPL PA2 setting for LCD_SEG3*/ 1796 #define LCD_SEG3_PH9 SYS_GPH_MFPH_PH9MFP_LCD_SEG3 /*!< GPH_MFPH PH9 setting for LCD_SEG3*/ 1797 #define LCD_SEG30_PE10 SYS_GPE_MFPH_PE10MFP_LCD_SEG30 /*!< GPE_MFPH PE10 setting for LCD_SEG30*/ 1798 #define LCD_SEG31_PE9 SYS_GPE_MFPH_PE9MFP_LCD_SEG31 /*!< GPE_MFPH PE9 setting for LCD_SEG31*/ 1799 #define LCD_SEG32_PE8 SYS_GPE_MFPH_PE8MFP_LCD_SEG32 /*!< GPE_MFPH PE8 setting for LCD_SEG32*/ 1800 #define LCD_SEG33_PH7 SYS_GPH_MFPL_PH7MFP_LCD_SEG33 /*!< GPH_MFPL PH7 setting for LCD_SEG33*/ 1801 #define LCD_SEG34_PH6 SYS_GPH_MFPL_PH6MFP_LCD_SEG34 /*!< GPH_MFPL PH6 setting for LCD_SEG34*/ 1802 #define LCD_SEG35_PH5 SYS_GPH_MFPL_PH5MFP_LCD_SEG35 /*!< GPH_MFPL PH5 setting for LCD_SEG35*/ 1803 #define LCD_SEG36_PH4 SYS_GPH_MFPL_PH4MFP_LCD_SEG36 /*!< GPH_MFPL PH4 setting for LCD_SEG36*/ 1804 #define LCD_SEG37_PG4 SYS_GPG_MFPL_PG4MFP_LCD_SEG37 /*!< GPG_MFPL PG4 setting for LCD_SEG37*/ 1805 #define LCD_SEG38_PG3 SYS_GPG_MFPL_PG3MFP_LCD_SEG38 /*!< GPG_MFPL PG3 setting for LCD_SEG38*/ 1806 #define LCD_SEG39_PG2 SYS_GPG_MFPL_PG2MFP_LCD_SEG39 /*!< GPG_MFPL PG2 setting for LCD_SEG39*/ 1807 #define LCD_SEG4_PH8 SYS_GPH_MFPH_PH8MFP_LCD_SEG4 /*!< GPH_MFPH PH8 setting for LCD_SEG4*/ 1808 #define LCD_SEG4_PA3 SYS_GPA_MFPL_PA3MFP_LCD_SEG4 /*!< GPA_MFPL PA3 setting for LCD_SEG4*/ 1809 #define LCD_SEG40_PD9 SYS_GPD_MFPH_PD9MFP_LCD_SEG40 /*!< GPD_MFPH PD9 setting for LCD_SEG40*/ 1810 #define LCD_SEG41_PD8 SYS_GPD_MFPH_PD8MFP_LCD_SEG41 /*!< GPD_MFPH PD8 setting for LCD_SEG41*/ 1811 #define LCD_SEG42_PC5 SYS_GPC_MFPL_PC5MFP_LCD_SEG42 /*!< GPC_MFPL PC5 setting for LCD_SEG42*/ 1812 #define LCD_SEG43_PC4 SYS_GPC_MFPL_PC4MFP_LCD_SEG43 /*!< GPC_MFPL PC4 setting for LCD_SEG43*/ 1813 #define LCD_SEG5_PA4 SYS_GPA_MFPL_PA4MFP_LCD_SEG5 /*!< GPA_MFPL PA4 setting for LCD_SEG5*/ 1814 #define LCD_SEG5_PE0 SYS_GPE_MFPL_PE0MFP_LCD_SEG5 /*!< GPE_MFPL PE0 setting for LCD_SEG5*/ 1815 #define LCD_SEG6_PE1 SYS_GPE_MFPL_PE1MFP_LCD_SEG6 /*!< GPE_MFPL PE1 setting for LCD_SEG6*/ 1816 #define LCD_SEG6_PA5 SYS_GPA_MFPL_PA5MFP_LCD_SEG6 /*!< GPA_MFPL PA5 setting for LCD_SEG6*/ 1817 #define LCD_SEG7_PA6 SYS_GPA_MFPL_PA6MFP_LCD_SEG7 /*!< GPA_MFPL PA6 setting for LCD_SEG7*/ 1818 #define LCD_SEG7_PE2 SYS_GPE_MFPL_PE2MFP_LCD_SEG7 /*!< GPE_MFPL PE2 setting for LCD_SEG7*/ 1819 #define LCD_SEG8_PE3 SYS_GPE_MFPL_PE3MFP_LCD_SEG8 /*!< GPE_MFPL PE3 setting for LCD_SEG8*/ 1820 #define LCD_SEG8_PA7 SYS_GPA_MFPL_PA7MFP_LCD_SEG8 /*!< GPA_MFPL PA7 setting for LCD_SEG8*/ 1821 #define LCD_SEG9_PC6 SYS_GPC_MFPL_PC6MFP_LCD_SEG9 /*!< GPC_MFPL PC6 setting for LCD_SEG9*/ 1822 #define LCD_SEG9_PE4 SYS_GPE_MFPL_PE4MFP_LCD_SEG9 /*!< GPE_MFPL PE4 setting for LCD_SEG9*/ 1823 #define QEI0_A_PD11 SYS_GPD_MFPH_PD11MFP_QEI0_A /*!< GPD_MFPH PD11 setting for QEI0_A*/ 1824 #define QEI0_A_PA4 SYS_GPA_MFPL_PA4MFP_QEI0_A /*!< GPA_MFPL PA4 setting for QEI0_A*/ 1825 #define QEI0_A_PE3 SYS_GPE_MFPL_PE3MFP_QEI0_A /*!< GPE_MFPL PE3 setting for QEI0_A*/ 1826 #define QEI0_B_PE2 SYS_GPE_MFPL_PE2MFP_QEI0_B /*!< GPE_MFPL PE2 setting for QEI0_B*/ 1827 #define QEI0_B_PD10 SYS_GPD_MFPH_PD10MFP_QEI0_B /*!< GPD_MFPH PD10 setting for QEI0_B*/ 1828 #define QEI0_B_PA3 SYS_GPA_MFPL_PA3MFP_QEI0_B /*!< GPA_MFPL PA3 setting for QEI0_B*/ 1829 #define QEI0_INDEX_PE4 SYS_GPE_MFPL_PE4MFP_QEI0_INDEX /*!< GPE_MFPL PE4 setting for QEI0_INDEX*/ 1830 #define QEI0_INDEX_PA5 SYS_GPA_MFPL_PA5MFP_QEI0_INDEX /*!< GPA_MFPL PA5 setting for QEI0_INDEX*/ 1831 #define QEI0_INDEX_PD12 SYS_GPD_MFPH_PD12MFP_QEI0_INDEX /*!< GPD_MFPH PD12 setting for QEI0_INDEX*/ 1832 #define QEI1_A_PA13 SYS_GPA_MFPH_PA13MFP_QEI1_A /*!< GPA_MFPH PA13 setting for QEI1_A*/ 1833 #define QEI1_A_PE6 SYS_GPE_MFPL_PE6MFP_QEI1_A /*!< GPE_MFPL PE6 setting for QEI1_A*/ 1834 #define QEI1_A_PA9 SYS_GPA_MFPH_PA9MFP_QEI1_A /*!< GPA_MFPH PA9 setting for QEI1_A*/ 1835 #define QEI1_B_PE5 SYS_GPE_MFPL_PE5MFP_QEI1_B /*!< GPE_MFPL PE5 setting for QEI1_B*/ 1836 #define QEI1_B_PA8 SYS_GPA_MFPH_PA8MFP_QEI1_B /*!< GPA_MFPH PA8 setting for QEI1_B*/ 1837 #define QEI1_B_PA14 SYS_GPA_MFPH_PA14MFP_QEI1_B /*!< GPA_MFPH PA14 setting for QEI1_B*/ 1838 #define QEI1_INDEX_PA10 SYS_GPA_MFPH_PA10MFP_QEI1_INDEX /*!< GPA_MFPH PA10 setting for QEI1_INDEX*/ 1839 #define QEI1_INDEX_PE7 SYS_GPE_MFPL_PE7MFP_QEI1_INDEX /*!< GPE_MFPL PE7 setting for QEI1_INDEX*/ 1840 #define QEI1_INDEX_PA12 SYS_GPA_MFPH_PA12MFP_QEI1_INDEX /*!< GPA_MFPH PA12 setting for QEI1_INDEX*/ 1841 #define QSPI0_CLK_PH8 SYS_GPH_MFPH_PH8MFP_QSPI0_CLK /*!< GPH_MFPH PH8 setting for QSPI0_CLK*/ 1842 #define QSPI0_CLK_PF2 SYS_GPF_MFPL_PF2MFP_QSPI0_CLK /*!< GPF_MFPL PF2 setting for QSPI0_CLK*/ 1843 #define QSPI0_CLK_PA2 SYS_GPA_MFPL_PA2MFP_QSPI0_CLK /*!< GPA_MFPL PA2 setting for QSPI0_CLK*/ 1844 #define QSPI0_CLK_PC2 SYS_GPC_MFPL_PC2MFP_QSPI0_CLK /*!< GPC_MFPL PC2 setting for QSPI0_CLK*/ 1845 #define QSPI0_MISO0_PC1 SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0 /*!< GPC_MFPL PC1 setting for QSPI0_MISO0*/ 1846 #define QSPI0_MISO0_PE1 SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0 /*!< GPE_MFPL PE1 setting for QSPI0_MISO0*/ 1847 #define QSPI0_MISO0_PA1 SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0 /*!< GPA_MFPL PA1 setting for QSPI0_MISO0*/ 1848 #define QSPI0_MISO1_PB1 SYS_GPB_MFPL_PB1MFP_QSPI0_MISO1 /*!< GPB_MFPL PB1 setting for QSPI0_MISO1*/ 1849 #define QSPI0_MISO1_PC5 SYS_GPC_MFPL_PC5MFP_QSPI0_MISO1 /*!< GPC_MFPL PC5 setting for QSPI0_MISO1*/ 1850 #define QSPI0_MISO1_PH10 SYS_GPH_MFPH_PH10MFP_QSPI0_MISO1 /*!< GPH_MFPH PH10 setting for QSPI0_MISO1*/ 1851 #define QSPI0_MISO1_PA5 SYS_GPA_MFPL_PA5MFP_QSPI0_MISO1 /*!< GPA_MFPL PA5 setting for QSPI0_MISO1*/ 1852 #define QSPI0_MOSI0_PC0 SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0 /*!< GPC_MFPL PC0 setting for QSPI0_MOSI0*/ 1853 #define QSPI0_MOSI0_PE0 SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0 /*!< GPE_MFPL PE0 setting for QSPI0_MOSI0*/ 1854 #define QSPI0_MOSI0_PA0 SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0 /*!< GPA_MFPL PA0 setting for QSPI0_MOSI0*/ 1855 #define QSPI0_MOSI1_PC4 SYS_GPC_MFPL_PC4MFP_QSPI0_MOSI1 /*!< GPC_MFPL PC4 setting for QSPI0_MOSI1*/ 1856 #define QSPI0_MOSI1_PH11 SYS_GPH_MFPH_PH11MFP_QSPI0_MOSI1 /*!< GPH_MFPH PH11 setting for QSPI0_MOSI1*/ 1857 #define QSPI0_MOSI1_PB0 SYS_GPB_MFPL_PB0MFP_QSPI0_MOSI1 /*!< GPB_MFPL PB0 setting for QSPI0_MOSI1*/ 1858 #define QSPI0_MOSI1_PA4 SYS_GPA_MFPL_PA4MFP_QSPI0_MOSI1 /*!< GPA_MFPL PA4 setting for QSPI0_MOSI1*/ 1859 #define QSPI0_SS_PA3 SYS_GPA_MFPL_PA3MFP_QSPI0_SS /*!< GPA_MFPL PA3 setting for QSPI0_SS*/ 1860 #define QSPI0_SS_PC3 SYS_GPC_MFPL_PC3MFP_QSPI0_SS /*!< GPC_MFPL PC3 setting for QSPI0_SS*/ 1861 #define QSPI0_SS_PH9 SYS_GPH_MFPH_PH9MFP_QSPI0_SS /*!< GPH_MFPH PH9 setting for QSPI0_SS*/ 1862 #define SC0_CLK_PA0 SYS_GPA_MFPL_PA0MFP_SC0_CLK /*!< GPA_MFPL PA0 setting for SC0_CLK*/ 1863 #define SC0_CLK_PF6 SYS_GPF_MFPL_PF6MFP_SC0_CLK /*!< GPF_MFPL PF6 setting for SC0_CLK*/ 1864 #define SC0_CLK_PE2 SYS_GPE_MFPL_PE2MFP_SC0_CLK /*!< GPE_MFPL PE2 setting for SC0_CLK*/ 1865 #define SC0_CLK_PB5 SYS_GPB_MFPL_PB5MFP_SC0_CLK /*!< GPB_MFPL PB5 setting for SC0_CLK*/ 1866 #define SC0_DAT_PF7 SYS_GPF_MFPL_PF7MFP_SC0_DAT /*!< GPF_MFPL PF7 setting for SC0_DAT*/ 1867 #define SC0_DAT_PA1 SYS_GPA_MFPL_PA1MFP_SC0_DAT /*!< GPA_MFPL PA1 setting for SC0_DAT*/ 1868 #define SC0_DAT_PE3 SYS_GPE_MFPL_PE3MFP_SC0_DAT /*!< GPE_MFPL PE3 setting for SC0_DAT*/ 1869 #define SC0_DAT_PB4 SYS_GPB_MFPL_PB4MFP_SC0_DAT /*!< GPB_MFPL PB4 setting for SC0_DAT*/ 1870 #define SC0_PWR_PF9 SYS_GPF_MFPH_PF9MFP_SC0_PWR /*!< GPF_MFPH PF9 setting for SC0_PWR*/ 1871 #define SC0_PWR_PE5 SYS_GPE_MFPL_PE5MFP_SC0_PWR /*!< GPE_MFPL PE5 setting for SC0_PWR*/ 1872 #define SC0_PWR_PA3 SYS_GPA_MFPL_PA3MFP_SC0_PWR /*!< GPA_MFPL PA3 setting for SC0_PWR*/ 1873 #define SC0_PWR_PB2 SYS_GPB_MFPL_PB2MFP_SC0_PWR /*!< GPB_MFPL PB2 setting for SC0_PWR*/ 1874 #define SC0_RST_PE4 SYS_GPE_MFPL_PE4MFP_SC0_RST /*!< GPE_MFPL PE4 setting for SC0_RST*/ 1875 #define SC0_RST_PF8 SYS_GPF_MFPH_PF8MFP_SC0_RST /*!< GPF_MFPH PF8 setting for SC0_RST*/ 1876 #define SC0_RST_PA2 SYS_GPA_MFPL_PA2MFP_SC0_RST /*!< GPA_MFPL PA2 setting for SC0_RST*/ 1877 #define SC0_RST_PB3 SYS_GPB_MFPL_PB3MFP_SC0_RST /*!< GPB_MFPL PB3 setting for SC0_RST*/ 1878 #define SC0_nCD_PC12 SYS_GPC_MFPH_PC12MFP_SC0_nCD /*!< GPC_MFPH PC12 setting for SC0_nCD*/ 1879 #define SC0_nCD_PA4 SYS_GPA_MFPL_PA4MFP_SC0_nCD /*!< GPA_MFPL PA4 setting for SC0_nCD*/ 1880 #define SC0_nCD_PF10 SYS_GPF_MFPH_PF10MFP_SC0_nCD /*!< GPF_MFPH PF10 setting for SC0_nCD*/ 1881 #define SC0_nCD_PE6 SYS_GPE_MFPL_PE6MFP_SC0_nCD /*!< GPE_MFPL PE6 setting for SC0_nCD*/ 1882 #define SC1_CLK_PB12 SYS_GPB_MFPH_PB12MFP_SC1_CLK /*!< GPB_MFPH PB12 setting for SC1_CLK*/ 1883 #define SC1_CLK_PC0 SYS_GPC_MFPL_PC0MFP_SC1_CLK /*!< GPC_MFPL PC0 setting for SC1_CLK*/ 1884 #define SC1_CLK_PD4 SYS_GPD_MFPL_PD4MFP_SC1_CLK /*!< GPD_MFPL PD4 setting for SC1_CLK*/ 1885 #define SC1_DAT_PD5 SYS_GPD_MFPL_PD5MFP_SC1_DAT /*!< GPD_MFPL PD5 setting for SC1_DAT*/ 1886 #define SC1_DAT_PC1 SYS_GPC_MFPL_PC1MFP_SC1_DAT /*!< GPC_MFPL PC1 setting for SC1_DAT*/ 1887 #define SC1_DAT_PB13 SYS_GPB_MFPH_PB13MFP_SC1_DAT /*!< GPB_MFPH PB13 setting for SC1_DAT*/ 1888 #define SC1_PWR_PD7 SYS_GPD_MFPL_PD7MFP_SC1_PWR /*!< GPD_MFPL PD7 setting for SC1_PWR*/ 1889 #define SC1_PWR_PC3 SYS_GPC_MFPL_PC3MFP_SC1_PWR /*!< GPC_MFPL PC3 setting for SC1_PWR*/ 1890 #define SC1_PWR_PB15 SYS_GPB_MFPH_PB15MFP_SC1_PWR /*!< GPB_MFPH PB15 setting for SC1_PWR*/ 1891 #define SC1_RST_PD6 SYS_GPD_MFPL_PD6MFP_SC1_RST /*!< GPD_MFPL PD6 setting for SC1_RST*/ 1892 #define SC1_RST_PB14 SYS_GPB_MFPH_PB14MFP_SC1_RST /*!< GPB_MFPH PB14 setting for SC1_RST*/ 1893 #define SC1_RST_PC2 SYS_GPC_MFPL_PC2MFP_SC1_RST /*!< GPC_MFPL PC2 setting for SC1_RST*/ 1894 #define SC1_nCD_PD14 SYS_GPD_MFPH_PD14MFP_SC1_nCD /*!< GPD_MFPH PD14 setting for SC1_nCD*/ 1895 #define SC1_nCD_PC4 SYS_GPC_MFPL_PC4MFP_SC1_nCD /*!< GPC_MFPL PC4 setting for SC1_nCD*/ 1896 #define SC1_nCD_PD3 SYS_GPD_MFPL_PD3MFP_SC1_nCD /*!< GPD_MFPL PD3 setting for SC1_nCD*/ 1897 #define SC2_CLK_PA6 SYS_GPA_MFPL_PA6MFP_SC2_CLK /*!< GPA_MFPL PA6 setting for SC2_CLK*/ 1898 #define SC2_CLK_PD0 SYS_GPD_MFPL_PD0MFP_SC2_CLK /*!< GPD_MFPL PD0 setting for SC2_CLK*/ 1899 #define SC2_CLK_PA15 SYS_GPA_MFPH_PA15MFP_SC2_CLK /*!< GPA_MFPH PA15 setting for SC2_CLK*/ 1900 #define SC2_CLK_PA8 SYS_GPA_MFPH_PA8MFP_SC2_CLK /*!< GPA_MFPH PA8 setting for SC2_CLK*/ 1901 #define SC2_CLK_PE0 SYS_GPE_MFPL_PE0MFP_SC2_CLK /*!< GPE_MFPL PE0 setting for SC2_CLK*/ 1902 #define SC2_DAT_PA9 SYS_GPA_MFPH_PA9MFP_SC2_DAT /*!< GPA_MFPH PA9 setting for SC2_DAT*/ 1903 #define SC2_DAT_PD1 SYS_GPD_MFPL_PD1MFP_SC2_DAT /*!< GPD_MFPL PD1 setting for SC2_DAT*/ 1904 #define SC2_DAT_PA7 SYS_GPA_MFPL_PA7MFP_SC2_DAT /*!< GPA_MFPL PA7 setting for SC2_DAT*/ 1905 #define SC2_DAT_PA14 SYS_GPA_MFPH_PA14MFP_SC2_DAT /*!< GPA_MFPH PA14 setting for SC2_DAT*/ 1906 #define SC2_DAT_PE1 SYS_GPE_MFPL_PE1MFP_SC2_DAT /*!< GPE_MFPL PE1 setting for SC2_DAT*/ 1907 #define SC2_PWR_PC7 SYS_GPC_MFPL_PC7MFP_SC2_PWR /*!< GPC_MFPL PC7 setting for SC2_PWR*/ 1908 #define SC2_PWR_PH8 SYS_GPH_MFPH_PH8MFP_SC2_PWR /*!< GPH_MFPH PH8 setting for SC2_PWR*/ 1909 #define SC2_PWR_PD3 SYS_GPD_MFPL_PD3MFP_SC2_PWR /*!< GPD_MFPL PD3 setting for SC2_PWR*/ 1910 #define SC2_PWR_PA11 SYS_GPA_MFPH_PA11MFP_SC2_PWR /*!< GPA_MFPH PA11 setting for SC2_PWR*/ 1911 #define SC2_PWR_PA12 SYS_GPA_MFPH_PA12MFP_SC2_PWR /*!< GPA_MFPH PA12 setting for SC2_PWR*/ 1912 #define SC2_RST_PD2 SYS_GPD_MFPL_PD2MFP_SC2_RST /*!< GPD_MFPL PD2 setting for SC2_RST*/ 1913 #define SC2_RST_PC6 SYS_GPC_MFPL_PC6MFP_SC2_RST /*!< GPC_MFPL PC6 setting for SC2_RST*/ 1914 #define SC2_RST_PH9 SYS_GPH_MFPH_PH9MFP_SC2_RST /*!< GPH_MFPH PH9 setting for SC2_RST*/ 1915 #define SC2_RST_PA13 SYS_GPA_MFPH_PA13MFP_SC2_RST /*!< GPA_MFPH PA13 setting for SC2_RST*/ 1916 #define SC2_RST_PA10 SYS_GPA_MFPH_PA10MFP_SC2_RST /*!< GPA_MFPH PA10 setting for SC2_RST*/ 1917 #define SC2_nCD_PA5 SYS_GPA_MFPL_PA5MFP_SC2_nCD /*!< GPA_MFPL PA5 setting for SC2_nCD*/ 1918 #define SC2_nCD_PH10 SYS_GPH_MFPH_PH10MFP_SC2_nCD /*!< GPH_MFPH PH10 setting for SC2_nCD*/ 1919 #define SC2_nCD_PD13 SYS_GPD_MFPH_PD13MFP_SC2_nCD /*!< GPD_MFPH PD13 setting for SC2_nCD*/ 1920 #define SC2_nCD_PC13 SYS_GPC_MFPH_PC13MFP_SC2_nCD /*!< GPC_MFPH PC13 setting for SC2_nCD*/ 1921 #define SD0_CLK_PB1 SYS_GPB_MFPL_PB1MFP_SD0_CLK /*!< GPB_MFPL PB1 setting for SD0_CLK*/ 1922 #define SD0_CLK_PE6 SYS_GPE_MFPL_PE6MFP_SD0_CLK /*!< GPE_MFPL PE6 setting for SD0_CLK*/ 1923 #define SD0_CMD_PE7 SYS_GPE_MFPL_PE7MFP_SD0_CMD /*!< GPE_MFPL PE7 setting for SD0_CMD*/ 1924 #define SD0_CMD_PB0 SYS_GPB_MFPL_PB0MFP_SD0_CMD /*!< GPB_MFPL PB0 setting for SD0_CMD*/ 1925 #define SD0_DAT0_PE2 SYS_GPE_MFPL_PE2MFP_SD0_DAT0 /*!< GPE_MFPL PE2 setting for SD0_DAT0*/ 1926 #define SD0_DAT0_PB2 SYS_GPB_MFPL_PB2MFP_SD0_DAT0 /*!< GPB_MFPL PB2 setting for SD0_DAT0*/ 1927 #define SD0_DAT1_PE3 SYS_GPE_MFPL_PE3MFP_SD0_DAT1 /*!< GPE_MFPL PE3 setting for SD0_DAT1*/ 1928 #define SD0_DAT1_PB3 SYS_GPB_MFPL_PB3MFP_SD0_DAT1 /*!< GPB_MFPL PB3 setting for SD0_DAT1*/ 1929 #define SD0_DAT2_PE4 SYS_GPE_MFPL_PE4MFP_SD0_DAT2 /*!< GPE_MFPL PE4 setting for SD0_DAT2*/ 1930 #define SD0_DAT2_PB4 SYS_GPB_MFPL_PB4MFP_SD0_DAT2 /*!< GPB_MFPL PB4 setting for SD0_DAT2*/ 1931 #define SD0_DAT3_PE5 SYS_GPE_MFPL_PE5MFP_SD0_DAT3 /*!< GPE_MFPL PE5 setting for SD0_DAT3*/ 1932 #define SD0_DAT3_PB5 SYS_GPB_MFPL_PB5MFP_SD0_DAT3 /*!< GPB_MFPL PB5 setting for SD0_DAT3*/ 1933 #define SD0_nCD_PD13 SYS_GPD_MFPH_PD13MFP_SD0_nCD /*!< GPD_MFPH PD13 setting for SD0_nCD*/ 1934 #define SD0_nCD_PB12 SYS_GPB_MFPH_PB12MFP_SD0_nCD /*!< GPB_MFPH PB12 setting for SD0_nCD*/ 1935 #define SEG15_PC5 SYS_GPC_MFPL_PC5MFP_SEG15 /*!< GPC_MFPL PC5 setting for SEG15*/ 1936 #define SEG16_PC4 SYS_GPC_MFPL_PC4MFP_SEG16 /*!< GPC_MFPL PC4 setting for SEG16*/ 1937 #define SPI0_CLK_PD2 SYS_GPD_MFPL_PD2MFP_SPI0_CLK /*!< GPD_MFPL PD2 setting for SPI0_CLK*/ 1938 #define SPI0_CLK_PB14 SYS_GPB_MFPH_PB14MFP_SPI0_CLK /*!< GPB_MFPH PB14 setting for SPI0_CLK*/ 1939 #define SPI0_CLK_PF8 SYS_GPF_MFPH_PF8MFP_SPI0_CLK /*!< GPF_MFPH PF8 setting for SPI0_CLK*/ 1940 #define SPI0_CLK_PA2 SYS_GPA_MFPL_PA2MFP_SPI0_CLK /*!< GPA_MFPL PA2 setting for SPI0_CLK*/ 1941 #define SPI0_I2SMCLK_PB11 SYS_GPB_MFPH_PB11MFP_SPI0_I2SMCLK /*!< GPB_MFPH PB11 setting for SPI0_I2SMCLK*/ 1942 #define SPI0_I2SMCLK_PB0 SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK*/ 1943 #define SPI0_I2SMCLK_PF10 SYS_GPF_MFPH_PF10MFP_SPI0_I2SMCLK /*!< GPF_MFPH PF10 setting for SPI0_I2SMCLK*/ 1944 #define SPI0_I2SMCLK_PA4 SYS_GPA_MFPL_PA4MFP_SPI0_I2SMCLK /*!< GPA_MFPL PA4 setting for SPI0_I2SMCLK*/ 1945 #define SPI0_I2SMCLK_PD14 SYS_GPD_MFPH_PD14MFP_SPI0_I2SMCLK /*!< GPD_MFPH PD14 setting for SPI0_I2SMCLK*/ 1946 #define SPI0_I2SMCLK_PD13 SYS_GPD_MFPH_PD13MFP_SPI0_I2SMCLK /*!< GPD_MFPH PD13 setting for SPI0_I2SMCLK*/ 1947 #define SPI0_MISO_PA1 SYS_GPA_MFPL_PA1MFP_SPI0_MISO /*!< GPA_MFPL PA1 setting for SPI0_MISO*/ 1948 #define SPI0_MISO_PF7 SYS_GPF_MFPL_PF7MFP_SPI0_MISO /*!< GPF_MFPL PF7 setting for SPI0_MISO*/ 1949 #define SPI0_MISO_PD1 SYS_GPD_MFPL_PD1MFP_SPI0_MISO /*!< GPD_MFPL PD1 setting for SPI0_MISO*/ 1950 #define SPI0_MISO_PB13 SYS_GPB_MFPH_PB13MFP_SPI0_MISO /*!< GPB_MFPH PB13 setting for SPI0_MISO*/ 1951 #define SPI0_MOSI_PF6 SYS_GPF_MFPL_PF6MFP_SPI0_MOSI /*!< GPF_MFPL PF6 setting for SPI0_MOSI*/ 1952 #define SPI0_MOSI_PD0 SYS_GPD_MFPL_PD0MFP_SPI0_MOSI /*!< GPD_MFPL PD0 setting for SPI0_MOSI*/ 1953 #define SPI0_MOSI_PB12 SYS_GPB_MFPH_PB12MFP_SPI0_MOSI /*!< GPB_MFPH PB12 setting for SPI0_MOSI*/ 1954 #define SPI0_MOSI_PA0 SYS_GPA_MFPL_PA0MFP_SPI0_MOSI /*!< GPA_MFPL PA0 setting for SPI0_MOSI*/ 1955 #define SPI0_SS_PF9 SYS_GPF_MFPH_PF9MFP_SPI0_SS /*!< GPF_MFPH PF9 setting for SPI0_SS*/ 1956 #define SPI0_SS_PA3 SYS_GPA_MFPL_PA3MFP_SPI0_SS /*!< GPA_MFPL PA3 setting for SPI0_SS*/ 1957 #define SPI0_SS_PB15 SYS_GPB_MFPH_PB15MFP_SPI0_SS /*!< GPB_MFPH PB15 setting for SPI0_SS*/ 1958 #define SPI0_SS_PD3 SYS_GPD_MFPL_PD3MFP_SPI0_SS /*!< GPD_MFPL PD3 setting for SPI0_SS*/ 1959 #define SPI1_CLK_PD5 SYS_GPD_MFPL_PD5MFP_SPI1_CLK /*!< GPD_MFPL PD5 setting for SPI1_CLK*/ 1960 #define SPI1_CLK_PH6 SYS_GPH_MFPL_PH6MFP_SPI1_CLK /*!< GPH_MFPL PH6 setting for SPI1_CLK*/ 1961 #define SPI1_CLK_PC1 SYS_GPC_MFPL_PC1MFP_SPI1_CLK /*!< GPC_MFPL PC1 setting for SPI1_CLK*/ 1962 #define SPI1_CLK_PB3 SYS_GPB_MFPL_PB3MFP_SPI1_CLK /*!< GPB_MFPL PB3 setting for SPI1_CLK*/ 1963 #define SPI1_CLK_PH8 SYS_GPH_MFPH_PH8MFP_SPI1_CLK /*!< GPH_MFPH PH8 setting for SPI1_CLK*/ 1964 #define SPI1_CLK_PA7 SYS_GPA_MFPL_PA7MFP_SPI1_CLK /*!< GPA_MFPL PA7 setting for SPI1_CLK*/ 1965 #define SPI1_I2SMCLK_PC4 SYS_GPC_MFPL_PC4MFP_SPI1_I2SMCLK /*!< GPC_MFPL PC4 setting for SPI1_I2SMCLK*/ 1966 #define SPI1_I2SMCLK_PB1 SYS_GPB_MFPL_PB1MFP_SPI1_I2SMCLK /*!< GPB_MFPL PB1 setting for SPI1_I2SMCLK*/ 1967 #define SPI1_I2SMCLK_PA5 SYS_GPA_MFPL_PA5MFP_SPI1_I2SMCLK /*!< GPA_MFPL PA5 setting for SPI1_I2SMCLK*/ 1968 #define SPI1_I2SMCLK_PD13 SYS_GPD_MFPH_PD13MFP_SPI1_I2SMCLK /*!< GPD_MFPH PD13 setting for SPI1_I2SMCLK*/ 1969 #define SPI1_I2SMCLK_PH10 SYS_GPH_MFPH_PH10MFP_SPI1_I2SMCLK /*!< GPH_MFPH PH10 setting for SPI1_I2SMCLK*/ 1970 #define SPI1_MISO_PC3 SYS_GPC_MFPL_PC3MFP_SPI1_MISO /*!< GPC_MFPL PC3 setting for SPI1_MISO*/ 1971 #define SPI1_MISO_PC7 SYS_GPC_MFPL_PC7MFP_SPI1_MISO /*!< GPC_MFPL PC7 setting for SPI1_MISO*/ 1972 #define SPI1_MISO_PH4 SYS_GPH_MFPL_PH4MFP_SPI1_MISO /*!< GPH_MFPL PH4 setting for SPI1_MISO*/ 1973 #define SPI1_MISO_PB5 SYS_GPB_MFPL_PB5MFP_SPI1_MISO /*!< GPB_MFPL PB5 setting for SPI1_MISO*/ 1974 #define SPI1_MISO_PE1 SYS_GPE_MFPL_PE1MFP_SPI1_MISO /*!< GPE_MFPL PE1 setting for SPI1_MISO*/ 1975 #define SPI1_MISO_PD7 SYS_GPD_MFPL_PD7MFP_SPI1_MISO /*!< GPD_MFPL PD7 setting for SPI1_MISO*/ 1976 #define SPI1_MOSI_PE0 SYS_GPE_MFPL_PE0MFP_SPI1_MOSI /*!< GPE_MFPL PE0 setting for SPI1_MOSI*/ 1977 #define SPI1_MOSI_PB4 SYS_GPB_MFPL_PB4MFP_SPI1_MOSI /*!< GPB_MFPL PB4 setting for SPI1_MOSI*/ 1978 #define SPI1_MOSI_PC6 SYS_GPC_MFPL_PC6MFP_SPI1_MOSI /*!< GPC_MFPL PC6 setting for SPI1_MOSI*/ 1979 #define SPI1_MOSI_PD6 SYS_GPD_MFPL_PD6MFP_SPI1_MOSI /*!< GPD_MFPL PD6 setting for SPI1_MOSI*/ 1980 #define SPI1_MOSI_PH5 SYS_GPH_MFPL_PH5MFP_SPI1_MOSI /*!< GPH_MFPL PH5 setting for SPI1_MOSI*/ 1981 #define SPI1_MOSI_PC2 SYS_GPC_MFPL_PC2MFP_SPI1_MOSI /*!< GPC_MFPL PC2 setting for SPI1_MOSI*/ 1982 #define SPI1_SS_PH7 SYS_GPH_MFPL_PH7MFP_SPI1_SS /*!< GPH_MFPL PH7 setting for SPI1_SS*/ 1983 #define SPI1_SS_PB2 SYS_GPB_MFPL_PB2MFP_SPI1_SS /*!< GPB_MFPL PB2 setting for SPI1_SS*/ 1984 #define SPI1_SS_PA6 SYS_GPA_MFPL_PA6MFP_SPI1_SS /*!< GPA_MFPL PA6 setting for SPI1_SS*/ 1985 #define SPI1_SS_PD4 SYS_GPD_MFPL_PD4MFP_SPI1_SS /*!< GPD_MFPL PD4 setting for SPI1_SS*/ 1986 #define SPI1_SS_PH9 SYS_GPH_MFPH_PH9MFP_SPI1_SS /*!< GPH_MFPH PH9 setting for SPI1_SS*/ 1987 #define SPI1_SS_PC0 SYS_GPC_MFPL_PC0MFP_SPI1_SS /*!< GPC_MFPL PC0 setting for SPI1_SS*/ 1988 #define SPI2_CLK_PE8 SYS_GPE_MFPH_PE8MFP_SPI2_CLK /*!< GPE_MFPH PE8 setting for SPI2_CLK*/ 1989 #define SPI2_CLK_PA10 SYS_GPA_MFPH_PA10MFP_SPI2_CLK /*!< GPA_MFPH PA10 setting for SPI2_CLK*/ 1990 #define SPI2_CLK_PA13 SYS_GPA_MFPH_PA13MFP_SPI2_CLK /*!< GPA_MFPH PA13 setting for SPI2_CLK*/ 1991 #define SPI2_CLK_PG3 SYS_GPG_MFPL_PG3MFP_SPI2_CLK /*!< GPG_MFPL PG3 setting for SPI2_CLK*/ 1992 #define SPI2_I2SMCLK_PE12 SYS_GPE_MFPH_PE12MFP_SPI2_I2SMCLK /*!< GPE_MFPH PE12 setting for SPI2_I2SMCLK*/ 1993 #define SPI2_I2SMCLK_PC13 SYS_GPC_MFPH_PC13MFP_SPI2_I2SMCLK /*!< GPC_MFPH PC13 setting for SPI2_I2SMCLK*/ 1994 #define SPI2_I2SMCLK_PB0 SYS_GPB_MFPL_PB0MFP_SPI2_I2SMCLK /*!< GPB_MFPL PB0 setting for SPI2_I2SMCLK*/ 1995 #define SPI2_MISO_PE9 SYS_GPE_MFPH_PE9MFP_SPI2_MISO /*!< GPE_MFPH PE9 setting for SPI2_MISO*/ 1996 #define SPI2_MISO_PA9 SYS_GPA_MFPH_PA9MFP_SPI2_MISO /*!< GPA_MFPH PA9 setting for SPI2_MISO*/ 1997 #define SPI2_MISO_PA14 SYS_GPA_MFPH_PA14MFP_SPI2_MISO /*!< GPA_MFPH PA14 setting for SPI2_MISO*/ 1998 #define SPI2_MISO_PG4 SYS_GPG_MFPL_PG4MFP_SPI2_MISO /*!< GPG_MFPL PG4 setting for SPI2_MISO*/ 1999 #define SPI2_MOSI_PF11 SYS_GPF_MFPH_PF11MFP_SPI2_MOSI /*!< GPF_MFPH PF11 setting for SPI2_MOSI*/ 2000 #define SPI2_MOSI_PA15 SYS_GPA_MFPH_PA15MFP_SPI2_MOSI /*!< GPA_MFPH PA15 setting for SPI2_MOSI*/ 2001 #define SPI2_MOSI_PE10 SYS_GPE_MFPH_PE10MFP_SPI2_MOSI /*!< GPE_MFPH PE10 setting for SPI2_MOSI*/ 2002 #define SPI2_MOSI_PA8 SYS_GPA_MFPH_PA8MFP_SPI2_MOSI /*!< GPA_MFPH PA8 setting for SPI2_MOSI*/ 2003 #define SPI2_SS_PE11 SYS_GPE_MFPH_PE11MFP_SPI2_SS /*!< GPE_MFPH PE11 setting for SPI2_SS*/ 2004 #define SPI2_SS_PG2 SYS_GPG_MFPL_PG2MFP_SPI2_SS /*!< GPG_MFPL PG2 setting for SPI2_SS*/ 2005 #define SPI2_SS_PA11 SYS_GPA_MFPH_PA11MFP_SPI2_SS /*!< GPA_MFPH PA11 setting for SPI2_SS*/ 2006 #define SPI2_SS_PA12 SYS_GPA_MFPH_PA12MFP_SPI2_SS /*!< GPA_MFPH PA12 setting for SPI2_SS*/ 2007 #define SPI3_CLK_PC10 SYS_GPC_MFPH_PC10MFP_SPI3_CLK /*!< GPC_MFPH PC10 setting for SPI3_CLK*/ 2008 #define SPI3_CLK_PE4 SYS_GPE_MFPL_PE4MFP_SPI3_CLK /*!< GPE_MFPL PE4 setting for SPI3_CLK*/ 2009 #define SPI3_CLK_PB11 SYS_GPB_MFPH_PB11MFP_SPI3_CLK /*!< GPB_MFPH PB11 setting for SPI3_CLK*/ 2010 #define SPI3_I2SMCLK_PE6 SYS_GPE_MFPL_PE6MFP_SPI3_I2SMCLK /*!< GPE_MFPL PE6 setting for SPI3_I2SMCLK*/ 2011 #define SPI3_I2SMCLK_PF6 SYS_GPF_MFPL_PF6MFP_SPI3_I2SMCLK /*!< GPF_MFPL PF6 setting for SPI3_I2SMCLK*/ 2012 #define SPI3_I2SMCLK_PB1 SYS_GPB_MFPL_PB1MFP_SPI3_I2SMCLK /*!< GPB_MFPL PB1 setting for SPI3_I2SMCLK*/ 2013 #define SPI3_I2SMCLK_PD14 SYS_GPD_MFPH_PD14MFP_SPI3_I2SMCLK /*!< GPD_MFPH PD14 setting for SPI3_I2SMCLK*/ 2014 #define SPI3_MISO_PE3 SYS_GPE_MFPL_PE3MFP_SPI3_MISO /*!< GPE_MFPL PE3 setting for SPI3_MISO*/ 2015 #define SPI3_MISO_PC12 SYS_GPC_MFPH_PC12MFP_SPI3_MISO /*!< GPC_MFPH PC12 setting for SPI3_MISO*/ 2016 #define SPI3_MISO_PB9 SYS_GPB_MFPH_PB9MFP_SPI3_MISO /*!< GPB_MFPH PB9 setting for SPI3_MISO*/ 2017 #define SPI3_MOSI_PC11 SYS_GPC_MFPH_PC11MFP_SPI3_MOSI /*!< GPC_MFPH PC11 setting for SPI3_MOSI*/ 2018 #define SPI3_MOSI_PE2 SYS_GPE_MFPL_PE2MFP_SPI3_MOSI /*!< GPE_MFPL PE2 setting for SPI3_MOSI*/ 2019 #define SPI3_MOSI_PB8 SYS_GPB_MFPH_PB8MFP_SPI3_MOSI /*!< GPB_MFPH PB8 setting for SPI3_MOSI*/ 2020 #define SPI3_SS_PE5 SYS_GPE_MFPL_PE5MFP_SPI3_SS /*!< GPE_MFPL PE5 setting for SPI3_SS*/ 2021 #define SPI3_SS_PB10 SYS_GPB_MFPH_PB10MFP_SPI3_SS /*!< GPB_MFPH PB10 setting for SPI3_SS*/ 2022 #define SPI3_SS_PC9 SYS_GPC_MFPH_PC9MFP_SPI3_SS /*!< GPC_MFPH PC9 setting for SPI3_SS*/ 2023 #define TAMPER0_PF6 SYS_GPF_MFPL_PF6MFP_TAMPER0 /*!< GPF_MFPL PF6 setting for TAMPER0*/ 2024 #define TAMPER1_PF7 SYS_GPF_MFPL_PF7MFP_TAMPER1 /*!< GPF_MFPL PF7 setting for TAMPER1*/ 2025 #define TAMPER2_PF8 SYS_GPF_MFPH_PF8MFP_TAMPER2 /*!< GPF_MFPH PF8 setting for TAMPER2*/ 2026 #define TAMPER3_PF9 SYS_GPF_MFPH_PF9MFP_TAMPER3 /*!< GPF_MFPH PF9 setting for TAMPER3*/ 2027 #define TAMPER4_PF10 SYS_GPF_MFPH_PF10MFP_TAMPER4 /*!< GPF_MFPH PF10 setting for TAMPER4*/ 2028 #define TAMPER5_PF11 SYS_GPF_MFPH_PF11MFP_TAMPER5 /*!< GPF_MFPH PF11 setting for TAMPER5*/ 2029 #define TM0_PG2 SYS_GPG_MFPL_PG2MFP_TM0 /*!< GPG_MFPL PG2 setting for TM0*/ 2030 #define TM0_PB5 SYS_GPB_MFPL_PB5MFP_TM0 /*!< GPB_MFPL PB5 setting for TM0*/ 2031 #define TM0_PC7 SYS_GPC_MFPL_PC7MFP_TM0 /*!< GPC_MFPL PC7 setting for TM0*/ 2032 #define TM0_EXT_PB15 SYS_GPB_MFPH_PB15MFP_TM0_EXT /*!< GPB_MFPH PB15 setting for TM0_EXT*/ 2033 #define TM0_EXT_PA11 SYS_GPA_MFPH_PA11MFP_TM0_EXT /*!< GPA_MFPH PA11 setting for TM0_EXT*/ 2034 #define TM1_PC6 SYS_GPC_MFPL_PC6MFP_TM1 /*!< GPC_MFPL PC6 setting for TM1*/ 2035 #define TM1_PB4 SYS_GPB_MFPL_PB4MFP_TM1 /*!< GPB_MFPL PB4 setting for TM1*/ 2036 #define TM1_PG3 SYS_GPG_MFPL_PG3MFP_TM1 /*!< GPG_MFPL PG3 setting for TM1*/ 2037 #define TM1_EXT_PB14 SYS_GPB_MFPH_PB14MFP_TM1_EXT /*!< GPB_MFPH PB14 setting for TM1_EXT*/ 2038 #define TM1_EXT_PA10 SYS_GPA_MFPH_PA10MFP_TM1_EXT /*!< GPA_MFPH PA10 setting for TM1_EXT*/ 2039 #define TM2_PB3 SYS_GPB_MFPL_PB3MFP_TM2 /*!< GPB_MFPL PB3 setting for TM2*/ 2040 #define TM2_PA7 SYS_GPA_MFPL_PA7MFP_TM2 /*!< GPA_MFPL PA7 setting for TM2*/ 2041 #define TM2_PD0 SYS_GPD_MFPL_PD0MFP_TM2 /*!< GPD_MFPL PD0 setting for TM2*/ 2042 #define TM2_PG4 SYS_GPG_MFPL_PG4MFP_TM2 /*!< GPG_MFPL PG4 setting for TM2*/ 2043 #define TM2_EXT_PB13 SYS_GPB_MFPH_PB13MFP_TM2_EXT /*!< GPB_MFPH PB13 setting for TM2_EXT*/ 2044 #define TM2_EXT_PA9 SYS_GPA_MFPH_PA9MFP_TM2_EXT /*!< GPA_MFPH PA9 setting for TM2_EXT*/ 2045 #define TM3_PB2 SYS_GPB_MFPL_PB2MFP_TM3 /*!< GPB_MFPL PB2 setting for TM3*/ 2046 #define TM3_PA6 SYS_GPA_MFPL_PA6MFP_TM3 /*!< GPA_MFPL PA6 setting for TM3*/ 2047 #define TM3_PF11 SYS_GPF_MFPH_PF11MFP_TM3 /*!< GPF_MFPH PF11 setting for TM3*/ 2048 #define TM3_EXT_PB12 SYS_GPB_MFPH_PB12MFP_TM3_EXT /*!< GPB_MFPH PB12 setting for TM3_EXT*/ 2049 #define TM3_EXT_PA8 SYS_GPA_MFPH_PA8MFP_TM3_EXT /*!< GPA_MFPH PA8 setting for TM3_EXT*/ 2050 #define TM4_PA7 SYS_GPA_MFPL_PA7MFP_TM4 /*!< GPA_MFPL PA7 setting for TM4*/ 2051 #define TM4_PG4 SYS_GPG_MFPL_PG4MFP_TM4 /*!< GPG_MFPL PG4 setting for TM4*/ 2052 #define TM4_PB3 SYS_GPB_MFPL_PB3MFP_TM4 /*!< GPB_MFPL PB3 setting for TM4*/ 2053 #define TM4_EXT_PB13 SYS_GPB_MFPH_PB13MFP_TM4_EXT /*!< GPB_MFPH PB13 setting for TM4_EXT*/ 2054 #define TM4_EXT_PA9 SYS_GPA_MFPH_PA9MFP_TM4_EXT /*!< GPA_MFPH PA9 setting for TM4_EXT*/ 2055 #define TM5_PF11 SYS_GPF_MFPH_PF11MFP_TM5 /*!< GPF_MFPH PF11 setting for TM5*/ 2056 #define TM5_PB2 SYS_GPB_MFPL_PB2MFP_TM5 /*!< GPB_MFPL PB2 setting for TM5*/ 2057 #define TM5_PA6 SYS_GPA_MFPL_PA6MFP_TM5 /*!< GPA_MFPL PA6 setting for TM5*/ 2058 #define TM5_EXT_PA8 SYS_GPA_MFPH_PA8MFP_TM5_EXT /*!< GPA_MFPH PA8 setting for TM5_EXT*/ 2059 #define TM5_EXT_PB12 SYS_GPB_MFPH_PB12MFP_TM5_EXT /*!< GPB_MFPH PB12 setting for TM5_EXT*/ 2060 #define TRACE_CLK_PE12 SYS_GPE_MFPH_PE12MFP_TRACE_CLK /*!< GPE_MFPH PE12 setting for TRACE_CLK*/ 2061 #define TRACE_DATA0_PE11 SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 /*!< GPE_MFPH PE11 setting for TRACE_DATA0*/ 2062 #define TRACE_DATA1_PE10 SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 /*!< GPE_MFPH PE10 setting for TRACE_DATA1*/ 2063 #define TRACE_DATA2_PE9 SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 /*!< GPE_MFPH PE9 setting for TRACE_DATA2*/ 2064 #define TRACE_DATA3_PE8 SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 /*!< GPE_MFPH PE8 setting for TRACE_DATA3*/ 2065 #define UART0_RXD_PA15 SYS_GPA_MFPH_PA15MFP_UART0_RXD /*!< GPA_MFPH PA15 setting for UART0_RXD*/ 2066 #define UART0_RXD_PD2 SYS_GPD_MFPL_PD2MFP_UART0_RXD /*!< GPD_MFPL PD2 setting for UART0_RXD*/ 2067 #define UART0_RXD_PA4 SYS_GPA_MFPL_PA4MFP_UART0_RXD /*!< GPA_MFPL PA4 setting for UART0_RXD*/ 2068 #define UART0_RXD_PB12 SYS_GPB_MFPH_PB12MFP_UART0_RXD /*!< GPB_MFPH PB12 setting for UART0_RXD*/ 2069 #define UART0_RXD_PA0 SYS_GPA_MFPL_PA0MFP_UART0_RXD /*!< GPA_MFPL PA0 setting for UART0_RXD*/ 2070 #define UART0_RXD_PF1 SYS_GPF_MFPL_PF1MFP_UART0_RXD /*!< GPF_MFPL PF1 setting for UART0_RXD*/ 2071 #define UART0_RXD_PC11 SYS_GPC_MFPH_PC11MFP_UART0_RXD /*!< GPC_MFPH PC11 setting for UART0_RXD*/ 2072 #define UART0_RXD_PB8 SYS_GPB_MFPH_PB8MFP_UART0_RXD /*!< GPB_MFPH PB8 setting for UART0_RXD*/ 2073 #define UART0_RXD_PH11 SYS_GPH_MFPH_PH11MFP_UART0_RXD /*!< GPH_MFPH PH11 setting for UART0_RXD*/ 2074 #define UART0_RXD_PA6 SYS_GPA_MFPL_PA6MFP_UART0_RXD /*!< GPA_MFPL PA6 setting for UART0_RXD*/ 2075 #define UART0_RXD_PF2 SYS_GPF_MFPL_PF2MFP_UART0_RXD /*!< GPF_MFPL PF2 setting for UART0_RXD*/ 2076 #define UART0_TXD_PA5 SYS_GPA_MFPL_PA5MFP_UART0_TXD /*!< GPA_MFPL PA5 setting for UART0_TXD*/ 2077 #define UART0_TXD_PA14 SYS_GPA_MFPH_PA14MFP_UART0_TXD /*!< GPA_MFPH PA14 setting for UART0_TXD*/ 2078 #define UART0_TXD_PF3 SYS_GPF_MFPL_PF3MFP_UART0_TXD /*!< GPF_MFPL PF3 setting for UART0_TXD*/ 2079 #define UART0_TXD_PA1 SYS_GPA_MFPL_PA1MFP_UART0_TXD /*!< GPA_MFPL PA1 setting for UART0_TXD*/ 2080 #define UART0_TXD_PH10 SYS_GPH_MFPH_PH10MFP_UART0_TXD /*!< GPH_MFPH PH10 setting for UART0_TXD*/ 2081 #define UART0_TXD_PD3 SYS_GPD_MFPL_PD3MFP_UART0_TXD /*!< GPD_MFPL PD3 setting for UART0_TXD*/ 2082 #define UART0_TXD_PB9 SYS_GPB_MFPH_PB9MFP_UART0_TXD /*!< GPB_MFPH PB9 setting for UART0_TXD*/ 2083 #define UART0_TXD_PB13 SYS_GPB_MFPH_PB13MFP_UART0_TXD /*!< GPB_MFPH PB13 setting for UART0_TXD*/ 2084 #define UART0_TXD_PA7 SYS_GPA_MFPL_PA7MFP_UART0_TXD /*!< GPA_MFPL PA7 setting for UART0_TXD*/ 2085 #define UART0_TXD_PF0 SYS_GPF_MFPL_PF0MFP_UART0_TXD /*!< GPF_MFPL PF0 setting for UART0_TXD*/ 2086 #define UART0_TXD_PC12 SYS_GPC_MFPH_PC12MFP_UART0_TXD /*!< GPC_MFPH PC12 setting for UART0_TXD*/ 2087 #define UART0_nCTS_PB15 SYS_GPB_MFPH_PB15MFP_UART0_nCTS /*!< GPB_MFPH PB15 setting for UART0_nCTS*/ 2088 #define UART0_nCTS_PB11 SYS_GPB_MFPH_PB11MFP_UART0_nCTS /*!< GPB_MFPH PB11 setting for UART0_nCTS*/ 2089 #define UART0_nCTS_PC7 SYS_GPC_MFPL_PC7MFP_UART0_nCTS /*!< GPC_MFPL PC7 setting for UART0_nCTS*/ 2090 #define UART0_nCTS_PA5 SYS_GPA_MFPL_PA5MFP_UART0_nCTS /*!< GPA_MFPL PA5 setting for UART0_nCTS*/ 2091 #define UART0_nRTS_PC6 SYS_GPC_MFPL_PC6MFP_UART0_nRTS /*!< GPC_MFPL PC6 setting for UART0_nRTS*/ 2092 #define UART0_nRTS_PB14 SYS_GPB_MFPH_PB14MFP_UART0_nRTS /*!< GPB_MFPH PB14 setting for UART0_nRTS*/ 2093 #define UART0_nRTS_PB10 SYS_GPB_MFPH_PB10MFP_UART0_nRTS /*!< GPB_MFPH PB10 setting for UART0_nRTS*/ 2094 #define UART0_nRTS_PA4 SYS_GPA_MFPL_PA4MFP_UART0_nRTS /*!< GPA_MFPL PA4 setting for UART0_nRTS*/ 2095 #define UART1_RXD_PA8 SYS_GPA_MFPH_PA8MFP_UART1_RXD /*!< GPA_MFPH PA8 setting for UART1_RXD*/ 2096 #define UART1_RXD_PB6 SYS_GPB_MFPL_PB6MFP_UART1_RXD /*!< GPB_MFPL PB6 setting for UART1_RXD*/ 2097 #define UART1_RXD_PC8 SYS_GPC_MFPH_PC8MFP_UART1_RXD /*!< GPC_MFPH PC8 setting for UART1_RXD*/ 2098 #define UART1_RXD_PA2 SYS_GPA_MFPL_PA2MFP_UART1_RXD /*!< GPA_MFPL PA2 setting for UART1_RXD*/ 2099 #define UART1_RXD_PH9 SYS_GPH_MFPH_PH9MFP_UART1_RXD /*!< GPH_MFPH PH9 setting for UART1_RXD*/ 2100 #define UART1_RXD_PD10 SYS_GPD_MFPH_PD10MFP_UART1_RXD /*!< GPD_MFPH PD10 setting for UART1_RXD*/ 2101 #define UART1_RXD_PB2 SYS_GPB_MFPL_PB2MFP_UART1_RXD /*!< GPB_MFPL PB2 setting for UART1_RXD*/ 2102 #define UART1_RXD_PD6 SYS_GPD_MFPL_PD6MFP_UART1_RXD /*!< GPD_MFPL PD6 setting for UART1_RXD*/ 2103 #define UART1_RXD_PF1 SYS_GPF_MFPL_PF1MFP_UART1_RXD /*!< GPF_MFPL PF1 setting for UART1_RXD*/ 2104 #define UART1_TXD_PA9 SYS_GPA_MFPH_PA9MFP_UART1_TXD /*!< GPA_MFPH PA9 setting for UART1_TXD*/ 2105 #define UART1_TXD_PD11 SYS_GPD_MFPH_PD11MFP_UART1_TXD /*!< GPD_MFPH PD11 setting for UART1_TXD*/ 2106 #define UART1_TXD_PF0 SYS_GPF_MFPL_PF0MFP_UART1_TXD /*!< GPF_MFPL PF0 setting for UART1_TXD*/ 2107 #define UART1_TXD_PB3 SYS_GPB_MFPL_PB3MFP_UART1_TXD /*!< GPB_MFPL PB3 setting for UART1_TXD*/ 2108 #define UART1_TXD_PH8 SYS_GPH_MFPH_PH8MFP_UART1_TXD /*!< GPH_MFPH PH8 setting for UART1_TXD*/ 2109 #define UART1_TXD_PA3 SYS_GPA_MFPL_PA3MFP_UART1_TXD /*!< GPA_MFPL PA3 setting for UART1_TXD*/ 2110 #define UART1_TXD_PD7 SYS_GPD_MFPL_PD7MFP_UART1_TXD /*!< GPD_MFPL PD7 setting for UART1_TXD*/ 2111 #define UART1_TXD_PE13 SYS_GPE_MFPH_PE13MFP_UART1_TXD /*!< GPE_MFPH PE13 setting for UART1_TXD*/ 2112 #define UART1_TXD_PB7 SYS_GPB_MFPL_PB7MFP_UART1_TXD /*!< GPB_MFPL PB7 setting for UART1_TXD*/ 2113 #define UART1_nCTS_PB9 SYS_GPB_MFPH_PB9MFP_UART1_nCTS /*!< GPB_MFPH PB9 setting for UART1_nCTS*/ 2114 #define UART1_nCTS_PE11 SYS_GPE_MFPH_PE11MFP_UART1_nCTS /*!< GPE_MFPH PE11 setting for UART1_nCTS*/ 2115 #define UART1_nCTS_PA1 SYS_GPA_MFPL_PA1MFP_UART1_nCTS /*!< GPA_MFPL PA1 setting for UART1_nCTS*/ 2116 #define UART1_nRTS_PB8 SYS_GPB_MFPH_PB8MFP_UART1_nRTS /*!< GPB_MFPH PB8 setting for UART1_nRTS*/ 2117 #define UART1_nRTS_PA0 SYS_GPA_MFPL_PA0MFP_UART1_nRTS /*!< GPA_MFPL PA0 setting for UART1_nRTS*/ 2118 #define UART1_nRTS_PE12 SYS_GPE_MFPH_PE12MFP_UART1_nRTS /*!< GPE_MFPH PE12 setting for UART1_nRTS*/ 2119 #define UART2_RXD_PE15 SYS_GPE_MFPH_PE15MFP_UART2_RXD /*!< GPE_MFPH PE15 setting for UART2_RXD*/ 2120 #define UART2_RXD_PC4 SYS_GPC_MFPL_PC4MFP_UART2_RXD /*!< GPC_MFPL PC4 setting for UART2_RXD*/ 2121 #define UART2_RXD_PD12 SYS_GPD_MFPH_PD12MFP_UART2_RXD /*!< GPD_MFPH PD12 setting for UART2_RXD*/ 2122 #define UART2_RXD_PF5 SYS_GPF_MFPL_PF5MFP_UART2_RXD /*!< GPF_MFPL PF5 setting for UART2_RXD*/ 2123 #define UART2_RXD_PE9 SYS_GPE_MFPH_PE9MFP_UART2_RXD /*!< GPE_MFPH PE9 setting for UART2_RXD*/ 2124 #define UART2_RXD_PC0 SYS_GPC_MFPL_PC0MFP_UART2_RXD /*!< GPC_MFPL PC0 setting for UART2_RXD*/ 2125 #define UART2_RXD_PB0 SYS_GPB_MFPL_PB0MFP_UART2_RXD /*!< GPB_MFPL PB0 setting for UART2_RXD*/ 2126 #define UART2_RXD_PB4 SYS_GPB_MFPL_PB4MFP_UART2_RXD /*!< GPB_MFPL PB4 setting for UART2_RXD*/ 2127 #define UART2_TXD_PF4 SYS_GPF_MFPL_PF4MFP_UART2_TXD /*!< GPF_MFPL PF4 setting for UART2_TXD*/ 2128 #define UART2_TXD_PC1 SYS_GPC_MFPL_PC1MFP_UART2_TXD /*!< GPC_MFPL PC1 setting for UART2_TXD*/ 2129 #define UART2_TXD_PB5 SYS_GPB_MFPL_PB5MFP_UART2_TXD /*!< GPB_MFPL PB5 setting for UART2_TXD*/ 2130 #define UART2_TXD_PE14 SYS_GPE_MFPH_PE14MFP_UART2_TXD /*!< GPE_MFPH PE14 setting for UART2_TXD*/ 2131 #define UART2_TXD_PC13 SYS_GPC_MFPH_PC13MFP_UART2_TXD /*!< GPC_MFPH PC13 setting for UART2_TXD*/ 2132 #define UART2_TXD_PC5 SYS_GPC_MFPL_PC5MFP_UART2_TXD /*!< GPC_MFPL PC5 setting for UART2_TXD*/ 2133 #define UART2_TXD_PE8 SYS_GPE_MFPH_PE8MFP_UART2_TXD /*!< GPE_MFPH PE8 setting for UART2_TXD*/ 2134 #define UART2_TXD_PB1 SYS_GPB_MFPL_PB1MFP_UART2_TXD /*!< GPB_MFPL PB1 setting for UART2_TXD*/ 2135 #define UART2_nCTS_PF5 SYS_GPF_MFPL_PF5MFP_UART2_nCTS /*!< GPF_MFPL PF5 setting for UART2_nCTS*/ 2136 #define UART2_nCTS_PD9 SYS_GPD_MFPH_PD9MFP_UART2_nCTS /*!< GPD_MFPH PD9 setting for UART2_nCTS*/ 2137 #define UART2_nCTS_PC2 SYS_GPC_MFPL_PC2MFP_UART2_nCTS /*!< GPC_MFPL PC2 setting for UART2_nCTS*/ 2138 #define UART2_nRTS_PC3 SYS_GPC_MFPL_PC3MFP_UART2_nRTS /*!< GPC_MFPL PC3 setting for UART2_nRTS*/ 2139 #define UART2_nRTS_PD8 SYS_GPD_MFPH_PD8MFP_UART2_nRTS /*!< GPD_MFPH PD8 setting for UART2_nRTS*/ 2140 #define UART2_nRTS_PF4 SYS_GPF_MFPL_PF4MFP_UART2_nRTS /*!< GPF_MFPL PF4 setting for UART2_nRTS*/ 2141 #define UART3_RXD_PD0 SYS_GPD_MFPL_PD0MFP_UART3_RXD /*!< GPD_MFPL PD0 setting for UART3_RXD*/ 2142 #define UART3_RXD_PC9 SYS_GPC_MFPH_PC9MFP_UART3_RXD /*!< GPC_MFPH PC9 setting for UART3_RXD*/ 2143 #define UART3_RXD_PE0 SYS_GPE_MFPL_PE0MFP_UART3_RXD /*!< GPE_MFPL PE0 setting for UART3_RXD*/ 2144 #define UART3_RXD_PC2 SYS_GPC_MFPL_PC2MFP_UART3_RXD /*!< GPC_MFPL PC2 setting for UART3_RXD*/ 2145 #define UART3_RXD_PB14 SYS_GPB_MFPH_PB14MFP_UART3_RXD /*!< GPB_MFPH PB14 setting for UART3_RXD*/ 2146 #define UART3_RXD_PE11 SYS_GPE_MFPH_PE11MFP_UART3_RXD /*!< GPE_MFPH PE11 setting for UART3_RXD*/ 2147 #define UART3_TXD_PC10 SYS_GPC_MFPH_PC10MFP_UART3_TXD /*!< GPC_MFPH PC10 setting for UART3_TXD*/ 2148 #define UART3_TXD_PB15 SYS_GPB_MFPH_PB15MFP_UART3_TXD /*!< GPB_MFPH PB15 setting for UART3_TXD*/ 2149 #define UART3_TXD_PE10 SYS_GPE_MFPH_PE10MFP_UART3_TXD /*!< GPE_MFPH PE10 setting for UART3_TXD*/ 2150 #define UART3_TXD_PC3 SYS_GPC_MFPL_PC3MFP_UART3_TXD /*!< GPC_MFPL PC3 setting for UART3_TXD*/ 2151 #define UART3_TXD_PD1 SYS_GPD_MFPL_PD1MFP_UART3_TXD /*!< GPD_MFPL PD1 setting for UART3_TXD*/ 2152 #define UART3_TXD_PE1 SYS_GPE_MFPL_PE1MFP_UART3_TXD /*!< GPE_MFPL PE1 setting for UART3_TXD*/ 2153 #define UART3_nCTS_PB12 SYS_GPB_MFPH_PB12MFP_UART3_nCTS /*!< GPB_MFPH PB12 setting for UART3_nCTS*/ 2154 #define UART3_nCTS_PH9 SYS_GPH_MFPH_PH9MFP_UART3_nCTS /*!< GPH_MFPH PH9 setting for UART3_nCTS*/ 2155 #define UART3_nCTS_PD2 SYS_GPD_MFPL_PD2MFP_UART3_nCTS /*!< GPD_MFPL PD2 setting for UART3_nCTS*/ 2156 #define UART3_nRTS_PH8 SYS_GPH_MFPH_PH8MFP_UART3_nRTS /*!< GPH_MFPH PH8 setting for UART3_nRTS*/ 2157 #define UART3_nRTS_PD3 SYS_GPD_MFPL_PD3MFP_UART3_nRTS /*!< GPD_MFPL PD3 setting for UART3_nRTS*/ 2158 #define UART3_nRTS_PB13 SYS_GPB_MFPH_PB13MFP_UART3_nRTS /*!< GPB_MFPH PB13 setting for UART3_nRTS*/ 2159 #define UART4_RXD_PA2 SYS_GPA_MFPL_PA2MFP_UART4_RXD /*!< GPA_MFPL PA2 setting for UART4_RXD*/ 2160 #define UART4_RXD_PA13 SYS_GPA_MFPH_PA13MFP_UART4_RXD /*!< GPA_MFPH PA13 setting for UART4_RXD*/ 2161 #define UART4_RXD_PC4 SYS_GPC_MFPL_PC4MFP_UART4_RXD /*!< GPC_MFPL PC4 setting for UART4_RXD*/ 2162 #define UART4_RXD_PH11 SYS_GPH_MFPH_PH11MFP_UART4_RXD /*!< GPH_MFPH PH11 setting for UART4_RXD*/ 2163 #define UART4_RXD_PF6 SYS_GPF_MFPL_PF6MFP_UART4_RXD /*!< GPF_MFPL PF6 setting for UART4_RXD*/ 2164 #define UART4_RXD_PB10 SYS_GPB_MFPH_PB10MFP_UART4_RXD /*!< GPB_MFPH PB10 setting for UART4_RXD*/ 2165 #define UART4_RXD_PC6 SYS_GPC_MFPL_PC6MFP_UART4_RXD /*!< GPC_MFPL PC6 setting for UART4_RXD*/ 2166 #define UART4_TXD_PA3 SYS_GPA_MFPL_PA3MFP_UART4_TXD /*!< GPA_MFPL PA3 setting for UART4_TXD*/ 2167 #define UART4_TXD_PC5 SYS_GPC_MFPL_PC5MFP_UART4_TXD /*!< GPC_MFPL PC5 setting for UART4_TXD*/ 2168 #define UART4_TXD_PC7 SYS_GPC_MFPL_PC7MFP_UART4_TXD /*!< GPC_MFPL PC7 setting for UART4_TXD*/ 2169 #define UART4_TXD_PA12 SYS_GPA_MFPH_PA12MFP_UART4_TXD /*!< GPA_MFPH PA12 setting for UART4_TXD*/ 2170 #define UART4_TXD_PF7 SYS_GPF_MFPL_PF7MFP_UART4_TXD /*!< GPF_MFPL PF7 setting for UART4_TXD*/ 2171 #define UART4_TXD_PH10 SYS_GPH_MFPH_PH10MFP_UART4_TXD /*!< GPH_MFPH PH10 setting for UART4_TXD*/ 2172 #define UART4_TXD_PB11 SYS_GPB_MFPH_PB11MFP_UART4_TXD /*!< GPB_MFPH PB11 setting for UART4_TXD*/ 2173 #define UART4_nCTS_PC8 SYS_GPC_MFPH_PC8MFP_UART4_nCTS /*!< GPC_MFPH PC8 setting for UART4_nCTS*/ 2174 #define UART4_nCTS_PE1 SYS_GPE_MFPL_PE1MFP_UART4_nCTS /*!< GPE_MFPL PE1 setting for UART4_nCTS*/ 2175 #define UART4_nRTS_PE0 SYS_GPE_MFPL_PE0MFP_UART4_nRTS /*!< GPE_MFPL PE0 setting for UART4_nRTS*/ 2176 #define UART4_nRTS_PE13 SYS_GPE_MFPH_PE13MFP_UART4_nRTS /*!< GPE_MFPH PE13 setting for UART4_nRTS*/ 2177 #define UART5_RXD_PB4 SYS_GPB_MFPL_PB4MFP_UART5_RXD /*!< GPB_MFPL PB4 setting for UART5_RXD*/ 2178 #define UART5_RXD_PF10 SYS_GPF_MFPH_PF10MFP_UART5_RXD /*!< GPF_MFPH PF10 setting for UART5_RXD*/ 2179 #define UART5_RXD_PE6 SYS_GPE_MFPL_PE6MFP_UART5_RXD /*!< GPE_MFPL PE6 setting for UART5_RXD*/ 2180 #define UART5_RXD_PA4 SYS_GPA_MFPL_PA4MFP_UART5_RXD /*!< GPA_MFPL PA4 setting for UART5_RXD*/ 2181 #define UART5_TXD_PF11 SYS_GPF_MFPH_PF11MFP_UART5_TXD /*!< GPF_MFPH PF11 setting for UART5_TXD*/ 2182 #define UART5_TXD_PB5 SYS_GPB_MFPL_PB5MFP_UART5_TXD /*!< GPB_MFPL PB5 setting for UART5_TXD*/ 2183 #define UART5_TXD_PE7 SYS_GPE_MFPL_PE7MFP_UART5_TXD /*!< GPE_MFPL PE7 setting for UART5_TXD*/ 2184 #define UART5_TXD_PA5 SYS_GPA_MFPL_PA5MFP_UART5_TXD /*!< GPA_MFPL PA5 setting for UART5_TXD*/ 2185 #define UART5_nCTS_PB2 SYS_GPB_MFPL_PB2MFP_UART5_nCTS /*!< GPB_MFPL PB2 setting for UART5_nCTS*/ 2186 #define UART5_nCTS_PF8 SYS_GPF_MFPH_PF8MFP_UART5_nCTS /*!< GPF_MFPH PF8 setting for UART5_nCTS*/ 2187 #define UART5_nRTS_PF9 SYS_GPF_MFPH_PF9MFP_UART5_nRTS /*!< GPF_MFPH PF9 setting for UART5_nRTS*/ 2188 #define UART5_nRTS_PB3 SYS_GPB_MFPL_PB3MFP_UART5_nRTS /*!< GPB_MFPL PB3 setting for UART5_nRTS*/ 2189 #define USB_D_P_PA14 SYS_GPA_MFPH_PA14MFP_USB_D_P /*!< GPA_MFPH PA14 setting for USB_D_P*/ 2190 #define USB_D_N_PA13 SYS_GPA_MFPH_PA13MFP_USB_D_N /*!< GPA_MFPH PA13 setting for USB_D_N*/ 2191 #define USB_OTG_ID_PA15 SYS_GPA_MFPH_PA15MFP_USB_OTG_ID /*!< GPA_MFPH PA15 setting for USB_OTG_ID*/ 2192 #define USB_VBUS_PA12 SYS_GPA_MFPH_PA12MFP_USB_VBUS /*!< GPA_MFPH PA12 setting for USB_VBUS*/ 2193 #define USB_VBUS_EN_PB15 SYS_GPB_MFPH_PB15MFP_USB_VBUS_EN /*!< GPB_MFPH PB15 setting for USB_VBUS_EN*/ 2194 #define USB_VBUS_EN_PB6 SYS_GPB_MFPL_PB6MFP_USB_VBUS_EN /*!< GPB_MFPL PB6 setting for USB_VBUS_EN*/ 2195 #define USB_VBUS_ST_PB14 SYS_GPB_MFPH_PB14MFP_USB_VBUS_ST /*!< GPB_MFPH PB14 setting for USB_VBUS_ST*/ 2196 #define USB_VBUS_ST_PB7 SYS_GPB_MFPL_PB7MFP_USB_VBUS_ST /*!< GPB_MFPL PB7 setting for USB_VBUS_ST*/ 2197 #define USB_VBUS_ST_PD4 SYS_GPD_MFPL_PD4MFP_USB_VBUS_ST /*!< GPD_MFPL PD4 setting for USB_VBUS_ST*/ 2198 #define USCI0_CLK_PA11 SYS_GPA_MFPH_PA11MFP_USCI0_CLK /*!< GPA_MFPH PA11 setting for USCI0_CLK*/ 2199 #define USCI0_CLK_PD0 SYS_GPD_MFPL_PD0MFP_USCI0_CLK /*!< GPD_MFPL PD0 setting for USCI0_CLK*/ 2200 #define USCI0_CLK_PB12 SYS_GPB_MFPH_PB12MFP_USCI0_CLK /*!< GPB_MFPH PB12 setting for USCI0_CLK*/ 2201 #define USCI0_CLK_PE2 SYS_GPE_MFPL_PE2MFP_USCI0_CLK /*!< GPE_MFPL PE2 setting for USCI0_CLK*/ 2202 #define USCI0_CTL0_PC13 SYS_GPC_MFPH_PC13MFP_USCI0_CTL0 /*!< GPC_MFPH PC13 setting for USCI0_CTL0*/ 2203 #define USCI0_CTL0_PD14 SYS_GPD_MFPH_PD14MFP_USCI0_CTL0 /*!< GPD_MFPH PD14 setting for USCI0_CTL0*/ 2204 #define USCI0_CTL0_PE6 SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 /*!< GPE_MFPL PE6 setting for USCI0_CTL0*/ 2205 #define USCI0_CTL0_PD4 SYS_GPD_MFPL_PD4MFP_USCI0_CTL0 /*!< GPD_MFPL PD4 setting for USCI0_CTL0*/ 2206 #define USCI0_CTL1_PD3 SYS_GPD_MFPL_PD3MFP_USCI0_CTL1 /*!< GPD_MFPL PD3 setting for USCI0_CTL1*/ 2207 #define USCI0_CTL1_PA8 SYS_GPA_MFPH_PA8MFP_USCI0_CTL1 /*!< GPA_MFPH PA8 setting for USCI0_CTL1*/ 2208 #define USCI0_CTL1_PE5 SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 /*!< GPE_MFPL PE5 setting for USCI0_CTL1*/ 2209 #define USCI0_CTL1_PB15 SYS_GPB_MFPH_PB15MFP_USCI0_CTL1 /*!< GPB_MFPH PB15 setting for USCI0_CTL1*/ 2210 #define USCI0_DAT0_PB13 SYS_GPB_MFPH_PB13MFP_USCI0_DAT0 /*!< GPB_MFPH PB13 setting for USCI0_DAT0*/ 2211 #define USCI0_DAT0_PE3 SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 /*!< GPE_MFPL PE3 setting for USCI0_DAT0*/ 2212 #define USCI0_DAT0_PA10 SYS_GPA_MFPH_PA10MFP_USCI0_DAT0 /*!< GPA_MFPH PA10 setting for USCI0_DAT0*/ 2213 #define USCI0_DAT0_PD1 SYS_GPD_MFPL_PD1MFP_USCI0_DAT0 /*!< GPD_MFPL PD1 setting for USCI0_DAT0*/ 2214 #define USCI0_DAT1_PA9 SYS_GPA_MFPH_PA9MFP_USCI0_DAT1 /*!< GPA_MFPH PA9 setting for USCI0_DAT1*/ 2215 #define USCI0_DAT1_PE4 SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 /*!< GPE_MFPL PE4 setting for USCI0_DAT1*/ 2216 #define USCI0_DAT1_PB14 SYS_GPB_MFPH_PB14MFP_USCI0_DAT1 /*!< GPB_MFPH PB14 setting for USCI0_DAT1*/ 2217 #define USCI0_DAT1_PD2 SYS_GPD_MFPL_PD2MFP_USCI0_DAT1 /*!< GPD_MFPL PD2 setting for USCI0_DAT1*/ 2218 #define USCI1_CLK_PE12 SYS_GPE_MFPH_PE12MFP_USCI1_CLK /*!< GPE_MFPH PE12 setting for USCI1_CLK*/ 2219 #define USCI1_CLK_PB1 SYS_GPB_MFPL_PB1MFP_USCI1_CLK /*!< GPB_MFPL PB1 setting for USCI1_CLK*/ 2220 #define USCI1_CLK_PD7 SYS_GPD_MFPL_PD7MFP_USCI1_CLK /*!< GPD_MFPL PD7 setting for USCI1_CLK*/ 2221 #define USCI1_CLK_PB8 SYS_GPB_MFPH_PB8MFP_USCI1_CLK /*!< GPB_MFPH PB8 setting for USCI1_CLK*/ 2222 #define USCI1_CTL0_PE9 SYS_GPE_MFPH_PE9MFP_USCI1_CTL0 /*!< GPE_MFPH PE9 setting for USCI1_CTL0*/ 2223 #define USCI1_CTL0_PB5 SYS_GPB_MFPL_PB5MFP_USCI1_CTL0 /*!< GPB_MFPL PB5 setting for USCI1_CTL0*/ 2224 #define USCI1_CTL0_PD3 SYS_GPD_MFPL_PD3MFP_USCI1_CTL0 /*!< GPD_MFPL PD3 setting for USCI1_CTL0*/ 2225 #define USCI1_CTL0_PB10 SYS_GPB_MFPH_PB10MFP_USCI1_CTL0 /*!< GPB_MFPH PB10 setting for USCI1_CTL0*/ 2226 #define USCI1_CTL1_PB4 SYS_GPB_MFPL_PB4MFP_USCI1_CTL1 /*!< GPB_MFPL PB4 setting for USCI1_CTL1*/ 2227 #define USCI1_CTL1_PD4 SYS_GPD_MFPL_PD4MFP_USCI1_CTL1 /*!< GPD_MFPL PD4 setting for USCI1_CTL1*/ 2228 #define USCI1_CTL1_PE8 SYS_GPE_MFPH_PE8MFP_USCI1_CTL1 /*!< GPE_MFPH PE8 setting for USCI1_CTL1*/ 2229 #define USCI1_CTL1_PB9 SYS_GPB_MFPH_PB9MFP_USCI1_CTL1 /*!< GPB_MFPH PB9 setting for USCI1_CTL1*/ 2230 #define USCI1_DAT0_PB7 SYS_GPB_MFPL_PB7MFP_USCI1_DAT0 /*!< GPB_MFPL PB7 setting for USCI1_DAT0*/ 2231 #define USCI1_DAT0_PE10 SYS_GPE_MFPH_PE10MFP_USCI1_DAT0 /*!< GPE_MFPH PE10 setting for USCI1_DAT0*/ 2232 #define USCI1_DAT0_PB2 SYS_GPB_MFPL_PB2MFP_USCI1_DAT0 /*!< GPB_MFPL PB2 setting for USCI1_DAT0*/ 2233 #define USCI1_DAT0_PD5 SYS_GPD_MFPL_PD5MFP_USCI1_DAT0 /*!< GPD_MFPL PD5 setting for USCI1_DAT0*/ 2234 #define USCI1_DAT1_PD6 SYS_GPD_MFPL_PD6MFP_USCI1_DAT1 /*!< GPD_MFPL PD6 setting for USCI1_DAT1*/ 2235 #define USCI1_DAT1_PB6 SYS_GPB_MFPL_PB6MFP_USCI1_DAT1 /*!< GPB_MFPL PB6 setting for USCI1_DAT1*/ 2236 #define USCI1_DAT1_PE11 SYS_GPE_MFPH_PE11MFP_USCI1_DAT1 /*!< GPE_MFPH PE11 setting for USCI1_DAT1*/ 2237 #define USCI1_DAT1_PB3 SYS_GPB_MFPL_PB3MFP_USCI1_DAT1 /*!< GPB_MFPL PB3 setting for USCI1_DAT1*/ 2238 #define X32_IN_PF5 SYS_GPF_MFPL_PF5MFP_X32_IN /*!< GPF_MFPL PF5 setting for X32_IN*/ 2239 #define X32_OUT_PF4 SYS_GPF_MFPL_PF4MFP_X32_OUT /*!< GPF_MFPL PF4 setting for X32_OUT*/ 2240 #define XT1_IN_PF3 SYS_GPF_MFPL_PF3MFP_XT1_IN /*!< GPF_MFPL PF3 setting for XT1_IN*/ 2241 #define XT1_OUT_PF2 SYS_GPF_MFPL_PF2MFP_XT1_OUT /*!< GPF_MFPL PF2 setting for XT1_OUT*/ 2242 2243 2244 /*---------------------------------------------------------------------------------------------------------*/ 2245 /* Multi-Function setting mask constant definitions abbreviation. */ 2246 /*---------------------------------------------------------------------------------------------------------*/ 2247 2248 2249 #define ACMP0_N_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! ACMP0_N PB3 MFP Mask */ 2250 #define ACMP0_O_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! ACMP0_O PB7 MFP Mask */ 2251 #define ACMP0_O_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! ACMP0_O PC1 MFP Mask */ 2252 #define ACMP0_O_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! ACMP0_O PC12 MFP Mask */ 2253 #define ACMP0_P0_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! ACMP0_P0 PA11 MFP Mask */ 2254 #define ACMP0_P1_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! ACMP0_P1 PB2 MFP Mask */ 2255 #define ACMP0_P2_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! ACMP0_P2 PB12 MFP Mask */ 2256 #define ACMP0_P3_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! ACMP0_P3 PB13 MFP Mask */ 2257 #define ACMP0_WLAT_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! ACMP0_WLAT PA7 MFP Mask */ 2258 #define ACMP1_N_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! ACMP1_N PB5 MFP Mask */ 2259 #define ACMP1_O_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! ACMP1_O PB6 MFP Mask */ 2260 #define ACMP1_O_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! ACMP1_O PC11 MFP Mask */ 2261 #define ACMP1_O_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! ACMP1_O PC0 MFP Mask */ 2262 #define ACMP1_P0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! ACMP1_P0 PA10 MFP Mask */ 2263 #define ACMP1_P1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! ACMP1_P1 PB4 MFP Mask */ 2264 #define ACMP1_P2_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! ACMP1_P2 PB12 MFP Mask */ 2265 #define ACMP1_P3_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! ACMP1_P3 PB13 MFP Mask */ 2266 #define ACMP1_WLAT_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! ACMP1_WLAT PA6 MFP Mask */ 2267 #define BPWM0_CH0_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! BPWM0_CH0 PA0 MFP Mask */ 2268 #define BPWM0_CH0_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! BPWM0_CH0 PA11 MFP Mask */ 2269 #define BPWM0_CH0_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! BPWM0_CH0 PE2 MFP Mask */ 2270 #define BPWM0_CH0_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! BPWM0_CH0 PG14 MFP Mask */ 2271 #define BPWM0_CH1_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! BPWM0_CH1 PA1 MFP Mask */ 2272 #define BPWM0_CH1_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! BPWM0_CH1 PE3 MFP Mask */ 2273 #define BPWM0_CH1_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! BPWM0_CH1 PG13 MFP Mask */ 2274 #define BPWM0_CH1_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! BPWM0_CH1 PA10 MFP Mask */ 2275 #define BPWM0_CH2_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! BPWM0_CH2 PE4 MFP Mask */ 2276 #define BPWM0_CH2_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! BPWM0_CH2 PG12 MFP Mask */ 2277 #define BPWM0_CH2_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! BPWM0_CH2 PA2 MFP Mask */ 2278 #define BPWM0_CH2_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! BPWM0_CH2 PA9 MFP Mask */ 2279 #define BPWM0_CH3_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! BPWM0_CH3 PG11 MFP Mask */ 2280 #define BPWM0_CH3_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! BPWM0_CH3 PA3 MFP Mask */ 2281 #define BPWM0_CH3_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! BPWM0_CH3 PA8 MFP Mask */ 2282 #define BPWM0_CH3_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! BPWM0_CH3 PE5 MFP Mask */ 2283 #define BPWM0_CH4_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! BPWM0_CH4 PG10 MFP Mask */ 2284 #define BPWM0_CH4_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! BPWM0_CH4 PA4 MFP Mask */ 2285 #define BPWM0_CH4_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! BPWM0_CH4 PC13 MFP Mask */ 2286 #define BPWM0_CH4_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! BPWM0_CH4 PE6 MFP Mask */ 2287 #define BPWM0_CH4_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! BPWM0_CH4 PF5 MFP Mask */ 2288 #define BPWM0_CH5_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! BPWM0_CH5 PA5 MFP Mask */ 2289 #define BPWM0_CH5_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! BPWM0_CH5 PE7 MFP Mask */ 2290 #define BPWM0_CH5_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! BPWM0_CH5 PF4 MFP Mask */ 2291 #define BPWM0_CH5_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! BPWM0_CH5 PD12 MFP Mask */ 2292 #define BPWM0_CH5_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! BPWM0_CH5 PG9 MFP Mask */ 2293 #define BPWM1_CH0_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! BPWM1_CH0 PB11 MFP Mask */ 2294 #define BPWM1_CH0_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! BPWM1_CH0 PC7 MFP Mask */ 2295 #define BPWM1_CH0_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! BPWM1_CH0 PF0 MFP Mask */ 2296 #define BPWM1_CH0_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! BPWM1_CH0 PF3 MFP Mask */ 2297 #define BPWM1_CH1_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! BPWM1_CH1 PC6 MFP Mask */ 2298 #define BPWM1_CH1_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! BPWM1_CH1 PF1 MFP Mask */ 2299 #define BPWM1_CH1_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! BPWM1_CH1 PF2 MFP Mask */ 2300 #define BPWM1_CH1_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! BPWM1_CH1 PB10 MFP Mask */ 2301 #define BPWM1_CH2_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! BPWM1_CH2 PB9 MFP Mask */ 2302 #define BPWM1_CH2_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! BPWM1_CH2 PA7 MFP Mask */ 2303 #define BPWM1_CH2_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! BPWM1_CH2 PA12 MFP Mask */ 2304 #define BPWM1_CH3_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! BPWM1_CH3 PA6 MFP Mask */ 2305 #define BPWM1_CH3_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! BPWM1_CH3 PA13 MFP Mask */ 2306 #define BPWM1_CH3_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! BPWM1_CH3 PB8 MFP Mask */ 2307 #define BPWM1_CH4_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! BPWM1_CH4 PA14 MFP Mask */ 2308 #define BPWM1_CH4_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! BPWM1_CH4 PC8 MFP Mask */ 2309 #define BPWM1_CH4_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! BPWM1_CH4 PB7 MFP Mask */ 2310 #define BPWM1_CH5_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! BPWM1_CH5 PA15 MFP Mask */ 2311 #define BPWM1_CH5_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! BPWM1_CH5 PB6 MFP Mask */ 2312 #define BPWM1_CH5_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! BPWM1_CH5 PE13 MFP Mask */ 2313 #define CAN0_RXD_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! CAN0_RXD PA13 MFP Mask */ 2314 #define CAN0_RXD_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! CAN0_RXD PD10 MFP Mask */ 2315 #define CAN0_RXD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! CAN0_RXD PA4 MFP Mask */ 2316 #define CAN0_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! CAN0_RXD PC4 MFP Mask */ 2317 #define CAN0_RXD_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! CAN0_RXD PB10 MFP Mask */ 2318 #define CAN0_RXD_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! CAN0_RXD PE15 MFP Mask */ 2319 #define CAN0_TXD_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! CAN0_TXD PD11 MFP Mask */ 2320 #define CAN0_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! CAN0_TXD PC5 MFP Mask */ 2321 #define CAN0_TXD_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! CAN0_TXD PB11 MFP Mask */ 2322 #define CAN0_TXD_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! CAN0_TXD PA12 MFP Mask */ 2323 #define CAN0_TXD_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! CAN0_TXD PE14 MFP Mask */ 2324 #define CAN0_TXD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! CAN0_TXD PA5 MFP Mask */ 2325 #define CLKO_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! CLKO PC13 MFP Mask */ 2326 #define CLKO_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! CLKO PB14 MFP Mask */ 2327 #define CLKO_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! CLKO PD12 MFP Mask */ 2328 #define CLKO_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! CLKO PG15 MFP Mask */ 2329 #define DAC0_OUT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! DAC0_OUT PB12 MFP Mask */ 2330 #define DAC0_OUT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! DAC0_OUT PB12 MFP Mask */ 2331 #define DAC0_ST_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! DAC0_ST PA0 MFP Mask */ 2332 #define DAC0_ST_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! DAC0_ST PA10 MFP Mask */ 2333 #define DAC1_OUT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! DAC1_OUT PB13 MFP Mask */ 2334 #define DAC1_OUT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! DAC1_OUT PB13 MFP Mask */ 2335 #define DAC1_ST_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! DAC1_ST PA1 MFP Mask */ 2336 #define DAC1_ST_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! DAC1_ST PA11 MFP Mask */ 2337 #define EADC0_CH0_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EADC0_CH0 PB0 MFP Mask */ 2338 #define EADC0_CH1_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EADC0_CH1 PB1 MFP Mask */ 2339 #define EADC0_CH10_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EADC0_CH10 PB10 MFP Mask */ 2340 #define EADC0_CH11_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! EADC0_CH11 PB11 MFP Mask */ 2341 #define EADC0_CH12_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EADC0_CH12 PB12 MFP Mask */ 2342 #define EADC0_CH13_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EADC0_CH13 PB13 MFP Mask */ 2343 #define EADC0_CH14_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EADC0_CH14 PB14 MFP Mask */ 2344 #define EADC0_CH15_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EADC0_CH15 PB15 MFP Mask */ 2345 #define EADC0_CH15_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! EADC0_CH15 PD10 MFP Mask */ 2346 #define EADC0_CH2_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EADC0_CH2 PB2 MFP Mask */ 2347 #define EADC0_CH3_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EADC0_CH3 PB3 MFP Mask */ 2348 #define EADC0_CH4_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EADC0_CH4 PB4 MFP Mask */ 2349 #define EADC0_CH5_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EADC0_CH5 PB5 MFP Mask */ 2350 #define EADC0_CH6_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EADC0_CH6 PB6 MFP Mask */ 2351 #define EADC0_CH7_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EADC0_CH7 PB7 MFP Mask */ 2352 #define EADC0_CH8_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! EADC0_CH8 PB8 MFP Mask */ 2353 #define EADC0_CH9_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! EADC0_CH9 PB9 MFP Mask */ 2354 #define EADC0_ST_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! EADC0_ST PF5 MFP Mask */ 2355 #define EADC0_ST_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! EADC0_ST PC13 MFP Mask */ 2356 #define EADC0_ST_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! EADC0_ST PC1 MFP Mask */ 2357 #define EADC0_ST_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! EADC0_ST PD12 MFP Mask */ 2358 #define EADC0_ST_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! EADC0_ST PG15 MFP Mask */ 2359 #define EBI_AD0_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! EBI_AD0 PC0 MFP Mask */ 2360 #define EBI_AD0_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! EBI_AD0 PG9 MFP Mask */ 2361 #define EBI_AD1_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! EBI_AD1 PG10 MFP Mask */ 2362 #define EBI_AD1_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! EBI_AD1 PC1 MFP Mask */ 2363 #define EBI_AD10_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! EBI_AD10 PE1 MFP Mask */ 2364 #define EBI_AD10_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! EBI_AD10 PD3 MFP Mask */ 2365 #define EBI_AD10_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! EBI_AD10 PD13 MFP Mask */ 2366 #define EBI_AD11_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! EBI_AD11 PE0 MFP Mask */ 2367 #define EBI_AD11_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! EBI_AD11 PD2 MFP Mask */ 2368 #define EBI_AD12_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! EBI_AD12 PD1 MFP Mask */ 2369 #define EBI_AD12_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EBI_AD12 PB15 MFP Mask */ 2370 #define EBI_AD12_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! EBI_AD12 PH8 MFP Mask */ 2371 #define EBI_AD13_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! EBI_AD13 PD0 MFP Mask */ 2372 #define EBI_AD13_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EBI_AD13 PB14 MFP Mask */ 2373 #define EBI_AD13_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! EBI_AD13 PH9 MFP Mask */ 2374 #define EBI_AD14_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EBI_AD14 PB13 MFP Mask */ 2375 #define EBI_AD14_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! EBI_AD14 PH10 MFP Mask */ 2376 #define EBI_AD15_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EBI_AD15 PB12 MFP Mask */ 2377 #define EBI_AD15_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! EBI_AD15 PH11 MFP Mask */ 2378 #define EBI_AD2_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! EBI_AD2 PC2 MFP Mask */ 2379 #define EBI_AD2_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! EBI_AD2 PG11 MFP Mask */ 2380 #define EBI_AD3_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! EBI_AD3 PG12 MFP Mask */ 2381 #define EBI_AD3_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! EBI_AD3 PC3 MFP Mask */ 2382 #define EBI_AD4_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! EBI_AD4 PC4 MFP Mask */ 2383 #define EBI_AD4_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! EBI_AD4 PG13 MFP Mask */ 2384 #define EBI_AD5_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! EBI_AD5 PG14 MFP Mask */ 2385 #define EBI_AD5_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! EBI_AD5 PC5 MFP Mask */ 2386 #define EBI_AD6_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! EBI_AD6 PD8 MFP Mask */ 2387 #define EBI_AD6_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! EBI_AD6 PA6 MFP Mask */ 2388 #define EBI_AD7_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! EBI_AD7 PD9 MFP Mask */ 2389 #define EBI_AD7_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! EBI_AD7 PA7 MFP Mask */ 2390 #define EBI_AD8_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! EBI_AD8 PE14 MFP Mask */ 2391 #define EBI_AD8_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! EBI_AD8 PC6 MFP Mask */ 2392 #define EBI_AD9_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! EBI_AD9 PC7 MFP Mask */ 2393 #define EBI_AD9_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! EBI_AD9 PE15 MFP Mask */ 2394 #define EBI_ADR0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EBI_ADR0 PB5 MFP Mask */ 2395 #define EBI_ADR0_PH7_Msk SYS_GPH_MFPL_PH7MFP_Msk /*<! EBI_ADR0 PH7 MFP Mask */ 2396 #define EBI_ADR1_PH6_Msk SYS_GPH_MFPL_PH6MFP_Msk /*<! EBI_ADR1 PH6 MFP Mask */ 2397 #define EBI_ADR1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EBI_ADR1 PB4 MFP Mask */ 2398 #define EBI_ADR10_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! EBI_ADR10 PC13 MFP Mask */ 2399 #define EBI_ADR10_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EBI_ADR10 PE8 MFP Mask */ 2400 #define EBI_ADR11_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EBI_ADR11 PE9 MFP Mask */ 2401 #define EBI_ADR11_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! EBI_ADR11 PG2 MFP Mask */ 2402 #define EBI_ADR12_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EBI_ADR12 PE10 MFP Mask */ 2403 #define EBI_ADR12_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! EBI_ADR12 PG3 MFP Mask */ 2404 #define EBI_ADR13_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EBI_ADR13 PE11 MFP Mask */ 2405 #define EBI_ADR13_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! EBI_ADR13 PG4 MFP Mask */ 2406 #define EBI_ADR14_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! EBI_ADR14 PF11 MFP Mask */ 2407 #define EBI_ADR14_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! EBI_ADR14 PE12 MFP Mask */ 2408 #define EBI_ADR15_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EBI_ADR15 PE13 MFP Mask */ 2409 #define EBI_ADR15_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! EBI_ADR15 PF10 MFP Mask */ 2410 #define EBI_ADR16_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! EBI_ADR16 PC8 MFP Mask */ 2411 #define EBI_ADR16_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! EBI_ADR16 PF9 MFP Mask */ 2412 #define EBI_ADR16_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! EBI_ADR16 PB11 MFP Mask */ 2413 #define EBI_ADR17_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EBI_ADR17 PB10 MFP Mask */ 2414 #define EBI_ADR17_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! EBI_ADR17 PF8 MFP Mask */ 2415 #define EBI_ADR18_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! EBI_ADR18 PF7 MFP Mask */ 2416 #define EBI_ADR18_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! EBI_ADR18 PB9 MFP Mask */ 2417 #define EBI_ADR19_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! EBI_ADR19 PB8 MFP Mask */ 2418 #define EBI_ADR19_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! EBI_ADR19 PF6 MFP Mask */ 2419 #define EBI_ADR2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EBI_ADR2 PB3 MFP Mask */ 2420 #define EBI_ADR2_PH5_Msk SYS_GPH_MFPL_PH5MFP_Msk /*<! EBI_ADR2 PH5 MFP Mask */ 2421 #define EBI_ADR3_PH4_Msk SYS_GPH_MFPL_PH4MFP_Msk /*<! EBI_ADR3 PH4 MFP Mask */ 2422 #define EBI_ADR3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EBI_ADR3 PB2 MFP Mask */ 2423 #define EBI_ADR4_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! EBI_ADR4 PC12 MFP Mask */ 2424 #define EBI_ADR5_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! EBI_ADR5 PC11 MFP Mask */ 2425 #define EBI_ADR6_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! EBI_ADR6 PC10 MFP Mask */ 2426 #define EBI_ADR7_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! EBI_ADR7 PC9 MFP Mask */ 2427 #define EBI_ADR8_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EBI_ADR8 PB1 MFP Mask */ 2428 #define EBI_ADR9_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EBI_ADR9 PB0 MFP Mask */ 2429 #define EBI_ALE_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! EBI_ALE PE2 MFP Mask */ 2430 #define EBI_ALE_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! EBI_ALE PA8 MFP Mask */ 2431 #define EBI_MCLK_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! EBI_MCLK PA9 MFP Mask */ 2432 #define EBI_MCLK_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! EBI_MCLK PE3 MFP Mask */ 2433 #define EBI_nCS0_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! EBI_nCS0 PD12 MFP Mask */ 2434 #define EBI_nCS0_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! EBI_nCS0 PD14 MFP Mask */ 2435 #define EBI_nCS0_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! EBI_nCS0 PF3 MFP Mask */ 2436 #define EBI_nCS0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EBI_nCS0 PB7 MFP Mask */ 2437 #define EBI_nCS0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! EBI_nCS0 PF6 MFP Mask */ 2438 #define EBI_nCS1_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! EBI_nCS1 PF2 MFP Mask */ 2439 #define EBI_nCS1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EBI_nCS1 PB6 MFP Mask */ 2440 #define EBI_nCS1_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! EBI_nCS1 PD11 MFP Mask */ 2441 #define EBI_nCS2_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! EBI_nCS2 PD10 MFP Mask */ 2442 #define EBI_nRD_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! EBI_nRD PE5 MFP Mask */ 2443 #define EBI_nRD_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! EBI_nRD PA11 MFP Mask */ 2444 #define EBI_nWR_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! EBI_nWR PE4 MFP Mask */ 2445 #define EBI_nWR_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! EBI_nWR PA10 MFP Mask */ 2446 #define EBI_nWRH_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EBI_nWRH PB6 MFP Mask */ 2447 #define EBI_nWRL_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EBI_nWRL PB7 MFP Mask */ 2448 #define ECAP0_IC0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! ECAP0_IC0 PE8 MFP Mask */ 2449 #define ECAP0_IC0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! ECAP0_IC0 PA10 MFP Mask */ 2450 #define ECAP0_IC1_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! ECAP0_IC1 PA9 MFP Mask */ 2451 #define ECAP0_IC1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! ECAP0_IC1 PE9 MFP Mask */ 2452 #define ECAP0_IC2_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! ECAP0_IC2 PE10 MFP Mask */ 2453 #define ECAP0_IC2_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! ECAP0_IC2 PA8 MFP Mask */ 2454 #define ECAP1_IC0_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! ECAP1_IC0 PE13 MFP Mask */ 2455 #define ECAP1_IC0_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! ECAP1_IC0 PC10 MFP Mask */ 2456 #define ECAP1_IC1_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! ECAP1_IC1 PC11 MFP Mask */ 2457 #define ECAP1_IC1_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! ECAP1_IC1 PE12 MFP Mask */ 2458 #define ECAP1_IC2_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! ECAP1_IC2 PC12 MFP Mask */ 2459 #define ECAP1_IC2_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! ECAP1_IC2 PE11 MFP Mask */ 2460 #define EPWM0_BRAKE0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EPWM0_BRAKE0 PE8 MFP Mask */ 2461 #define EPWM0_BRAKE0_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM0_BRAKE0 PB1 MFP Mask */ 2462 #define EPWM0_BRAKE1_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EPWM0_BRAKE1 PB14 MFP Mask */ 2463 #define EPWM0_BRAKE1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EPWM0_BRAKE1 PE9 MFP Mask */ 2464 #define EPWM0_BRAKE1_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM0_BRAKE1 PB0 MFP Mask */ 2465 #define EPWM0_CH0_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! EPWM0_CH0 PF5 MFP Mask */ 2466 #define EPWM0_CH0_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! EPWM0_CH0 PA5 MFP Mask */ 2467 #define EPWM0_CH0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! EPWM0_CH0 PB5 MFP Mask */ 2468 #define EPWM0_CH0_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! EPWM0_CH0 PE8 MFP Mask */ 2469 #define EPWM0_CH0_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! EPWM0_CH0 PE7 MFP Mask */ 2470 #define EPWM0_CH1_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! EPWM0_CH1 PA4 MFP Mask */ 2471 #define EPWM0_CH1_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! EPWM0_CH1 PE9 MFP Mask */ 2472 #define EPWM0_CH1_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! EPWM0_CH1 PE6 MFP Mask */ 2473 #define EPWM0_CH1_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! EPWM0_CH1 PF4 MFP Mask */ 2474 #define EPWM0_CH1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! EPWM0_CH1 PB4 MFP Mask */ 2475 #define EPWM0_CH2_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EPWM0_CH2 PE10 MFP Mask */ 2476 #define EPWM0_CH2_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! EPWM0_CH2 PE5 MFP Mask */ 2477 #define EPWM0_CH2_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! EPWM0_CH2 PA3 MFP Mask */ 2478 #define EPWM0_CH2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! EPWM0_CH2 PB3 MFP Mask */ 2479 #define EPWM0_CH3_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! EPWM0_CH3 PA2 MFP Mask */ 2480 #define EPWM0_CH3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! EPWM0_CH3 PB2 MFP Mask */ 2481 #define EPWM0_CH3_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EPWM0_CH3 PE11 MFP Mask */ 2482 #define EPWM0_CH3_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! EPWM0_CH3 PE4 MFP Mask */ 2483 #define EPWM0_CH4_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! EPWM0_CH4 PE3 MFP Mask */ 2484 #define EPWM0_CH4_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! EPWM0_CH4 PD14 MFP Mask */ 2485 #define EPWM0_CH4_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! EPWM0_CH4 PA1 MFP Mask */ 2486 #define EPWM0_CH4_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! EPWM0_CH4 PE12 MFP Mask */ 2487 #define EPWM0_CH4_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM0_CH4 PB1 MFP Mask */ 2488 #define EPWM0_CH5_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! EPWM0_CH5 PA0 MFP Mask */ 2489 #define EPWM0_CH5_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM0_CH5 PB0 MFP Mask */ 2490 #define EPWM0_CH5_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EPWM0_CH5 PE13 MFP Mask */ 2491 #define EPWM0_CH5_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! EPWM0_CH5 PE2 MFP Mask */ 2492 #define EPWM0_CH5_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! EPWM0_CH5 PH11 MFP Mask */ 2493 #define EPWM0_SYNC_IN_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! EPWM0_SYNC_IN PA15 MFP Mask */ 2494 #define EPWM0_SYNC_OUT_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! EPWM0_SYNC_OUT PA11 MFP Mask */ 2495 #define EPWM0_SYNC_OUT_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! EPWM0_SYNC_OUT PF5 MFP Mask */ 2496 #define EPWM1_BRAKE0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EPWM1_BRAKE0 PB7 MFP Mask */ 2497 #define EPWM1_BRAKE0_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! EPWM1_BRAKE0 PE10 MFP Mask */ 2498 #define EPWM1_BRAKE1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EPWM1_BRAKE1 PB6 MFP Mask */ 2499 #define EPWM1_BRAKE1_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! EPWM1_BRAKE1 PA3 MFP Mask */ 2500 #define EPWM1_BRAKE1_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! EPWM1_BRAKE1 PE11 MFP Mask */ 2501 #define EPWM1_CH0_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! EPWM1_CH0 PE13 MFP Mask */ 2502 #define EPWM1_CH0_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! EPWM1_CH0 PC12 MFP Mask */ 2503 #define EPWM1_CH0_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! EPWM1_CH0 PB15 MFP Mask */ 2504 #define EPWM1_CH0_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! EPWM1_CH0 PC5 MFP Mask */ 2505 #define EPWM1_CH1_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! EPWM1_CH1 PC8 MFP Mask */ 2506 #define EPWM1_CH1_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! EPWM1_CH1 PC11 MFP Mask */ 2507 #define EPWM1_CH1_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! EPWM1_CH1 PB14 MFP Mask */ 2508 #define EPWM1_CH1_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! EPWM1_CH1 PC4 MFP Mask */ 2509 #define EPWM1_CH2_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! EPWM1_CH2 PC7 MFP Mask */ 2510 #define EPWM1_CH2_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! EPWM1_CH2 PC3 MFP Mask */ 2511 #define EPWM1_CH2_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! EPWM1_CH2 PC10 MFP Mask */ 2512 #define EPWM1_CH2_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! EPWM1_CH2 PB13 MFP Mask */ 2513 #define EPWM1_CH3_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! EPWM1_CH3 PC6 MFP Mask */ 2514 #define EPWM1_CH3_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! EPWM1_CH3 PC2 MFP Mask */ 2515 #define EPWM1_CH3_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! EPWM1_CH3 PB12 MFP Mask */ 2516 #define EPWM1_CH3_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! EPWM1_CH3 PC9 MFP Mask */ 2517 #define EPWM1_CH4_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! EPWM1_CH4 PC1 MFP Mask */ 2518 #define EPWM1_CH4_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EPWM1_CH4 PB1 MFP Mask */ 2519 #define EPWM1_CH4_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! EPWM1_CH4 PB7 MFP Mask */ 2520 #define EPWM1_CH4_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! EPWM1_CH4 PA7 MFP Mask */ 2521 #define EPWM1_CH5_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! EPWM1_CH5 PB6 MFP Mask */ 2522 #define EPWM1_CH5_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! EPWM1_CH5 PC0 MFP Mask */ 2523 #define EPWM1_CH5_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EPWM1_CH5 PB0 MFP Mask */ 2524 #define EPWM1_CH5_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! EPWM1_CH5 PA6 MFP Mask */ 2525 #define I2C0_SCL_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! I2C0_SCL PE13 MFP Mask */ 2526 #define I2C0_SCL_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! I2C0_SCL PB9 MFP Mask */ 2527 #define I2C0_SCL_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! I2C0_SCL PD7 MFP Mask */ 2528 #define I2C0_SCL_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! I2C0_SCL PA5 MFP Mask */ 2529 #define I2C0_SCL_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! I2C0_SCL PB5 MFP Mask */ 2530 #define I2C0_SCL_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! I2C0_SCL PC1 MFP Mask */ 2531 #define I2C0_SCL_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! I2C0_SCL PC12 MFP Mask */ 2532 #define I2C0_SCL_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! I2C0_SCL PF3 MFP Mask */ 2533 #define I2C0_SDA_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! I2C0_SDA PB4 MFP Mask */ 2534 #define I2C0_SDA_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! I2C0_SDA PD6 MFP Mask */ 2535 #define I2C0_SDA_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! I2C0_SDA PB8 MFP Mask */ 2536 #define I2C0_SDA_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! I2C0_SDA PC11 MFP Mask */ 2537 #define I2C0_SDA_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! I2C0_SDA PF2 MFP Mask */ 2538 #define I2C0_SDA_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! I2C0_SDA PC0 MFP Mask */ 2539 #define I2C0_SDA_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! I2C0_SDA PC8 MFP Mask */ 2540 #define I2C0_SDA_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! I2C0_SDA PA4 MFP Mask */ 2541 #define I2C0_SMBAL_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! I2C0_SMBAL PA3 MFP Mask */ 2542 #define I2C0_SMBAL_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! I2C0_SMBAL PG2 MFP Mask */ 2543 #define I2C0_SMBAL_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! I2C0_SMBAL PC3 MFP Mask */ 2544 #define I2C0_SMBSUS_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! I2C0_SMBSUS PA2 MFP Mask */ 2545 #define I2C0_SMBSUS_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! I2C0_SMBSUS PC2 MFP Mask */ 2546 #define I2C0_SMBSUS_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! I2C0_SMBSUS PG3 MFP Mask */ 2547 #define I2C1_SCL_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! I2C1_SCL PB1 MFP Mask */ 2548 #define I2C1_SCL_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! I2C1_SCL PE1 MFP Mask */ 2549 #define I2C1_SCL_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! I2C1_SCL PF0 MFP Mask */ 2550 #define I2C1_SCL_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! I2C1_SCL PA12 MFP Mask */ 2551 #define I2C1_SCL_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! I2C1_SCL PA7 MFP Mask */ 2552 #define I2C1_SCL_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! I2C1_SCL PB11 MFP Mask */ 2553 #define I2C1_SCL_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! I2C1_SCL PG2 MFP Mask */ 2554 #define I2C1_SCL_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! I2C1_SCL PA3 MFP Mask */ 2555 #define I2C1_SCL_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! I2C1_SCL PC5 MFP Mask */ 2556 #define I2C1_SCL_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! I2C1_SCL PD5 MFP Mask */ 2557 #define I2C1_SCL_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! I2C1_SCL PB3 MFP Mask */ 2558 #define I2C1_SDA_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! I2C1_SDA PA2 MFP Mask */ 2559 #define I2C1_SDA_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! I2C1_SDA PB10 MFP Mask */ 2560 #define I2C1_SDA_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! I2C1_SDA PF1 MFP Mask */ 2561 #define I2C1_SDA_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! I2C1_SDA PB2 MFP Mask */ 2562 #define I2C1_SDA_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! I2C1_SDA PD4 MFP Mask */ 2563 #define I2C1_SDA_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! I2C1_SDA PA13 MFP Mask */ 2564 #define I2C1_SDA_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! I2C1_SDA PA6 MFP Mask */ 2565 #define I2C1_SDA_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! I2C1_SDA PE0 MFP Mask */ 2566 #define I2C1_SDA_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! I2C1_SDA PG3 MFP Mask */ 2567 #define I2C1_SDA_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! I2C1_SDA PC4 MFP Mask */ 2568 #define I2C1_SDA_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! I2C1_SDA PB0 MFP Mask */ 2569 #define I2C1_SMBAL_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! I2C1_SMBAL PB9 MFP Mask */ 2570 #define I2C1_SMBAL_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2C1_SMBAL PH8 MFP Mask */ 2571 #define I2C1_SMBAL_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! I2C1_SMBAL PC7 MFP Mask */ 2572 #define I2C1_SMBSUS_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! I2C1_SMBSUS PC6 MFP Mask */ 2573 #define I2C1_SMBSUS_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! I2C1_SMBSUS PB8 MFP Mask */ 2574 #define I2C1_SMBSUS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2C1_SMBSUS PH9 MFP Mask */ 2575 #define I2C2_SCL_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! I2C2_SCL PA14 MFP Mask */ 2576 #define I2C2_SCL_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2C2_SCL PH8 MFP Mask */ 2577 #define I2C2_SCL_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! I2C2_SCL PA11 MFP Mask */ 2578 #define I2C2_SCL_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! I2C2_SCL PB13 MFP Mask */ 2579 #define I2C2_SCL_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! I2C2_SCL PD9 MFP Mask */ 2580 #define I2C2_SCL_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! I2C2_SCL PA1 MFP Mask */ 2581 #define I2C2_SCL_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! I2C2_SCL PD1 MFP Mask */ 2582 #define I2C2_SDA_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! I2C2_SDA PD8 MFP Mask */ 2583 #define I2C2_SDA_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! I2C2_SDA PD0 MFP Mask */ 2584 #define I2C2_SDA_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! I2C2_SDA PA15 MFP Mask */ 2585 #define I2C2_SDA_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2C2_SDA PH9 MFP Mask */ 2586 #define I2C2_SDA_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! I2C2_SDA PA10 MFP Mask */ 2587 #define I2C2_SDA_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! I2C2_SDA PA0 MFP Mask */ 2588 #define I2C2_SDA_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! I2C2_SDA PB12 MFP Mask */ 2589 #define I2C2_SMBAL_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! I2C2_SMBAL PB15 MFP Mask */ 2590 #define I2C2_SMBSUS_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! I2C2_SMBSUS PB14 MFP Mask */ 2591 #define I2S0_BCLK_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! I2S0_BCLK PF10 MFP Mask */ 2592 #define I2S0_BCLK_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! I2S0_BCLK PB5 MFP Mask */ 2593 #define I2S0_BCLK_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! I2S0_BCLK PE1 MFP Mask */ 2594 #define I2S0_BCLK_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! I2S0_BCLK PA12 MFP Mask */ 2595 #define I2S0_BCLK_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! I2S0_BCLK PC4 MFP Mask */ 2596 #define I2S0_BCLK_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! I2S0_BCLK PE8 MFP Mask */ 2597 #define I2S0_DI_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! I2S0_DI PC2 MFP Mask */ 2598 #define I2S0_DI_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! I2S0_DI PE10 MFP Mask */ 2599 #define I2S0_DI_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! I2S0_DI PF8 MFP Mask */ 2600 #define I2S0_DI_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! I2S0_DI PH8 MFP Mask */ 2601 #define I2S0_DI_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! I2S0_DI PB3 MFP Mask */ 2602 #define I2S0_DI_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! I2S0_DI PA14 MFP Mask */ 2603 #define I2S0_DO_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! I2S0_DO PH9 MFP Mask */ 2604 #define I2S0_DO_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! I2S0_DO PC1 MFP Mask */ 2605 #define I2S0_DO_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! I2S0_DO PA15 MFP Mask */ 2606 #define I2S0_DO_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! I2S0_DO PB2 MFP Mask */ 2607 #define I2S0_DO_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! I2S0_DO PF7 MFP Mask */ 2608 #define I2S0_DO_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! I2S0_DO PE11 MFP Mask */ 2609 #define I2S0_LRCK_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! I2S0_LRCK PC0 MFP Mask */ 2610 #define I2S0_LRCK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! I2S0_LRCK PB1 MFP Mask */ 2611 #define I2S0_LRCK_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! I2S0_LRCK PH10 MFP Mask */ 2612 #define I2S0_LRCK_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! I2S0_LRCK PF6 MFP Mask */ 2613 #define I2S0_LRCK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! I2S0_LRCK PE12 MFP Mask */ 2614 #define I2S0_MCLK_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! I2S0_MCLK PC3 MFP Mask */ 2615 #define I2S0_MCLK_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! I2S0_MCLK PF9 MFP Mask */ 2616 #define I2S0_MCLK_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! I2S0_MCLK PE0 MFP Mask */ 2617 #define I2S0_MCLK_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! I2S0_MCLK PB4 MFP Mask */ 2618 #define I2S0_MCLK_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! I2S0_MCLK PA13 MFP Mask */ 2619 #define I2S0_MCLK_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! I2S0_MCLK PE9 MFP Mask */ 2620 #define ICE_CLK_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! ICE_CLK PF1 MFP Mask */ 2621 #define ICE_DAT_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! ICE_DAT PF0 MFP Mask */ 2622 #define INT0_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! INT0 PA6 MFP Mask */ 2623 #define INT0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! INT0 PB5 MFP Mask */ 2624 #define INT1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! INT1 PB4 MFP Mask */ 2625 #define INT1_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! INT1 PA7 MFP Mask */ 2626 #define INT2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! INT2 PB3 MFP Mask */ 2627 #define INT2_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! INT2 PC6 MFP Mask */ 2628 #define INT3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! INT3 PB2 MFP Mask */ 2629 #define INT3_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! INT3 PC7 MFP Mask */ 2630 #define INT4_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! INT4 PA8 MFP Mask */ 2631 #define INT4_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! INT4 PB6 MFP Mask */ 2632 #define INT5_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! INT5 PB7 MFP Mask */ 2633 #define INT5_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! INT5 PD12 MFP Mask */ 2634 #define INT6_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! INT6 PD11 MFP Mask */ 2635 #define INT6_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! INT6 PB8 MFP Mask */ 2636 #define INT7_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! INT7 PB9 MFP Mask */ 2637 #define INT7_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! INT7 PD10 MFP Mask */ 2638 #define LCD_COM0_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! LCD_COM0 PC0 MFP Mask */ 2639 #define LCD_COM1_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! LCD_COM1 PC1 MFP Mask */ 2640 #define LCD_COM2_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! LCD_COM2 PC2 MFP Mask */ 2641 #define LCD_COM3_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! LCD_COM3 PC3 MFP Mask */ 2642 #define LCD_COM4_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! LCD_COM4 PC4 MFP Mask */ 2643 #define LCD_COM5_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! LCD_COM5 PC5 MFP Mask */ 2644 #define LCD_COM6_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! LCD_COM6 PA0 MFP Mask */ 2645 #define LCD_COM6_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! LCD_COM6 PD8 MFP Mask */ 2646 #define LCD_COM7_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! LCD_COM7 PA1 MFP Mask */ 2647 #define LCD_COM7_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! LCD_COM7 PD9 MFP Mask */ 2648 #define LCD_SEG0_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! LCD_SEG0 PD14 MFP Mask */ 2649 #define LCD_SEG0_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! LCD_SEG0 PD1 MFP Mask */ 2650 #define LCD_SEG1_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! LCD_SEG1 PD2 MFP Mask */ 2651 #define LCD_SEG1_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! LCD_SEG1 PH11 MFP Mask */ 2652 #define LCD_SEG10_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! LCD_SEG10 PC7 MFP Mask */ 2653 #define LCD_SEG10_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! LCD_SEG10 PE5 MFP Mask */ 2654 #define LCD_SEG11_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! LCD_SEG11 PA8 MFP Mask */ 2655 #define LCD_SEG11_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! LCD_SEG11 PE6 MFP Mask */ 2656 #define LCD_SEG12_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! LCD_SEG12 PA9 MFP Mask */ 2657 #define LCD_SEG12_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! LCD_SEG12 PE7 MFP Mask */ 2658 #define LCD_SEG13_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! LCD_SEG13 PD6 MFP Mask */ 2659 #define LCD_SEG13_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! LCD_SEG13 PA1 MFP Mask */ 2660 #define LCD_SEG14_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! LCD_SEG14 PD7 MFP Mask */ 2661 #define LCD_SEG14_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! LCD_SEG14 PA0 MFP Mask */ 2662 #define LCD_SEG15_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! LCD_SEG15 PG15 MFP Mask */ 2663 #define LCD_SEG16_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! LCD_SEG16 PG14 MFP Mask */ 2664 #define LCD_SEG17_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! LCD_SEG17 PG13 MFP Mask */ 2665 #define LCD_SEG18_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! LCD_SEG18 PG12 MFP Mask */ 2666 #define LCD_SEG19_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! LCD_SEG19 PG11 MFP Mask */ 2667 #define LCD_SEG2_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! LCD_SEG2 PH10 MFP Mask */ 2668 #define LCD_SEG2_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! LCD_SEG2 PD3 MFP Mask */ 2669 #define LCD_SEG20_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! LCD_SEG20 PG10 MFP Mask */ 2670 #define LCD_SEG21_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! LCD_SEG21 PG9 MFP Mask */ 2671 #define LCD_SEG22_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! LCD_SEG22 PE15 MFP Mask */ 2672 #define LCD_SEG23_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! LCD_SEG23 PE14 MFP Mask */ 2673 #define LCD_SEG24_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! LCD_SEG24 PA0 MFP Mask */ 2674 #define LCD_SEG25_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! LCD_SEG25 PA1 MFP Mask */ 2675 #define LCD_SEG26_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! LCD_SEG26 PA2 MFP Mask */ 2676 #define LCD_SEG27_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! LCD_SEG27 PA3 MFP Mask */ 2677 #define LCD_SEG28_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! LCD_SEG28 PA4 MFP Mask */ 2678 #define LCD_SEG29_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! LCD_SEG29 PA5 MFP Mask */ 2679 #define LCD_SEG3_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! LCD_SEG3 PA2 MFP Mask */ 2680 #define LCD_SEG3_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! LCD_SEG3 PH9 MFP Mask */ 2681 #define LCD_SEG30_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! LCD_SEG30 PE10 MFP Mask */ 2682 #define LCD_SEG31_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! LCD_SEG31 PE9 MFP Mask */ 2683 #define LCD_SEG32_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! LCD_SEG32 PE8 MFP Mask */ 2684 #define LCD_SEG33_PH7_Msk SYS_GPH_MFPL_PH7MFP_Msk /*<! LCD_SEG33 PH7 MFP Mask */ 2685 #define LCD_SEG34_PH6_Msk SYS_GPH_MFPL_PH6MFP_Msk /*<! LCD_SEG34 PH6 MFP Mask */ 2686 #define LCD_SEG35_PH5_Msk SYS_GPH_MFPL_PH5MFP_Msk /*<! LCD_SEG35 PH5 MFP Mask */ 2687 #define LCD_SEG36_PH4_Msk SYS_GPH_MFPL_PH4MFP_Msk /*<! LCD_SEG36 PH4 MFP Mask */ 2688 #define LCD_SEG37_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! LCD_SEG37 PG4 MFP Mask */ 2689 #define LCD_SEG38_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! LCD_SEG38 PG3 MFP Mask */ 2690 #define LCD_SEG39_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! LCD_SEG39 PG2 MFP Mask */ 2691 #define LCD_SEG4_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! LCD_SEG4 PH8 MFP Mask */ 2692 #define LCD_SEG4_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! LCD_SEG4 PA3 MFP Mask */ 2693 #define LCD_SEG40_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! LCD_SEG40 PD9 MFP Mask */ 2694 #define LCD_SEG41_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! LCD_SEG41 PD8 MFP Mask */ 2695 #define LCD_SEG42_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! LCD_SEG42 PC5 MFP Mask */ 2696 #define LCD_SEG43_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! LCD_SEG43 PC4 MFP Mask */ 2697 #define LCD_SEG5_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! LCD_SEG5 PA4 MFP Mask */ 2698 #define LCD_SEG5_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! LCD_SEG5 PE0 MFP Mask */ 2699 #define LCD_SEG6_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! LCD_SEG6 PE1 MFP Mask */ 2700 #define LCD_SEG6_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! LCD_SEG6 PA5 MFP Mask */ 2701 #define LCD_SEG7_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! LCD_SEG7 PA6 MFP Mask */ 2702 #define LCD_SEG7_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! LCD_SEG7 PE2 MFP Mask */ 2703 #define LCD_SEG8_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! LCD_SEG8 PE3 MFP Mask */ 2704 #define LCD_SEG8_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! LCD_SEG8 PA7 MFP Mask */ 2705 #define LCD_SEG9_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! LCD_SEG9 PC6 MFP Mask */ 2706 #define LCD_SEG9_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! LCD_SEG9 PE4 MFP Mask */ 2707 #define QEI0_A_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! QEI0_A PD11 MFP Mask */ 2708 #define QEI0_A_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! QEI0_A PA4 MFP Mask */ 2709 #define QEI0_A_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! QEI0_A PE3 MFP Mask */ 2710 #define QEI0_B_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! QEI0_B PE2 MFP Mask */ 2711 #define QEI0_B_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! QEI0_B PD10 MFP Mask */ 2712 #define QEI0_B_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! QEI0_B PA3 MFP Mask */ 2713 #define QEI0_INDEX_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! QEI0_INDEX PE4 MFP Mask */ 2714 #define QEI0_INDEX_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! QEI0_INDEX PA5 MFP Mask */ 2715 #define QEI0_INDEX_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! QEI0_INDEX PD12 MFP Mask */ 2716 #define QEI1_A_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! QEI1_A PA13 MFP Mask */ 2717 #define QEI1_A_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! QEI1_A PE6 MFP Mask */ 2718 #define QEI1_A_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! QEI1_A PA9 MFP Mask */ 2719 #define QEI1_B_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! QEI1_B PE5 MFP Mask */ 2720 #define QEI1_B_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! QEI1_B PA8 MFP Mask */ 2721 #define QEI1_B_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! QEI1_B PA14 MFP Mask */ 2722 #define QEI1_INDEX_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! QEI1_INDEX PA10 MFP Mask */ 2723 #define QEI1_INDEX_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! QEI1_INDEX PE7 MFP Mask */ 2724 #define QEI1_INDEX_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! QEI1_INDEX PA12 MFP Mask */ 2725 #define QSPI0_CLK_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! QSPI0_CLK PH8 MFP Mask */ 2726 #define QSPI0_CLK_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! QSPI0_CLK PF2 MFP Mask */ 2727 #define QSPI0_CLK_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! QSPI0_CLK PA2 MFP Mask */ 2728 #define QSPI0_CLK_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! QSPI0_CLK PC2 MFP Mask */ 2729 #define QSPI0_MISO0_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! QSPI0_MISO0 PC1 MFP Mask */ 2730 #define QSPI0_MISO0_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! QSPI0_MISO0 PE1 MFP Mask */ 2731 #define QSPI0_MISO0_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! QSPI0_MISO0 PA1 MFP Mask */ 2732 #define QSPI0_MISO1_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! QSPI0_MISO1 PB1 MFP Mask */ 2733 #define QSPI0_MISO1_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! QSPI0_MISO1 PC5 MFP Mask */ 2734 #define QSPI0_MISO1_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! QSPI0_MISO1 PH10 MFP Mask */ 2735 #define QSPI0_MISO1_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! QSPI0_MISO1 PA5 MFP Mask */ 2736 #define QSPI0_MOSI0_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! QSPI0_MOSI0 PC0 MFP Mask */ 2737 #define QSPI0_MOSI0_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! QSPI0_MOSI0 PE0 MFP Mask */ 2738 #define QSPI0_MOSI0_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! QSPI0_MOSI0 PA0 MFP Mask */ 2739 #define QSPI0_MOSI1_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! QSPI0_MOSI1 PC4 MFP Mask */ 2740 #define QSPI0_MOSI1_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! QSPI0_MOSI1 PH11 MFP Mask */ 2741 #define QSPI0_MOSI1_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! QSPI0_MOSI1 PB0 MFP Mask */ 2742 #define QSPI0_MOSI1_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! QSPI0_MOSI1 PA4 MFP Mask */ 2743 #define QSPI0_SS_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! QSPI0_SS PA3 MFP Mask */ 2744 #define QSPI0_SS_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! QSPI0_SS PC3 MFP Mask */ 2745 #define QSPI0_SS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! QSPI0_SS PH9 MFP Mask */ 2746 #define SC0_CLK_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! SC0_CLK PA0 MFP Mask */ 2747 #define SC0_CLK_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! SC0_CLK PF6 MFP Mask */ 2748 #define SC0_CLK_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SC0_CLK PE2 MFP Mask */ 2749 #define SC0_CLK_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SC0_CLK PB5 MFP Mask */ 2750 #define SC0_DAT_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! SC0_DAT PF7 MFP Mask */ 2751 #define SC0_DAT_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! SC0_DAT PA1 MFP Mask */ 2752 #define SC0_DAT_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SC0_DAT PE3 MFP Mask */ 2753 #define SC0_DAT_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SC0_DAT PB4 MFP Mask */ 2754 #define SC0_PWR_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! SC0_PWR PF9 MFP Mask */ 2755 #define SC0_PWR_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SC0_PWR PE5 MFP Mask */ 2756 #define SC0_PWR_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! SC0_PWR PA3 MFP Mask */ 2757 #define SC0_PWR_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SC0_PWR PB2 MFP Mask */ 2758 #define SC0_RST_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SC0_RST PE4 MFP Mask */ 2759 #define SC0_RST_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! SC0_RST PF8 MFP Mask */ 2760 #define SC0_RST_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! SC0_RST PA2 MFP Mask */ 2761 #define SC0_RST_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SC0_RST PB3 MFP Mask */ 2762 #define SC0_nCD_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! SC0_nCD PC12 MFP Mask */ 2763 #define SC0_nCD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! SC0_nCD PA4 MFP Mask */ 2764 #define SC0_nCD_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! SC0_nCD PF10 MFP Mask */ 2765 #define SC0_nCD_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SC0_nCD PE6 MFP Mask */ 2766 #define SC1_CLK_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SC1_CLK PB12 MFP Mask */ 2767 #define SC1_CLK_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! SC1_CLK PC0 MFP Mask */ 2768 #define SC1_CLK_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! SC1_CLK PD4 MFP Mask */ 2769 #define SC1_DAT_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! SC1_DAT PD5 MFP Mask */ 2770 #define SC1_DAT_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! SC1_DAT PC1 MFP Mask */ 2771 #define SC1_DAT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! SC1_DAT PB13 MFP Mask */ 2772 #define SC1_PWR_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! SC1_PWR PD7 MFP Mask */ 2773 #define SC1_PWR_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! SC1_PWR PC3 MFP Mask */ 2774 #define SC1_PWR_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! SC1_PWR PB15 MFP Mask */ 2775 #define SC1_RST_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! SC1_RST PD6 MFP Mask */ 2776 #define SC1_RST_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! SC1_RST PB14 MFP Mask */ 2777 #define SC1_RST_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! SC1_RST PC2 MFP Mask */ 2778 #define SC1_nCD_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SC1_nCD PD14 MFP Mask */ 2779 #define SC1_nCD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! SC1_nCD PC4 MFP Mask */ 2780 #define SC1_nCD_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SC1_nCD PD3 MFP Mask */ 2781 #define SC2_CLK_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! SC2_CLK PA6 MFP Mask */ 2782 #define SC2_CLK_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! SC2_CLK PD0 MFP Mask */ 2783 #define SC2_CLK_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! SC2_CLK PA15 MFP Mask */ 2784 #define SC2_CLK_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! SC2_CLK PA8 MFP Mask */ 2785 #define SC2_CLK_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! SC2_CLK PE0 MFP Mask */ 2786 #define SC2_DAT_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! SC2_DAT PA9 MFP Mask */ 2787 #define SC2_DAT_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! SC2_DAT PD1 MFP Mask */ 2788 #define SC2_DAT_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! SC2_DAT PA7 MFP Mask */ 2789 #define SC2_DAT_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! SC2_DAT PA14 MFP Mask */ 2790 #define SC2_DAT_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! SC2_DAT PE1 MFP Mask */ 2791 #define SC2_PWR_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! SC2_PWR PC7 MFP Mask */ 2792 #define SC2_PWR_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! SC2_PWR PH8 MFP Mask */ 2793 #define SC2_PWR_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SC2_PWR PD3 MFP Mask */ 2794 #define SC2_PWR_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! SC2_PWR PA11 MFP Mask */ 2795 #define SC2_PWR_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! SC2_PWR PA12 MFP Mask */ 2796 #define SC2_RST_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! SC2_RST PD2 MFP Mask */ 2797 #define SC2_RST_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! SC2_RST PC6 MFP Mask */ 2798 #define SC2_RST_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! SC2_RST PH9 MFP Mask */ 2799 #define SC2_RST_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! SC2_RST PA13 MFP Mask */ 2800 #define SC2_RST_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! SC2_RST PA10 MFP Mask */ 2801 #define SC2_nCD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! SC2_nCD PA5 MFP Mask */ 2802 #define SC2_nCD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! SC2_nCD PH10 MFP Mask */ 2803 #define SC2_nCD_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SC2_nCD PD13 MFP Mask */ 2804 #define SC2_nCD_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! SC2_nCD PC13 MFP Mask */ 2805 #define SD0_CLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SD0_CLK PB1 MFP Mask */ 2806 #define SD0_CLK_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SD0_CLK PE6 MFP Mask */ 2807 #define SD0_CMD_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! SD0_CMD PE7 MFP Mask */ 2808 #define SD0_CMD_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! SD0_CMD PB0 MFP Mask */ 2809 #define SD0_DAT0_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SD0_DAT0 PE2 MFP Mask */ 2810 #define SD0_DAT0_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SD0_DAT0 PB2 MFP Mask */ 2811 #define SD0_DAT1_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SD0_DAT1 PE3 MFP Mask */ 2812 #define SD0_DAT1_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SD0_DAT1 PB3 MFP Mask */ 2813 #define SD0_DAT2_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SD0_DAT2 PE4 MFP Mask */ 2814 #define SD0_DAT2_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SD0_DAT2 PB4 MFP Mask */ 2815 #define SD0_DAT3_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SD0_DAT3 PE5 MFP Mask */ 2816 #define SD0_DAT3_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SD0_DAT3 PB5 MFP Mask */ 2817 #define SD0_nCD_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SD0_nCD PD13 MFP Mask */ 2818 #define SD0_nCD_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SD0_nCD PB12 MFP Mask */ 2819 #define SEG15_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! SEG15 PC5 MFP Mask */ 2820 #define SEG16_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! SEG16 PC4 MFP Mask */ 2821 #define SPI0_CLK_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! SPI0_CLK PD2 MFP Mask */ 2822 #define SPI0_CLK_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! SPI0_CLK PB14 MFP Mask */ 2823 #define SPI0_CLK_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! SPI0_CLK PF8 MFP Mask */ 2824 #define SPI0_CLK_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! SPI0_CLK PA2 MFP Mask */ 2825 #define SPI0_I2SMCLK_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! SPI0_I2SMCLK PB11 MFP Mask */ 2826 #define SPI0_I2SMCLK_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! SPI0_I2SMCLK PB0 MFP Mask */ 2827 #define SPI0_I2SMCLK_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! SPI0_I2SMCLK PF10 MFP Mask */ 2828 #define SPI0_I2SMCLK_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! SPI0_I2SMCLK PA4 MFP Mask */ 2829 #define SPI0_I2SMCLK_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SPI0_I2SMCLK PD14 MFP Mask */ 2830 #define SPI0_I2SMCLK_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SPI0_I2SMCLK PD13 MFP Mask */ 2831 #define SPI0_MISO_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! SPI0_MISO PA1 MFP Mask */ 2832 #define SPI0_MISO_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! SPI0_MISO PF7 MFP Mask */ 2833 #define SPI0_MISO_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! SPI0_MISO PD1 MFP Mask */ 2834 #define SPI0_MISO_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! SPI0_MISO PB13 MFP Mask */ 2835 #define SPI0_MOSI_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! SPI0_MOSI PF6 MFP Mask */ 2836 #define SPI0_MOSI_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! SPI0_MOSI PD0 MFP Mask */ 2837 #define SPI0_MOSI_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! SPI0_MOSI PB12 MFP Mask */ 2838 #define SPI0_MOSI_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! SPI0_MOSI PA0 MFP Mask */ 2839 #define SPI0_SS_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! SPI0_SS PF9 MFP Mask */ 2840 #define SPI0_SS_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! SPI0_SS PA3 MFP Mask */ 2841 #define SPI0_SS_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! SPI0_SS PB15 MFP Mask */ 2842 #define SPI0_SS_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! SPI0_SS PD3 MFP Mask */ 2843 #define SPI1_CLK_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! SPI1_CLK PD5 MFP Mask */ 2844 #define SPI1_CLK_PH6_Msk SYS_GPH_MFPL_PH6MFP_Msk /*<! SPI1_CLK PH6 MFP Mask */ 2845 #define SPI1_CLK_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! SPI1_CLK PC1 MFP Mask */ 2846 #define SPI1_CLK_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! SPI1_CLK PB3 MFP Mask */ 2847 #define SPI1_CLK_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! SPI1_CLK PH8 MFP Mask */ 2848 #define SPI1_CLK_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! SPI1_CLK PA7 MFP Mask */ 2849 #define SPI1_I2SMCLK_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! SPI1_I2SMCLK PC4 MFP Mask */ 2850 #define SPI1_I2SMCLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SPI1_I2SMCLK PB1 MFP Mask */ 2851 #define SPI1_I2SMCLK_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! SPI1_I2SMCLK PA5 MFP Mask */ 2852 #define SPI1_I2SMCLK_PD13_Msk SYS_GPD_MFPH_PD13MFP_Msk /*<! SPI1_I2SMCLK PD13 MFP Mask */ 2853 #define SPI1_I2SMCLK_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! SPI1_I2SMCLK PH10 MFP Mask */ 2854 #define SPI1_MISO_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! SPI1_MISO PC3 MFP Mask */ 2855 #define SPI1_MISO_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! SPI1_MISO PC7 MFP Mask */ 2856 #define SPI1_MISO_PH4_Msk SYS_GPH_MFPL_PH4MFP_Msk /*<! SPI1_MISO PH4 MFP Mask */ 2857 #define SPI1_MISO_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! SPI1_MISO PB5 MFP Mask */ 2858 #define SPI1_MISO_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! SPI1_MISO PE1 MFP Mask */ 2859 #define SPI1_MISO_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! SPI1_MISO PD7 MFP Mask */ 2860 #define SPI1_MOSI_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! SPI1_MOSI PE0 MFP Mask */ 2861 #define SPI1_MOSI_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! SPI1_MOSI PB4 MFP Mask */ 2862 #define SPI1_MOSI_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! SPI1_MOSI PC6 MFP Mask */ 2863 #define SPI1_MOSI_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! SPI1_MOSI PD6 MFP Mask */ 2864 #define SPI1_MOSI_PH5_Msk SYS_GPH_MFPL_PH5MFP_Msk /*<! SPI1_MOSI PH5 MFP Mask */ 2865 #define SPI1_MOSI_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! SPI1_MOSI PC2 MFP Mask */ 2866 #define SPI1_SS_PH7_Msk SYS_GPH_MFPL_PH7MFP_Msk /*<! SPI1_SS PH7 MFP Mask */ 2867 #define SPI1_SS_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! SPI1_SS PB2 MFP Mask */ 2868 #define SPI1_SS_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! SPI1_SS PA6 MFP Mask */ 2869 #define SPI1_SS_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! SPI1_SS PD4 MFP Mask */ 2870 #define SPI1_SS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! SPI1_SS PH9 MFP Mask */ 2871 #define SPI1_SS_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! SPI1_SS PC0 MFP Mask */ 2872 #define SPI2_CLK_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! SPI2_CLK PE8 MFP Mask */ 2873 #define SPI2_CLK_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! SPI2_CLK PA10 MFP Mask */ 2874 #define SPI2_CLK_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! SPI2_CLK PA13 MFP Mask */ 2875 #define SPI2_CLK_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! SPI2_CLK PG3 MFP Mask */ 2876 #define SPI2_I2SMCLK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! SPI2_I2SMCLK PE12 MFP Mask */ 2877 #define SPI2_I2SMCLK_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! SPI2_I2SMCLK PC13 MFP Mask */ 2878 #define SPI2_I2SMCLK_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! SPI2_I2SMCLK PB0 MFP Mask */ 2879 #define SPI2_MISO_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! SPI2_MISO PE9 MFP Mask */ 2880 #define SPI2_MISO_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! SPI2_MISO PA9 MFP Mask */ 2881 #define SPI2_MISO_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! SPI2_MISO PA14 MFP Mask */ 2882 #define SPI2_MISO_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! SPI2_MISO PG4 MFP Mask */ 2883 #define SPI2_MOSI_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! SPI2_MOSI PF11 MFP Mask */ 2884 #define SPI2_MOSI_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! SPI2_MOSI PA15 MFP Mask */ 2885 #define SPI2_MOSI_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! SPI2_MOSI PE10 MFP Mask */ 2886 #define SPI2_MOSI_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! SPI2_MOSI PA8 MFP Mask */ 2887 #define SPI2_SS_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! SPI2_SS PE11 MFP Mask */ 2888 #define SPI2_SS_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! SPI2_SS PG2 MFP Mask */ 2889 #define SPI2_SS_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! SPI2_SS PA11 MFP Mask */ 2890 #define SPI2_SS_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! SPI2_SS PA12 MFP Mask */ 2891 #define SPI3_CLK_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! SPI3_CLK PC10 MFP Mask */ 2892 #define SPI3_CLK_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SPI3_CLK PE4 MFP Mask */ 2893 #define SPI3_CLK_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! SPI3_CLK PB11 MFP Mask */ 2894 #define SPI3_I2SMCLK_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! SPI3_I2SMCLK PE6 MFP Mask */ 2895 #define SPI3_I2SMCLK_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! SPI3_I2SMCLK PF6 MFP Mask */ 2896 #define SPI3_I2SMCLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! SPI3_I2SMCLK PB1 MFP Mask */ 2897 #define SPI3_I2SMCLK_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! SPI3_I2SMCLK PD14 MFP Mask */ 2898 #define SPI3_MISO_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SPI3_MISO PE3 MFP Mask */ 2899 #define SPI3_MISO_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! SPI3_MISO PC12 MFP Mask */ 2900 #define SPI3_MISO_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! SPI3_MISO PB9 MFP Mask */ 2901 #define SPI3_MOSI_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! SPI3_MOSI PC11 MFP Mask */ 2902 #define SPI3_MOSI_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SPI3_MOSI PE2 MFP Mask */ 2903 #define SPI3_MOSI_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! SPI3_MOSI PB8 MFP Mask */ 2904 #define SPI3_SS_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SPI3_SS PE5 MFP Mask */ 2905 #define SPI3_SS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! SPI3_SS PB10 MFP Mask */ 2906 #define SPI3_SS_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! SPI3_SS PC9 MFP Mask */ 2907 #define TAMPER0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! TAMPER0 PF6 MFP Mask */ 2908 #define TAMPER1_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! TAMPER1 PF7 MFP Mask */ 2909 #define TAMPER2_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! TAMPER2 PF8 MFP Mask */ 2910 #define TAMPER3_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! TAMPER3 PF9 MFP Mask */ 2911 #define TAMPER4_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! TAMPER4 PF10 MFP Mask */ 2912 #define TAMPER5_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! TAMPER5 PF11 MFP Mask */ 2913 #define TM0_PG2_Msk SYS_GPG_MFPL_PG2MFP_Msk /*<! TM0 PG2 MFP Mask */ 2914 #define TM0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! TM0 PB5 MFP Mask */ 2915 #define TM0_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! TM0 PC7 MFP Mask */ 2916 #define TM0_EXT_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! TM0_EXT PB15 MFP Mask */ 2917 #define TM0_EXT_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! TM0_EXT PA11 MFP Mask */ 2918 #define TM1_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! TM1 PC6 MFP Mask */ 2919 #define TM1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! TM1 PB4 MFP Mask */ 2920 #define TM1_PG3_Msk SYS_GPG_MFPL_PG3MFP_Msk /*<! TM1 PG3 MFP Mask */ 2921 #define TM1_EXT_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! TM1_EXT PB14 MFP Mask */ 2922 #define TM1_EXT_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! TM1_EXT PA10 MFP Mask */ 2923 #define TM2_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! TM2 PB3 MFP Mask */ 2924 #define TM2_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! TM2 PA7 MFP Mask */ 2925 #define TM2_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! TM2 PD0 MFP Mask */ 2926 #define TM2_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! TM2 PG4 MFP Mask */ 2927 #define TM2_EXT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! TM2_EXT PB13 MFP Mask */ 2928 #define TM2_EXT_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! TM2_EXT PA9 MFP Mask */ 2929 #define TM3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! TM3 PB2 MFP Mask */ 2930 #define TM3_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! TM3 PA6 MFP Mask */ 2931 #define TM3_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! TM3 PF11 MFP Mask */ 2932 #define TM3_EXT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! TM3_EXT PB12 MFP Mask */ 2933 #define TM3_EXT_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! TM3_EXT PA8 MFP Mask */ 2934 #define TM4_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! TM4 PA7 MFP Mask */ 2935 #define TM4_PG4_Msk SYS_GPG_MFPL_PG4MFP_Msk /*<! TM4 PG4 MFP Mask */ 2936 #define TM4_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! TM4 PB3 MFP Mask */ 2937 #define TM4_EXT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! TM4_EXT PB13 MFP Mask */ 2938 #define TM4_EXT_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! TM4_EXT PA9 MFP Mask */ 2939 #define TM5_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! TM5 PF11 MFP Mask */ 2940 #define TM5_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! TM5 PB2 MFP Mask */ 2941 #define TM5_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! TM5 PA6 MFP Mask */ 2942 #define TM5_EXT_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! TM5_EXT PA8 MFP Mask */ 2943 #define TM5_EXT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! TM5_EXT PB12 MFP Mask */ 2944 #define TRACE_CLK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! TRACE_CLK PE12 MFP Mask */ 2945 #define TRACE_DATA0_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! TRACE_DATA0 PE11 MFP Mask */ 2946 #define TRACE_DATA1_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! TRACE_DATA1 PE10 MFP Mask */ 2947 #define TRACE_DATA2_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! TRACE_DATA2 PE9 MFP Mask */ 2948 #define TRACE_DATA3_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! TRACE_DATA3 PE8 MFP Mask */ 2949 #define UART0_RXD_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! UART0_RXD PA15 MFP Mask */ 2950 #define UART0_RXD_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART0_RXD PD2 MFP Mask */ 2951 #define UART0_RXD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! UART0_RXD PA4 MFP Mask */ 2952 #define UART0_RXD_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! UART0_RXD PB12 MFP Mask */ 2953 #define UART0_RXD_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART0_RXD PA0 MFP Mask */ 2954 #define UART0_RXD_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! UART0_RXD PF1 MFP Mask */ 2955 #define UART0_RXD_PC11_Msk SYS_GPC_MFPH_PC11MFP_Msk /*<! UART0_RXD PC11 MFP Mask */ 2956 #define UART0_RXD_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART0_RXD PB8 MFP Mask */ 2957 #define UART0_RXD_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! UART0_RXD PH11 MFP Mask */ 2958 #define UART0_RXD_PA6_Msk SYS_GPA_MFPL_PA6MFP_Msk /*<! UART0_RXD PA6 MFP Mask */ 2959 #define UART0_RXD_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! UART0_RXD PF2 MFP Mask */ 2960 #define UART0_TXD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! UART0_TXD PA5 MFP Mask */ 2961 #define UART0_TXD_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! UART0_TXD PA14 MFP Mask */ 2962 #define UART0_TXD_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! UART0_TXD PF3 MFP Mask */ 2963 #define UART0_TXD_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! UART0_TXD PA1 MFP Mask */ 2964 #define UART0_TXD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! UART0_TXD PH10 MFP Mask */ 2965 #define UART0_TXD_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! UART0_TXD PD3 MFP Mask */ 2966 #define UART0_TXD_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! UART0_TXD PB9 MFP Mask */ 2967 #define UART0_TXD_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! UART0_TXD PB13 MFP Mask */ 2968 #define UART0_TXD_PA7_Msk SYS_GPA_MFPL_PA7MFP_Msk /*<! UART0_TXD PA7 MFP Mask */ 2969 #define UART0_TXD_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! UART0_TXD PF0 MFP Mask */ 2970 #define UART0_TXD_PC12_Msk SYS_GPC_MFPH_PC12MFP_Msk /*<! UART0_TXD PC12 MFP Mask */ 2971 #define UART0_nCTS_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! UART0_nCTS PB15 MFP Mask */ 2972 #define UART0_nCTS_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! UART0_nCTS PB11 MFP Mask */ 2973 #define UART0_nCTS_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! UART0_nCTS PC7 MFP Mask */ 2974 #define UART0_nCTS_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! UART0_nCTS PA5 MFP Mask */ 2975 #define UART0_nRTS_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! UART0_nRTS PC6 MFP Mask */ 2976 #define UART0_nRTS_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! UART0_nRTS PB14 MFP Mask */ 2977 #define UART0_nRTS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! UART0_nRTS PB10 MFP Mask */ 2978 #define UART0_nRTS_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! UART0_nRTS PA4 MFP Mask */ 2979 #define UART1_RXD_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! UART1_RXD PA8 MFP Mask */ 2980 #define UART1_RXD_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! UART1_RXD PB6 MFP Mask */ 2981 #define UART1_RXD_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! UART1_RXD PC8 MFP Mask */ 2982 #define UART1_RXD_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! UART1_RXD PA2 MFP Mask */ 2983 #define UART1_RXD_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! UART1_RXD PH9 MFP Mask */ 2984 #define UART1_RXD_PD10_Msk SYS_GPD_MFPH_PD10MFP_Msk /*<! UART1_RXD PD10 MFP Mask */ 2985 #define UART1_RXD_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! UART1_RXD PB2 MFP Mask */ 2986 #define UART1_RXD_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! UART1_RXD PD6 MFP Mask */ 2987 #define UART1_RXD_PF1_Msk SYS_GPF_MFPL_PF1MFP_Msk /*<! UART1_RXD PF1 MFP Mask */ 2988 #define UART1_TXD_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! UART1_TXD PA9 MFP Mask */ 2989 #define UART1_TXD_PD11_Msk SYS_GPD_MFPH_PD11MFP_Msk /*<! UART1_TXD PD11 MFP Mask */ 2990 #define UART1_TXD_PF0_Msk SYS_GPF_MFPL_PF0MFP_Msk /*<! UART1_TXD PF0 MFP Mask */ 2991 #define UART1_TXD_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! UART1_TXD PB3 MFP Mask */ 2992 #define UART1_TXD_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! UART1_TXD PH8 MFP Mask */ 2993 #define UART1_TXD_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! UART1_TXD PA3 MFP Mask */ 2994 #define UART1_TXD_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! UART1_TXD PD7 MFP Mask */ 2995 #define UART1_TXD_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! UART1_TXD PE13 MFP Mask */ 2996 #define UART1_TXD_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! UART1_TXD PB7 MFP Mask */ 2997 #define UART1_nCTS_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! UART1_nCTS PB9 MFP Mask */ 2998 #define UART1_nCTS_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! UART1_nCTS PE11 MFP Mask */ 2999 #define UART1_nCTS_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! UART1_nCTS PA1 MFP Mask */ 3000 #define UART1_nRTS_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART1_nRTS PB8 MFP Mask */ 3001 #define UART1_nRTS_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART1_nRTS PA0 MFP Mask */ 3002 #define UART1_nRTS_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! UART1_nRTS PE12 MFP Mask */ 3003 #define UART2_RXD_PE15_Msk SYS_GPE_MFPH_PE15MFP_Msk /*<! UART2_RXD PE15 MFP Mask */ 3004 #define UART2_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! UART2_RXD PC4 MFP Mask */ 3005 #define UART2_RXD_PD12_Msk SYS_GPD_MFPH_PD12MFP_Msk /*<! UART2_RXD PD12 MFP Mask */ 3006 #define UART2_RXD_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! UART2_RXD PF5 MFP Mask */ 3007 #define UART2_RXD_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! UART2_RXD PE9 MFP Mask */ 3008 #define UART2_RXD_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! UART2_RXD PC0 MFP Mask */ 3009 #define UART2_RXD_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! UART2_RXD PB0 MFP Mask */ 3010 #define UART2_RXD_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! UART2_RXD PB4 MFP Mask */ 3011 #define UART2_TXD_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! UART2_TXD PF4 MFP Mask */ 3012 #define UART2_TXD_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! UART2_TXD PC1 MFP Mask */ 3013 #define UART2_TXD_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! UART2_TXD PB5 MFP Mask */ 3014 #define UART2_TXD_PE14_Msk SYS_GPE_MFPH_PE14MFP_Msk /*<! UART2_TXD PE14 MFP Mask */ 3015 #define UART2_TXD_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! UART2_TXD PC13 MFP Mask */ 3016 #define UART2_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! UART2_TXD PC5 MFP Mask */ 3017 #define UART2_TXD_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! UART2_TXD PE8 MFP Mask */ 3018 #define UART2_TXD_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! UART2_TXD PB1 MFP Mask */ 3019 #define UART2_nCTS_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! UART2_nCTS PF5 MFP Mask */ 3020 #define UART2_nCTS_PD9_Msk SYS_GPD_MFPH_PD9MFP_Msk /*<! UART2_nCTS PD9 MFP Mask */ 3021 #define UART2_nCTS_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! UART2_nCTS PC2 MFP Mask */ 3022 #define UART2_nRTS_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! UART2_nRTS PC3 MFP Mask */ 3023 #define UART2_nRTS_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! UART2_nRTS PD8 MFP Mask */ 3024 #define UART2_nRTS_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! UART2_nRTS PF4 MFP Mask */ 3025 #define UART3_RXD_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! UART3_RXD PD0 MFP Mask */ 3026 #define UART3_RXD_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! UART3_RXD PC9 MFP Mask */ 3027 #define UART3_RXD_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! UART3_RXD PE0 MFP Mask */ 3028 #define UART3_RXD_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! UART3_RXD PC2 MFP Mask */ 3029 #define UART3_RXD_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! UART3_RXD PB14 MFP Mask */ 3030 #define UART3_RXD_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! UART3_RXD PE11 MFP Mask */ 3031 #define UART3_TXD_PC10_Msk SYS_GPC_MFPH_PC10MFP_Msk /*<! UART3_TXD PC10 MFP Mask */ 3032 #define UART3_TXD_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! UART3_TXD PB15 MFP Mask */ 3033 #define UART3_TXD_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! UART3_TXD PE10 MFP Mask */ 3034 #define UART3_TXD_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! UART3_TXD PC3 MFP Mask */ 3035 #define UART3_TXD_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! UART3_TXD PD1 MFP Mask */ 3036 #define UART3_TXD_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! UART3_TXD PE1 MFP Mask */ 3037 #define UART3_nCTS_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! UART3_nCTS PB12 MFP Mask */ 3038 #define UART3_nCTS_PH9_Msk SYS_GPH_MFPH_PH9MFP_Msk /*<! UART3_nCTS PH9 MFP Mask */ 3039 #define UART3_nCTS_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART3_nCTS PD2 MFP Mask */ 3040 #define UART3_nRTS_PH8_Msk SYS_GPH_MFPH_PH8MFP_Msk /*<! UART3_nRTS PH8 MFP Mask */ 3041 #define UART3_nRTS_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! UART3_nRTS PD3 MFP Mask */ 3042 #define UART3_nRTS_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! UART3_nRTS PB13 MFP Mask */ 3043 #define UART4_RXD_PA2_Msk SYS_GPA_MFPL_PA2MFP_Msk /*<! UART4_RXD PA2 MFP Mask */ 3044 #define UART4_RXD_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! UART4_RXD PA13 MFP Mask */ 3045 #define UART4_RXD_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! UART4_RXD PC4 MFP Mask */ 3046 #define UART4_RXD_PH11_Msk SYS_GPH_MFPH_PH11MFP_Msk /*<! UART4_RXD PH11 MFP Mask */ 3047 #define UART4_RXD_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! UART4_RXD PF6 MFP Mask */ 3048 #define UART4_RXD_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! UART4_RXD PB10 MFP Mask */ 3049 #define UART4_RXD_PC6_Msk SYS_GPC_MFPL_PC6MFP_Msk /*<! UART4_RXD PC6 MFP Mask */ 3050 #define UART4_TXD_PA3_Msk SYS_GPA_MFPL_PA3MFP_Msk /*<! UART4_TXD PA3 MFP Mask */ 3051 #define UART4_TXD_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! UART4_TXD PC5 MFP Mask */ 3052 #define UART4_TXD_PC7_Msk SYS_GPC_MFPL_PC7MFP_Msk /*<! UART4_TXD PC7 MFP Mask */ 3053 #define UART4_TXD_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! UART4_TXD PA12 MFP Mask */ 3054 #define UART4_TXD_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! UART4_TXD PF7 MFP Mask */ 3055 #define UART4_TXD_PH10_Msk SYS_GPH_MFPH_PH10MFP_Msk /*<! UART4_TXD PH10 MFP Mask */ 3056 #define UART4_TXD_PB11_Msk SYS_GPB_MFPH_PB11MFP_Msk /*<! UART4_TXD PB11 MFP Mask */ 3057 #define UART4_nCTS_PC8_Msk SYS_GPC_MFPH_PC8MFP_Msk /*<! UART4_nCTS PC8 MFP Mask */ 3058 #define UART4_nCTS_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! UART4_nCTS PE1 MFP Mask */ 3059 #define UART4_nRTS_PE0_Msk SYS_GPE_MFPL_PE0MFP_Msk /*<! UART4_nRTS PE0 MFP Mask */ 3060 #define UART4_nRTS_PE13_Msk SYS_GPE_MFPH_PE13MFP_Msk /*<! UART4_nRTS PE13 MFP Mask */ 3061 #define UART5_RXD_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! UART5_RXD PB4 MFP Mask */ 3062 #define UART5_RXD_PF10_Msk SYS_GPF_MFPH_PF10MFP_Msk /*<! UART5_RXD PF10 MFP Mask */ 3063 #define UART5_RXD_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! UART5_RXD PE6 MFP Mask */ 3064 #define UART5_RXD_PA4_Msk SYS_GPA_MFPL_PA4MFP_Msk /*<! UART5_RXD PA4 MFP Mask */ 3065 #define UART5_TXD_PF11_Msk SYS_GPF_MFPH_PF11MFP_Msk /*<! UART5_TXD PF11 MFP Mask */ 3066 #define UART5_TXD_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! UART5_TXD PB5 MFP Mask */ 3067 #define UART5_TXD_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! UART5_TXD PE7 MFP Mask */ 3068 #define UART5_TXD_PA5_Msk SYS_GPA_MFPL_PA5MFP_Msk /*<! UART5_TXD PA5 MFP Mask */ 3069 #define UART5_nCTS_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! UART5_nCTS PB2 MFP Mask */ 3070 #define UART5_nCTS_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! UART5_nCTS PF8 MFP Mask */ 3071 #define UART5_nRTS_PF9_Msk SYS_GPF_MFPH_PF9MFP_Msk /*<! UART5_nRTS PF9 MFP Mask */ 3072 #define UART5_nRTS_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! UART5_nRTS PB3 MFP Mask */ 3073 #define USB_D_P_PA14_Msk SYS_GPA_MFPH_PA14MFP_Msk /*<! USB_D_P PA14 MFP Mask */ 3074 #define USB_D_N_PA13_Msk SYS_GPA_MFPH_PA13MFP_Msk /*<! USB_D_N PA13 MFP Mask */ 3075 #define USB_OTG_ID_PA15_Msk SYS_GPA_MFPH_PA15MFP_Msk /*<! USB_OTG_ID PA15 MFP Mask */ 3076 #define USB_VBUS_PA12_Msk SYS_GPA_MFPH_PA12MFP_Msk /*<! USB_VBUS PA12 MFP Mask */ 3077 #define USB_VBUS_EN_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! USB_VBUS_EN PB15 MFP Mask */ 3078 #define USB_VBUS_EN_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! USB_VBUS_EN PB6 MFP Mask */ 3079 #define USB_VBUS_ST_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! USB_VBUS_ST PB14 MFP Mask */ 3080 #define USB_VBUS_ST_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! USB_VBUS_ST PB7 MFP Mask */ 3081 #define USB_VBUS_ST_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USB_VBUS_ST PD4 MFP Mask */ 3082 #define USCI0_CLK_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! USCI0_CLK PA11 MFP Mask */ 3083 #define USCI0_CLK_PD0_Msk SYS_GPD_MFPL_PD0MFP_Msk /*<! USCI0_CLK PD0 MFP Mask */ 3084 #define USCI0_CLK_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! USCI0_CLK PB12 MFP Mask */ 3085 #define USCI0_CLK_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! USCI0_CLK PE2 MFP Mask */ 3086 #define USCI0_CTL0_PC13_Msk SYS_GPC_MFPH_PC13MFP_Msk /*<! USCI0_CTL0 PC13 MFP Mask */ 3087 #define USCI0_CTL0_PD14_Msk SYS_GPD_MFPH_PD14MFP_Msk /*<! USCI0_CTL0 PD14 MFP Mask */ 3088 #define USCI0_CTL0_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! USCI0_CTL0 PE6 MFP Mask */ 3089 #define USCI0_CTL0_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USCI0_CTL0 PD4 MFP Mask */ 3090 #define USCI0_CTL1_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! USCI0_CTL1 PD3 MFP Mask */ 3091 #define USCI0_CTL1_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! USCI0_CTL1 PA8 MFP Mask */ 3092 #define USCI0_CTL1_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! USCI0_CTL1 PE5 MFP Mask */ 3093 #define USCI0_CTL1_PB15_Msk SYS_GPB_MFPH_PB15MFP_Msk /*<! USCI0_CTL1 PB15 MFP Mask */ 3094 #define USCI0_DAT0_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! USCI0_DAT0 PB13 MFP Mask */ 3095 #define USCI0_DAT0_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! USCI0_DAT0 PE3 MFP Mask */ 3096 #define USCI0_DAT0_PA10_Msk SYS_GPA_MFPH_PA10MFP_Msk /*<! USCI0_DAT0 PA10 MFP Mask */ 3097 #define USCI0_DAT0_PD1_Msk SYS_GPD_MFPL_PD1MFP_Msk /*<! USCI0_DAT0 PD1 MFP Mask */ 3098 #define USCI0_DAT1_PA9_Msk SYS_GPA_MFPH_PA9MFP_Msk /*<! USCI0_DAT1 PA9 MFP Mask */ 3099 #define USCI0_DAT1_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! USCI0_DAT1 PE4 MFP Mask */ 3100 #define USCI0_DAT1_PB14_Msk SYS_GPB_MFPH_PB14MFP_Msk /*<! USCI0_DAT1 PB14 MFP Mask */ 3101 #define USCI0_DAT1_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! USCI0_DAT1 PD2 MFP Mask */ 3102 #define USCI1_CLK_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! USCI1_CLK PE12 MFP Mask */ 3103 #define USCI1_CLK_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! USCI1_CLK PB1 MFP Mask */ 3104 #define USCI1_CLK_PD7_Msk SYS_GPD_MFPL_PD7MFP_Msk /*<! USCI1_CLK PD7 MFP Mask */ 3105 #define USCI1_CLK_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! USCI1_CLK PB8 MFP Mask */ 3106 #define USCI1_CTL0_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! USCI1_CTL0 PE9 MFP Mask */ 3107 #define USCI1_CTL0_PB5_Msk SYS_GPB_MFPL_PB5MFP_Msk /*<! USCI1_CTL0 PB5 MFP Mask */ 3108 #define USCI1_CTL0_PD3_Msk SYS_GPD_MFPL_PD3MFP_Msk /*<! USCI1_CTL0 PD3 MFP Mask */ 3109 #define USCI1_CTL0_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! USCI1_CTL0 PB10 MFP Mask */ 3110 #define USCI1_CTL1_PB4_Msk SYS_GPB_MFPL_PB4MFP_Msk /*<! USCI1_CTL1 PB4 MFP Mask */ 3111 #define USCI1_CTL1_PD4_Msk SYS_GPD_MFPL_PD4MFP_Msk /*<! USCI1_CTL1 PD4 MFP Mask */ 3112 #define USCI1_CTL1_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! USCI1_CTL1 PE8 MFP Mask */ 3113 #define USCI1_CTL1_PB9_Msk SYS_GPB_MFPH_PB9MFP_Msk /*<! USCI1_CTL1 PB9 MFP Mask */ 3114 #define USCI1_DAT0_PB7_Msk SYS_GPB_MFPL_PB7MFP_Msk /*<! USCI1_DAT0 PB7 MFP Mask */ 3115 #define USCI1_DAT0_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! USCI1_DAT0 PE10 MFP Mask */ 3116 #define USCI1_DAT0_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! USCI1_DAT0 PB2 MFP Mask */ 3117 #define USCI1_DAT0_PD5_Msk SYS_GPD_MFPL_PD5MFP_Msk /*<! USCI1_DAT0 PD5 MFP Mask */ 3118 #define USCI1_DAT1_PD6_Msk SYS_GPD_MFPL_PD6MFP_Msk /*<! USCI1_DAT1 PD6 MFP Mask */ 3119 #define USCI1_DAT1_PB6_Msk SYS_GPB_MFPL_PB6MFP_Msk /*<! USCI1_DAT1 PB6 MFP Mask */ 3120 #define USCI1_DAT1_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! USCI1_DAT1 PE11 MFP Mask */ 3121 #define USCI1_DAT1_PB3_Msk SYS_GPB_MFPL_PB3MFP_Msk /*<! USCI1_DAT1 PB3 MFP Mask */ 3122 #define X32_IN_PF5_Msk SYS_GPF_MFPL_PF5MFP_Msk /*<! X32_IN PF5 MFP Mask */ 3123 #define X32_OUT_PF4_Msk SYS_GPF_MFPL_PF4MFP_Msk /*<! X32_OUT PF4 MFP Mask */ 3124 #define XT1_IN_PF3_Msk SYS_GPF_MFPL_PF3MFP_Msk /*<! XT1_IN PF3 MFP Mask */ 3125 #define XT1_OUT_PF2_Msk SYS_GPF_MFPL_PF2MFP_Msk /*<! XT1_OUT PF2 MFP Mask */ 3126 3127 3128 /**@}*/ /* end of group SYS_EXPORTED_CONSTANTS */ 3129 3130 /** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions 3131 @{ 3132 */ 3133 3134 /*---------------------------------------------------------------------------------------------------------*/ 3135 /* Multi-Function macro definitions. */ 3136 /*---------------------------------------------------------------------------------------------------------*/ 3137 3138 #define SET_ACMP0_N_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_N_PB3_Msk)) | ACMP0_N_PB3 /*!< Set PB3 function to ACMP0_N */ 3139 #define SET_ACMP0_O_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_O_PB7_Msk)) | ACMP0_O_PB7 /*!< Set PB7 function to ACMP0_O */ 3140 #define SET_ACMP0_O_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP0_O_PC1_Msk)) | ACMP0_O_PC1 /*!< Set PC1 function to ACMP0_O */ 3141 #define SET_ACMP0_O_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP0_O_PC12_Msk)) | ACMP0_O_PC12 /*!< Set PC12 function to ACMP0_O */ 3142 #define SET_ACMP0_P0_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP0_P0_PA11_Msk)) | ACMP0_P0_PA11 /*!< Set PA11 function to ACMP0_P0 */ 3143 #define SET_ACMP0_P1_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP0_P1_PB2_Msk)) | ACMP0_P1_PB2 /*!< Set PB2 function to ACMP0_P1 */ 3144 #define SET_ACMP0_P2_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P2_PB12_Msk)) | ACMP0_P2_PB12 /*!< Set PB12 function to ACMP0_P2 */ 3145 #define SET_ACMP0_P3_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP0_P3_PB13_Msk)) | ACMP0_P3_PB13 /*!< Set PB13 function to ACMP0_P3 */ 3146 #define SET_ACMP0_WLAT_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP0_WLAT_PA7_Msk)) | ACMP0_WLAT_PA7 /*!< Set PA7 function to ACMP0_WLAT */ 3147 #define SET_ACMP1_N_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_N_PB5_Msk)) | ACMP1_N_PB5 /*!< Set PB5 function to ACMP1_N */ 3148 #define SET_ACMP1_O_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_O_PB6_Msk)) | ACMP1_O_PB6 /*!< Set PB6 function to ACMP1_O */ 3149 #define SET_ACMP1_O_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ACMP1_O_PC11_Msk)) | ACMP1_O_PC11 /*!< Set PC11 function to ACMP1_O */ 3150 #define SET_ACMP1_O_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~ACMP1_O_PC0_Msk)) | ACMP1_O_PC0 /*!< Set PC0 function to ACMP1_O */ 3151 #define SET_ACMP1_P0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ACMP1_P0_PA10_Msk)) | ACMP1_P0_PA10 /*!< Set PA10 function to ACMP1_P0 */ 3152 #define SET_ACMP1_P1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~ACMP1_P1_PB4_Msk)) | ACMP1_P1_PB4 /*!< Set PB4 function to ACMP1_P1 */ 3153 #define SET_ACMP1_P2_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P2_PB12_Msk)) | ACMP1_P2_PB12 /*!< Set PB12 function to ACMP1_P2 */ 3154 #define SET_ACMP1_P3_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~ACMP1_P3_PB13_Msk)) | ACMP1_P3_PB13 /*!< Set PB13 function to ACMP1_P3 */ 3155 #define SET_ACMP1_WLAT_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~ACMP1_WLAT_PA6_Msk)) | ACMP1_WLAT_PA6 /*!< Set PA6 function to ACMP1_WLAT */ 3156 #define SET_BPWM0_CH0_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH0_PA0_Msk)) | BPWM0_CH0_PA0 /*!< Set PA0 function to BPWM0_CH0 */ 3157 #define SET_BPWM0_CH0_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH0_PA11_Msk)) | BPWM0_CH0_PA11 /*!< Set PA11 function to BPWM0_CH0 */ 3158 #define SET_BPWM0_CH0_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH0_PE2_Msk)) | BPWM0_CH0_PE2 /*!< Set PE2 function to BPWM0_CH0 */ 3159 #define SET_BPWM0_CH0_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH0_PG14_Msk)) | BPWM0_CH0_PG14 /*!< Set PG14 function to BPWM0_CH0 */ 3160 #define SET_BPWM0_CH1_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH1_PA1_Msk)) | BPWM0_CH1_PA1 /*!< Set PA1 function to BPWM0_CH1 */ 3161 #define SET_BPWM0_CH1_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH1_PE3_Msk)) | BPWM0_CH1_PE3 /*!< Set PE3 function to BPWM0_CH1 */ 3162 #define SET_BPWM0_CH1_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH1_PG13_Msk)) | BPWM0_CH1_PG13 /*!< Set PG13 function to BPWM0_CH1 */ 3163 #define SET_BPWM0_CH1_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH1_PA10_Msk)) | BPWM0_CH1_PA10 /*!< Set PA10 function to BPWM0_CH1 */ 3164 #define SET_BPWM0_CH2_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH2_PE4_Msk)) | BPWM0_CH2_PE4 /*!< Set PE4 function to BPWM0_CH2 */ 3165 #define SET_BPWM0_CH2_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH2_PG12_Msk)) | BPWM0_CH2_PG12 /*!< Set PG12 function to BPWM0_CH2 */ 3166 #define SET_BPWM0_CH2_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH2_PA2_Msk)) | BPWM0_CH2_PA2 /*!< Set PA2 function to BPWM0_CH2 */ 3167 #define SET_BPWM0_CH2_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH2_PA9_Msk)) | BPWM0_CH2_PA9 /*!< Set PA9 function to BPWM0_CH2 */ 3168 #define SET_BPWM0_CH3_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH3_PG11_Msk)) | BPWM0_CH3_PG11 /*!< Set PG11 function to BPWM0_CH3 */ 3169 #define SET_BPWM0_CH3_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH3_PA3_Msk)) | BPWM0_CH3_PA3 /*!< Set PA3 function to BPWM0_CH3 */ 3170 #define SET_BPWM0_CH3_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM0_CH3_PA8_Msk)) | BPWM0_CH3_PA8 /*!< Set PA8 function to BPWM0_CH3 */ 3171 #define SET_BPWM0_CH3_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH3_PE5_Msk)) | BPWM0_CH3_PE5 /*!< Set PE5 function to BPWM0_CH3 */ 3172 #define SET_BPWM0_CH4_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH4_PG10_Msk)) | BPWM0_CH4_PG10 /*!< Set PG10 function to BPWM0_CH4 */ 3173 #define SET_BPWM0_CH4_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH4_PA4_Msk)) | BPWM0_CH4_PA4 /*!< Set PA4 function to BPWM0_CH4 */ 3174 #define SET_BPWM0_CH4_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM0_CH4_PC13_Msk)) | BPWM0_CH4_PC13 /*!< Set PC13 function to BPWM0_CH4 */ 3175 #define SET_BPWM0_CH4_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH4_PE6_Msk)) | BPWM0_CH4_PE6 /*!< Set PE6 function to BPWM0_CH4 */ 3176 #define SET_BPWM0_CH4_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH4_PF5_Msk)) | BPWM0_CH4_PF5 /*!< Set PF5 function to BPWM0_CH4 */ 3177 #define SET_BPWM0_CH5_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM0_CH5_PA5_Msk)) | BPWM0_CH5_PA5 /*!< Set PA5 function to BPWM0_CH5 */ 3178 #define SET_BPWM0_CH5_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~BPWM0_CH5_PE7_Msk)) | BPWM0_CH5_PE7 /*!< Set PE7 function to BPWM0_CH5 */ 3179 #define SET_BPWM0_CH5_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM0_CH5_PF4_Msk)) | BPWM0_CH5_PF4 /*!< Set PF4 function to BPWM0_CH5 */ 3180 #define SET_BPWM0_CH5_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~BPWM0_CH5_PD12_Msk)) | BPWM0_CH5_PD12 /*!< Set PD12 function to BPWM0_CH5 */ 3181 #define SET_BPWM0_CH5_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~BPWM0_CH5_PG9_Msk)) | BPWM0_CH5_PG9 /*!< Set PG9 function to BPWM0_CH5 */ 3182 #define SET_BPWM1_CH0_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH0_PB11_Msk)) | BPWM1_CH0_PB11 /*!< Set PB11 function to BPWM1_CH0 */ 3183 #define SET_BPWM1_CH0_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH0_PC7_Msk)) | BPWM1_CH0_PC7 /*!< Set PC7 function to BPWM1_CH0 */ 3184 #define SET_BPWM1_CH0_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF0_Msk)) | BPWM1_CH0_PF0 /*!< Set PF0 function to BPWM1_CH0 */ 3185 #define SET_BPWM1_CH0_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH0_PF3_Msk)) | BPWM1_CH0_PF3 /*!< Set PF3 function to BPWM1_CH0 */ 3186 #define SET_BPWM1_CH1_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~BPWM1_CH1_PC6_Msk)) | BPWM1_CH1_PC6 /*!< Set PC6 function to BPWM1_CH1 */ 3187 #define SET_BPWM1_CH1_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF1_Msk)) | BPWM1_CH1_PF1 /*!< Set PF1 function to BPWM1_CH1 */ 3188 #define SET_BPWM1_CH1_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~BPWM1_CH1_PF2_Msk)) | BPWM1_CH1_PF2 /*!< Set PF2 function to BPWM1_CH1 */ 3189 #define SET_BPWM1_CH1_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH1_PB10_Msk)) | BPWM1_CH1_PB10 /*!< Set PB10 function to BPWM1_CH1 */ 3190 #define SET_BPWM1_CH2_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH2_PB9_Msk)) | BPWM1_CH2_PB9 /*!< Set PB9 function to BPWM1_CH2 */ 3191 #define SET_BPWM1_CH2_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH2_PA7_Msk)) | BPWM1_CH2_PA7 /*!< Set PA7 function to BPWM1_CH2 */ 3192 #define SET_BPWM1_CH2_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH2_PA12_Msk)) | BPWM1_CH2_PA12 /*!< Set PA12 function to BPWM1_CH2 */ 3193 #define SET_BPWM1_CH3_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~BPWM1_CH3_PA6_Msk)) | BPWM1_CH3_PA6 /*!< Set PA6 function to BPWM1_CH3 */ 3194 #define SET_BPWM1_CH3_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH3_PA13_Msk)) | BPWM1_CH3_PA13 /*!< Set PA13 function to BPWM1_CH3 */ 3195 #define SET_BPWM1_CH3_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~BPWM1_CH3_PB8_Msk)) | BPWM1_CH3_PB8 /*!< Set PB8 function to BPWM1_CH3 */ 3196 #define SET_BPWM1_CH4_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH4_PA14_Msk)) | BPWM1_CH4_PA14 /*!< Set PA14 function to BPWM1_CH4 */ 3197 #define SET_BPWM1_CH4_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~BPWM1_CH4_PC8_Msk)) | BPWM1_CH4_PC8 /*!< Set PC8 function to BPWM1_CH4 */ 3198 #define SET_BPWM1_CH4_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH4_PB7_Msk)) | BPWM1_CH4_PB7 /*!< Set PB7 function to BPWM1_CH4 */ 3199 #define SET_BPWM1_CH5_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~BPWM1_CH5_PA15_Msk)) | BPWM1_CH5_PA15 /*!< Set PA15 function to BPWM1_CH5 */ 3200 #define SET_BPWM1_CH5_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~BPWM1_CH5_PB6_Msk)) | BPWM1_CH5_PB6 /*!< Set PB6 function to BPWM1_CH5 */ 3201 #define SET_BPWM1_CH5_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~BPWM1_CH5_PE13_Msk)) | BPWM1_CH5_PE13 /*!< Set PE13 function to BPWM1_CH5 */ 3202 #define SET_CAN0_RXD_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_RXD_PA13_Msk)) | CAN0_RXD_PA13 /*!< Set PA13 function to CAN0_RXD */ 3203 #define SET_CAN0_RXD_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_RXD_PD10_Msk)) | CAN0_RXD_PD10 /*!< Set PD10 function to CAN0_RXD */ 3204 #define SET_CAN0_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_RXD_PA4_Msk)) | CAN0_RXD_PA4 /*!< Set PA4 function to CAN0_RXD */ 3205 #define SET_CAN0_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_RXD_PC4_Msk)) | CAN0_RXD_PC4 /*!< Set PC4 function to CAN0_RXD */ 3206 #define SET_CAN0_RXD_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_RXD_PB10_Msk)) | CAN0_RXD_PB10 /*!< Set PB10 function to CAN0_RXD */ 3207 #define SET_CAN0_RXD_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_RXD_PE15_Msk)) | CAN0_RXD_PE15 /*!< Set PE15 function to CAN0_RXD */ 3208 #define SET_CAN0_TXD_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CAN0_TXD_PD11_Msk)) | CAN0_TXD_PD11 /*!< Set PD11 function to CAN0_TXD */ 3209 #define SET_CAN0_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~CAN0_TXD_PC5_Msk)) | CAN0_TXD_PC5 /*!< Set PC5 function to CAN0_TXD */ 3210 #define SET_CAN0_TXD_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CAN0_TXD_PB11_Msk)) | CAN0_TXD_PB11 /*!< Set PB11 function to CAN0_TXD */ 3211 #define SET_CAN0_TXD_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~CAN0_TXD_PA12_Msk)) | CAN0_TXD_PA12 /*!< Set PA12 function to CAN0_TXD */ 3212 #define SET_CAN0_TXD_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~CAN0_TXD_PE14_Msk)) | CAN0_TXD_PE14 /*!< Set PE14 function to CAN0_TXD */ 3213 #define SET_CAN0_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~CAN0_TXD_PA5_Msk)) | CAN0_TXD_PA5 /*!< Set PA5 function to CAN0_TXD */ 3214 #define SET_CLKO_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~CLKO_PC13_Msk)) | CLKO_PC13 /*!< Set PC13 function to CLKO */ 3215 #define SET_CLKO_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~CLKO_PB14_Msk)) | CLKO_PB14 /*!< Set PB14 function to CLKO */ 3216 #define SET_CLKO_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~CLKO_PD12_Msk)) | CLKO_PD12 /*!< Set PD12 function to CLKO */ 3217 #define SET_CLKO_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~CLKO_PG15_Msk)) | CLKO_PG15 /*!< Set PG15 function to CLKO */ 3218 #define SET_DAC0_OUT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12 /*!< Set PB12 function to DAC0_OUT */ 3219 #define SET_DAC0_OUT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC0_OUT_PB12_Msk)) | DAC0_OUT_PB12 /*!< Set PB12 function to DAC0_OUT */ 3220 #define SET_DAC0_ST_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC0_ST_PA0_Msk)) | DAC0_ST_PA0 /*!< Set PA0 function to DAC0_ST */ 3221 #define SET_DAC0_ST_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC0_ST_PA10_Msk)) | DAC0_ST_PA10 /*!< Set PA10 function to DAC0_ST */ 3222 #define SET_DAC1_OUT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13 /*!< Set PB13 function to DAC1_OUT */ 3223 #define SET_DAC1_OUT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~DAC1_OUT_PB13_Msk)) | DAC1_OUT_PB13 /*!< Set PB13 function to DAC1_OUT */ 3224 #define SET_DAC1_ST_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~DAC1_ST_PA1_Msk)) | DAC1_ST_PA1 /*!< Set PA1 function to DAC1_ST */ 3225 #define SET_DAC1_ST_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~DAC1_ST_PA11_Msk)) | DAC1_ST_PA11 /*!< Set PA11 function to DAC1_ST */ 3226 #define SET_EADC0_CH0_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH0_PB0_Msk)) | EADC0_CH0_PB0 /*!< Set PB0 function to EADC0_CH0 */ 3227 #define SET_EADC0_CH1_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH1_PB1_Msk)) | EADC0_CH1_PB1 /*!< Set PB1 function to EADC0_CH1 */ 3228 #define SET_EADC0_CH10_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH10_PB10_Msk)) | EADC0_CH10_PB10 /*!< Set PB10 function to EADC0_CH10 */ 3229 #define SET_EADC0_CH11_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH11_PB11_Msk)) | EADC0_CH11_PB11 /*!< Set PB11 function to EADC0_CH11 */ 3230 #define SET_EADC0_CH12_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH12_PB12_Msk)) | EADC0_CH12_PB12 /*!< Set PB12 function to EADC0_CH12 */ 3231 #define SET_EADC0_CH13_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH13_PB13_Msk)) | EADC0_CH13_PB13 /*!< Set PB13 function to EADC0_CH13 */ 3232 #define SET_EADC0_CH14_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH14_PB14_Msk)) | EADC0_CH14_PB14 /*!< Set PB14 function to EADC0_CH14 */ 3233 #define SET_EADC0_CH15_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH15_PB15_Msk)) | EADC0_CH15_PB15 /*!< Set PB15 function to EADC0_CH15 */ 3234 #define SET_EADC0_CH15_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_CH15_PD10_Msk)) | EADC0_CH15_PD10 /*!< Set PD10 function to EADC0_CH15 */ 3235 #define SET_EADC0_CH2_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH2_PB2_Msk)) | EADC0_CH2_PB2 /*!< Set PB2 function to EADC0_CH2 */ 3236 #define SET_EADC0_CH3_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH3_PB3_Msk)) | EADC0_CH3_PB3 /*!< Set PB3 function to EADC0_CH3 */ 3237 #define SET_EADC0_CH4_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH4_PB4_Msk)) | EADC0_CH4_PB4 /*!< Set PB4 function to EADC0_CH4 */ 3238 #define SET_EADC0_CH5_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH5_PB5_Msk)) | EADC0_CH5_PB5 /*!< Set PB5 function to EADC0_CH5 */ 3239 #define SET_EADC0_CH6_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH6_PB6_Msk)) | EADC0_CH6_PB6 /*!< Set PB6 function to EADC0_CH6 */ 3240 #define SET_EADC0_CH7_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EADC0_CH7_PB7_Msk)) | EADC0_CH7_PB7 /*!< Set PB7 function to EADC0_CH7 */ 3241 #define SET_EADC0_CH8_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH8_PB8_Msk)) | EADC0_CH8_PB8 /*!< Set PB8 function to EADC0_CH8 */ 3242 #define SET_EADC0_CH9_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EADC0_CH9_PB9_Msk)) | EADC0_CH9_PB9 /*!< Set PB9 function to EADC0_CH9 */ 3243 #define SET_EADC0_ST_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EADC0_ST_PF5_Msk)) | EADC0_ST_PF5 /*!< Set PF5 function to EADC0_ST */ 3244 #define SET_EADC0_ST_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EADC0_ST_PC13_Msk)) | EADC0_ST_PC13 /*!< Set PC13 function to EADC0_ST */ 3245 #define SET_EADC0_ST_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EADC0_ST_PC1_Msk)) | EADC0_ST_PC1 /*!< Set PC1 function to EADC0_ST */ 3246 #define SET_EADC0_ST_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EADC0_ST_PD12_Msk)) | EADC0_ST_PD12 /*!< Set PD12 function to EADC0_ST */ 3247 #define SET_EADC0_ST_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EADC0_ST_PG15_Msk)) | EADC0_ST_PG15 /*!< Set PG15 function to EADC0_ST */ 3248 #define SET_EBI_AD0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD0_PC0_Msk)) | EBI_AD0_PC0 /*!< Set PC0 function to EBI_AD0 */ 3249 #define SET_EBI_AD0_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD0_PG9_Msk)) | EBI_AD0_PG9 /*!< Set PG9 function to EBI_AD0 */ 3250 #define SET_EBI_AD1_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD1_PG10_Msk)) | EBI_AD1_PG10 /*!< Set PG10 function to EBI_AD1 */ 3251 #define SET_EBI_AD1_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD1_PC1_Msk)) | EBI_AD1_PC1 /*!< Set PC1 function to EBI_AD1 */ 3252 #define SET_EBI_AD10_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD10_PE1_Msk)) | EBI_AD10_PE1 /*!< Set PE1 function to EBI_AD10 */ 3253 #define SET_EBI_AD10_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD10_PD3_Msk)) | EBI_AD10_PD3 /*!< Set PD3 function to EBI_AD10 */ 3254 #define SET_EBI_AD10_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD10_PD13_Msk)) | EBI_AD10_PD13 /*!< Set PD13 function to EBI_AD10 */ 3255 #define SET_EBI_AD11_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_AD11_PE0_Msk)) | EBI_AD11_PE0 /*!< Set PE0 function to EBI_AD11 */ 3256 #define SET_EBI_AD11_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD11_PD2_Msk)) | EBI_AD11_PD2 /*!< Set PD2 function to EBI_AD11 */ 3257 #define SET_EBI_AD12_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD12_PD1_Msk)) | EBI_AD12_PD1 /*!< Set PD1 function to EBI_AD12 */ 3258 #define SET_EBI_AD12_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD12_PB15_Msk)) | EBI_AD12_PB15 /*!< Set PB15 function to EBI_AD12 */ 3259 #define SET_EBI_AD12_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD12_PH8_Msk)) | EBI_AD12_PH8 /*!< Set PH8 function to EBI_AD12 */ 3260 #define SET_EBI_AD13_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~EBI_AD13_PD0_Msk)) | EBI_AD13_PD0 /*!< Set PD0 function to EBI_AD13 */ 3261 #define SET_EBI_AD13_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD13_PB14_Msk)) | EBI_AD13_PB14 /*!< Set PB14 function to EBI_AD13 */ 3262 #define SET_EBI_AD13_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD13_PH9_Msk)) | EBI_AD13_PH9 /*!< Set PH9 function to EBI_AD13 */ 3263 #define SET_EBI_AD14_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD14_PB13_Msk)) | EBI_AD14_PB13 /*!< Set PB13 function to EBI_AD14 */ 3264 #define SET_EBI_AD14_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD14_PH10_Msk)) | EBI_AD14_PH10 /*!< Set PH10 function to EBI_AD14 */ 3265 #define SET_EBI_AD15_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_AD15_PB12_Msk)) | EBI_AD15_PB12 /*!< Set PB12 function to EBI_AD15 */ 3266 #define SET_EBI_AD15_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EBI_AD15_PH11_Msk)) | EBI_AD15_PH11 /*!< Set PH11 function to EBI_AD15 */ 3267 #define SET_EBI_AD2_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD2_PC2_Msk)) | EBI_AD2_PC2 /*!< Set PC2 function to EBI_AD2 */ 3268 #define SET_EBI_AD2_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD2_PG11_Msk)) | EBI_AD2_PG11 /*!< Set PG11 function to EBI_AD2 */ 3269 #define SET_EBI_AD3_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD3_PG12_Msk)) | EBI_AD3_PG12 /*!< Set PG12 function to EBI_AD3 */ 3270 #define SET_EBI_AD3_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD3_PC3_Msk)) | EBI_AD3_PC3 /*!< Set PC3 function to EBI_AD3 */ 3271 #define SET_EBI_AD4_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD4_PC4_Msk)) | EBI_AD4_PC4 /*!< Set PC4 function to EBI_AD4 */ 3272 #define SET_EBI_AD4_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD4_PG13_Msk)) | EBI_AD4_PG13 /*!< Set PG13 function to EBI_AD4 */ 3273 #define SET_EBI_AD5_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~EBI_AD5_PG14_Msk)) | EBI_AD5_PG14 /*!< Set PG14 function to EBI_AD5 */ 3274 #define SET_EBI_AD5_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD5_PC5_Msk)) | EBI_AD5_PC5 /*!< Set PC5 function to EBI_AD5 */ 3275 #define SET_EBI_AD6_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD6_PD8_Msk)) | EBI_AD6_PD8 /*!< Set PD8 function to EBI_AD6 */ 3276 #define SET_EBI_AD6_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD6_PA6_Msk)) | EBI_AD6_PA6 /*!< Set PA6 function to EBI_AD6 */ 3277 #define SET_EBI_AD7_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_AD7_PD9_Msk)) | EBI_AD7_PD9 /*!< Set PD9 function to EBI_AD7 */ 3278 #define SET_EBI_AD7_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EBI_AD7_PA7_Msk)) | EBI_AD7_PA7 /*!< Set PA7 function to EBI_AD7 */ 3279 #define SET_EBI_AD8_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD8_PE14_Msk)) | EBI_AD8_PE14 /*!< Set PE14 function to EBI_AD8 */ 3280 #define SET_EBI_AD8_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD8_PC6_Msk)) | EBI_AD8_PC6 /*!< Set PC6 function to EBI_AD8 */ 3281 #define SET_EBI_AD9_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EBI_AD9_PC7_Msk)) | EBI_AD9_PC7 /*!< Set PC7 function to EBI_AD9 */ 3282 #define SET_EBI_AD9_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_AD9_PE15_Msk)) | EBI_AD9_PE15 /*!< Set PE15 function to EBI_AD9 */ 3283 #define SET_EBI_ADR0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR0_PB5_Msk)) | EBI_ADR0_PB5 /*!< Set PB5 function to EBI_ADR0 */ 3284 #define SET_EBI_ADR0_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR0_PH7_Msk)) | EBI_ADR0_PH7 /*!< Set PH7 function to EBI_ADR0 */ 3285 #define SET_EBI_ADR1_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR1_PH6_Msk)) | EBI_ADR1_PH6 /*!< Set PH6 function to EBI_ADR1 */ 3286 #define SET_EBI_ADR1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR1_PB4_Msk)) | EBI_ADR1_PB4 /*!< Set PB4 function to EBI_ADR1 */ 3287 #define SET_EBI_ADR10_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR10_PC13_Msk)) | EBI_ADR10_PC13 /*!< Set PC13 function to EBI_ADR10 */ 3288 #define SET_EBI_ADR10_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR10_PE8_Msk)) | EBI_ADR10_PE8 /*!< Set PE8 function to EBI_ADR10 */ 3289 #define SET_EBI_ADR11_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR11_PE9_Msk)) | EBI_ADR11_PE9 /*!< Set PE9 function to EBI_ADR11 */ 3290 #define SET_EBI_ADR11_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR11_PG2_Msk)) | EBI_ADR11_PG2 /*!< Set PG2 function to EBI_ADR11 */ 3291 #define SET_EBI_ADR12_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR12_PE10_Msk)) | EBI_ADR12_PE10 /*!< Set PE10 function to EBI_ADR12 */ 3292 #define SET_EBI_ADR12_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR12_PG3_Msk)) | EBI_ADR12_PG3 /*!< Set PG3 function to EBI_ADR12 */ 3293 #define SET_EBI_ADR13_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR13_PE11_Msk)) | EBI_ADR13_PE11 /*!< Set PE11 function to EBI_ADR13 */ 3294 #define SET_EBI_ADR13_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~EBI_ADR13_PG4_Msk)) | EBI_ADR13_PG4 /*!< Set PG4 function to EBI_ADR13 */ 3295 #define SET_EBI_ADR14_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR14_PF11_Msk)) | EBI_ADR14_PF11 /*!< Set PF11 function to EBI_ADR14 */ 3296 #define SET_EBI_ADR14_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR14_PE12_Msk)) | EBI_ADR14_PE12 /*!< Set PE12 function to EBI_ADR14 */ 3297 #define SET_EBI_ADR15_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EBI_ADR15_PE13_Msk)) | EBI_ADR15_PE13 /*!< Set PE13 function to EBI_ADR15 */ 3298 #define SET_EBI_ADR15_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR15_PF10_Msk)) | EBI_ADR15_PF10 /*!< Set PF10 function to EBI_ADR15 */ 3299 #define SET_EBI_ADR16_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR16_PC8_Msk)) | EBI_ADR16_PC8 /*!< Set PC8 function to EBI_ADR16 */ 3300 #define SET_EBI_ADR16_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR16_PF9_Msk)) | EBI_ADR16_PF9 /*!< Set PF9 function to EBI_ADR16 */ 3301 #define SET_EBI_ADR16_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR16_PB11_Msk)) | EBI_ADR16_PB11 /*!< Set PB11 function to EBI_ADR16 */ 3302 #define SET_EBI_ADR17_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR17_PB10_Msk)) | EBI_ADR17_PB10 /*!< Set PB10 function to EBI_ADR17 */ 3303 #define SET_EBI_ADR17_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~EBI_ADR17_PF8_Msk)) | EBI_ADR17_PF8 /*!< Set PF8 function to EBI_ADR17 */ 3304 #define SET_EBI_ADR18_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR18_PF7_Msk)) | EBI_ADR18_PF7 /*!< Set PF7 function to EBI_ADR18 */ 3305 #define SET_EBI_ADR18_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR18_PB9_Msk)) | EBI_ADR18_PB9 /*!< Set PB9 function to EBI_ADR18 */ 3306 #define SET_EBI_ADR19_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EBI_ADR19_PB8_Msk)) | EBI_ADR19_PB8 /*!< Set PB8 function to EBI_ADR19 */ 3307 #define SET_EBI_ADR19_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_ADR19_PF6_Msk)) | EBI_ADR19_PF6 /*!< Set PF6 function to EBI_ADR19 */ 3308 #define SET_EBI_ADR2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR2_PB3_Msk)) | EBI_ADR2_PB3 /*!< Set PB3 function to EBI_ADR2 */ 3309 #define SET_EBI_ADR2_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR2_PH5_Msk)) | EBI_ADR2_PH5 /*!< Set PH5 function to EBI_ADR2 */ 3310 #define SET_EBI_ADR3_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~EBI_ADR3_PH4_Msk)) | EBI_ADR3_PH4 /*!< Set PH4 function to EBI_ADR3 */ 3311 #define SET_EBI_ADR3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR3_PB2_Msk)) | EBI_ADR3_PB2 /*!< Set PB2 function to EBI_ADR3 */ 3312 #define SET_EBI_ADR4_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR4_PC12_Msk)) | EBI_ADR4_PC12 /*!< Set PC12 function to EBI_ADR4 */ 3313 #define SET_EBI_ADR5_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR5_PC11_Msk)) | EBI_ADR5_PC11 /*!< Set PC11 function to EBI_ADR5 */ 3314 #define SET_EBI_ADR6_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR6_PC10_Msk)) | EBI_ADR6_PC10 /*!< Set PC10 function to EBI_ADR6 */ 3315 #define SET_EBI_ADR7_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EBI_ADR7_PC9_Msk)) | EBI_ADR7_PC9 /*!< Set PC9 function to EBI_ADR7 */ 3316 #define SET_EBI_ADR8_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR8_PB1_Msk)) | EBI_ADR8_PB1 /*!< Set PB1 function to EBI_ADR8 */ 3317 #define SET_EBI_ADR9_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_ADR9_PB0_Msk)) | EBI_ADR9_PB0 /*!< Set PB0 function to EBI_ADR9 */ 3318 #define SET_EBI_ALE_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_ALE_PE2_Msk)) | EBI_ALE_PE2 /*!< Set PE2 function to EBI_ALE */ 3319 #define SET_EBI_ALE_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_ALE_PA8_Msk)) | EBI_ALE_PA8 /*!< Set PA8 function to EBI_ALE */ 3320 #define SET_EBI_MCLK_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_MCLK_PA9_Msk)) | EBI_MCLK_PA9 /*!< Set PA9 function to EBI_MCLK */ 3321 #define SET_EBI_MCLK_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_MCLK_PE3_Msk)) | EBI_MCLK_PE3 /*!< Set PE3 function to EBI_MCLK */ 3322 #define SET_EBI_nCS0_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD12_Msk)) | EBI_nCS0_PD12 /*!< Set PD12 function to EBI_nCS0 */ 3323 #define SET_EBI_nCS0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS0_PD14_Msk)) | EBI_nCS0_PD14 /*!< Set PD14 function to EBI_nCS0 */ 3324 #define SET_EBI_nCS0_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF3_Msk)) | EBI_nCS0_PF3 /*!< Set PF3 function to EBI_nCS0 */ 3325 #define SET_EBI_nCS0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS0_PB7_Msk)) | EBI_nCS0_PB7 /*!< Set PB7 function to EBI_nCS0 */ 3326 #define SET_EBI_nCS0_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS0_PF6_Msk)) | EBI_nCS0_PF6 /*!< Set PF6 function to EBI_nCS0 */ 3327 #define SET_EBI_nCS1_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EBI_nCS1_PF2_Msk)) | EBI_nCS1_PF2 /*!< Set PF2 function to EBI_nCS1 */ 3328 #define SET_EBI_nCS1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nCS1_PB6_Msk)) | EBI_nCS1_PB6 /*!< Set PB6 function to EBI_nCS1 */ 3329 #define SET_EBI_nCS1_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS1_PD11_Msk)) | EBI_nCS1_PD11 /*!< Set PD11 function to EBI_nCS1 */ 3330 #define SET_EBI_nCS2_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EBI_nCS2_PD10_Msk)) | EBI_nCS2_PD10 /*!< Set PD10 function to EBI_nCS2 */ 3331 #define SET_EBI_nRD_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nRD_PE5_Msk)) | EBI_nRD_PE5 /*!< Set PE5 function to EBI_nRD */ 3332 #define SET_EBI_nRD_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nRD_PA11_Msk)) | EBI_nRD_PA11 /*!< Set PA11 function to EBI_nRD */ 3333 #define SET_EBI_nWR_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EBI_nWR_PE4_Msk)) | EBI_nWR_PE4 /*!< Set PE4 function to EBI_nWR */ 3334 #define SET_EBI_nWR_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EBI_nWR_PA10_Msk)) | EBI_nWR_PA10 /*!< Set PA10 function to EBI_nWR */ 3335 #define SET_EBI_nWRH_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRH_PB6_Msk)) | EBI_nWRH_PB6 /*!< Set PB6 function to EBI_nWRH */ 3336 #define SET_EBI_nWRL_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EBI_nWRL_PB7_Msk)) | EBI_nWRL_PB7 /*!< Set PB7 function to EBI_nWRL */ 3337 #define SET_ECAP0_IC0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC0_PE8_Msk)) | ECAP0_IC0_PE8 /*!< Set PE8 function to ECAP0_IC0 */ 3338 #define SET_ECAP0_IC0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC0_PA10_Msk)) | ECAP0_IC0_PA10 /*!< Set PA10 function to ECAP0_IC0 */ 3339 #define SET_ECAP0_IC1_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC1_PA9_Msk)) | ECAP0_IC1_PA9 /*!< Set PA9 function to ECAP0_IC1 */ 3340 #define SET_ECAP0_IC1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC1_PE9_Msk)) | ECAP0_IC1_PE9 /*!< Set PE9 function to ECAP0_IC1 */ 3341 #define SET_ECAP0_IC2_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP0_IC2_PE10_Msk)) | ECAP0_IC2_PE10 /*!< Set PE10 function to ECAP0_IC2 */ 3342 #define SET_ECAP0_IC2_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~ECAP0_IC2_PA8_Msk)) | ECAP0_IC2_PA8 /*!< Set PA8 function to ECAP0_IC2 */ 3343 #define SET_ECAP1_IC0_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC0_PE13_Msk)) | ECAP1_IC0_PE13 /*!< Set PE13 function to ECAP1_IC0 */ 3344 #define SET_ECAP1_IC0_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC0_PC10_Msk)) | ECAP1_IC0_PC10 /*!< Set PC10 function to ECAP1_IC0 */ 3345 #define SET_ECAP1_IC1_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC1_PC11_Msk)) | ECAP1_IC1_PC11 /*!< Set PC11 function to ECAP1_IC1 */ 3346 #define SET_ECAP1_IC1_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC1_PE12_Msk)) | ECAP1_IC1_PE12 /*!< Set PE12 function to ECAP1_IC1 */ 3347 #define SET_ECAP1_IC2_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~ECAP1_IC2_PC12_Msk)) | ECAP1_IC2_PC12 /*!< Set PC12 function to ECAP1_IC2 */ 3348 #define SET_ECAP1_IC2_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~ECAP1_IC2_PE11_Msk)) | ECAP1_IC2_PE11 /*!< Set PE11 function to ECAP1_IC2 */ 3349 #define SET_EPWM0_BRAKE0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE0_PE8_Msk)) | EPWM0_BRAKE0_PE8 /*!< Set PE8 function to EPWM0_BRAKE0 */ 3350 #define SET_EPWM0_BRAKE0_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE0_PB1_Msk)) | EPWM0_BRAKE0_PB1 /*!< Set PB1 function to EPWM0_BRAKE0 */ 3351 #define SET_EPWM0_BRAKE1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM0_BRAKE1_PB14_Msk)) | EPWM0_BRAKE1_PB14 /*!< Set PB14 function to EPWM0_BRAKE1 */ 3352 #define SET_EPWM0_BRAKE1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_BRAKE1_PE9_Msk)) | EPWM0_BRAKE1_PE9 /*!< Set PE9 function to EPWM0_BRAKE1 */ 3353 #define SET_EPWM0_BRAKE1_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_BRAKE1_PB0_Msk)) | EPWM0_BRAKE1_PB0 /*!< Set PB0 function to EPWM0_BRAKE1 */ 3354 #define SET_EPWM0_CH0_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH0_PF5_Msk)) | EPWM0_CH0_PF5 /*!< Set PF5 function to EPWM0_CH0 */ 3355 #define SET_EPWM0_CH0_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH0_PA5_Msk)) | EPWM0_CH0_PA5 /*!< Set PA5 function to EPWM0_CH0 */ 3356 #define SET_EPWM0_CH0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH0_PB5_Msk)) | EPWM0_CH0_PB5 /*!< Set PB5 function to EPWM0_CH0 */ 3357 #define SET_EPWM0_CH0_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH0_PE8_Msk)) | EPWM0_CH0_PE8 /*!< Set PE8 function to EPWM0_CH0 */ 3358 #define SET_EPWM0_CH0_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH0_PE7_Msk)) | EPWM0_CH0_PE7 /*!< Set PE7 function to EPWM0_CH0 */ 3359 #define SET_EPWM0_CH1_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH1_PA4_Msk)) | EPWM0_CH1_PA4 /*!< Set PA4 function to EPWM0_CH1 */ 3360 #define SET_EPWM0_CH1_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH1_PE9_Msk)) | EPWM0_CH1_PE9 /*!< Set PE9 function to EPWM0_CH1 */ 3361 #define SET_EPWM0_CH1_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH1_PE6_Msk)) | EPWM0_CH1_PE6 /*!< Set PE6 function to EPWM0_CH1 */ 3362 #define SET_EPWM0_CH1_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_CH1_PF4_Msk)) | EPWM0_CH1_PF4 /*!< Set PF4 function to EPWM0_CH1 */ 3363 #define SET_EPWM0_CH1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH1_PB4_Msk)) | EPWM0_CH1_PB4 /*!< Set PB4 function to EPWM0_CH1 */ 3364 #define SET_EPWM0_CH2_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH2_PE10_Msk)) | EPWM0_CH2_PE10 /*!< Set PE10 function to EPWM0_CH2 */ 3365 #define SET_EPWM0_CH2_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH2_PE5_Msk)) | EPWM0_CH2_PE5 /*!< Set PE5 function to EPWM0_CH2 */ 3366 #define SET_EPWM0_CH2_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH2_PA3_Msk)) | EPWM0_CH2_PA3 /*!< Set PA3 function to EPWM0_CH2 */ 3367 #define SET_EPWM0_CH2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH2_PB3_Msk)) | EPWM0_CH2_PB3 /*!< Set PB3 function to EPWM0_CH2 */ 3368 #define SET_EPWM0_CH3_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH3_PA2_Msk)) | EPWM0_CH3_PA2 /*!< Set PA2 function to EPWM0_CH3 */ 3369 #define SET_EPWM0_CH3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH3_PB2_Msk)) | EPWM0_CH3_PB2 /*!< Set PB2 function to EPWM0_CH3 */ 3370 #define SET_EPWM0_CH3_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH3_PE11_Msk)) | EPWM0_CH3_PE11 /*!< Set PE11 function to EPWM0_CH3 */ 3371 #define SET_EPWM0_CH3_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH3_PE4_Msk)) | EPWM0_CH3_PE4 /*!< Set PE4 function to EPWM0_CH3 */ 3372 #define SET_EPWM0_CH4_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH4_PE3_Msk)) | EPWM0_CH4_PE3 /*!< Set PE3 function to EPWM0_CH4 */ 3373 #define SET_EPWM0_CH4_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~EPWM0_CH4_PD14_Msk)) | EPWM0_CH4_PD14 /*!< Set PD14 function to EPWM0_CH4 */ 3374 #define SET_EPWM0_CH4_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH4_PA1_Msk)) | EPWM0_CH4_PA1 /*!< Set PA1 function to EPWM0_CH4 */ 3375 #define SET_EPWM0_CH4_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH4_PE12_Msk)) | EPWM0_CH4_PE12 /*!< Set PE12 function to EPWM0_CH4 */ 3376 #define SET_EPWM0_CH4_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH4_PB1_Msk)) | EPWM0_CH4_PB1 /*!< Set PB1 function to EPWM0_CH4 */ 3377 #define SET_EPWM0_CH5_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM0_CH5_PA0_Msk)) | EPWM0_CH5_PA0 /*!< Set PA0 function to EPWM0_CH5 */ 3378 #define SET_EPWM0_CH5_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM0_CH5_PB0_Msk)) | EPWM0_CH5_PB0 /*!< Set PB0 function to EPWM0_CH5 */ 3379 #define SET_EPWM0_CH5_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM0_CH5_PE13_Msk)) | EPWM0_CH5_PE13 /*!< Set PE13 function to EPWM0_CH5 */ 3380 #define SET_EPWM0_CH5_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~EPWM0_CH5_PE2_Msk)) | EPWM0_CH5_PE2 /*!< Set PE2 function to EPWM0_CH5 */ 3381 #define SET_EPWM0_CH5_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~EPWM0_CH5_PH11_Msk)) | EPWM0_CH5_PH11 /*!< Set PH11 function to EPWM0_CH5 */ 3382 #define SET_EPWM0_SYNC_IN_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_IN_PA15_Msk)) | EPWM0_SYNC_IN_PA15/*!< Set PA15 function to EPWM0_SYNC_IN */ 3383 #define SET_EPWM0_SYNC_OUT_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~EPWM0_SYNC_OUT_PA11_Msk)) | EPWM0_SYNC_OUT_PA11/*!< Set PA11 function to EPWM0_SYNC_OUT */ 3384 #define SET_EPWM0_SYNC_OUT_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~EPWM0_SYNC_OUT_PF5_Msk)) | EPWM0_SYNC_OUT_PF5/*!< Set PF5 function to EPWM0_SYNC_OUT */ 3385 #define SET_EPWM1_BRAKE0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE0_PB7_Msk)) | EPWM1_BRAKE0_PB7 /*!< Set PB7 function to EPWM1_BRAKE0 */ 3386 #define SET_EPWM1_BRAKE0_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE0_PE10_Msk)) | EPWM1_BRAKE0_PE10 /*!< Set PE10 function to EPWM1_BRAKE0 */ 3387 #define SET_EPWM1_BRAKE1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_BRAKE1_PB6_Msk)) | EPWM1_BRAKE1_PB6 /*!< Set PB6 function to EPWM1_BRAKE1 */ 3388 #define SET_EPWM1_BRAKE1_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_BRAKE1_PA3_Msk)) | EPWM1_BRAKE1_PA3 /*!< Set PA3 function to EPWM1_BRAKE1 */ 3389 #define SET_EPWM1_BRAKE1_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_BRAKE1_PE11_Msk)) | EPWM1_BRAKE1_PE11 /*!< Set PE11 function to EPWM1_BRAKE1 */ 3390 #define SET_EPWM1_CH0_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~EPWM1_CH0_PE13_Msk)) | EPWM1_CH0_PE13 /*!< Set PE13 function to EPWM1_CH0 */ 3391 #define SET_EPWM1_CH0_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH0_PC12_Msk)) | EPWM1_CH0_PC12 /*!< Set PC12 function to EPWM1_CH0 */ 3392 #define SET_EPWM1_CH0_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH0_PB15_Msk)) | EPWM1_CH0_PB15 /*!< Set PB15 function to EPWM1_CH0 */ 3393 #define SET_EPWM1_CH0_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH0_PC5_Msk)) | EPWM1_CH0_PC5 /*!< Set PC5 function to EPWM1_CH0 */ 3394 #define SET_EPWM1_CH1_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC8_Msk)) | EPWM1_CH1_PC8 /*!< Set PC8 function to EPWM1_CH1 */ 3395 #define SET_EPWM1_CH1_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH1_PC11_Msk)) | EPWM1_CH1_PC11 /*!< Set PC11 function to EPWM1_CH1 */ 3396 #define SET_EPWM1_CH1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH1_PB14_Msk)) | EPWM1_CH1_PB14 /*!< Set PB14 function to EPWM1_CH1 */ 3397 #define SET_EPWM1_CH1_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH1_PC4_Msk)) | EPWM1_CH1_PC4 /*!< Set PC4 function to EPWM1_CH1 */ 3398 #define SET_EPWM1_CH2_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC7_Msk)) | EPWM1_CH2_PC7 /*!< Set PC7 function to EPWM1_CH2 */ 3399 #define SET_EPWM1_CH2_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH2_PC3_Msk)) | EPWM1_CH2_PC3 /*!< Set PC3 function to EPWM1_CH2 */ 3400 #define SET_EPWM1_CH2_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH2_PC10_Msk)) | EPWM1_CH2_PC10 /*!< Set PC10 function to EPWM1_CH2 */ 3401 #define SET_EPWM1_CH2_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH2_PB13_Msk)) | EPWM1_CH2_PB13 /*!< Set PB13 function to EPWM1_CH2 */ 3402 #define SET_EPWM1_CH3_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC6_Msk)) | EPWM1_CH3_PC6 /*!< Set PC6 function to EPWM1_CH3 */ 3403 #define SET_EPWM1_CH3_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH3_PC2_Msk)) | EPWM1_CH3_PC2 /*!< Set PC2 function to EPWM1_CH3 */ 3404 #define SET_EPWM1_CH3_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~EPWM1_CH3_PB12_Msk)) | EPWM1_CH3_PB12 /*!< Set PB12 function to EPWM1_CH3 */ 3405 #define SET_EPWM1_CH3_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~EPWM1_CH3_PC9_Msk)) | EPWM1_CH3_PC9 /*!< Set PC9 function to EPWM1_CH3 */ 3406 #define SET_EPWM1_CH4_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH4_PC1_Msk)) | EPWM1_CH4_PC1 /*!< Set PC1 function to EPWM1_CH4 */ 3407 #define SET_EPWM1_CH4_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB1_Msk)) | EPWM1_CH4_PB1 /*!< Set PB1 function to EPWM1_CH4 */ 3408 #define SET_EPWM1_CH4_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH4_PB7_Msk)) | EPWM1_CH4_PB7 /*!< Set PB7 function to EPWM1_CH4 */ 3409 #define SET_EPWM1_CH4_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH4_PA7_Msk)) | EPWM1_CH4_PA7 /*!< Set PA7 function to EPWM1_CH4 */ 3410 #define SET_EPWM1_CH5_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB6_Msk)) | EPWM1_CH5_PB6 /*!< Set PB6 function to EPWM1_CH5 */ 3411 #define SET_EPWM1_CH5_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~EPWM1_CH5_PC0_Msk)) | EPWM1_CH5_PC0 /*!< Set PC0 function to EPWM1_CH5 */ 3412 #define SET_EPWM1_CH5_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~EPWM1_CH5_PB0_Msk)) | EPWM1_CH5_PB0 /*!< Set PB0 function to EPWM1_CH5 */ 3413 #define SET_EPWM1_CH5_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~EPWM1_CH5_PA6_Msk)) | EPWM1_CH5_PA6 /*!< Set PA6 function to EPWM1_CH5 */ 3414 #define SET_I2C0_SCL_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2C0_SCL_PE13_Msk)) | I2C0_SCL_PE13 /*!< Set PE13 function to I2C0_SCL */ 3415 #define SET_I2C0_SCL_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SCL_PB9_Msk)) | I2C0_SCL_PB9 /*!< Set PB9 function to I2C0_SCL */ 3416 #define SET_I2C0_SCL_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SCL_PD7_Msk)) | I2C0_SCL_PD7 /*!< Set PD7 function to I2C0_SCL */ 3417 #define SET_I2C0_SCL_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SCL_PA5_Msk)) | I2C0_SCL_PA5 /*!< Set PA5 function to I2C0_SCL */ 3418 #define SET_I2C0_SCL_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SCL_PB5_Msk)) | I2C0_SCL_PB5 /*!< Set PB5 function to I2C0_SCL */ 3419 #define SET_I2C0_SCL_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SCL_PC1_Msk)) | I2C0_SCL_PC1 /*!< Set PC1 function to I2C0_SCL */ 3420 #define SET_I2C0_SCL_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SCL_PC12_Msk)) | I2C0_SCL_PC12 /*!< Set PC12 function to I2C0_SCL */ 3421 #define SET_I2C0_SCL_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SCL_PF3_Msk)) | I2C0_SCL_PF3 /*!< Set PF3 function to I2C0_SCL */ 3422 #define SET_I2C0_SDA_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C0_SDA_PB4_Msk)) | I2C0_SDA_PB4 /*!< Set PB4 function to I2C0_SDA */ 3423 #define SET_I2C0_SDA_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C0_SDA_PD6_Msk)) | I2C0_SDA_PD6 /*!< Set PD6 function to I2C0_SDA */ 3424 #define SET_I2C0_SDA_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C0_SDA_PB8_Msk)) | I2C0_SDA_PB8 /*!< Set PB8 function to I2C0_SDA */ 3425 #define SET_I2C0_SDA_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC11_Msk)) | I2C0_SDA_PC11 /*!< Set PC11 function to I2C0_SDA */ 3426 #define SET_I2C0_SDA_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C0_SDA_PF2_Msk)) | I2C0_SDA_PF2 /*!< Set PF2 function to I2C0_SDA */ 3427 #define SET_I2C0_SDA_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SDA_PC0_Msk)) | I2C0_SDA_PC0 /*!< Set PC0 function to I2C0_SDA */ 3428 #define SET_I2C0_SDA_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~I2C0_SDA_PC8_Msk)) | I2C0_SDA_PC8 /*!< Set PC8 function to I2C0_SDA */ 3429 #define SET_I2C0_SDA_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SDA_PA4_Msk)) | I2C0_SDA_PA4 /*!< Set PA4 function to I2C0_SDA */ 3430 #define SET_I2C0_SMBAL_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBAL_PA3_Msk)) | I2C0_SMBAL_PA3 /*!< Set PA3 function to I2C0_SMBAL */ 3431 #define SET_I2C0_SMBAL_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBAL_PG2_Msk)) | I2C0_SMBAL_PG2 /*!< Set PG2 function to I2C0_SMBAL */ 3432 #define SET_I2C0_SMBAL_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBAL_PC3_Msk)) | I2C0_SMBAL_PC3 /*!< Set PC3 function to I2C0_SMBAL */ 3433 #define SET_I2C0_SMBSUS_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C0_SMBSUS_PA2_Msk)) | I2C0_SMBSUS_PA2 /*!< Set PA2 function to I2C0_SMBSUS */ 3434 #define SET_I2C0_SMBSUS_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C0_SMBSUS_PC2_Msk)) | I2C0_SMBSUS_PC2 /*!< Set PC2 function to I2C0_SMBSUS */ 3435 #define SET_I2C0_SMBSUS_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C0_SMBSUS_PG3_Msk)) | I2C0_SMBSUS_PG3 /*!< Set PG3 function to I2C0_SMBSUS */ 3436 #define SET_I2C1_SCL_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB1_Msk)) | I2C1_SCL_PB1 /*!< Set PB1 function to I2C1_SCL */ 3437 #define SET_I2C1_SCL_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SCL_PE1_Msk)) | I2C1_SCL_PE1 /*!< Set PE1 function to I2C1_SCL */ 3438 #define SET_I2C1_SCL_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SCL_PF0_Msk)) | I2C1_SCL_PF0 /*!< Set PF0 function to I2C1_SCL */ 3439 #define SET_I2C1_SCL_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SCL_PA12_Msk)) | I2C1_SCL_PA12 /*!< Set PA12 function to I2C1_SCL */ 3440 #define SET_I2C1_SCL_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA7_Msk)) | I2C1_SCL_PA7 /*!< Set PA7 function to I2C1_SCL */ 3441 #define SET_I2C1_SCL_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SCL_PB11_Msk)) | I2C1_SCL_PB11 /*!< Set PB11 function to I2C1_SCL */ 3442 #define SET_I2C1_SCL_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SCL_PG2_Msk)) | I2C1_SCL_PG2 /*!< Set PG2 function to I2C1_SCL */ 3443 #define SET_I2C1_SCL_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SCL_PA3_Msk)) | I2C1_SCL_PA3 /*!< Set PA3 function to I2C1_SCL */ 3444 #define SET_I2C1_SCL_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SCL_PC5_Msk)) | I2C1_SCL_PC5 /*!< Set PC5 function to I2C1_SCL */ 3445 #define SET_I2C1_SCL_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SCL_PD5_Msk)) | I2C1_SCL_PD5 /*!< Set PD5 function to I2C1_SCL */ 3446 #define SET_I2C1_SCL_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SCL_PB3_Msk)) | I2C1_SCL_PB3 /*!< Set PB3 function to I2C1_SCL */ 3447 #define SET_I2C1_SDA_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA2_Msk)) | I2C1_SDA_PA2 /*!< Set PA2 function to I2C1_SDA */ 3448 #define SET_I2C1_SDA_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SDA_PB10_Msk)) | I2C1_SDA_PB10 /*!< Set PB10 function to I2C1_SDA */ 3449 #define SET_I2C1_SDA_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2C1_SDA_PF1_Msk)) | I2C1_SDA_PF1 /*!< Set PF1 function to I2C1_SDA */ 3450 #define SET_I2C1_SDA_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB2_Msk)) | I2C1_SDA_PB2 /*!< Set PB2 function to I2C1_SDA */ 3451 #define SET_I2C1_SDA_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C1_SDA_PD4_Msk)) | I2C1_SDA_PD4 /*!< Set PD4 function to I2C1_SDA */ 3452 #define SET_I2C1_SDA_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C1_SDA_PA13_Msk)) | I2C1_SDA_PA13 /*!< Set PA13 function to I2C1_SDA */ 3453 #define SET_I2C1_SDA_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C1_SDA_PA6_Msk)) | I2C1_SDA_PA6 /*!< Set PA6 function to I2C1_SDA */ 3454 #define SET_I2C1_SDA_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2C1_SDA_PE0_Msk)) | I2C1_SDA_PE0 /*!< Set PE0 function to I2C1_SDA */ 3455 #define SET_I2C1_SDA_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~I2C1_SDA_PG3_Msk)) | I2C1_SDA_PG3 /*!< Set PG3 function to I2C1_SDA */ 3456 #define SET_I2C1_SDA_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SDA_PC4_Msk)) | I2C1_SDA_PC4 /*!< Set PC4 function to I2C1_SDA */ 3457 #define SET_I2C1_SDA_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2C1_SDA_PB0_Msk)) | I2C1_SDA_PB0 /*!< Set PB0 function to I2C1_SDA */ 3458 #define SET_I2C1_SMBAL_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBAL_PB9_Msk)) | I2C1_SMBAL_PB9 /*!< Set PB9 function to I2C1_SMBAL */ 3459 #define SET_I2C1_SMBAL_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBAL_PH8_Msk)) | I2C1_SMBAL_PH8 /*!< Set PH8 function to I2C1_SMBAL */ 3460 #define SET_I2C1_SMBAL_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBAL_PC7_Msk)) | I2C1_SMBAL_PC7 /*!< Set PC7 function to I2C1_SMBAL */ 3461 #define SET_I2C1_SMBSUS_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2C1_SMBSUS_PC6_Msk)) | I2C1_SMBSUS_PC6 /*!< Set PC6 function to I2C1_SMBSUS */ 3462 #define SET_I2C1_SMBSUS_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C1_SMBSUS_PB8_Msk)) | I2C1_SMBSUS_PB8 /*!< Set PB8 function to I2C1_SMBSUS */ 3463 #define SET_I2C1_SMBSUS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C1_SMBSUS_PH9_Msk)) | I2C1_SMBSUS_PH9 /*!< Set PH9 function to I2C1_SMBSUS */ 3464 #define SET_I2C2_SCL_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA14_Msk)) | I2C2_SCL_PA14 /*!< Set PA14 function to I2C2_SCL */ 3465 #define SET_I2C2_SCL_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SCL_PH8_Msk)) | I2C2_SCL_PH8 /*!< Set PH8 function to I2C2_SCL */ 3466 #define SET_I2C2_SCL_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SCL_PA11_Msk)) | I2C2_SCL_PA11 /*!< Set PA11 function to I2C2_SCL */ 3467 #define SET_I2C2_SCL_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SCL_PB13_Msk)) | I2C2_SCL_PB13 /*!< Set PB13 function to I2C2_SCL */ 3468 #define SET_I2C2_SCL_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SCL_PD9_Msk)) | I2C2_SCL_PD9 /*!< Set PD9 function to I2C2_SCL */ 3469 #define SET_I2C2_SCL_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SCL_PA1_Msk)) | I2C2_SCL_PA1 /*!< Set PA1 function to I2C2_SCL */ 3470 #define SET_I2C2_SCL_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SCL_PD1_Msk)) | I2C2_SCL_PD1 /*!< Set PD1 function to I2C2_SCL */ 3471 #define SET_I2C2_SDA_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~I2C2_SDA_PD8_Msk)) | I2C2_SDA_PD8 /*!< Set PD8 function to I2C2_SDA */ 3472 #define SET_I2C2_SDA_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~I2C2_SDA_PD0_Msk)) | I2C2_SDA_PD0 /*!< Set PD0 function to I2C2_SDA */ 3473 #define SET_I2C2_SDA_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA15_Msk)) | I2C2_SDA_PA15 /*!< Set PA15 function to I2C2_SDA */ 3474 #define SET_I2C2_SDA_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2C2_SDA_PH9_Msk)) | I2C2_SDA_PH9 /*!< Set PH9 function to I2C2_SDA */ 3475 #define SET_I2C2_SDA_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2C2_SDA_PA10_Msk)) | I2C2_SDA_PA10 /*!< Set PA10 function to I2C2_SDA */ 3476 #define SET_I2C2_SDA_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~I2C2_SDA_PA0_Msk)) | I2C2_SDA_PA0 /*!< Set PA0 function to I2C2_SDA */ 3477 #define SET_I2C2_SDA_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SDA_PB12_Msk)) | I2C2_SDA_PB12 /*!< Set PB12 function to I2C2_SDA */ 3478 #define SET_I2C2_SMBAL_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBAL_PB15_Msk)) | I2C2_SMBAL_PB15 /*!< Set PB15 function to I2C2_SMBAL */ 3479 #define SET_I2C2_SMBSUS_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~I2C2_SMBSUS_PB14_Msk)) | I2C2_SMBSUS_PB14 /*!< Set PB14 function to I2C2_SMBSUS */ 3480 #define SET_I2S0_BCLK_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_BCLK_PF10_Msk)) | I2S0_BCLK_PF10 /*!< Set PF10 function to I2S0_BCLK */ 3481 #define SET_I2S0_BCLK_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_BCLK_PB5_Msk)) | I2S0_BCLK_PB5 /*!< Set PB5 function to I2S0_BCLK */ 3482 #define SET_I2S0_BCLK_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_BCLK_PE1_Msk)) | I2S0_BCLK_PE1 /*!< Set PE1 function to I2S0_BCLK */ 3483 #define SET_I2S0_BCLK_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_BCLK_PA12_Msk)) | I2S0_BCLK_PA12 /*!< Set PA12 function to I2S0_BCLK */ 3484 #define SET_I2S0_BCLK_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_BCLK_PC4_Msk)) | I2S0_BCLK_PC4 /*!< Set PC4 function to I2S0_BCLK */ 3485 #define SET_I2S0_BCLK_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_BCLK_PE8_Msk)) | I2S0_BCLK_PE8 /*!< Set PE8 function to I2S0_BCLK */ 3486 #define SET_I2S0_DI_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DI_PC2_Msk)) | I2S0_DI_PC2 /*!< Set PC2 function to I2S0_DI */ 3487 #define SET_I2S0_DI_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DI_PE10_Msk)) | I2S0_DI_PE10 /*!< Set PE10 function to I2S0_DI */ 3488 #define SET_I2S0_DI_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_DI_PF8_Msk)) | I2S0_DI_PF8 /*!< Set PF8 function to I2S0_DI */ 3489 #define SET_I2S0_DI_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DI_PH8_Msk)) | I2S0_DI_PH8 /*!< Set PH8 function to I2S0_DI */ 3490 #define SET_I2S0_DI_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DI_PB3_Msk)) | I2S0_DI_PB3 /*!< Set PB3 function to I2S0_DI */ 3491 #define SET_I2S0_DI_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DI_PA14_Msk)) | I2S0_DI_PA14 /*!< Set PA14 function to I2S0_DI */ 3492 #define SET_I2S0_DO_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_DO_PH9_Msk)) | I2S0_DO_PH9 /*!< Set PH9 function to I2S0_DO */ 3493 #define SET_I2S0_DO_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_DO_PC1_Msk)) | I2S0_DO_PC1 /*!< Set PC1 function to I2S0_DO */ 3494 #define SET_I2S0_DO_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_DO_PA15_Msk)) | I2S0_DO_PA15 /*!< Set PA15 function to I2S0_DO */ 3495 #define SET_I2S0_DO_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_DO_PB2_Msk)) | I2S0_DO_PB2 /*!< Set PB2 function to I2S0_DO */ 3496 #define SET_I2S0_DO_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_DO_PF7_Msk)) | I2S0_DO_PF7 /*!< Set PF7 function to I2S0_DO */ 3497 #define SET_I2S0_DO_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_DO_PE11_Msk)) | I2S0_DO_PE11 /*!< Set PE11 function to I2S0_DO */ 3498 #define SET_I2S0_LRCK_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_LRCK_PC0_Msk)) | I2S0_LRCK_PC0 /*!< Set PC0 function to I2S0_LRCK */ 3499 #define SET_I2S0_LRCK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_LRCK_PB1_Msk)) | I2S0_LRCK_PB1 /*!< Set PB1 function to I2S0_LRCK */ 3500 #define SET_I2S0_LRCK_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~I2S0_LRCK_PH10_Msk)) | I2S0_LRCK_PH10 /*!< Set PH10 function to I2S0_LRCK */ 3501 #define SET_I2S0_LRCK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~I2S0_LRCK_PF6_Msk)) | I2S0_LRCK_PF6 /*!< Set PF6 function to I2S0_LRCK */ 3502 #define SET_I2S0_LRCK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_LRCK_PE12_Msk)) | I2S0_LRCK_PE12 /*!< Set PE12 function to I2S0_LRCK */ 3503 #define SET_I2S0_MCLK_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~I2S0_MCLK_PC3_Msk)) | I2S0_MCLK_PC3 /*!< Set PC3 function to I2S0_MCLK */ 3504 #define SET_I2S0_MCLK_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~I2S0_MCLK_PF9_Msk)) | I2S0_MCLK_PF9 /*!< Set PF9 function to I2S0_MCLK */ 3505 #define SET_I2S0_MCLK_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~I2S0_MCLK_PE0_Msk)) | I2S0_MCLK_PE0 /*!< Set PE0 function to I2S0_MCLK */ 3506 #define SET_I2S0_MCLK_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~I2S0_MCLK_PB4_Msk)) | I2S0_MCLK_PB4 /*!< Set PB4 function to I2S0_MCLK */ 3507 #define SET_I2S0_MCLK_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~I2S0_MCLK_PA13_Msk)) | I2S0_MCLK_PA13 /*!< Set PA13 function to I2S0_MCLK */ 3508 #define SET_I2S0_MCLK_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~I2S0_MCLK_PE9_Msk)) | I2S0_MCLK_PE9 /*!< Set PE9 function to I2S0_MCLK */ 3509 #define SET_ICE_CLK_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_CLK_PF1_Msk)) | ICE_CLK_PF1 /*!< Set PF1 function to ICE_CLK */ 3510 #define SET_ICE_DAT_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~ICE_DAT_PF0_Msk)) | ICE_DAT_PF0 /*!< Set PF0 function to ICE_DAT */ 3511 #define SET_INT0_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT0_PA6_Msk)) | INT0_PA6 /*!< Set PA6 function to INT0 */ 3512 #define SET_INT0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT0_PB5_Msk)) | INT0_PB5 /*!< Set PB5 function to INT0 */ 3513 #define SET_INT1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT1_PB4_Msk)) | INT1_PB4 /*!< Set PB4 function to INT1 */ 3514 #define SET_INT1_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~INT1_PA7_Msk)) | INT1_PA7 /*!< Set PA7 function to INT1 */ 3515 #define SET_INT2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT2_PB3_Msk)) | INT2_PB3 /*!< Set PB3 function to INT2 */ 3516 #define SET_INT2_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT2_PC6_Msk)) | INT2_PC6 /*!< Set PC6 function to INT2 */ 3517 #define SET_INT3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT3_PB2_Msk)) | INT3_PB2 /*!< Set PB2 function to INT3 */ 3518 #define SET_INT3_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~INT3_PC7_Msk)) | INT3_PC7 /*!< Set PC7 function to INT3 */ 3519 #define SET_INT4_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~INT4_PA8_Msk)) | INT4_PA8 /*!< Set PA8 function to INT4 */ 3520 #define SET_INT4_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT4_PB6_Msk)) | INT4_PB6 /*!< Set PB6 function to INT4 */ 3521 #define SET_INT5_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~INT5_PB7_Msk)) | INT5_PB7 /*!< Set PB7 function to INT5 */ 3522 #define SET_INT5_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT5_PD12_Msk)) | INT5_PD12 /*!< Set PD12 function to INT5 */ 3523 #define SET_INT6_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT6_PD11_Msk)) | INT6_PD11 /*!< Set PD11 function to INT6 */ 3524 #define SET_INT6_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT6_PB8_Msk)) | INT6_PB8 /*!< Set PB8 function to INT6 */ 3525 #define SET_INT7_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~INT7_PB9_Msk)) | INT7_PB9 /*!< Set PB9 function to INT7 */ 3526 #define SET_INT7_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~INT7_PD10_Msk)) | INT7_PD10 /*!< Set PD10 function to INT7 */ 3527 #define SET_LCD_COM0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM0_PC0_Msk)) | LCD_COM0_PC0 /*!< Set PC0 function to LCD_COM0 */ 3528 #define SET_LCD_COM1_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM1_PC1_Msk)) | LCD_COM1_PC1 /*!< Set PC1 function to LCD_COM1 */ 3529 #define SET_LCD_COM2_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM2_PC2_Msk)) | LCD_COM2_PC2 /*!< Set PC2 function to LCD_COM2 */ 3530 #define SET_LCD_COM3_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM3_PC3_Msk)) | LCD_COM3_PC3 /*!< Set PC3 function to LCD_COM3 */ 3531 #define SET_LCD_COM4_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM4_PC4_Msk)) | LCD_COM4_PC4 /*!< Set PC4 function to LCD_COM4 */ 3532 #define SET_LCD_COM5_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_COM5_PC5_Msk)) | LCD_COM5_PC5 /*!< Set PC5 function to LCD_COM5 */ 3533 #define SET_LCD_COM6_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM6_PA0_Msk)) | LCD_COM6_PA0 /*!< Set PA0 function to LCD_COM6 */ 3534 #define SET_LCD_COM6_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM6_PD8_Msk)) | LCD_COM6_PD8 /*!< Set PD8 function to LCD_SEG41 */ 3535 #define SET_LCD_COM7_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_COM7_PA1_Msk)) | LCD_COM7_PA1 /*!< Set PA1 function to LCD_COM7 */ 3536 #define SET_LCD_COM7_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_COM7_PD9_Msk)) | LCD_COM7_PD9 /*!< Set PD9 function to LCD_COM7 */ 3537 #define SET_LCD_SEG0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG0_PD14_Msk)) | LCD_SEG0_PD14 /*!< Set PD14 function to LCD_SEG0 */ 3538 #define SET_LCD_SEG0_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG0_PD1_Msk)) | LCD_SEG0_PD1 /*!< Set PD1 function to LCD_SEG0 */ 3539 #define SET_LCD_SEG1_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG1_PD2_Msk)) | LCD_SEG1_PD2 /*!< Set PD2 function to LCD_SEG1 */ 3540 #define SET_LCD_SEG1_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG1_PH11_Msk)) | LCD_SEG1_PH11 /*!< Set PH11 function to LCD_SEG1 */ 3541 #define SET_LCD_SEG10_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG10_PC7_Msk)) | LCD_SEG10_PC7 /*!< Set PC7 function to LCD_SEG10 */ 3542 #define SET_LCD_SEG10_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG10_PE5_Msk)) | LCD_SEG10_PE5 /*!< Set PE5 function to LCD_SEG10 */ 3543 #define SET_LCD_SEG11_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG11_PA8_Msk)) | LCD_SEG11_PA8 /*!< Set PA8 function to LCD_SEG11 */ 3544 #define SET_LCD_SEG11_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG11_PE6_Msk)) | LCD_SEG11_PE6 /*!< Set PE6 function to LCD_SEG11 */ 3545 #define SET_LCD_SEG12_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~LCD_SEG12_PA9_Msk)) | LCD_SEG12_PA9 /*!< Set PA9 function to LCD_SEG12 */ 3546 #define SET_LCD_SEG12_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG12_PE7_Msk)) | LCD_SEG12_PE7 /*!< Set PE7 function to LCD_SEG12 */ 3547 #define SET_LCD_SEG13_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG13_PD6_Msk)) | LCD_SEG13_PD6 /*!< Set PD6 function to LCD_SEG13 */ 3548 #define SET_LCD_SEG13_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG13_PA1_Msk)) | LCD_SEG13_PA1 /*!< Set PA1 function to LCD_SEG13 */ 3549 #define SET_LCD_SEG14_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG14_PD7_Msk)) | LCD_SEG14_PD7 /*!< Set PD7 function to LCD_SEG14 */ 3550 #define SET_LCD_SEG14_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG14_PA0_Msk)) | LCD_SEG14_PA0 /*!< Set PA0 function to LCD_SEG14 */ 3551 #define SET_LCD_SEG15_PG15() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG15_PG15_Msk)) | LCD_SEG15_PG15 /*!< Set PG15 function to LCD_SEG15 */ 3552 #define SET_LCD_SEG16_PG14() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG16_PG14_Msk)) | LCD_SEG16_PG14 /*!< Set PG14 function to LCD_SEG16 */ 3553 #define SET_LCD_SEG17_PG13() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG17_PG13_Msk)) | LCD_SEG17_PG13 /*!< Set PG13 function to LCD_SEG17 */ 3554 #define SET_LCD_SEG18_PG12() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG18_PG12_Msk)) | LCD_SEG18_PG12 /*!< Set PG12 function to LCD_SEG18 */ 3555 #define SET_LCD_SEG19_PG11() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG19_PG11_Msk)) | LCD_SEG19_PG11 /*!< Set PG11 function to LCD_SEG19 */ 3556 #define SET_LCD_SEG2_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG2_PH10_Msk)) | LCD_SEG2_PH10 /*!< Set PH10 function to LCD_SEG2 */ 3557 #define SET_LCD_SEG2_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~LCD_SEG2_PD3_Msk)) | LCD_SEG2_PD3 /*!< Set PD3 function to LCD_SEG2 */ 3558 #define SET_LCD_SEG20_PG10() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG20_PG10_Msk)) | LCD_SEG20_PG10 /*!< Set PG10 function to LCD_SEG20 */ 3559 #define SET_LCD_SEG21_PG9() SYS->GPG_MFPH = (SYS->GPG_MFPH & (~LCD_SEG21_PG9_Msk)) | LCD_SEG21_PG9 /*!< Set PG9 function to LCD_SEG21 */ 3560 #define SET_LCD_SEG22_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG22_PE15_Msk)) | LCD_SEG22_PE15 /*!< Set PE15 function to LCD_SEG22 */ 3561 #define SET_LCD_SEG23_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG23_PE14_Msk)) | LCD_SEG23_PE14 /*!< Set PE14 function to LCD_SEG23 */ 3562 #define SET_LCD_SEG24_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG24_PA0_Msk)) | LCD_SEG24_PA0 /*!< Set PA0 function to LCD_SEG24 */ 3563 #define SET_LCD_SEG25_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG25_PA1_Msk)) | LCD_SEG25_PA1 /*!< Set PA1 function to LCD_SEG25 */ 3564 #define SET_LCD_SEG26_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG26_PA2_Msk)) | LCD_SEG26_PA2 /*!< Set PA2 function to LCD_SEG26 */ 3565 #define SET_LCD_SEG27_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG27_PA3_Msk)) | LCD_SEG27_PA3 /*!< Set PA3 function to LCD_SEG27 */ 3566 #define SET_LCD_SEG28_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG28_PA4_Msk)) | LCD_SEG28_PA4 /*!< Set PA4 function to LCD_SEG28 */ 3567 #define SET_LCD_SEG29_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG29_PA5_Msk)) | LCD_SEG29_PA5 /*!< Set PA5 function to LCD_SEG29 */ 3568 #define SET_LCD_SEG3_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG3_PA2_Msk)) | LCD_SEG3_PA2 /*!< Set PA2 function to LCD_SEG3 */ 3569 #define SET_LCD_SEG3_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG3_PH9_Msk)) | LCD_SEG3_PH9 /*!< Set PH9 function to LCD_SEG3 */ 3570 #define SET_LCD_SEG30_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG30_PE10_Msk)) | LCD_SEG30_PE10 /*!< Set PE10 function to LCD_SEG30 */ 3571 #define SET_LCD_SEG31_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG31_PE9_Msk)) | LCD_SEG31_PE9 /*!< Set PE9 function to LCD_SEG31 */ 3572 #define SET_LCD_SEG32_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~LCD_SEG32_PE8_Msk)) | LCD_SEG32_PE8 /*!< Set PE8 function to LCD_SEG32 */ 3573 #define SET_LCD_SEG33_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG33_PH7_Msk)) | LCD_SEG33_PH7 /*!< Set PH7 function to LCD_SEG33 */ 3574 #define SET_LCD_SEG34_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG34_PH6_Msk)) | LCD_SEG34_PH6 /*!< Set PH6 function to LCD_SEG34 */ 3575 #define SET_LCD_SEG35_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG35_PH5_Msk)) | LCD_SEG35_PH5 /*!< Set PH5 function to LCD_SEG35 */ 3576 #define SET_LCD_SEG36_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~LCD_SEG36_PH4_Msk)) | LCD_SEG36_PH4 /*!< Set PH4 function to LCD_SEG36 */ 3577 #define SET_LCD_SEG37_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG37_PG4_Msk)) | LCD_SEG37_PG4 /*!< Set PG4 function to LCD_SEG37 */ 3578 #define SET_LCD_SEG38_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG38_PG3_Msk)) | LCD_SEG38_PG3 /*!< Set PG3 function to LCD_SEG38 */ 3579 #define SET_LCD_SEG39_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~LCD_SEG39_PG2_Msk)) | LCD_SEG39_PG2 /*!< Set PG2 function to LCD_SEG39 */ 3580 #define SET_LCD_SEG4_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~LCD_SEG4_PH8_Msk)) | LCD_SEG4_PH8 /*!< Set PH8 function to LCD_SEG4 */ 3581 #define SET_LCD_SEG4_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG4_PA3_Msk)) | LCD_SEG4_PA3 /*!< Set PA3 function to LCD_SEG4 */ 3582 #define SET_LCD_SEG40_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG40_PD9_Msk)) | LCD_SEG40_PD9 /*!< Set PD9 function to LCD_SEG40 */ 3583 #define SET_LCD_SEG41_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~LCD_SEG41_PD8_Msk)) | LCD_SEG41_PD8 /*!< Set PD8 function to LCD_SEG41 */ 3584 #define SET_LCD_SEG42_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG42_PC5_Msk)) | LCD_SEG42_PC5 /*!< Set PC5 function to LCD_SEG42 */ 3585 #define SET_LCD_SEG43_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG43_PC4_Msk)) | LCD_SEG43_PC4 /*!< Set PC4 function to LCD_SEG43 */ 3586 #define SET_LCD_SEG5_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG5_PA4_Msk)) | LCD_SEG5_PA4 /*!< Set PA4 function to LCD_SEG5 */ 3587 #define SET_LCD_SEG5_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG5_PE0_Msk)) | LCD_SEG5_PE0 /*!< Set PE0 function to LCD_SEG5 */ 3588 #define SET_LCD_SEG6_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG6_PE1_Msk)) | LCD_SEG6_PE1 /*!< Set PE1 function to LCD_SEG6 */ 3589 #define SET_LCD_SEG6_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG6_PA5_Msk)) | LCD_SEG6_PA5 /*!< Set PA5 function to LCD_SEG6 */ 3590 #define SET_LCD_SEG7_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG7_PA6_Msk)) | LCD_SEG7_PA6 /*!< Set PA6 function to LCD_SEG7 */ 3591 #define SET_LCD_SEG7_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG7_PE2_Msk)) | LCD_SEG7_PE2 /*!< Set PE2 function to LCD_SEG7 */ 3592 #define SET_LCD_SEG8_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG8_PE3_Msk)) | LCD_SEG8_PE3 /*!< Set PE3 function to LCD_SEG8 */ 3593 #define SET_LCD_SEG8_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~LCD_SEG8_PA7_Msk)) | LCD_SEG8_PA7 /*!< Set PA7 function to LCD_SEG8 */ 3594 #define SET_LCD_SEG9_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~LCD_SEG9_PC6_Msk)) | LCD_SEG9_PC6 /*!< Set PC6 function to LCD_SEG9 */ 3595 #define SET_LCD_SEG9_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~LCD_SEG9_PE4_Msk)) | LCD_SEG9_PE4 /*!< Set PE4 function to LCD_SEG9 */ 3596 #define SET_QEI0_A_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_A_PD11_Msk)) | QEI0_A_PD11 /*!< Set PD11 function to QEI0_A */ 3597 #define SET_QEI0_A_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_A_PA4_Msk)) | QEI0_A_PA4 /*!< Set PA4 function to QEI0_A */ 3598 #define SET_QEI0_A_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_A_PE3_Msk)) | QEI0_A_PE3 /*!< Set PE3 function to QEI0_A */ 3599 #define SET_QEI0_B_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_B_PE2_Msk)) | QEI0_B_PE2 /*!< Set PE2 function to QEI0_B */ 3600 #define SET_QEI0_B_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_B_PD10_Msk)) | QEI0_B_PD10 /*!< Set PD10 function to QEI0_B */ 3601 #define SET_QEI0_B_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_B_PA3_Msk)) | QEI0_B_PA3 /*!< Set PA3 function to QEI0_B */ 3602 #define SET_QEI0_INDEX_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI0_INDEX_PE4_Msk)) | QEI0_INDEX_PE4 /*!< Set PE4 function to QEI0_INDEX */ 3603 #define SET_QEI0_INDEX_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QEI0_INDEX_PA5_Msk)) | QEI0_INDEX_PA5 /*!< Set PA5 function to QEI0_INDEX */ 3604 #define SET_QEI0_INDEX_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~QEI0_INDEX_PD12_Msk)) | QEI0_INDEX_PD12 /*!< Set PD12 function to QEI0_INDEX */ 3605 #define SET_QEI1_A_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA13_Msk)) | QEI1_A_PA13 /*!< Set PA13 function to QEI1_A */ 3606 #define SET_QEI1_A_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_A_PE6_Msk)) | QEI1_A_PE6 /*!< Set PE6 function to QEI1_A */ 3607 #define SET_QEI1_A_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_A_PA9_Msk)) | QEI1_A_PA9 /*!< Set PA9 function to QEI1_A */ 3608 #define SET_QEI1_B_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_B_PE5_Msk)) | QEI1_B_PE5 /*!< Set PE5 function to QEI1_B */ 3609 #define SET_QEI1_B_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA8_Msk)) | QEI1_B_PA8 /*!< Set PA8 function to QEI1_B */ 3610 #define SET_QEI1_B_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_B_PA14_Msk)) | QEI1_B_PA14 /*!< Set PA14 function to QEI1_B */ 3611 #define SET_QEI1_INDEX_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA10_Msk)) | QEI1_INDEX_PA10 /*!< Set PA10 function to QEI1_INDEX */ 3612 #define SET_QEI1_INDEX_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QEI1_INDEX_PE7_Msk)) | QEI1_INDEX_PE7 /*!< Set PE7 function to QEI1_INDEX */ 3613 #define SET_QEI1_INDEX_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~QEI1_INDEX_PA12_Msk)) | QEI1_INDEX_PA12 /*!< Set PA12 function to QEI1_INDEX */ 3614 #define SET_QSPI0_CLK_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_CLK_PH8_Msk)) | QSPI0_CLK_PH8 /*!< Set PH8 function to QSPI0_CLK */ 3615 #define SET_QSPI0_CLK_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~QSPI0_CLK_PF2_Msk)) | QSPI0_CLK_PF2 /*!< Set PF2 function to QSPI0_CLK */ 3616 #define SET_QSPI0_CLK_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_CLK_PA2_Msk)) | QSPI0_CLK_PA2 /*!< Set PA2 function to QSPI0_CLK */ 3617 #define SET_QSPI0_CLK_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_CLK_PC2_Msk)) | QSPI0_CLK_PC2 /*!< Set PC2 function to QSPI0_CLK */ 3618 #define SET_QSPI0_MISO0_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO0_PC1_Msk)) | QSPI0_MISO0_PC1 /*!< Set PC1 function to QSPI0_MISO0 */ 3619 #define SET_QSPI0_MISO0_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MISO0_PE1_Msk)) | QSPI0_MISO0_PE1 /*!< Set PE1 function to QSPI0_MISO0 */ 3620 #define SET_QSPI0_MISO0_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO0_PA1_Msk)) | QSPI0_MISO0_PA1 /*!< Set PA1 function to QSPI0_MISO0 */ 3621 #define SET_QSPI0_MISO1_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MISO1_PB1_Msk)) | QSPI0_MISO1_PB1 /*!< Set PB1 function to QSPI0_MISO1 */ 3622 #define SET_QSPI0_MISO1_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MISO1_PC5_Msk)) | QSPI0_MISO1_PC5 /*!< Set PC5 function to QSPI0_MISO1 */ 3623 #define SET_QSPI0_MISO1_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MISO1_PH10_Msk)) | QSPI0_MISO1_PH10 /*!< Set PH10 function to QSPI0_MISO1 */ 3624 #define SET_QSPI0_MISO1_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MISO1_PA5_Msk)) | QSPI0_MISO1_PA5 /*!< Set PA5 function to QSPI0_MISO1 */ 3625 #define SET_QSPI0_MOSI0_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI0_PC0_Msk)) | QSPI0_MOSI0_PC0 /*!< Set PC0 function to QSPI0_MOSI0 */ 3626 #define SET_QSPI0_MOSI0_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~QSPI0_MOSI0_PE0_Msk)) | QSPI0_MOSI0_PE0 /*!< Set PE0 function to QSPI0_MOSI0 */ 3627 #define SET_QSPI0_MOSI0_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI0_PA0_Msk)) | QSPI0_MOSI0_PA0 /*!< Set PA0 function to QSPI0_MOSI0 */ 3628 #define SET_QSPI0_MOSI1_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_MOSI1_PC4_Msk)) | QSPI0_MOSI1_PC4 /*!< Set PC4 function to QSPI0_MOSI1 */ 3629 #define SET_QSPI0_MOSI1_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_MOSI1_PH11_Msk)) | QSPI0_MOSI1_PH11 /*!< Set PH11 function to QSPI0_MOSI1 */ 3630 #define SET_QSPI0_MOSI1_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~QSPI0_MOSI1_PB0_Msk)) | QSPI0_MOSI1_PB0 /*!< Set PB0 function to QSPI0_MOSI1 */ 3631 #define SET_QSPI0_MOSI1_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_MOSI1_PA4_Msk)) | QSPI0_MOSI1_PA4 /*!< Set PA4 function to QSPI0_MOSI1 */ 3632 #define SET_QSPI0_SS_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~QSPI0_SS_PA3_Msk)) | QSPI0_SS_PA3 /*!< Set PA3 function to QSPI0_SS */ 3633 #define SET_QSPI0_SS_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~QSPI0_SS_PC3_Msk)) | QSPI0_SS_PC3 /*!< Set PC3 function to QSPI0_SS */ 3634 #define SET_QSPI0_SS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~QSPI0_SS_PH9_Msk)) | QSPI0_SS_PH9 /*!< Set PH9 function to QSPI0_SS */ 3635 #define SET_SC0_CLK_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_CLK_PA0_Msk)) | SC0_CLK_PA0 /*!< Set PA0 function to SC0_CLK */ 3636 #define SET_SC0_CLK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_CLK_PF6_Msk)) | SC0_CLK_PF6 /*!< Set PF6 function to SC0_CLK */ 3637 #define SET_SC0_CLK_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_CLK_PE2_Msk)) | SC0_CLK_PE2 /*!< Set PE2 function to SC0_CLK */ 3638 #define SET_SC0_CLK_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_CLK_PB5_Msk)) | SC0_CLK_PB5 /*!< Set PB5 function to SC0_CLK */ 3639 #define SET_SC0_DAT_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SC0_DAT_PF7_Msk)) | SC0_DAT_PF7 /*!< Set PF7 function to SC0_DAT */ 3640 #define SET_SC0_DAT_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_DAT_PA1_Msk)) | SC0_DAT_PA1 /*!< Set PA1 function to SC0_DAT */ 3641 #define SET_SC0_DAT_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_DAT_PE3_Msk)) | SC0_DAT_PE3 /*!< Set PE3 function to SC0_DAT */ 3642 #define SET_SC0_DAT_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_DAT_PB4_Msk)) | SC0_DAT_PB4 /*!< Set PB4 function to SC0_DAT */ 3643 #define SET_SC0_PWR_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_PWR_PF9_Msk)) | SC0_PWR_PF9 /*!< Set PF9 function to SC0_PWR */ 3644 #define SET_SC0_PWR_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_PWR_PE5_Msk)) | SC0_PWR_PE5 /*!< Set PE5 function to SC0_PWR */ 3645 #define SET_SC0_PWR_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_PWR_PA3_Msk)) | SC0_PWR_PA3 /*!< Set PA3 function to SC0_PWR */ 3646 #define SET_SC0_PWR_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_PWR_PB2_Msk)) | SC0_PWR_PB2 /*!< Set PB2 function to SC0_PWR */ 3647 #define SET_SC0_RST_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_RST_PE4_Msk)) | SC0_RST_PE4 /*!< Set PE4 function to SC0_RST */ 3648 #define SET_SC0_RST_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_RST_PF8_Msk)) | SC0_RST_PF8 /*!< Set PF8 function to SC0_RST */ 3649 #define SET_SC0_RST_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_RST_PA2_Msk)) | SC0_RST_PA2 /*!< Set PA2 function to SC0_RST */ 3650 #define SET_SC0_RST_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SC0_RST_PB3_Msk)) | SC0_RST_PB3 /*!< Set PB3 function to SC0_RST */ 3651 #define SET_SC0_nCD_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC0_nCD_PC12_Msk)) | SC0_nCD_PC12 /*!< Set PC12 function to SC0_nCD */ 3652 #define SET_SC0_nCD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC0_nCD_PA4_Msk)) | SC0_nCD_PA4 /*!< Set PA4 function to SC0_nCD */ 3653 #define SET_SC0_nCD_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SC0_nCD_PF10_Msk)) | SC0_nCD_PF10 /*!< Set PF10 function to SC0_nCD */ 3654 #define SET_SC0_nCD_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC0_nCD_PE6_Msk)) | SC0_nCD_PE6 /*!< Set PE6 function to SC0_nCD */ 3655 #define SET_SC1_CLK_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_CLK_PB12_Msk)) | SC1_CLK_PB12 /*!< Set PB12 function to SC1_CLK */ 3656 #define SET_SC1_CLK_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_CLK_PC0_Msk)) | SC1_CLK_PC0 /*!< Set PC0 function to SC1_CLK */ 3657 #define SET_SC1_CLK_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_CLK_PD4_Msk)) | SC1_CLK_PD4 /*!< Set PD4 function to SC1_CLK */ 3658 #define SET_SC1_DAT_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_DAT_PD5_Msk)) | SC1_DAT_PD5 /*!< Set PD5 function to SC1_DAT */ 3659 #define SET_SC1_DAT_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_DAT_PC1_Msk)) | SC1_DAT_PC1 /*!< Set PC1 function to SC1_DAT */ 3660 #define SET_SC1_DAT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_DAT_PB13_Msk)) | SC1_DAT_PB13 /*!< Set PB13 function to SC1_DAT */ 3661 #define SET_SC1_PWR_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_PWR_PD7_Msk)) | SC1_PWR_PD7 /*!< Set PD7 function to SC1_PWR */ 3662 #define SET_SC1_PWR_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_PWR_PC3_Msk)) | SC1_PWR_PC3 /*!< Set PC3 function to SC1_PWR */ 3663 #define SET_SC1_PWR_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_PWR_PB15_Msk)) | SC1_PWR_PB15 /*!< Set PB15 function to SC1_PWR */ 3664 #define SET_SC1_RST_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_RST_PD6_Msk)) | SC1_RST_PD6 /*!< Set PD6 function to SC1_RST */ 3665 #define SET_SC1_RST_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SC1_RST_PB14_Msk)) | SC1_RST_PB14 /*!< Set PB14 function to SC1_RST */ 3666 #define SET_SC1_RST_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_RST_PC2_Msk)) | SC1_RST_PC2 /*!< Set PC2 function to SC1_RST */ 3667 #define SET_SC1_nCD_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC1_nCD_PD14_Msk)) | SC1_nCD_PD14 /*!< Set PD14 function to SC1_nCD */ 3668 #define SET_SC1_nCD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC1_nCD_PC4_Msk)) | SC1_nCD_PC4 /*!< Set PC4 function to SC1_nCD */ 3669 #define SET_SC1_nCD_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC1_nCD_PD3_Msk)) | SC1_nCD_PD3 /*!< Set PD3 function to SC1_nCD */ 3670 #define SET_SC2_CLK_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_CLK_PA6_Msk)) | SC2_CLK_PA6 /*!< Set PA6 function to SC2_CLK */ 3671 #define SET_SC2_CLK_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_CLK_PD0_Msk)) | SC2_CLK_PD0 /*!< Set PD0 function to SC2_CLK */ 3672 #define SET_SC2_CLK_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA15_Msk)) | SC2_CLK_PA15 /*!< Set PA15 function to SC2_CLK */ 3673 #define SET_SC2_CLK_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_CLK_PA8_Msk)) | SC2_CLK_PA8 /*!< Set PA8 function to SC2_CLK */ 3674 #define SET_SC2_CLK_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_CLK_PE0_Msk)) | SC2_CLK_PE0 /*!< Set PE0 function to SC2_CLK */ 3675 #define SET_SC2_DAT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA9_Msk)) | SC2_DAT_PA9 /*!< Set PA9 function to SC2_DAT */ 3676 #define SET_SC2_DAT_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_DAT_PD1_Msk)) | SC2_DAT_PD1 /*!< Set PD1 function to SC2_DAT */ 3677 #define SET_SC2_DAT_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_DAT_PA7_Msk)) | SC2_DAT_PA7 /*!< Set PA7 function to SC2_DAT */ 3678 #define SET_SC2_DAT_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_DAT_PA14_Msk)) | SC2_DAT_PA14 /*!< Set PA14 function to SC2_DAT */ 3679 #define SET_SC2_DAT_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SC2_DAT_PE1_Msk)) | SC2_DAT_PE1 /*!< Set PE1 function to SC2_DAT */ 3680 #define SET_SC2_PWR_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_PWR_PC7_Msk)) | SC2_PWR_PC7 /*!< Set PC7 function to SC2_PWR */ 3681 #define SET_SC2_PWR_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_PWR_PH8_Msk)) | SC2_PWR_PH8 /*!< Set PH8 function to SC2_PWR */ 3682 #define SET_SC2_PWR_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_PWR_PD3_Msk)) | SC2_PWR_PD3 /*!< Set PD3 function to SC2_PWR */ 3683 #define SET_SC2_PWR_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA11_Msk)) | SC2_PWR_PA11 /*!< Set PA11 function to SC2_PWR */ 3684 #define SET_SC2_PWR_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_PWR_PA12_Msk)) | SC2_PWR_PA12 /*!< Set PA12 function to SC2_PWR */ 3685 #define SET_SC2_RST_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SC2_RST_PD2_Msk)) | SC2_RST_PD2 /*!< Set PD2 function to SC2_RST */ 3686 #define SET_SC2_RST_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SC2_RST_PC6_Msk)) | SC2_RST_PC6 /*!< Set PC6 function to SC2_RST */ 3687 #define SET_SC2_RST_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_RST_PH9_Msk)) | SC2_RST_PH9 /*!< Set PH9 function to SC2_RST */ 3688 #define SET_SC2_RST_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA13_Msk)) | SC2_RST_PA13 /*!< Set PA13 function to SC2_RST */ 3689 #define SET_SC2_RST_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SC2_RST_PA10_Msk)) | SC2_RST_PA10 /*!< Set PA10 function to SC2_RST */ 3690 #define SET_SC2_nCD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SC2_nCD_PA5_Msk)) | SC2_nCD_PA5 /*!< Set PA5 function to SC2_nCD */ 3691 #define SET_SC2_nCD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SC2_nCD_PH10_Msk)) | SC2_nCD_PH10 /*!< Set PH10 function to SC2_nCD */ 3692 #define SET_SC2_nCD_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SC2_nCD_PD13_Msk)) | SC2_nCD_PD13 /*!< Set PD13 function to SC2_nCD */ 3693 #define SET_SC2_nCD_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SC2_nCD_PC13_Msk)) | SC2_nCD_PC13 /*!< Set PC13 function to SC2_nCD */ 3694 #define SET_SD0_CLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CLK_PB1_Msk)) | SD0_CLK_PB1 /*!< Set PB1 function to SD0_CLK */ 3695 #define SET_SD0_CLK_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CLK_PE6_Msk)) | SD0_CLK_PE6 /*!< Set PE6 function to SD0_CLK */ 3696 #define SET_SD0_CMD_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_CMD_PE7_Msk)) | SD0_CMD_PE7 /*!< Set PE7 function to SD0_CMD */ 3697 #define SET_SD0_CMD_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_CMD_PB0_Msk)) | SD0_CMD_PB0 /*!< Set PB0 function to SD0_CMD */ 3698 #define SET_SD0_DAT0_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT0_PE2_Msk)) | SD0_DAT0_PE2 /*!< Set PE2 function to SD0_DAT0 */ 3699 #define SET_SD0_DAT0_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT0_PB2_Msk)) | SD0_DAT0_PB2 /*!< Set PB2 function to SD0_DAT0 */ 3700 #define SET_SD0_DAT1_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT1_PE3_Msk)) | SD0_DAT1_PE3 /*!< Set PE3 function to SD0_DAT1 */ 3701 #define SET_SD0_DAT1_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT1_PB3_Msk)) | SD0_DAT1_PB3 /*!< Set PB3 function to SD0_DAT1 */ 3702 #define SET_SD0_DAT2_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT2_PE4_Msk)) | SD0_DAT2_PE4 /*!< Set PE4 function to SD0_DAT2 */ 3703 #define SET_SD0_DAT2_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT2_PB4_Msk)) | SD0_DAT2_PB4 /*!< Set PB4 function to SD0_DAT2 */ 3704 #define SET_SD0_DAT3_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SD0_DAT3_PE5_Msk)) | SD0_DAT3_PE5 /*!< Set PE5 function to SD0_DAT3 */ 3705 #define SET_SD0_DAT3_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SD0_DAT3_PB5_Msk)) | SD0_DAT3_PB5 /*!< Set PB5 function to SD0_DAT3 */ 3706 #define SET_SD0_nCD_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SD0_nCD_PD13_Msk)) | SD0_nCD_PD13 /*!< Set PD13 function to SD0_nCD */ 3707 #define SET_SD0_nCD_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SD0_nCD_PB12_Msk)) | SD0_nCD_PB12 /*!< Set PB12 function to SD0_nCD */ 3708 #define SET_SEG15_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG15_PC5_Msk)) | SEG15_PC5 /*!< Set PC5 function to SEG15 */ 3709 #define SET_SEG16_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SEG16_PC4_Msk)) | SEG16_PC4 /*!< Set PC4 function to SEG16 */ 3710 #define SET_SPI0_CLK_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_CLK_PD2_Msk)) | SPI0_CLK_PD2 /*!< Set PD2 function to SPI0_CLK */ 3711 #define SET_SPI0_CLK_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_CLK_PB14_Msk)) | SPI0_CLK_PB14 /*!< Set PB14 function to SPI0_CLK */ 3712 #define SET_SPI0_CLK_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_CLK_PF8_Msk)) | SPI0_CLK_PF8 /*!< Set PF8 function to SPI0_CLK */ 3713 #define SET_SPI0_CLK_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_CLK_PA2_Msk)) | SPI0_CLK_PA2 /*!< Set PA2 function to SPI0_CLK */ 3714 #define SET_SPI0_I2SMCLK_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_I2SMCLK_PB11_Msk)) | SPI0_I2SMCLK_PB11 /*!< Set PB11 function to SPI0_I2SMCLK */ 3715 #define SET_SPI0_I2SMCLK_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI0_I2SMCLK_PB0_Msk)) | SPI0_I2SMCLK_PB0 /*!< Set PB0 function to SPI0_I2SMCLK */ 3716 #define SET_SPI0_I2SMCLK_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_I2SMCLK_PF10_Msk)) | SPI0_I2SMCLK_PF10 /*!< Set PF10 function to SPI0_I2SMCLK */ 3717 #define SET_SPI0_I2SMCLK_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_I2SMCLK_PA4_Msk)) | SPI0_I2SMCLK_PA4 /*!< Set PA4 function to SPI0_I2SMCLK */ 3718 #define SET_SPI0_I2SMCLK_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD14_Msk)) | SPI0_I2SMCLK_PD14 /*!< Set PD14 function to SPI0_I2SMCLK */ 3719 #define SET_SPI0_I2SMCLK_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI0_I2SMCLK_PD13_Msk)) | SPI0_I2SMCLK_PD13 /*!< Set PD13 function to SPI0_I2SMCLK */ 3720 #define SET_SPI0_MISO_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MISO_PA1_Msk)) | SPI0_MISO_PA1 /*!< Set PA1 function to SPI0_MISO */ 3721 #define SET_SPI0_MISO_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MISO_PF7_Msk)) | SPI0_MISO_PF7 /*!< Set PF7 function to SPI0_MISO */ 3722 #define SET_SPI0_MISO_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MISO_PD1_Msk)) | SPI0_MISO_PD1 /*!< Set PD1 function to SPI0_MISO */ 3723 #define SET_SPI0_MISO_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MISO_PB13_Msk)) | SPI0_MISO_PB13 /*!< Set PB13 function to SPI0_MISO */ 3724 #define SET_SPI0_MOSI_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI0_MOSI_PF6_Msk)) | SPI0_MOSI_PF6 /*!< Set PF6 function to SPI0_MOSI */ 3725 #define SET_SPI0_MOSI_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_MOSI_PD0_Msk)) | SPI0_MOSI_PD0 /*!< Set PD0 function to SPI0_MOSI */ 3726 #define SET_SPI0_MOSI_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_MOSI_PB12_Msk)) | SPI0_MOSI_PB12 /*!< Set PB12 function to SPI0_MOSI */ 3727 #define SET_SPI0_MOSI_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_MOSI_PA0_Msk)) | SPI0_MOSI_PA0 /*!< Set PA0 function to SPI0_MOSI */ 3728 #define SET_SPI0_SS_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI0_SS_PF9_Msk)) | SPI0_SS_PF9 /*!< Set PF9 function to SPI0_SS */ 3729 #define SET_SPI0_SS_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI0_SS_PA3_Msk)) | SPI0_SS_PA3 /*!< Set PA3 function to SPI0_SS */ 3730 #define SET_SPI0_SS_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI0_SS_PB15_Msk)) | SPI0_SS_PB15 /*!< Set PB15 function to SPI0_SS */ 3731 #define SET_SPI0_SS_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI0_SS_PD3_Msk)) | SPI0_SS_PD3 /*!< Set PD3 function to SPI0_SS */ 3732 #define SET_SPI1_CLK_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_CLK_PD5_Msk)) | SPI1_CLK_PD5 /*!< Set PD5 function to SPI1_CLK */ 3733 #define SET_SPI1_CLK_PH6() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_CLK_PH6_Msk)) | SPI1_CLK_PH6 /*!< Set PH6 function to SPI1_CLK */ 3734 #define SET_SPI1_CLK_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_CLK_PC1_Msk)) | SPI1_CLK_PC1 /*!< Set PC1 function to SPI1_CLK */ 3735 #define SET_SPI1_CLK_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_CLK_PB3_Msk)) | SPI1_CLK_PB3 /*!< Set PB3 function to SPI1_CLK */ 3736 #define SET_SPI1_CLK_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_CLK_PH8_Msk)) | SPI1_CLK_PH8 /*!< Set PH8 function to SPI1_CLK */ 3737 #define SET_SPI1_CLK_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_CLK_PA7_Msk)) | SPI1_CLK_PA7 /*!< Set PA7 function to SPI1_CLK */ 3738 #define SET_SPI1_I2SMCLK_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_I2SMCLK_PC4_Msk)) | SPI1_I2SMCLK_PC4 /*!< Set PC4 function to SPI1_I2SMCLK */ 3739 #define SET_SPI1_I2SMCLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_I2SMCLK_PB1_Msk)) | SPI1_I2SMCLK_PB1 /*!< Set PB1 function to SPI1_I2SMCLK */ 3740 #define SET_SPI1_I2SMCLK_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_I2SMCLK_PA5_Msk)) | SPI1_I2SMCLK_PA5 /*!< Set PA5 function to SPI1_I2SMCLK */ 3741 #define SET_SPI1_I2SMCLK_PD13() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI1_I2SMCLK_PD13_Msk)) | SPI1_I2SMCLK_PD13 /*!< Set PD13 function to SPI1_I2SMCLK */ 3742 #define SET_SPI1_I2SMCLK_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_I2SMCLK_PH10_Msk)) | SPI1_I2SMCLK_PH10 /*!< Set PH10 function to SPI1_I2SMCLK */ 3743 #define SET_SPI1_MISO_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC3_Msk)) | SPI1_MISO_PC3 /*!< Set PC3 function to SPI1_MISO */ 3744 #define SET_SPI1_MISO_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MISO_PC7_Msk)) | SPI1_MISO_PC7 /*!< Set PC7 function to SPI1_MISO */ 3745 #define SET_SPI1_MISO_PH4() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MISO_PH4_Msk)) | SPI1_MISO_PH4 /*!< Set PH4 function to SPI1_MISO */ 3746 #define SET_SPI1_MISO_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MISO_PB5_Msk)) | SPI1_MISO_PB5 /*!< Set PB5 function to SPI1_MISO */ 3747 #define SET_SPI1_MISO_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MISO_PE1_Msk)) | SPI1_MISO_PE1 /*!< Set PE1 function to SPI1_MISO */ 3748 #define SET_SPI1_MISO_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MISO_PD7_Msk)) | SPI1_MISO_PD7 /*!< Set PD7 function to SPI1_MISO */ 3749 #define SET_SPI1_MOSI_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI1_MOSI_PE0_Msk)) | SPI1_MOSI_PE0 /*!< Set PE0 function to SPI1_MOSI */ 3750 #define SET_SPI1_MOSI_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_MOSI_PB4_Msk)) | SPI1_MOSI_PB4 /*!< Set PB4 function to SPI1_MOSI */ 3751 #define SET_SPI1_MOSI_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC6_Msk)) | SPI1_MOSI_PC6 /*!< Set PC6 function to SPI1_MOSI */ 3752 #define SET_SPI1_MOSI_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_MOSI_PD6_Msk)) | SPI1_MOSI_PD6 /*!< Set PD6 function to SPI1_MOSI */ 3753 #define SET_SPI1_MOSI_PH5() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_MOSI_PH5_Msk)) | SPI1_MOSI_PH5 /*!< Set PH5 function to SPI1_MOSI */ 3754 #define SET_SPI1_MOSI_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_MOSI_PC2_Msk)) | SPI1_MOSI_PC2 /*!< Set PC2 function to SPI1_MOSI */ 3755 #define SET_SPI1_SS_PH7() SYS->GPH_MFPL = (SYS->GPH_MFPL & (~SPI1_SS_PH7_Msk)) | SPI1_SS_PH7 /*!< Set PH7 function to SPI1_SS */ 3756 #define SET_SPI1_SS_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI1_SS_PB2_Msk)) | SPI1_SS_PB2 /*!< Set PB2 function to SPI1_SS */ 3757 #define SET_SPI1_SS_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SPI1_SS_PA6_Msk)) | SPI1_SS_PA6 /*!< Set PA6 function to SPI1_SS */ 3758 #define SET_SPI1_SS_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~SPI1_SS_PD4_Msk)) | SPI1_SS_PD4 /*!< Set PD4 function to SPI1_SS */ 3759 #define SET_SPI1_SS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~SPI1_SS_PH9_Msk)) | SPI1_SS_PH9 /*!< Set PH9 function to SPI1_SS */ 3760 #define SET_SPI1_SS_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~SPI1_SS_PC0_Msk)) | SPI1_SS_PC0 /*!< Set PC0 function to SPI1_SS */ 3761 #define SET_SPI2_CLK_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_CLK_PE8_Msk)) | SPI2_CLK_PE8 /*!< Set PE8 function to SPI2_CLK */ 3762 #define SET_SPI2_CLK_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA10_Msk)) | SPI2_CLK_PA10 /*!< Set PA10 function to SPI2_CLK */ 3763 #define SET_SPI2_CLK_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_CLK_PA13_Msk)) | SPI2_CLK_PA13 /*!< Set PA13 function to SPI2_CLK */ 3764 #define SET_SPI2_CLK_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_CLK_PG3_Msk)) | SPI2_CLK_PG3 /*!< Set PG3 function to SPI2_CLK */ 3765 #define SET_SPI2_I2SMCLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_I2SMCLK_PE12_Msk)) | SPI2_I2SMCLK_PE12 /*!< Set PE12 function to SPI2_I2SMCLK */ 3766 #define SET_SPI2_I2SMCLK_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI2_I2SMCLK_PC13_Msk)) | SPI2_I2SMCLK_PC13 /*!< Set PC13 function to SPI2_I2SMCLK */ 3767 #define SET_SPI2_I2SMCLK_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI2_I2SMCLK_PB0_Msk)) | SPI2_I2SMCLK_PB0 /*!< Set PB0 function to SPI2_I2SMCLK */ 3768 #define SET_SPI2_MISO_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MISO_PE9_Msk)) | SPI2_MISO_PE9 /*!< Set PE9 function to SPI2_MISO */ 3769 #define SET_SPI2_MISO_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA9_Msk)) | SPI2_MISO_PA9 /*!< Set PA9 function to SPI2_MISO */ 3770 #define SET_SPI2_MISO_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MISO_PA14_Msk)) | SPI2_MISO_PA14 /*!< Set PA14 function to SPI2_MISO */ 3771 #define SET_SPI2_MISO_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_MISO_PG4_Msk)) | SPI2_MISO_PG4 /*!< Set PG4 function to SPI2_MISO */ 3772 #define SET_SPI2_MOSI_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~SPI2_MOSI_PF11_Msk)) | SPI2_MOSI_PF11 /*!< Set PF11 function to SPI2_MOSI */ 3773 #define SET_SPI2_MOSI_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA15_Msk)) | SPI2_MOSI_PA15 /*!< Set PA15 function to SPI2_MOSI */ 3774 #define SET_SPI2_MOSI_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_MOSI_PE10_Msk)) | SPI2_MOSI_PE10 /*!< Set PE10 function to SPI2_MOSI */ 3775 #define SET_SPI2_MOSI_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_MOSI_PA8_Msk)) | SPI2_MOSI_PA8 /*!< Set PA8 function to SPI2_MOSI */ 3776 #define SET_SPI2_SS_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~SPI2_SS_PE11_Msk)) | SPI2_SS_PE11 /*!< Set PE11 function to SPI2_SS */ 3777 #define SET_SPI2_SS_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~SPI2_SS_PG2_Msk)) | SPI2_SS_PG2 /*!< Set PG2 function to SPI2_SS */ 3778 #define SET_SPI2_SS_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA11_Msk)) | SPI2_SS_PA11 /*!< Set PA11 function to SPI2_SS */ 3779 #define SET_SPI2_SS_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~SPI2_SS_PA12_Msk)) | SPI2_SS_PA12 /*!< Set PA12 function to SPI2_SS */ 3780 #define SET_SPI3_CLK_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_CLK_PC10_Msk)) | SPI3_CLK_PC10 /*!< Set PC10 function to SPI3_CLK */ 3781 #define SET_SPI3_CLK_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_CLK_PE4_Msk)) | SPI3_CLK_PE4 /*!< Set PE4 function to SPI3_CLK */ 3782 #define SET_SPI3_CLK_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_CLK_PB11_Msk)) | SPI3_CLK_PB11 /*!< Set PB11 function to SPI3_CLK */ 3783 #define SET_SPI3_I2SMCLK_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_I2SMCLK_PE6_Msk)) | SPI3_I2SMCLK_PE6 /*!< Set PE6 function to SPI3_I2SMCLK */ 3784 #define SET_SPI3_I2SMCLK_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~SPI3_I2SMCLK_PF6_Msk)) | SPI3_I2SMCLK_PF6 /*!< Set PF6 function to SPI3_I2SMCLK */ 3785 #define SET_SPI3_I2SMCLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~SPI3_I2SMCLK_PB1_Msk)) | SPI3_I2SMCLK_PB1 /*!< Set PB1 function to SPI3_I2SMCLK */ 3786 #define SET_SPI3_I2SMCLK_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~SPI3_I2SMCLK_PD14_Msk)) | SPI3_I2SMCLK_PD14 /*!< Set PD14 function to SPI3_I2SMCLK */ 3787 #define SET_SPI3_MISO_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MISO_PE3_Msk)) | SPI3_MISO_PE3 /*!< Set PE3 function to SPI3_MISO */ 3788 #define SET_SPI3_MISO_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MISO_PC12_Msk)) | SPI3_MISO_PC12 /*!< Set PC12 function to SPI3_MISO */ 3789 #define SET_SPI3_MISO_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MISO_PB9_Msk)) | SPI3_MISO_PB9 /*!< Set PB9 function to SPI3_MISO */ 3790 #define SET_SPI3_MOSI_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_MOSI_PC11_Msk)) | SPI3_MOSI_PC11 /*!< Set PC11 function to SPI3_MOSI */ 3791 #define SET_SPI3_MOSI_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_MOSI_PE2_Msk)) | SPI3_MOSI_PE2 /*!< Set PE2 function to SPI3_MOSI */ 3792 #define SET_SPI3_MOSI_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_MOSI_PB8_Msk)) | SPI3_MOSI_PB8 /*!< Set PB8 function to SPI3_MOSI */ 3793 #define SET_SPI3_SS_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~SPI3_SS_PE5_Msk)) | SPI3_SS_PE5 /*!< Set PE5 function to SPI3_SS */ 3794 #define SET_SPI3_SS_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~SPI3_SS_PB10_Msk)) | SPI3_SS_PB10 /*!< Set PB10 function to SPI3_SS */ 3795 #define SET_SPI3_SS_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~SPI3_SS_PC9_Msk)) | SPI3_SS_PC9 /*!< Set PC9 function to SPI3_SS */ 3796 #define SET_TAMPER0_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER0_PF6_Msk)) | TAMPER0_PF6 /*!< Set PF6 function to TAMPER0 */ 3797 #define SET_TAMPER1_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~TAMPER1_PF7_Msk)) | TAMPER1_PF7 /*!< Set PF7 function to TAMPER1 */ 3798 #define SET_TAMPER2_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER2_PF8_Msk)) | TAMPER2_PF8 /*!< Set PF8 function to TAMPER2 */ 3799 #define SET_TAMPER3_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER3_PF9_Msk)) | TAMPER3_PF9 /*!< Set PF9 function to TAMPER3 */ 3800 #define SET_TAMPER4_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER4_PF10_Msk)) | TAMPER4_PF10 /*!< Set PF10 function to TAMPER4 */ 3801 #define SET_TAMPER5_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TAMPER5_PF11_Msk)) | TAMPER5_PF11 /*!< Set PF11 function to TAMPER5 */ 3802 #define SET_TM0_PG2() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM0_PG2_Msk)) | TM0_PG2 /*!< Set PG2 function to TM0 */ 3803 #define SET_TM0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM0_PB5_Msk)) | TM0_PB5 /*!< Set PB5 function to TM0 */ 3804 #define SET_TM0_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM0_PC7_Msk)) | TM0_PC7 /*!< Set PC7 function to TM0 */ 3805 #define SET_TM0_EXT_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM0_EXT_PB15_Msk)) | TM0_EXT_PB15 /*!< Set PB15 function to TM0_EXT */ 3806 #define SET_TM0_EXT_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM0_EXT_PA11_Msk)) | TM0_EXT_PA11 /*!< Set PA11 function to TM0_EXT */ 3807 #define SET_TM1_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~TM1_PC6_Msk)) | TM1_PC6 /*!< Set PC6 function to TM1 */ 3808 #define SET_TM1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM1_PB4_Msk)) | TM1_PB4 /*!< Set PB4 function to TM1 */ 3809 #define SET_TM1_PG3() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM1_PG3_Msk)) | TM1_PG3 /*!< Set PG3 function to TM1 */ 3810 #define SET_TM1_EXT_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM1_EXT_PB14_Msk)) | TM1_EXT_PB14 /*!< Set PB14 function to TM1_EXT */ 3811 #define SET_TM1_EXT_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM1_EXT_PA10_Msk)) | TM1_EXT_PA10 /*!< Set PA10 function to TM1_EXT */ 3812 #define SET_TM2_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM2_PB3_Msk)) | TM2_PB3 /*!< Set PB3 function to TM2 */ 3813 #define SET_TM2_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM2_PA7_Msk)) | TM2_PA7 /*!< Set PA7 function to TM2 */ 3814 #define SET_TM2_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~TM2_PD0_Msk)) | TM2_PD0 /*!< Set PD0 function to TM2 */ 3815 #define SET_TM2_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM2_PG4_Msk)) | TM2_PG4 /*!< Set PG4 function to TM2 */ 3816 #define SET_TM2_EXT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM2_EXT_PB13_Msk)) | TM2_EXT_PB13 /*!< Set PB13 function to TM2_EXT */ 3817 #define SET_TM2_EXT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM2_EXT_PA9_Msk)) | TM2_EXT_PA9 /*!< Set PA9 function to TM2_EXT */ 3818 #define SET_TM3_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM3_PB2_Msk)) | TM3_PB2 /*!< Set PB2 function to TM3 */ 3819 #define SET_TM3_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM3_PA6_Msk)) | TM3_PA6 /*!< Set PA6 function to TM3 */ 3820 #define SET_TM3_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM3_PF11_Msk)) | TM3_PF11 /*!< Set PF11 function to TM3 */ 3821 #define SET_TM3_EXT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM3_EXT_PB12_Msk)) | TM3_EXT_PB12 /*!< Set PB12 function to TM3_EXT */ 3822 #define SET_TM3_EXT_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM3_EXT_PA8_Msk)) | TM3_EXT_PA8 /*!< Set PA8 function to TM3_EXT */ 3823 #define SET_TM4_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM4_PA7_Msk)) | TM4_PA7 /*!< Set PA7 function to TM4 */ 3824 #define SET_TM4_PG4() SYS->GPG_MFPL = (SYS->GPG_MFPL & (~TM4_PG4_Msk)) | TM4_PG4 /*!< Set PG4 function to TM4 */ 3825 #define SET_TM4_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM4_PB3_Msk)) | TM4_PB3 /*!< Set PB3 function to TM4 */ 3826 #define SET_TM4_EXT_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM4_EXT_PB13_Msk)) | TM4_EXT_PB13 /*!< Set PB13 function to TM4_EXT */ 3827 #define SET_TM4_EXT_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM4_EXT_PA9_Msk)) | TM4_EXT_PA9 /*!< Set PA9 function to TM4_EXT */ 3828 #define SET_TM5_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~TM5_PF11_Msk)) | TM5_PF11 /*!< Set PF11 function to TM5 */ 3829 #define SET_TM5_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~TM5_PB2_Msk)) | TM5_PB2 /*!< Set PB2 function to TM5 */ 3830 #define SET_TM5_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~TM5_PA6_Msk)) | TM5_PA6 /*!< Set PA6 function to TM5 */ 3831 #define SET_TM5_EXT_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~TM5_EXT_PA8_Msk)) | TM5_EXT_PA8 /*!< Set PA8 function to TM5_EXT */ 3832 #define SET_TM5_EXT_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~TM5_EXT_PB12_Msk)) | TM5_EXT_PB12 /*!< Set PB12 function to TM5_EXT */ 3833 #define SET_TRACE_CLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_CLK_PE12_Msk)) | TRACE_CLK_PE12 /*!< Set PE12 function to TRACE_CLK */ 3834 #define SET_TRACE_DATA0_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA0_PE11_Msk)) | TRACE_DATA0_PE11 /*!< Set PE11 function to TRACE_DATA0 */ 3835 #define SET_TRACE_DATA1_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA1_PE10_Msk)) | TRACE_DATA1_PE10 /*!< Set PE10 function to TRACE_DATA1 */ 3836 #define SET_TRACE_DATA2_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA2_PE9_Msk)) | TRACE_DATA2_PE9 /*!< Set PE9 function to TRACE_DATA2 */ 3837 #define SET_TRACE_DATA3_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~TRACE_DATA3_PE8_Msk)) | TRACE_DATA3_PE8 /*!< Set PE8 function to TRACE_DATA3 */ 3838 #define SET_UART0_RXD_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_RXD_PA15_Msk)) | UART0_RXD_PA15 /*!< Set PA15 function to UART0_RXD */ 3839 #define SET_UART0_RXD_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_RXD_PD2_Msk)) | UART0_RXD_PD2 /*!< Set PD2 function to UART0_RXD */ 3840 #define SET_UART0_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA4_Msk)) | UART0_RXD_PA4 /*!< Set PA4 function to UART0_RXD */ 3841 #define SET_UART0_RXD_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB12_Msk)) | UART0_RXD_PB12 /*!< Set PB12 function to UART0_RXD */ 3842 #define SET_UART0_RXD_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA0_Msk)) | UART0_RXD_PA0 /*!< Set PA0 function to UART0_RXD */ 3843 #define SET_UART0_RXD_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF1_Msk)) | UART0_RXD_PF1 /*!< Set PF1 function to UART0_RXD */ 3844 #define SET_UART0_RXD_PC11() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_RXD_PC11_Msk)) | UART0_RXD_PC11 /*!< Set PC11 function to UART0_RXD */ 3845 #define SET_UART0_RXD_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_RXD_PB8_Msk)) | UART0_RXD_PB8 /*!< Set PB8 function to UART0_RXD */ 3846 #define SET_UART0_RXD_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_RXD_PH11_Msk)) | UART0_RXD_PH11 /*!< Set PH11 function to UART0_RXD */ 3847 #define SET_UART0_RXD_PA6() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_RXD_PA6_Msk)) | UART0_RXD_PA6 /*!< Set PA6 function to UART0_RXD */ 3848 #define SET_UART0_RXD_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_RXD_PF2_Msk)) | UART0_RXD_PF2 /*!< Set PF2 function to UART0_RXD */ 3849 #define SET_UART0_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA5_Msk)) | UART0_TXD_PA5 /*!< Set PA5 function to UART0_TXD */ 3850 #define SET_UART0_TXD_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART0_TXD_PA14_Msk)) | UART0_TXD_PA14 /*!< Set PA14 function to UART0_TXD */ 3851 #define SET_UART0_TXD_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF3_Msk)) | UART0_TXD_PF3 /*!< Set PF3 function to UART0_TXD */ 3852 #define SET_UART0_TXD_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA1_Msk)) | UART0_TXD_PA1 /*!< Set PA1 function to UART0_TXD */ 3853 #define SET_UART0_TXD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART0_TXD_PH10_Msk)) | UART0_TXD_PH10 /*!< Set PH10 function to UART0_TXD */ 3854 #define SET_UART0_TXD_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART0_TXD_PD3_Msk)) | UART0_TXD_PD3 /*!< Set PD3 function to UART0_TXD */ 3855 #define SET_UART0_TXD_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB9_Msk)) | UART0_TXD_PB9 /*!< Set PB9 function to UART0_TXD */ 3856 #define SET_UART0_TXD_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_TXD_PB13_Msk)) | UART0_TXD_PB13 /*!< Set PB13 function to UART0_TXD */ 3857 #define SET_UART0_TXD_PA7() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_TXD_PA7_Msk)) | UART0_TXD_PA7 /*!< Set PA7 function to UART0_TXD */ 3858 #define SET_UART0_TXD_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART0_TXD_PF0_Msk)) | UART0_TXD_PF0 /*!< Set PF0 function to UART0_TXD */ 3859 #define SET_UART0_TXD_PC12() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART0_TXD_PC12_Msk)) | UART0_TXD_PC12 /*!< Set PC12 function to UART0_TXD */ 3860 #define SET_UART0_nCTS_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB15_Msk)) | UART0_nCTS_PB15 /*!< Set PB15 function to UART0_nCTS */ 3861 #define SET_UART0_nCTS_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nCTS_PB11_Msk)) | UART0_nCTS_PB11 /*!< Set PB11 function to UART0_nCTS */ 3862 #define SET_UART0_nCTS_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nCTS_PC7_Msk)) | UART0_nCTS_PC7 /*!< Set PC7 function to UART0_nCTS */ 3863 #define SET_UART0_nCTS_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nCTS_PA5_Msk)) | UART0_nCTS_PA5 /*!< Set PA5 function to UART0_nCTS */ 3864 #define SET_UART0_nRTS_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART0_nRTS_PC6_Msk)) | UART0_nRTS_PC6 /*!< Set PC6 function to UART0_nRTS */ 3865 #define SET_UART0_nRTS_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB14_Msk)) | UART0_nRTS_PB14 /*!< Set PB14 function to UART0_nRTS */ 3866 #define SET_UART0_nRTS_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART0_nRTS_PB10_Msk)) | UART0_nRTS_PB10 /*!< Set PB10 function to UART0_nRTS */ 3867 #define SET_UART0_nRTS_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART0_nRTS_PA4_Msk)) | UART0_nRTS_PA4 /*!< Set PA4 function to UART0_nRTS */ 3868 #define SET_UART1_RXD_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_RXD_PA8_Msk)) | UART1_RXD_PA8 /*!< Set PA8 function to UART1_RXD */ 3869 #define SET_UART1_RXD_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB6_Msk)) | UART1_RXD_PB6 /*!< Set PB6 function to UART1_RXD */ 3870 #define SET_UART1_RXD_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART1_RXD_PC8_Msk)) | UART1_RXD_PC8 /*!< Set PC8 function to UART1_RXD */ 3871 #define SET_UART1_RXD_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_RXD_PA2_Msk)) | UART1_RXD_PA2 /*!< Set PA2 function to UART1_RXD */ 3872 #define SET_UART1_RXD_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_RXD_PH9_Msk)) | UART1_RXD_PH9 /*!< Set PH9 function to UART1_RXD */ 3873 #define SET_UART1_RXD_PD10() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_RXD_PD10_Msk)) | UART1_RXD_PD10 /*!< Set PD10 function to UART1_RXD */ 3874 #define SET_UART1_RXD_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_RXD_PB2_Msk)) | UART1_RXD_PB2 /*!< Set PB2 function to UART1_RXD */ 3875 #define SET_UART1_RXD_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_RXD_PD6_Msk)) | UART1_RXD_PD6 /*!< Set PD6 function to UART1_RXD */ 3876 #define SET_UART1_RXD_PF1() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_RXD_PF1_Msk)) | UART1_RXD_PF1 /*!< Set PF1 function to UART1_RXD */ 3877 #define SET_UART1_TXD_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART1_TXD_PA9_Msk)) | UART1_TXD_PA9 /*!< Set PA9 function to UART1_TXD */ 3878 #define SET_UART1_TXD_PD11() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART1_TXD_PD11_Msk)) | UART1_TXD_PD11 /*!< Set PD11 function to UART1_TXD */ 3879 #define SET_UART1_TXD_PF0() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART1_TXD_PF0_Msk)) | UART1_TXD_PF0 /*!< Set PF0 function to UART1_TXD */ 3880 #define SET_UART1_TXD_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB3_Msk)) | UART1_TXD_PB3 /*!< Set PB3 function to UART1_TXD */ 3881 #define SET_UART1_TXD_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART1_TXD_PH8_Msk)) | UART1_TXD_PH8 /*!< Set PH8 function to UART1_TXD */ 3882 #define SET_UART1_TXD_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_TXD_PA3_Msk)) | UART1_TXD_PA3 /*!< Set PA3 function to UART1_TXD */ 3883 #define SET_UART1_TXD_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART1_TXD_PD7_Msk)) | UART1_TXD_PD7 /*!< Set PD7 function to UART1_TXD */ 3884 #define SET_UART1_TXD_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_TXD_PE13_Msk)) | UART1_TXD_PE13 /*!< Set PE13 function to UART1_TXD */ 3885 #define SET_UART1_TXD_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART1_TXD_PB7_Msk)) | UART1_TXD_PB7 /*!< Set PB7 function to UART1_TXD */ 3886 #define SET_UART1_nCTS_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nCTS_PB9_Msk)) | UART1_nCTS_PB9 /*!< Set PB9 function to UART1_nCTS */ 3887 #define SET_UART1_nCTS_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nCTS_PE11_Msk)) | UART1_nCTS_PE11 /*!< Set PE11 function to UART1_nCTS */ 3888 #define SET_UART1_nCTS_PA1() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nCTS_PA1_Msk)) | UART1_nCTS_PA1 /*!< Set PA1 function to UART1_nCTS */ 3889 #define SET_UART1_nRTS_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART1_nRTS_PB8_Msk)) | UART1_nRTS_PB8 /*!< Set PB8 function to UART1_nRTS */ 3890 #define SET_UART1_nRTS_PA0() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART1_nRTS_PA0_Msk)) | UART1_nRTS_PA0 /*!< Set PA0 function to UART1_nRTS */ 3891 #define SET_UART1_nRTS_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART1_nRTS_PE12_Msk)) | UART1_nRTS_PE12 /*!< Set PE12 function to UART1_nRTS */ 3892 #define SET_UART2_RXD_PE15() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE15_Msk)) | UART2_RXD_PE15 /*!< Set PE15 function to UART2_RXD */ 3893 #define SET_UART2_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC4_Msk)) | UART2_RXD_PC4 /*!< Set PC4 function to UART2_RXD */ 3894 #define SET_UART2_RXD_PD12() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_RXD_PD12_Msk)) | UART2_RXD_PD12 /*!< Set PD12 function to UART2_RXD */ 3895 #define SET_UART2_RXD_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_RXD_PF5_Msk)) | UART2_RXD_PF5 /*!< Set PF5 function to UART2_RXD */ 3896 #define SET_UART2_RXD_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_RXD_PE9_Msk)) | UART2_RXD_PE9 /*!< Set PE9 function to UART2_RXD */ 3897 #define SET_UART2_RXD_PC0() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_RXD_PC0_Msk)) | UART2_RXD_PC0 /*!< Set PC0 function to UART2_RXD */ 3898 #define SET_UART2_RXD_PB0() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB0_Msk)) | UART2_RXD_PB0 /*!< Set PB0 function to UART2_RXD */ 3899 #define SET_UART2_RXD_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_RXD_PB4_Msk)) | UART2_RXD_PB4 /*!< Set PB4 function to UART2_RXD */ 3900 #define SET_UART2_TXD_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_TXD_PF4_Msk)) | UART2_TXD_PF4 /*!< Set PF4 function to UART2_TXD */ 3901 #define SET_UART2_TXD_PC1() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC1_Msk)) | UART2_TXD_PC1 /*!< Set PC1 function to UART2_TXD */ 3902 #define SET_UART2_TXD_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB5_Msk)) | UART2_TXD_PB5 /*!< Set PB5 function to UART2_TXD */ 3903 #define SET_UART2_TXD_PE14() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE14_Msk)) | UART2_TXD_PE14 /*!< Set PE14 function to UART2_TXD */ 3904 #define SET_UART2_TXD_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART2_TXD_PC13_Msk)) | UART2_TXD_PC13 /*!< Set PC13 function to UART2_TXD */ 3905 #define SET_UART2_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_TXD_PC5_Msk)) | UART2_TXD_PC5 /*!< Set PC5 function to UART2_TXD */ 3906 #define SET_UART2_TXD_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART2_TXD_PE8_Msk)) | UART2_TXD_PE8 /*!< Set PE8 function to UART2_TXD */ 3907 #define SET_UART2_TXD_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART2_TXD_PB1_Msk)) | UART2_TXD_PB1 /*!< Set PB1 function to UART2_TXD */ 3908 #define SET_UART2_nCTS_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nCTS_PF5_Msk)) | UART2_nCTS_PF5 /*!< Set PF5 function to UART2_nCTS */ 3909 #define SET_UART2_nCTS_PD9() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nCTS_PD9_Msk)) | UART2_nCTS_PD9 /*!< Set PD9 function to UART2_nCTS */ 3910 #define SET_UART2_nCTS_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nCTS_PC2_Msk)) | UART2_nCTS_PC2 /*!< Set PC2 function to UART2_nCTS */ 3911 #define SET_UART2_nRTS_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART2_nRTS_PC3_Msk)) | UART2_nRTS_PC3 /*!< Set PC3 function to UART2_nRTS */ 3912 #define SET_UART2_nRTS_PD8() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~UART2_nRTS_PD8_Msk)) | UART2_nRTS_PD8 /*!< Set PD8 function to UART2_nRTS */ 3913 #define SET_UART2_nRTS_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART2_nRTS_PF4_Msk)) | UART2_nRTS_PF4 /*!< Set PF4 function to UART2_nRTS */ 3914 #define SET_UART3_RXD_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_RXD_PD0_Msk)) | UART3_RXD_PD0 /*!< Set PD0 function to UART3_RXD */ 3915 #define SET_UART3_RXD_PC9() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_RXD_PC9_Msk)) | UART3_RXD_PC9 /*!< Set PC9 function to UART3_RXD */ 3916 #define SET_UART3_RXD_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_RXD_PE0_Msk)) | UART3_RXD_PE0 /*!< Set PE0 function to UART3_RXD */ 3917 #define SET_UART3_RXD_PC2() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_RXD_PC2_Msk)) | UART3_RXD_PC2 /*!< Set PC2 function to UART3_RXD */ 3918 #define SET_UART3_RXD_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_RXD_PB14_Msk)) | UART3_RXD_PB14 /*!< Set PB14 function to UART3_RXD */ 3919 #define SET_UART3_RXD_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_RXD_PE11_Msk)) | UART3_RXD_PE11 /*!< Set PE11 function to UART3_RXD */ 3920 #define SET_UART3_TXD_PC10() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART3_TXD_PC10_Msk)) | UART3_TXD_PC10 /*!< Set PC10 function to UART3_TXD */ 3921 #define SET_UART3_TXD_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_TXD_PB15_Msk)) | UART3_TXD_PB15 /*!< Set PB15 function to UART3_TXD */ 3922 #define SET_UART3_TXD_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART3_TXD_PE10_Msk)) | UART3_TXD_PE10 /*!< Set PE10 function to UART3_TXD */ 3923 #define SET_UART3_TXD_PC3() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART3_TXD_PC3_Msk)) | UART3_TXD_PC3 /*!< Set PC3 function to UART3_TXD */ 3924 #define SET_UART3_TXD_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_TXD_PD1_Msk)) | UART3_TXD_PD1 /*!< Set PD1 function to UART3_TXD */ 3925 #define SET_UART3_TXD_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART3_TXD_PE1_Msk)) | UART3_TXD_PE1 /*!< Set PE1 function to UART3_TXD */ 3926 #define SET_UART3_nCTS_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nCTS_PB12_Msk)) | UART3_nCTS_PB12 /*!< Set PB12 function to UART3_nCTS */ 3927 #define SET_UART3_nCTS_PH9() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nCTS_PH9_Msk)) | UART3_nCTS_PH9 /*!< Set PH9 function to UART3_nCTS */ 3928 #define SET_UART3_nCTS_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nCTS_PD2_Msk)) | UART3_nCTS_PD2 /*!< Set PD2 function to UART3_nCTS */ 3929 #define SET_UART3_nRTS_PH8() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART3_nRTS_PH8_Msk)) | UART3_nRTS_PH8 /*!< Set PH8 function to UART3_nRTS */ 3930 #define SET_UART3_nRTS_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~UART3_nRTS_PD3_Msk)) | UART3_nRTS_PD3 /*!< Set PD3 function to UART3_nRTS */ 3931 #define SET_UART3_nRTS_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART3_nRTS_PB13_Msk)) | UART3_nRTS_PB13 /*!< Set PB13 function to UART3_nRTS */ 3932 #define SET_UART4_RXD_PA2() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_RXD_PA2_Msk)) | UART4_RXD_PA2 /*!< Set PA2 function to UART4_RXD */ 3933 #define SET_UART4_RXD_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_RXD_PA13_Msk)) | UART4_RXD_PA13 /*!< Set PA13 function to UART4_RXD */ 3934 #define SET_UART4_RXD_PC4() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC4_Msk)) | UART4_RXD_PC4 /*!< Set PC4 function to UART4_RXD */ 3935 #define SET_UART4_RXD_PH11() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_RXD_PH11_Msk)) | UART4_RXD_PH11 /*!< Set PH11 function to UART4_RXD */ 3936 #define SET_UART4_RXD_PF6() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_RXD_PF6_Msk)) | UART4_RXD_PF6 /*!< Set PF6 function to UART4_RXD */ 3937 #define SET_UART4_RXD_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_RXD_PB10_Msk)) | UART4_RXD_PB10 /*!< Set PB10 function to UART4_RXD */ 3938 #define SET_UART4_RXD_PC6() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_RXD_PC6_Msk)) | UART4_RXD_PC6 /*!< Set PC6 function to UART4_RXD */ 3939 #define SET_UART4_TXD_PA3() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART4_TXD_PA3_Msk)) | UART4_TXD_PA3 /*!< Set PA3 function to UART4_TXD */ 3940 #define SET_UART4_TXD_PC5() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC5_Msk)) | UART4_TXD_PC5 /*!< Set PC5 function to UART4_TXD */ 3941 #define SET_UART4_TXD_PC7() SYS->GPC_MFPL = (SYS->GPC_MFPL & (~UART4_TXD_PC7_Msk)) | UART4_TXD_PC7 /*!< Set PC7 function to UART4_TXD */ 3942 #define SET_UART4_TXD_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~UART4_TXD_PA12_Msk)) | UART4_TXD_PA12 /*!< Set PA12 function to UART4_TXD */ 3943 #define SET_UART4_TXD_PF7() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~UART4_TXD_PF7_Msk)) | UART4_TXD_PF7 /*!< Set PF7 function to UART4_TXD */ 3944 #define SET_UART4_TXD_PH10() SYS->GPH_MFPH = (SYS->GPH_MFPH & (~UART4_TXD_PH10_Msk)) | UART4_TXD_PH10 /*!< Set PH10 function to UART4_TXD */ 3945 #define SET_UART4_TXD_PB11() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~UART4_TXD_PB11_Msk)) | UART4_TXD_PB11 /*!< Set PB11 function to UART4_TXD */ 3946 #define SET_UART4_nCTS_PC8() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~UART4_nCTS_PC8_Msk)) | UART4_nCTS_PC8 /*!< Set PC8 function to UART4_nCTS */ 3947 #define SET_UART4_nCTS_PE1() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nCTS_PE1_Msk)) | UART4_nCTS_PE1 /*!< Set PE1 function to UART4_nCTS */ 3948 #define SET_UART4_nRTS_PE0() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART4_nRTS_PE0_Msk)) | UART4_nRTS_PE0 /*!< Set PE0 function to UART4_nRTS */ 3949 #define SET_UART4_nRTS_PE13() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~UART4_nRTS_PE13_Msk)) | UART4_nRTS_PE13 /*!< Set PE13 function to UART4_nRTS */ 3950 #define SET_UART5_RXD_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_RXD_PB4_Msk)) | UART5_RXD_PB4 /*!< Set PB4 function to UART5_RXD */ 3951 #define SET_UART5_RXD_PF10() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_RXD_PF10_Msk)) | UART5_RXD_PF10 /*!< Set PF10 function to UART5_RXD */ 3952 #define SET_UART5_RXD_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_RXD_PE6_Msk)) | UART5_RXD_PE6 /*!< Set PE6 function to UART5_RXD */ 3953 #define SET_UART5_RXD_PA4() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_RXD_PA4_Msk)) | UART5_RXD_PA4 /*!< Set PA4 function to UART5_RXD */ 3954 #define SET_UART5_TXD_PF11() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_TXD_PF11_Msk)) | UART5_TXD_PF11 /*!< Set PF11 function to UART5_TXD */ 3955 #define SET_UART5_TXD_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_TXD_PB5_Msk)) | UART5_TXD_PB5 /*!< Set PB5 function to UART5_TXD */ 3956 #define SET_UART5_TXD_PE7() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~UART5_TXD_PE7_Msk)) | UART5_TXD_PE7 /*!< Set PE7 function to UART5_TXD */ 3957 #define SET_UART5_TXD_PA5() SYS->GPA_MFPL = (SYS->GPA_MFPL & (~UART5_TXD_PA5_Msk)) | UART5_TXD_PA5 /*!< Set PA5 function to UART5_TXD */ 3958 #define SET_UART5_nCTS_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nCTS_PB2_Msk)) | UART5_nCTS_PB2 /*!< Set PB2 function to UART5_nCTS */ 3959 #define SET_UART5_nCTS_PF8() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nCTS_PF8_Msk)) | UART5_nCTS_PF8 /*!< Set PF8 function to UART5_nCTS */ 3960 #define SET_UART5_nRTS_PF9() SYS->GPF_MFPH = (SYS->GPF_MFPH & (~UART5_nRTS_PF9_Msk)) | UART5_nRTS_PF9 /*!< Set PF9 function to UART5_nRTS */ 3961 #define SET_UART5_nRTS_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~UART5_nRTS_PB3_Msk)) | UART5_nRTS_PB3 /*!< Set PB3 function to UART5_nRTS */ 3962 #define SET_USB_D_P_PA14() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_P_PA14_Msk)) | USB_D_P_PA14 /*!< Set PA14 function to USB_D_P */ 3963 #define SET_USB_D_N_PA13() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_D_N_PA13_Msk)) | USB_D_N_PA13 /*!< Set PA13 function to USB_D_N */ 3964 #define SET_USB_OTG_ID_PA15() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_OTG_ID_PA15_Msk)) | USB_OTG_ID_PA15 /*!< Set PA15 function to USB_OTG_ID */ 3965 #define SET_USB_VBUS_PA12() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USB_VBUS_PA12_Msk)) | USB_VBUS_PA12 /*!< Set PA12 function to USB_VBUS */ 3966 #define SET_USB_VBUS_EN_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_EN_PB15_Msk)) | USB_VBUS_EN_PB15 /*!< Set PB15 function to USB_VBUS_EN */ 3967 #define SET_USB_VBUS_EN_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_EN_PB6_Msk)) | USB_VBUS_EN_PB6 /*!< Set PB6 function to USB_VBUS_EN */ 3968 #define SET_USB_VBUS_ST_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USB_VBUS_ST_PB14_Msk)) | USB_VBUS_ST_PB14 /*!< Set PB14 function to USB_VBUS_ST */ 3969 #define SET_USB_VBUS_ST_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USB_VBUS_ST_PB7_Msk)) | USB_VBUS_ST_PB7 /*!< Set PB7 function to USB_VBUS_ST */ 3970 #define SET_USB_VBUS_ST_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USB_VBUS_ST_PD4_Msk)) | USB_VBUS_ST_PD4 /*!< Set PD4 function to USB_VBUS_ST */ 3971 #define SET_USCI0_CLK_PA11() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CLK_PA11_Msk)) | USCI0_CLK_PA11 /*!< Set PA11 function to USCI0_CLK */ 3972 #define SET_USCI0_CLK_PD0() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CLK_PD0_Msk)) | USCI0_CLK_PD0 /*!< Set PD0 function to USCI0_CLK */ 3973 #define SET_USCI0_CLK_PB12() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CLK_PB12_Msk)) | USCI0_CLK_PB12 /*!< Set PB12 function to USCI0_CLK */ 3974 #define SET_USCI0_CLK_PE2() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CLK_PE2_Msk)) | USCI0_CLK_PE2 /*!< Set PE2 function to USCI0_CLK */ 3975 #define SET_USCI0_CTL0_PC13() SYS->GPC_MFPH = (SYS->GPC_MFPH & (~USCI0_CTL0_PC13_Msk)) | USCI0_CTL0_PC13 /*!< Set PC13 function to USCI0_CTL0 */ 3976 #define SET_USCI0_CTL0_PD14() SYS->GPD_MFPH = (SYS->GPD_MFPH & (~USCI0_CTL0_PD14_Msk)) | USCI0_CTL0_PD14 /*!< Set PD14 function to USCI0_CTL0 */ 3977 #define SET_USCI0_CTL0_PE6() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL0_PE6_Msk)) | USCI0_CTL0_PE6 /*!< Set PE6 function to USCI0_CTL0 */ 3978 #define SET_USCI0_CTL0_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL0_PD4_Msk)) | USCI0_CTL0_PD4 /*!< Set PD4 function to USCI0_CTL0 */ 3979 #define SET_USCI0_CTL1_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_CTL1_PD3_Msk)) | USCI0_CTL1_PD3 /*!< Set PD3 function to USCI0_CTL1 */ 3980 #define SET_USCI0_CTL1_PA8() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_CTL1_PA8_Msk)) | USCI0_CTL1_PA8 /*!< Set PA8 function to USCI0_CTL1 */ 3981 #define SET_USCI0_CTL1_PE5() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_CTL1_PE5_Msk)) | USCI0_CTL1_PE5 /*!< Set PE5 function to USCI0_CTL1 */ 3982 #define SET_USCI0_CTL1_PB15() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_CTL1_PB15_Msk)) | USCI0_CTL1_PB15 /*!< Set PB15 function to USCI0_CTL1 */ 3983 #define SET_USCI0_DAT0_PB13() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT0_PB13_Msk)) | USCI0_DAT0_PB13 /*!< Set PB13 function to USCI0_DAT0 */ 3984 #define SET_USCI0_DAT0_PE3() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT0_PE3_Msk)) | USCI0_DAT0_PE3 /*!< Set PE3 function to USCI0_DAT0 */ 3985 #define SET_USCI0_DAT0_PA10() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT0_PA10_Msk)) | USCI0_DAT0_PA10 /*!< Set PA10 function to USCI0_DAT0 */ 3986 #define SET_USCI0_DAT0_PD1() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT0_PD1_Msk)) | USCI0_DAT0_PD1 /*!< Set PD1 function to USCI0_DAT0 */ 3987 #define SET_USCI0_DAT1_PA9() SYS->GPA_MFPH = (SYS->GPA_MFPH & (~USCI0_DAT1_PA9_Msk)) | USCI0_DAT1_PA9 /*!< Set PA9 function to USCI0_DAT1 */ 3988 #define SET_USCI0_DAT1_PE4() SYS->GPE_MFPL = (SYS->GPE_MFPL & (~USCI0_DAT1_PE4_Msk)) | USCI0_DAT1_PE4 /*!< Set PE4 function to USCI0_DAT1 */ 3989 #define SET_USCI0_DAT1_PB14() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI0_DAT1_PB14_Msk)) | USCI0_DAT1_PB14 /*!< Set PB14 function to USCI0_DAT1 */ 3990 #define SET_USCI0_DAT1_PD2() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI0_DAT1_PD2_Msk)) | USCI0_DAT1_PD2 /*!< Set PD2 function to USCI0_DAT1 */ 3991 #define SET_USCI1_CLK_PE12() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CLK_PE12_Msk)) | USCI1_CLK_PE12 /*!< Set PE12 function to USCI1_CLK */ 3992 #define SET_USCI1_CLK_PB1() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CLK_PB1_Msk)) | USCI1_CLK_PB1 /*!< Set PB1 function to USCI1_CLK */ 3993 #define SET_USCI1_CLK_PD7() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CLK_PD7_Msk)) | USCI1_CLK_PD7 /*!< Set PD7 function to USCI1_CLK */ 3994 #define SET_USCI1_CLK_PB8() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CLK_PB8_Msk)) | USCI1_CLK_PB8 /*!< Set PB8 function to USCI1_CLK */ 3995 #define SET_USCI1_CTL0_PE9() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL0_PE9_Msk)) | USCI1_CTL0_PE9 /*!< Set PE9 function to USCI1_CTL0 */ 3996 #define SET_USCI1_CTL0_PB5() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL0_PB5_Msk)) | USCI1_CTL0_PB5 /*!< Set PB5 function to USCI1_CTL0 */ 3997 #define SET_USCI1_CTL0_PD3() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL0_PD3_Msk)) | USCI1_CTL0_PD3 /*!< Set PD3 function to USCI1_CTL0 */ 3998 #define SET_USCI1_CTL0_PB10() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL0_PB10_Msk)) | USCI1_CTL0_PB10 /*!< Set PB10 function to USCI1_CTL0 */ 3999 #define SET_USCI1_CTL1_PB4() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_CTL1_PB4_Msk)) | USCI1_CTL1_PB4 /*!< Set PB4 function to USCI1_CTL1 */ 4000 #define SET_USCI1_CTL1_PD4() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_CTL1_PD4_Msk)) | USCI1_CTL1_PD4 /*!< Set PD4 function to USCI1_CTL1 */ 4001 #define SET_USCI1_CTL1_PE8() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_CTL1_PE8_Msk)) | USCI1_CTL1_PE8 /*!< Set PE8 function to USCI1_CTL1 */ 4002 #define SET_USCI1_CTL1_PB9() SYS->GPB_MFPH = (SYS->GPB_MFPH & (~USCI1_CTL1_PB9_Msk)) | USCI1_CTL1_PB9 /*!< Set PB9 function to USCI1_CTL1 */ 4003 #define SET_USCI1_DAT0_PB7() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB7_Msk)) | USCI1_DAT0_PB7 /*!< Set PB7 function to USCI1_DAT0 */ 4004 #define SET_USCI1_DAT0_PE10() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT0_PE10_Msk)) | USCI1_DAT0_PE10 /*!< Set PE10 function to USCI1_DAT0 */ 4005 #define SET_USCI1_DAT0_PB2() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT0_PB2_Msk)) | USCI1_DAT0_PB2 /*!< Set PB2 function to USCI1_DAT0 */ 4006 #define SET_USCI1_DAT0_PD5() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT0_PD5_Msk)) | USCI1_DAT0_PD5 /*!< Set PD5 function to USCI1_DAT0 */ 4007 #define SET_USCI1_DAT1_PD6() SYS->GPD_MFPL = (SYS->GPD_MFPL & (~USCI1_DAT1_PD6_Msk)) | USCI1_DAT1_PD6 /*!< Set PD6 function to USCI1_DAT1 */ 4008 #define SET_USCI1_DAT1_PB6() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB6_Msk)) | USCI1_DAT1_PB6 /*!< Set PB6 function to USCI1_DAT1 */ 4009 #define SET_USCI1_DAT1_PE11() SYS->GPE_MFPH = (SYS->GPE_MFPH & (~USCI1_DAT1_PE11_Msk)) | USCI1_DAT1_PE11 /*!< Set PE11 function to USCI1_DAT1 */ 4010 #define SET_USCI1_DAT1_PB3() SYS->GPB_MFPL = (SYS->GPB_MFPL & (~USCI1_DAT1_PB3_Msk)) | USCI1_DAT1_PB3 /*!< Set PB3 function to USCI1_DAT1 */ 4011 #define SET_X32_IN_PF5() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_IN_PF5_Msk)) | X32_IN_PF5 /*!< Set PF5 function to X32_IN */ 4012 #define SET_X32_OUT_PF4() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~X32_OUT_PF4_Msk)) | X32_OUT_PF4 /*!< Set PF4 function to X32_OUT */ 4013 #define SET_XT1_IN_PF3() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_IN_PF3_Msk)) | XT1_IN_PF3 /*!< Set PF3 function to XT1_IN */ 4014 #define SET_XT1_OUT_PF2() SYS->GPF_MFPL = (SYS->GPF_MFPL & (~XT1_OUT_PF2_Msk)) | XT1_OUT_PF2 /*!< Set PF2 function to XT1_OUT */ 4015 4016 4017 /** 4018 * @brief Clear Brown-out detector interrupt flag 4019 * @param None 4020 * @return None 4021 * @details This macro clear Brown-out detector interrupt flag. 4022 */ 4023 #define SYS_CLEAR_BOD_INT_FLAG() \ 4024 do{ \ 4025 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4026 SYS->BODCTL |= SYS_BODCTL_BODIF_Msk; \ 4027 }while(0) 4028 4029 /** 4030 * @brief Disable Brown-out detector function 4031 * @param None 4032 * @return None 4033 * @details This macro disable Brown-out detector function. 4034 * The register write-protection function should be disabled before using this macro. 4035 */ 4036 #define SYS_DISABLE_BOD() \ 4037 do{ \ 4038 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4039 SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; \ 4040 }while(0) 4041 4042 /** 4043 * @brief Enable Brown-out detector function 4044 * @param None 4045 * @return None 4046 * @details This macro enable Brown-out detector function. 4047 * The register write-protection function should be disabled before using this macro. 4048 */ 4049 #define SYS_ENABLE_BOD() \ 4050 do{ \ 4051 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4052 SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; \ 4053 }while(0) 4054 4055 /** 4056 * @brief Get Brown-out detector interrupt flag 4057 * @param None 4058 * @retval 0 Brown-out detect interrupt flag is not set. 4059 * @retval >=1 Brown-out detect interrupt flag is set. 4060 * @details This macro get Brown-out detector interrupt flag. 4061 */ 4062 #define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) 4063 4064 /** 4065 * @brief Get Brown-out detector status 4066 * @param None 4067 * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. 4068 * @retval >=1 System voltage is lower than BOD threshold voltage setting. 4069 * @details This macro get Brown-out detector output status. 4070 * If the BOD function is disabled, this function always return 0. 4071 */ 4072 #define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) 4073 4074 /** 4075 * @brief Enable Brown-out detector interrupt function 4076 * @param None 4077 * @return None 4078 * @details This macro enable Brown-out detector interrupt function. 4079 * The register write-protection function should be disabled before using this macro. 4080 */ 4081 #define SYS_DISABLE_BOD_RST() \ 4082 do{ \ 4083 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4084 SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk; \ 4085 }while(0) 4086 4087 /** 4088 * @brief Enable Brown-out detector reset function 4089 * @param None 4090 * @return None 4091 * @details This macro enable Brown-out detect reset function. 4092 * The register write-protection function should be disabled before using this macro. 4093 */ 4094 #define SYS_ENABLE_BOD_RST() \ 4095 do{ \ 4096 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4097 SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk; \ 4098 }while(0) 4099 4100 /** 4101 * @brief Set Brown-out detector voltage level 4102 * @param[in] u32Level is Brown-out voltage level. Including : 4103 * - \ref SYS_BODCTL_BODVL_1_6V 4104 * - \ref SYS_BODCTL_BODVL_1_8V 4105 * - \ref SYS_BODCTL_BODVL_2_0V 4106 * - \ref SYS_BODCTL_BODVL_2_2V 4107 * - \ref SYS_BODCTL_BODVL_2_4V 4108 * - \ref SYS_BODCTL_BODVL_2_6V 4109 * - \ref SYS_BODCTL_BODVL_2_8V 4110 * - \ref SYS_BODCTL_BODVL_3_0V 4111 * @return None 4112 * @details This macro set Brown-out detector voltage level. 4113 * The write-protection function should be disabled before using this macro. 4114 */ 4115 #define SYS_SET_BOD_LEVEL(u32Level) \ 4116 do{ \ 4117 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4118 SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level); \ 4119 }while(0) 4120 4121 /** 4122 * @brief Get reset source is from Brown-out detector reset 4123 * @param None 4124 * @retval 0 Previous reset source is not from Brown-out detector reset 4125 * @retval >=1 Previous reset source is from Brown-out detector reset 4126 * @details This macro get previous reset source is from Brown-out detect reset or not. 4127 */ 4128 #define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) 4129 4130 /** 4131 * @brief Get reset source is from CPU reset 4132 * @param None 4133 * @retval 0 Previous reset source is not from CPU reset 4134 * @retval >=1 Previous reset source is from CPU reset 4135 * @details This macro get previous reset source is from CPU reset. 4136 */ 4137 #define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) 4138 4139 /** 4140 * @brief Get reset source is from LVR Reset 4141 * @param None 4142 * @retval 0 Previous reset source is not from Low-Voltage-Reset 4143 * @retval >=1 Previous reset source is from Low-Voltage-Reset 4144 * @details This macro get previous reset source is from Low-Voltage-Reset. 4145 */ 4146 #define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) 4147 4148 /** 4149 * @brief Get reset source is from Power-on Reset 4150 * @param None 4151 * @retval 0 Previous reset source is not from Power-on Reset 4152 * @retval >=1 Previous reset source is from Power-on Reset 4153 * @details This macro get previous reset source is from Power-on Reset. 4154 */ 4155 #define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) 4156 4157 /** 4158 * @brief Get reset source is from reset pin reset 4159 * @param None 4160 * @retval 0 Previous reset source is not from reset pin reset 4161 * @retval >=1 Previous reset source is from reset pin reset 4162 * @details This macro get previous reset source is from reset pin reset. 4163 */ 4164 #define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) 4165 4166 /** 4167 * @brief Get reset source is from system reset 4168 * @param None 4169 * @retval 0 Previous reset source is not from system reset 4170 * @retval >=1 Previous reset source is from system reset 4171 * @details This macro get previous reset source is from system reset. 4172 */ 4173 #define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) 4174 4175 /** 4176 * @brief Get reset source is from window watch dog reset 4177 * @param None 4178 * @retval 0 Previous reset source is not from window watch dog reset 4179 * @retval >=1 Previous reset source is from window watch dog reset 4180 * @details This macro get previous reset source is from window watch dog reset. 4181 */ 4182 #define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) 4183 4184 /** 4185 * @brief Disable Low-Voltage-Reset function 4186 * @param None 4187 * @return None 4188 * @details This macro disable Low-Voltage-Reset function. 4189 * The register write-protection function should be disabled before using this macro. 4190 */ 4191 #define SYS_DISABLE_LVR() \ 4192 do{ \ 4193 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4194 SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk; \ 4195 }while(0) 4196 4197 /** 4198 * @brief Enable Low-Voltage-Reset function 4199 * @param None 4200 * @return None 4201 * @details This macro enable Low-Voltage-Reset function. 4202 * The register write-protection function should be disabled before using this macro. 4203 */ 4204 #define SYS_ENABLE_LVR() \ 4205 do{ \ 4206 while(SYS->BODCTL & SYS_BODCTL_WRBUSY_Msk); \ 4207 SYS->BODCTL |= SYS_BODCTL_LVREN_Msk; \ 4208 }while(0) 4209 4210 /** 4211 * @brief Disable Power-on Reset function 4212 * @param None 4213 * @return None 4214 * @details This macro disable Power-on Reset function. 4215 * The register write-protection function should be disabled before using this macro. 4216 */ 4217 #define SYS_DISABLE_POR() (SYS->PORCTL0 = 0x5AA5) 4218 4219 /** 4220 * @brief Enable Power-on Reset function 4221 * @param None 4222 * @return None 4223 * @details This macro enable Power-on Reset function. 4224 * The register write-protection function should be disabled before using this macro. 4225 */ 4226 #define SYS_ENABLE_POR() (SYS->PORCTL0 = 0) 4227 4228 /** 4229 * @brief Clear reset source flag 4230 * @param[in] u32RstSrc is reset source. Including : 4231 * - \ref SYS_RSTSTS_PORF_Msk 4232 * - \ref SYS_RSTSTS_PINRF_Msk 4233 * - \ref SYS_RSTSTS_WDTRF_Msk 4234 * - \ref SYS_RSTSTS_LVRF_Msk 4235 * - \ref SYS_RSTSTS_BODRF_Msk 4236 * - \ref SYS_RSTSTS_SYSRF_Msk 4237 * - \ref SYS_RSTSTS_CPURF_Msk 4238 * - \ref SYS_RSTSTS_CPULKRF_Msk 4239 * @return None 4240 * @details This macro clear reset source flag. 4241 */ 4242 #define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) 4243 4244 4245 /*---------------------------------------------------------------------------------------------------------*/ 4246 /* static inline functions */ 4247 /*---------------------------------------------------------------------------------------------------------*/ 4248 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ 4249 __STATIC_INLINE void SYS_UnlockReg(void); 4250 __STATIC_INLINE void SYS_LockReg(void); 4251 4252 4253 /** 4254 * @brief Disable register write-protection function 4255 * @param None 4256 * @return None 4257 * @details This function disable register write-protection function. 4258 * To unlock the protected register to allow write access. 4259 */ SYS_UnlockReg(void)4260 __STATIC_INLINE void SYS_UnlockReg(void) 4261 { 4262 do 4263 { 4264 SYS->REGLCTL = 0x59UL; 4265 SYS->REGLCTL = 0x16UL; 4266 SYS->REGLCTL = 0x88UL; 4267 } 4268 while(SYS->REGLCTL == 0UL); 4269 } 4270 4271 /** 4272 * @brief Enable register write-protection function 4273 * @param None 4274 * @return None 4275 * @details This function is used to enable register write-protection function. 4276 * To lock the protected register to forbid write access. 4277 */ SYS_LockReg(void)4278 __STATIC_INLINE void SYS_LockReg(void) 4279 { 4280 SYS->REGLCTL = 0UL; 4281 } 4282 4283 4284 void SYS_ClearResetSrc(uint32_t u32Src); 4285 uint32_t SYS_GetBODStatus(void); 4286 uint32_t SYS_GetResetSrc(void); 4287 uint32_t SYS_IsRegLocked(void); 4288 uint32_t SYS_ReadPDID(void); 4289 void SYS_ResetChip(void); 4290 void SYS_ResetCPU(void); 4291 void SYS_ResetModule(uint32_t u32ModuleIndex); 4292 void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); 4293 void SYS_DisableBOD(void); 4294 void SYS_SetPowerLevel(uint32_t u32PowerLevel); 4295 uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator); 4296 void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); 4297 void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); 4298 void SYS_SetVRef(uint32_t u32VRefCTL); 4299 4300 4301 /**@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ 4302 4303 /**@}*/ /* end of group SYS_Driver */ 4304 4305 /**@}*/ /* end of group Standard_Driver */ 4306 4307 4308 #ifdef __cplusplus 4309 } 4310 #endif 4311 4312 #endif /* __SYS_H__ */ 4313