1 /* 2 * Copyright (c) 2017-2020 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /* 18 * This file is derivative of CMSIS V5.01 Device\_Template_Vendor\Vendor\Device\Include\Device.h 19 */ 20 21 #ifndef __PLATFORM_BASE_ADDRESS_H__ 22 #define __PLATFORM_BASE_ADDRESS_H__ 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 29 /* =========================================================================================================================== */ 30 /* ================ Device Specific Peripheral Address Map ================ */ 31 /* =========================================================================================================================== */ 32 33 34 /** @addtogroup Device_Peripheral_peripheralAddr 35 * @{ 36 */ 37 38 /* Non-Secure Peripheral and SRAM base address */ 39 #define MUSCA_S1_CODE_SRAM_NS_BASE (0x00000000UL) /*!< (Non-Secure Code SRAM ) Base Address */ 40 #define MUSCA_S1_QSPI_FLASH_NS_BASE (0x00200000UL) /*!< (Non-Secure QSPI FLASH ) Base Address */ 41 #define MUSCA_S1_MRAM_NS_BASE (0x0A000000UL) /*!< (Non-Secure MRAM ) Base Address */ 42 #define MUSCA_S1_OTP_NS_BASE (0x0E000000UL) /*!< (Non-Secure OTP ) Base Address */ 43 #define MUSCA_S1_SRAM_NS_BASE (0x20000000UL) /*!< (Non-Secure Internal SRAM ) Base Address */ 44 #define MUSCA_S1_BASE_ELEMENT_NS_BASE (0x40000000UL) /*!< (Non-Secure Base Peripherals ) Base Address */ 45 #define MUSCA_S1_CMSDK_TIMER0_NS_BASE (0x40000000UL) /*!< (Non-Secure CMSDK Timer0 ) Base Address */ 46 #define MUSCA_S1_CMSDK_TIMER1_NS_BASE (0x40001000UL) /*!< (Non-Secure CMSDK Timer1 ) Base Address */ 47 #define MUSCA_S1_CMSDK_DUALTIMER_NS_BASE (0x40002000UL) /*!< (Non-Secure CMSDK Dual Timer ) Base Address */ 48 #define MUSCA_S1_MHU0_NS_BASE (0x40003000UL) /*!< (Non-Secure MHU0 ) Base Address */ 49 #define MUSCA_S1_MHU1_NS_BASE (0x40004000UL) /*!< (Non-Secure MHU1 ) Base Address */ 50 #define MUSCA_S1_CPU_ELEMENT_NS_BASE (0x40010000UL) /*!< (Non-Secure CPU Peripherals ) Base Address */ 51 #define MUSCA_S1_SYSTEM_INFO_NS_BASE (0x40020000UL) /*!< (Non-Secure System Info ) Base Address */ 52 #define MUSCA_S1_CMSDK_S32KTIMER_NS_BASE (0x4002F000UL) /*!< (Non-Secure CMSDK S32K Timer ) Base Address */ 53 #define MUSCA_S1_NSPCTRL_NS_BASE (0x40080000UL) /*!< (Non-Secure Privilege Ctrl Blk) Base Address */ 54 #define MUSCA_S1_CMSDK_WATCHDOG_NS_BASE (0x40081000UL) /*!< (Non-Secure CMSDK Watchdog ) Base Address */ 55 #define MUSCA_S1_UART0_NS_BASE (0x40101000UL) /*!< (Non-Secure UART0 ) Base Address */ 56 #define MUSCA_S1_UART1_NS_BASE (0x40102000UL) /*!< (Non-Secure UART1 ) Base Address */ 57 #define MUSCA_S1_SPI0_NS_BASE (0x40103000UL) /*!< (Non-Secure SPI0 ) Base Address */ 58 #define MUSCA_S1_I2C0_NS_BASE (0x40104000UL) /*!< (Non-Secure I2C0 ) Base Address */ 59 #define MUSCA_S1_I2C1_NS_BASE (0x40105000UL) /*!< (Non-Secure I2C1 ) Base Address */ 60 #define MUSCA_S1_I2S_NS_BASE (0x40106000UL) /*!< (Non-Secure I2S ) Base Address */ 61 #define MUSCA_S1_PWM0_NS_BASE (0x40107000UL) /*!< (Non-Secure PWM0 ) Base Address */ 62 #define MUSCA_S1_RTC_NS_BASE (0x40108000UL) /*!< (Non-Secure RTC ) Base Address */ 63 #define MUSCA_S1_PVT_NS_BASE (0x40109000UL) /*!< (Non-Secure PVT sensors ) Base Address */ 64 #define MUSCA_S1_QSPI_REG_NS_BASE (0x4010A000UL) /*!< (Non-Secure QSPI registers ) Base Address */ 65 #define MUSCA_S1_TIMER_NS_BASE (0x4010B000UL) /*!< (Non-Secure Timer ) Base Address */ 66 #define MUSCA_S1_SCC_NS_BASE (0x4010C000UL) /*!< (Non-Secure SCC ) Base Address */ 67 #define MUSCA_S1_PWM1_NS_BASE (0x4010E000UL) /*!< (Non-Secure PWM1 ) Base Address */ 68 #define MUSCA_S1_PWM2_NS_BASE (0x4010F000UL) /*!< (Non-Secure PWM2 ) Base Address */ 69 #define MUSCA_S1_GPIO_NS_BASE (0x40110000UL) /*!< (Non-Secure GPIO ) Base Address */ 70 #define MUSCA_S1_QSPI_MPC_NS_BASE (0x40120000UL) /*!< (Non-Secure QSPI MPC ) Base Address */ 71 #define MUSCA_S1_CODE_SRAM_MPC_NS_BASE (0x40130000UL) /*!< (Non-Secure Code SRAM MPC ) Base Address */ 72 #define MUSCA_S1_MRAM_MPC_NS_BASE (0x40140000UL) /*!< (Non-Secure MRAM MPC ) Base Address */ 73 #define MUSCA_S1_DEFAULT_SLAVE_NS_BASE (0x60000000UL) /*!< (Non-Secure Unused AHB ) Base Address */ 74 /* Secure Peripheral and SRAM base address */ 75 #define MUSCA_S1_CODE_SRAM_S_BASE (0x10000000UL) /*!< (Secure Code SRAM ) Base Address */ 76 #define MUSCA_S1_QSPI_FLASH_S_BASE (0x10200000UL) /*!< (Secure QSPI FLASH ) Base Address */ 77 #define MUSCA_S1_MRAM_S_BASE (0x1A000000UL) /*!< (Secure MRAM ) Base Address */ 78 #define MUSCA_S1_OTP_S_BASE (0x1E000000UL) /*!< (Secure OTP ) Base Address */ 79 #define MUSCA_S1_SRAM_S_BASE (0x30000000UL) /*!< (Secure Internal SRAM ) Base Address */ 80 #define MUSCA_S1_BASE_ELEMENT_S_BASE (0x50000000UL) /*!< (Secure Base Peripherals ) Base Address */ 81 #define MUSCA_S1_MHU0_S_BASE (0x50003000UL) /*!< (Secure MHU0 ) Base Address */ 82 #define MUSCA_S1_MHU1_S_BASE (0x50004000UL) /*!< (Secure MHU1 ) Base Address */ 83 #define MUSCA_S1_CPU_ELEMENT_S_BASE (0x50010000UL) /*!< (Secure CPU Peripherals ) Base Address */ 84 #define MUSCA_S1_SYSTEM_INFO_S_BASE (0x50020000UL) /*!< (Secure System Info ) Base Address */ 85 #define MUSCA_S1_SYSTEM_CTRL_S_BASE (0x50021000UL) /*!< (Secure System Control ) Base Address */ 86 #define MUSCA_S1_CMSDK_S32KTIMER_S_BASE (0x5002F000UL) /*!< (Secure CMSDK S32K Timer ) Base Address */ 87 #define MUSCA_S1_CMSDK_TIMER0_S_BASE (0x50000000UL) /*!< (Secure CMSDK Timer0 ) Base Address */ 88 #define MUSCA_S1_CMSDK_TIMER1_S_BASE (0x50001000UL) /*!< (Secure CMSDK Timer1 ) Base Address */ 89 #define MUSCA_S1_CMSDK_DUALTIMER_S_BASE (0x50002000UL) /*!< (Secure CMSDK Dual Timer ) Base Address */ 90 #define MUSCA_S1_SPCTRL_S_BASE (0x50080000UL) /*!< (Secure Privilege Ctrl Blk) Base Address */ 91 #define MUSCA_S1_CMSDK_WATCHDOG_S_BASE (0x50081000UL) /*!< (Secure CMSDK Watchdog ) Base Address */ 92 #define MUSCA_S1_MPC_SRAM0_S_BASE (0x50083000UL) /*!< (Secure MPC SRAM Bank 0 ) Base Address */ 93 #define MUSCA_S1_MPC_SRAM1_S_BASE (0x50084000UL) /*!< (Secure MPC SRAM Bank 1 ) Base Address */ 94 #define MUSCA_S1_MPC_SRAM2_S_BASE (0x50085000UL) /*!< (Secure MPC SRAM Bank 2 ) Base Address */ 95 #define MUSCA_S1_MPC_SRAM3_S_BASE (0x50086000UL) /*!< (Secure MPC SRAM Bank 3 ) Base Address */ 96 #define MUSCA_S1_UART0_S_BASE (0x50101000UL) /*!< (Secure UART0 ) Base Address */ 97 #define MUSCA_S1_UART1_S_BASE (0x50102000UL) /*!< (Secure UART1 ) Base Address */ 98 #define MUSCA_S1_SPI0_S_BASE (0x50103000UL) /*!< (Secure SPI0 ) Base Address */ 99 #define MUSCA_S1_I2C0_S_BASE (0x50104000UL) /*!< (Secure I2C0 ) Base Address */ 100 #define MUSCA_S1_I2C1_S_BASE (0x50105000UL) /*!< (Secure I2C1 ) Base Address */ 101 #define MUSCA_S1_I2S_S_BASE (0x50106000UL) /*!< (Secure I2S ) Base Address */ 102 #define MUSCA_S1_PWM0_S_BASE (0x50107000UL) /*!< (Secure PWM0 ) Base Address */ 103 #define MUSCA_S1_RTC_S_BASE (0x50108000UL) /*!< (Secure RTC ) Base Address */ 104 #define MUSCA_S1_PVT_S_BASE (0x50109000UL) /*!< (Secure PVT sensors ) Base Address */ 105 #define MUSCA_S1_QSPI_REG_S_BASE (0x5010A000UL) /*!< (Secure QSPI registers ) Base Address */ 106 #define MUSCA_S1_TIMER_S_BASE (0x5010B000UL) /*!< (Secure Timer ) Base Address */ 107 #define MUSCA_S1_SCC_S_BASE (0x5010C000UL) /*!< (Secure SCC ) Base Address */ 108 #define MUSCA_S1_PWM1_S_BASE (0x5010E000UL) /*!< (Secure PWM1 ) Base Address */ 109 #define MUSCA_S1_PWM2_S_BASE (0x5010F000UL) /*!< (Secure PWM2 ) Base Address */ 110 #define MUSCA_S1_GPIO_S_BASE (0x50110000UL) /*!< (Secure GPIO ) Base Address */ 111 #define MUSCA_S1_QSPI_MPC_S_BASE (0x50120000UL) /*!< (Secure QSPI MPC ) Base Address */ 112 #define MUSCA_S1_CODE_SRAM_MPC_S_BASE (0x50130000UL) /*!< (Secure Code SRAM MPC ) Base Address */ 113 #define MUSCA_S1_MRAM_MPC_S_BASE (0x50140000UL) /*!< (Secure MRAM MPC ) Base Address */ 114 #define MUSCA_S1_DEFAULT_SLAVE_S_BASE (0x70000000UL) /*!< (Secure Unused AHB ) Base Address */ 115 116 /* SRAM MPC ranges and limits */ 117 /* Internal memory */ 118 #define MPC_ISRAM0_RANGE_BASE_NS (0x20000000) 119 #define MPC_ISRAM0_RANGE_LIMIT_NS (0x2001FFFF) 120 #define MPC_ISRAM0_RANGE_BASE_S (0x30000000) 121 #define MPC_ISRAM0_RANGE_LIMIT_S (0x3001FFFF) 122 123 #define MPC_ISRAM1_RANGE_BASE_NS (0x20020000) 124 #define MPC_ISRAM1_RANGE_LIMIT_NS (0x2003FFFF) 125 #define MPC_ISRAM1_RANGE_BASE_S (0x30020000) 126 #define MPC_ISRAM1_RANGE_LIMIT_S (0x3003FFFF) 127 128 #define MPC_ISRAM2_RANGE_BASE_NS (0x20040000) 129 #define MPC_ISRAM2_RANGE_LIMIT_NS (0x2005FFFF) 130 #define MPC_ISRAM2_RANGE_BASE_S (0x30040000) 131 #define MPC_ISRAM2_RANGE_LIMIT_S (0x3005FFFF) 132 133 #define MPC_ISRAM3_RANGE_BASE_NS (0x20060000) 134 #define MPC_ISRAM3_RANGE_LIMIT_NS (0x2007FFFF) 135 #define MPC_ISRAM3_RANGE_BASE_S (0x30060000) 136 #define MPC_ISRAM3_RANGE_LIMIT_S (0x3007FFFF) 137 138 /* Code SRAM memory */ 139 #define MPC_CODE_SRAM_RANGE_BASE_NS (0x00000000) 140 #define MPC_CODE_SRAM_RANGE_LIMIT_NS (0x001FFFFF) 141 #define MPC_CODE_SRAM_RANGE_BASE_S (0x10000000) 142 #define MPC_CODE_SRAM_RANGE_LIMIT_S (0x101FFFFF) 143 144 /* QSPI Flash memory */ 145 #define MPC_QSPI_RANGE_BASE_NS (0x00200000) 146 #define MPC_QSPI_RANGE_LIMIT_NS (0x021FFFFF) 147 #define MPC_QSPI_RANGE_BASE_S (0x10200000) 148 #define MPC_QSPI_RANGE_LIMIT_S (0x121FFFFF) 149 150 /* MRAM memory */ 151 #define MPC_MRAM_RANGE_BASE_NS (0x0A000000) 152 #define MPC_MRAM_RANGE_LIMIT_NS (0x0A1FFFFF) 153 #define MPC_MRAM_RANGE_BASE_S (0x1A000000) 154 #define MPC_MRAM_RANGE_LIMIT_S (0x1A1FFFFF) 155 156 /** @} */ /* End of group Device_Peripheral_peripheralAddr */ 157 158 159 #ifdef __cplusplus 160 } 161 #endif 162 163 #endif /* __PLATFORM_BASE_ADDRESS_H__ */ 164
