1 /* 2 * Copyright (c) 2016-2018 ARM Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __SMM_MPS2_H__ 18 #define __SMM_MPS2_H__ 19 20 #include "cmsis.h" /* device specific header file */ 21 22 /* FPGAIO register map structure */ 23 struct arm_mps2_fpgaio_t { 24 volatile uint32_t LED; /* Offset: 0x000 (R/W) LED connections 25 * [31:2] : Reserved 26 * [1:0] : LEDs */ 27 volatile uint32_t RESERVED1[1]; 28 volatile uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons 29 * [31:2] : Reserved 30 * [1:0] : Buttons */ 31 volatile uint32_t RESERVED2[1]; 32 volatile uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */ 33 volatile uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */ 34 volatile uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter 35 * Increments when 36 * 32bit prescale 37 * counter reach 38 * zero */ 39 volatile uint32_t RESERVED3[1]; 40 volatile uint32_t PRESCALE; /* Offset: 0x020 (R/W) Prescaler 41 * Bit[31:0] : reload 42 * value for prescale 43 * counter */ 44 volatile uint32_t PSCNTR; /* Offset: 0x024 (R/W) 32bit Prescale 45 * counter. Current 46 * value of the 47 * prescaler counter. 48 * 49 * The Cycle Up Counter increment when the 50 * prescale down counter reach 0. 51 * The prescaler counter is reloaded with 52 * PRESCALE after reaching 0. */ 53 volatile uint32_t RESERVED4[9]; 54 volatile uint32_t MISC; /* Offset: 0x04C (R/W) Misc control 55 * [31:10] : Reserved 56 * [9] : SHIELD_1_SPI_nCS 57 * [8] : SHIELD_0_SPI_nCS 58 * [7] : ADC_SPI_nCS 59 * [6] : CLCD_BL_CTRL 60 * [5] : CLCD_RD 61 * [4] : CLCD_RS 62 * [3] : CLCD_RESET 63 * [2] : RESERVED 64 * [1] : SPI_nSS 65 * [0] : CLCD_CS */ 66 }; 67 68 /* SCC register map structure */ 69 struct arm_mps2_scc_t { 70 volatile uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to 71 * ZBT 72 * [31:1] : Reserved 73 * [0] 1 : REMAP BlockRam to ZBT */ 74 volatile uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user 75 * LEDs 76 * [31:8] : Reserved 77 * [7:0] : MCC LEDs */ 78 volatile uint32_t RESERVED0[1]; 79 volatile uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state 80 * of the MCC user 81 * switches 82 * [31:8] : Reserved 83 * [7:0] : These bits indicate state 84 * of the MCC switches */ 85 volatile uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board 86 * revision 87 * [31:4] : Reserved 88 * [3:0] : Used by the MCC to pass 89 * PCB revision. 90 * 0 = A 1 = B */ 91 volatile uint32_t RESERVED1[35]; 92 volatile uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register 93 * [31:0] : Data */ 94 volatile uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data 95 * register 96 * [31:0] : Data */ 97 volatile uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register 98 * [31] : Start (generates 99 * interrupt on write 100 * to this bit) 101 * [30] : R/W access 102 * [29:26] : Reserved 103 * [25:20] : Function value 104 * [19:12] : Reserved 105 * [11:0] : Device (value of 106 * 0/1/2 for supported 107 * clocks) */ 108 volatile uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status 109 * information 110 * [31:2] : Reserved 111 * [1] : Error 112 * [0] : Complete */ 113 volatile uint32_t RESERVED2[20]; 114 volatile uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register 115 * [31:24] : DLL LOCK MASK[7:0] 116 * Indicate if the DLL 117 * locked is masked 118 * [23:16] : DLL LOCK MASK[7:0] 119 * Indicate if the DLLs 120 * are locked or 121 * unlocked 122 * [15:1] : Reserved 123 * [0] : This bit indicates 124 * if all enabled DLLs 125 * are locked */ 126 volatile uint32_t RESERVED3[957]; 127 volatile uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register 128 * [31:24] : FPGA build number 129 * [23:20] : V2MMPS2 target 130 * board revision 131 * (A = 0, B = 1) 132 * [19:11] : Reserved 133 * [10] : if “1” SCC_SW 134 * register has been 135 * implemented 136 * [9] : if “1” SCC_LED 137 * register has been 138 * implemented 139 * [8] : if “1” DLL lock 140 * register has been 141 * implemented 142 * [7:0] : number of SCC 143 * configuration 144 * register */ 145 volatile uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains 146 * information about 147 * the FPGA image 148 * [31:24] : Implementer ID: 149 * 0x41 = ARM 150 * [23:20] : Application note 151 * IP variant number 152 * [19:16] : IP Architecture: 153 * 0x4 =AHB 154 * [15:4] : Primary part number: 155 * 386 = AN386 156 * [3:0] : Application note IP 157 * revision number */ 158 }; 159 160 /* Peripheral declaration */ 161 #define MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_IO_FPGAIO_BASE_NS) 162 #define MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_IO_SCC_BASE_NS) 163 164 /* Secure Peripheral declaration */ 165 #define SEC_MPS2_FPGAIO ((struct arm_mps2_fpgaio_t*) MPS2_IO_FPGAIO_BASE_S) 166 #define SEC_MPS2_SCC ((struct arm_mps2_scc_t*) MPS2_IO_SCC_BASE_S) 167 168 #endif /* __SMM_MPS2_H__ */ 169
