1 /* 2 * Copyright (c) 2019-2022 Arm Limited 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file platform_base_address.h 19 * \brief This file defines all the peripheral base addresses for RSS platform. 20 */ 21 22 #ifndef __PLATFORM_BASE_ADDRESS_H__ 23 #define __PLATFORM_BASE_ADDRESS_H__ 24 25 /* ======= Defines peripherals memory map addresses ======= */ 26 /* Non-secure memory map addresses */ 27 #define ITCM_BASE_NS 0x00000000 /* Instruction TCM Non-Secure base address */ 28 #define DTCM_BASE_NS 0x20000000 /* Data TCM Non-Secure base address */ 29 #define VM0_BASE_NS 0x21000000 /* Volatile Memory 0 Non-Secure base address */ 30 #define VM1_BASE_NS 0x21800000 /* Volatile Memory 1 Non-Secure base address */ 31 /* Non-Secure Private CPU region */ 32 #define CPU0_PWRCTRL_BASE_NS 0x40012000 /* CPU 0 Power Control Block Non-Secure base address */ 33 #define CPU0_IDENTITY_BASE_NS 0x4001F000 /* CPU 0 Identity Block Non-Secure base address */ 34 /* Non-Secure Peripheral region */ 35 #define DMA_350_BASE_NS 0x40002000 /* DMA350 Non-Secure base address */ 36 #define RSS_NSACFG_BASE_NS 0x40080000 /* RSS Non-Secure Access Configuration Register Block Non-Secure base address */ 37 #define GPIO0_CMSDK_BASE_NS 0x40100000 /* GPIO 0 Non-Secure base address */ 38 #define GPIO1_CMSDK_BASE_NS 0x40101000 /* GPIO 1 Non-Secure base address */ 39 #define MHU0_SENDER_BASE_NS 0x40160000 /* Combined MHU 0 Sender Non-Secure base address */ 40 #define MHU0_RECEIVER_BASE_NS 0x40170000 /* Combined MHU 0 Receiver Non-Secure base address */ 41 #define MHU1_SENDER_BASE_NS 0x40180000 /* Combined MHU 1 Sender Non-Secure base address */ 42 #define MHU1_RECEIVER_BASE_NS 0x40190000 /* Combined MHU 1 Receiver Non-Secure base address */ 43 #define MHU2_SENDER_BASE_NS 0x401A0000 /* Combined MHU 2 Sender Non-Secure base address */ 44 #define MHU2_RECEIVER_BASE_NS 0x401B0000 /* Combined MHU 2 Receiver Non-Secure base address */ 45 #define MHU3_SENDER_BASE_NS 0x401C0000 /* Combined MHU 3 Sender Non-Secure base address */ 46 #define MHU3_RECEIVER_BASE_NS 0x401D0000 /* Combined MHU 3 Receiver Non-Secure base address */ 47 #define MHU4_SENDER_BASE_NS 0x401E0000 /* Combined MHU 4 Sender Non-Secure base address */ 48 #define MHU4_RECEIVER_BASE_NS 0x401F0000 /* Combined MHU 4 Receiver Non-Secure base address */ 49 #define MHU5_SENDER_BASE_NS 0x40200000 /* Combined MHU 5 Sender Non-Secure base address */ 50 #define MHU5_RECEIVER_BASE_NS 0x40210000 /* Combined MHU 5 Receiver Non-Secure base address */ 51 #define MHU6_SENDER_BASE_NS 0x40220000 /* Combined MHU 6 Sender Non-Secure base address */ 52 #define MHU6_RECEIVER_BASE_NS 0x40230000 /* Combined MHU 6 Receiver Non-Secure base address */ 53 #define MHU7_SENDER_BASE_NS 0x40240000 /* Combined MHU 7 Sender Non-Secure base address */ 54 #define MHU7_RECEIVER_BASE_NS 0x40250000 /* Combined MHU 7 Receiver Non-Secure base address */ 55 #define MHU8_SENDER_BASE_NS 0x40260000 /* Combined MHU 8 Sender Non-Secure base address */ 56 #define MHU8_RECEIVER_BASE_NS 0x40270000 /* Combined MHU 8 Receiver Non-Secure base address */ 57 #define SYSTIMER0_ARMV8_M_BASE_NS 0x48000000 /* System Timer 0 Non-Secure base address */ 58 #define SYSTIMER1_ARMV8_M_BASE_NS 0x48001000 /* System Timer 1 Non-Secure base address */ 59 #define SYSTIMER2_ARMV8_M_BASE_NS 0x48002000 /* System Timer 2 Non-Secure base address */ 60 #define SYSTIMER3_ARMV8_M_BASE_NS 0x48003000 /* System Timer 3 Non-Secure base address */ 61 #define RSS_SYSINFO_BASE_NS 0x48020000 /* RSS System info Block Non-Secure base address */ 62 #define SLOWCLK_TIMER_CMSDK_BASE_NS 0x4802F000 /* CMSDK based SLOWCLK Timer Non-Secure base address */ 63 #define SYSWDOG_ARMV8_M_CNTRL_BASE_NS 0x48040000 /* Non-Secure Watchdog Timer control frame Non-Secure base address */ 64 #define SYSWDOG_ARMV8_M_REFRESH_BASE_NS 0x48041000 /* Non-Secure Watchdog Timer refresh frame Non-Secure base address */ 65 /* Non-Secure Host region */ 66 #define HOST_ACCESS_BASE_NS 0x60000000 /* Can access the Host region based on ATU config */ 67 #define HOST_ACCESS_LIMIT_NS (HOST_ACCESS_BASE_NS + HOST_ACCESS_SIZE - 1) 68 /* ATU regions open in bootloader and runtime */ 69 #define UART0_BASE_NS (HOST_ACCESS_BASE_NS + 0xFF00000) /* UART 0 Non-Secure base address */ 70 71 /* Secure memory map addresses */ 72 #define ITCM_BASE_S 0x10000000 /* Instruction TCM Secure base address */ 73 #define ROM_BASE_S 0x11000000 /* CODE ROM Secure base address. No NS alias for ROM */ 74 #define DTCM_BASE_S 0x30000000 /* Data TCM Secure base address */ 75 #define VM0_BASE_S 0x31000000 /* Volatile Memory 0 Secure base address */ 76 #define VM1_BASE_S 0x31800000 /* Volatile Memory 1 Secure base address */ 77 /* Secure Private CPU region */ 78 #define CPU0_SECCTRL_BASE_S 0x50011000 /* CPU 0 Local Security Control Block Secure base address */ 79 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base address */ 80 #define CPU0_IDENTITY_BASE_S 0x5001F000 /* CPU 0 Identity Block Secure base address */ 81 /* Secure Peripheral region */ 82 #define DMA_350_BASE_S 0x50002000 /* DMA350 Secure base address */ 83 #define RSS_SACFG_BASE_S 0x50080000 /* RSS Secure Access Configuration Register Secure base address */ 84 #define MPC_VM0_BASE_S 0x50083000 /* VM0 Memory Protection Controller Secure base address */ 85 #define MPC_VM1_BASE_S 0x50084000 /* VM1 Memory Protection Controller Secure base address */ 86 #define KMU_BASE_S 0x5009E000 /* KMU Secure base address */ 87 #define LCM_BASE_S 0x500A0000 /* LCM Secure base address */ 88 #define GPIO0_CMSDK_BASE_S 0x50100000 /* GPIO 0 Secure base address */ 89 #define GPIO1_CMSDK_BASE_S 0x50101000 /* GPIO 1 Secure base address */ 90 #define ATU_BASE_S 0x50150000 /* ATU Secure base address */ 91 #define SYSCNTR_CNTRL_BASE_S 0x5015A000 /* System Counter Control Secure base address */ 92 #define SYSCNTR_READ_BASE_S 0x5015B000 /* System Counter Read Secure base address */ 93 #define MHU0_SENDER_BASE_S 0x50160000 /* Combined MHU 0 Sender Secure base address */ 94 #define MHU0_RECEIVER_BASE_S 0x50170000 /* Combined MHU 0 Receiver Secure base address */ 95 #define MHU1_SENDER_BASE_S 0x50180000 /* Combined MHU 1 Sender Secure base address */ 96 #define MHU1_RECEIVER_BASE_S 0x50190000 /* Combined MHU 1 Receiver Secure base address */ 97 #define MHU2_SENDER_BASE_S 0x501A0000 /* Combined MHU 2 Sender Secure base address */ 98 #define MHU2_RECEIVER_BASE_S 0x501B0000 /* Combined MHU 2 Receiver Secure base address */ 99 #define MHU3_SENDER_BASE_S 0x501C0000 /* Combined MHU 3 Sender Secure base address */ 100 #define MHU3_RECEIVER_BASE_S 0x501D0000 /* Combined MHU 3 Receiver Secure base address */ 101 #define MHU4_SENDER_BASE_S 0x501E0000 /* Combined MHU 4 Sender Secure base address */ 102 #define MHU4_RECEIVER_BASE_S 0x501F0000 /* Combined MHU 4 Receiver Secure base address */ 103 #define MHU5_SENDER_BASE_S 0x50200000 /* Combined MHU 5 Sender Secure base address */ 104 #define MHU5_RECEIVER_BASE_S 0x50210000 /* Combined MHU 5 Receiver Secure base address */ 105 #define MHU6_SENDER_BASE_S 0x50220000 /* Combined MHU 6 Sender Secure base address */ 106 #define MHU6_RECEIVER_BASE_S 0x50230000 /* Combined MHU 6 Receiver Secure base address */ 107 #define MHU7_SENDER_BASE_S 0x50240000 /* Combined MHU 7 Sender Secure base address */ 108 #define MHU7_RECEIVER_BASE_S 0x50250000 /* Combined MHU 7 Receiver Secure base address */ 109 #define MHU8_SENDER_BASE_S 0x50260000 /* Combined MHU 8 Sender Secure base address */ 110 #define MHU8_RECEIVER_BASE_S 0x50270000 /* Combined MHU 8 Receiver Secure base address */ 111 #define SYSTIMER0_ARMV8_M_BASE_S 0x58000000 /* System Timer 0 Secure base address */ 112 #define SYSTIMER1_ARMV8_M_BASE_S 0x58001000 /* System Timer 1 Secure base address */ 113 #define SYSTIMER2_ARMV8_M_BASE_S 0x58002000 /* System Timer 2 Secure base address */ 114 #define SYSTIMER3_ARMV8_M_BASE_S 0x58003000 /* System Timer 3 Secure base address */ 115 #define RSS_SYSINFO_BASE_S 0x58020000 /* RSS System info Block Secure base address */ 116 #define RSS_SYSCTRL_BASE_S 0x58021000 /* RSS System control Block Secure base address */ 117 #define RSS_SYSPPU_BASE_S 0x58022000 /* RSS System Power Policy Unit Secure base address */ 118 #define RSS_CPU0PPU_BASE_S 0x58023000 /* RSS CPU 0 Power Policy Unit Secure base address */ 119 #define RSS_MGMTPPU_BASE_S 0x58028000 /* RSS Management Power Policy Unit Secure base address */ 120 #define RSS_DBGPPU_BASE_S 0x58029000 /* RSS Debug Power Policy Unit Secure base address */ 121 #define SLOWCLK_WDOG_CMSDK_BASE_S 0x5802E000 /* CMSDK based SLOWCLK Watchdog Secure base address */ 122 #define SLOWCLK_TIMER_CMSDK_BASE_S 0x5802F000 /* CMSDK based SLOWCLK Timer Secure base address */ 123 #define SYSWDOG_ARMV8_M_CNTRL_BASE_S 0x58040000 /* Secure Watchdog Timer control frame Secure base address */ 124 #define SYSWDOG_ARMV8_M_REFRESH_BASE_S 0x58041000 /* Secure Watchdog Timer refresh frame Secure base address */ 125 /* Secure Host region */ 126 #define HOST_ACCESS_BASE_S 0x70000000 /* Can access the Host region based on ATU config */ 127 #define HOST_ACCESS_LIMIT_S (HOST_ACCESS_BASE_S + HOST_ACCESS_SIZE - 1) 128 /* ATU regions open in bootloader and runtime */ 129 #define UART0_BASE_S (HOST_ACCESS_BASE_S + 0xFF00000) /* UART 0 Secure base address */ 130 /* ATU regions open in BL2 */ 131 #define HOST_BOOT0_LOAD_BASE_S HOST_ACCESS_BASE_S /* Host boot image 0 base address */ 132 #define HOST_BOOT1_LOAD_BASE_S (HOST_ACCESS_BASE_S + 0x100000) /* Host boot image 1 base address */ 133 /* Regions open at runtime */ 134 #define HOST_COMMS_MAPPABLE_BASE_S HOST_ACCESS_BASE_S 135 136 /* Memory map addresses exempt from memory attribution by both the SAU and IDAU */ 137 #define RSS_EWIC_BASE 0xE0047000 /* External Wakeup Interrupt Controller 138 * Access from Non-secure software is only allowed 139 * if AIRCR.BFHFNMINS is set to 1 */ 140 141 /* Memory size definitions */ 142 #define ITCM_SIZE 0x00008000 /* 32 kB */ 143 #define ROM_SIZE 0x00020000 /* 128 kB */ 144 #define DTCM_SIZE 0x00008000 /* 32 kB */ 145 #define VM0_SIZE 0x00800000 /* 8 MB */ 146 #define VM1_SIZE 0x00800000 /* 8 MB */ 147 #define HOST_ACCESS_SIZE 0x10000000 /* 256 MB */ 148 149 /* Defines for Driver MPC's */ 150 /* VM0 -- 8 MB */ 151 #define MPC_VM0_RANGE_BASE_NS (VM0_BASE_NS) 152 #define MPC_VM0_RANGE_LIMIT_NS (VM0_BASE_NS + VM0_SIZE-1) 153 #define MPC_VM0_RANGE_OFFSET_NS (0x0) 154 #define MPC_VM0_RANGE_BASE_S (VM0_BASE_S) 155 #define MPC_VM0_RANGE_LIMIT_S (VM0_BASE_S + VM0_SIZE-1) 156 #define MPC_VM0_RANGE_OFFSET_S (0x0) 157 158 /* VM1 -- 8 MB */ 159 #define MPC_VM1_RANGE_BASE_NS (VM1_BASE_NS) 160 #define MPC_VM1_RANGE_LIMIT_NS (VM1_BASE_NS + VM1_SIZE-1) 161 #define MPC_VM1_RANGE_OFFSET_NS (0x0) 162 #define MPC_VM1_RANGE_BASE_S (VM1_BASE_S) 163 #define MPC_VM1_RANGE_LIMIT_S (VM1_BASE_S + VM1_SIZE-1) 164 #define MPC_VM1_RANGE_OFFSET_S (0x0) 165 166 #endif /* __PLATFORM_BASE_ADDRESS_H__ */ 167
