1 /* 2 * Copyright (c) 2019-2020 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file platform_base_address.h 19 * \brief This file defines all the peripheral base addresses for MPS3 SSE-200 20 * AN524 platform. 21 */ 22 23 #ifndef __PLATFORM_BASE_ADDRESS_H_ 24 #define __PLATFORM_BASE_ADDRESS_H_ 25 26 /* ======= Defines peripherals memory map addresses ======= */ 27 /* Non-secure memory map addresses */ 28 #define CMSDK_TIMER0_BASE_NS 0x40000000 29 #define CMSDK_TIMER1_BASE_NS 0x40001000 30 #define CMSDK_DUALTIMER_BASE_NS 0x40002000 31 #define CMSDK_SYSINFO_BASE_NS 0x40020000 32 #define S32K_TIMER_BASE_NS 0x4002F000 33 #define CMSDK_NSPCTRL_BASE_NS 0x40080000 34 #define APB_WATCHDOG_BASE_NS 0x40081000 35 #define GPIO0_BASE_NS 0x41100000 36 #define GPIO1_BASE_NS 0x41101000 37 #define GPIO2_BASE_NS 0x41102000 38 #define GPIO3_BASE_NS 0x41103000 39 #define I2C0_SBCON_BASE_NS 0x41200000 /* Touchscreen I2C Base Address */ 40 #define I2C1_SBCON_BASE_NS 0x41201000 /* Audio I2C Base Address */ 41 #define SSP0_BASE_NS 0x41202000 /* ADC SPI PL022 Base Address */ 42 #define SSP1_BASE_NS 0x41203000 /* Shield 0 SPI PL022 Base Address */ 43 #define SSP2_BASE_NS 0x41204000 /* Shield 1 SPI PL022 Base Address */ 44 #define I2C2_SBCON_BASE_NS 0x41205000 /* Shield 0 SBCon Base Address */ 45 #define I2C3_SBCON_BASE_NS 0x41206000 /* Shield 1 SBCon Base Address */ 46 #define I2C4_SBCON_BASE_NS 0x41208000 /* DDR4 EEPROM I2C Base Address */ 47 #define MPS3_IO_SCC_BASE_NS 0x41300000 48 #define I2S_BASE_NS 0x41301000 /* Audio I2S Base Address */ 49 #define MPS3_IO_FPGAIO_BASE_NS 0x41302000 50 #define UART0_BASE_NS 0x41303000 51 #define UART1_BASE_NS 0x41304000 52 #define UART2_BASE_NS 0x41305000 53 #define UART3_BASE_NS 0x41306000 54 #define UART4_BASE_NS 0x41307000 55 #define UART5_BASE_NS 0x41308000 56 #define CLCD_CONFIG_BASE_NS 0x4130A000 57 #define RTC_BASE_NS 0x4130B000 58 #define ETHERNET_BASE_NS 0x41400000 59 60 /* Secure memory map addresses */ 61 #define CMSDK_TIMER0_BASE_S 0x50000000 62 #define CMSDK_TIMER1_BASE_S 0x50001000 63 #define CMSDK_DUALTIMER_BASE_S 0x50002000 64 #define CMSDK_SYSINFO_BASE_S 0x50020000 65 #define CMSDK_SYSCTRL_BASE_S 0x50021000 66 #define S32K_WATCHDOG_BASE_S 0x5002E000 67 #define S32K_TIMER_BASE_S 0x5002F000 68 #define CMSDK_SPCTRL_BASE_S 0x50080000 69 #define APB_WATCHDOG_BASE_S 0x50081000 70 #define GPIO0_BASE_S 0x51100000 71 #define GPIO1_BASE_S 0x51101000 72 #define GPIO2_BASE_S 0x51102000 73 #define GPIO3_BASE_S 0x51103000 74 #define I2C0_SBCON_BASE_S 0x51200000 75 #define I2C1_SBCON_BASE_S 0x51201000 76 #define SSP0_BASE_S 0x51202000 77 #define SSP1_BASE_S 0x51203000 78 #define SSP2_BASE_S 0x51204000 79 #define I2C2_SBCON_BASE_S 0x51205000 80 #define I2C3_SBCON_BASE_S 0x51206000 81 #define I2C4_SBCON_BASE_S 0x51208000 82 #define MPS3_IO_SCC_BASE_S 0x51300000 83 #define I2S_BASE_S 0x51301000 84 #define MPS3_IO_FPGAIO_BASE_S 0x51302000 85 #define UART0_BASE_S 0x51303000 86 #define UART1_BASE_S 0x51304000 87 #define UART2_BASE_S 0x51305000 88 #define UART3_BASE_S 0x51306000 89 #define UART4_BASE_S 0x51307000 90 #define UART5_BASE_S 0x51308000 91 #define CLCD_CONFIG_BASE_S 0x5130A000 92 #define RTC_BASE_S 0x5130B000 93 #define ETHERNET_BASE_S 0x51400000 94 #define MPC_ISRAM0_BASE_S 0x50083000 95 #define MPC_ISRAM1_BASE_S 0x50084000 96 #define MPC_ISRAM2_BASE_S 0x50085000 97 #define MPC_ISRAM3_BASE_S 0x50086000 98 #define MPC_BRAM_BASE_S 0x58007000 99 #define MPC_QSPI_BASE_S 0x58008000 100 #define MPC_DDR4_BASE_S 0x58009000 101 102 /* SRAM MPC ranges and limits */ 103 /* Internal memory */ 104 #define MPC_ISRAM0_RANGE_BASE_NS 0x20000000 105 #define MPC_ISRAM0_RANGE_LIMIT_NS 0x20007FFF 106 #define MPC_ISRAM0_RANGE_BASE_S 0x30000000 107 #define MPC_ISRAM0_RANGE_LIMIT_S 0x30007FFF 108 109 #define MPC_ISRAM1_RANGE_BASE_NS 0x20008000 110 #define MPC_ISRAM1_RANGE_LIMIT_NS 0x2000FFFF 111 #define MPC_ISRAM1_RANGE_BASE_S 0x30008000 112 #define MPC_ISRAM1_RANGE_LIMIT_S 0x3000FFFF 113 114 #define MPC_ISRAM2_RANGE_BASE_NS 0x20010000 115 #define MPC_ISRAM2_RANGE_LIMIT_NS 0x20017FFF 116 #define MPC_ISRAM2_RANGE_BASE_S 0x30010000 117 #define MPC_ISRAM2_RANGE_LIMIT_S 0x30017FFF 118 119 #define MPC_ISRAM3_RANGE_BASE_NS 0x20018000 120 #define MPC_ISRAM3_RANGE_LIMIT_NS 0x2001FFFF 121 #define MPC_ISRAM3_RANGE_BASE_S 0x30018000 122 #define MPC_ISRAM3_RANGE_LIMIT_S 0x3001FFFF 123 124 /* 125 * TF-M only supports booting up from QSPI flash. 126 * The following addresses for BRAM and QSPI are for QSPI boot. 127 */ 128 /* FPGA BRAM memory */ 129 #define MPC_BRAM_RANGE_BASE_NS 0x28000000 130 #define MPC_BRAM_RANGE_LIMIT_NS 0x2807FFFF 131 #define MPC_BRAM_RANGE_BASE_S 0x38000000 132 #define MPC_BRAM_RANGE_LIMIT_S 0x3807FFFF 133 134 /* QSPI flash memory */ 135 #define MPC_QSPI_RANGE_BASE_NS 0x00000000 136 #define MPC_QSPI_RANGE_LIMIT_NS 0x007FFFFF 137 #define MPC_QSPI_RANGE_BASE_S 0x10000000 138 #define MPC_QSPI_RANGE_LIMIT_S 0x107FFFFF 139 140 /* DDR4 memory */ 141 #define MPC_DDR4_RANGE0_BASE_NS 0x60000000 142 #define MPC_DDR4_RANGE0_LIMIT_NS 0x6FFFFFFF 143 #define MPC_DDR4_RANGE0_BASE_S 0x70000000 144 #define MPC_DDR4_RANGE0_LIMIT_S 0x7FFFFFFF 145 146 #endif /* __PLATFORM_BASE_ADDRESS_H_ */ 147
