1 /**************************************************************************//** 2 * @file eadc.h 3 * @version V0.10 4 * @brief M2351 series EADC driver header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __EADC_H__ 10 #define __EADC_H__ 11 12 #ifdef __cplusplus 13 extern "C" 14 { 15 #endif 16 17 18 /** @addtogroup Standard_Driver Standard Driver 19 @{ 20 */ 21 22 /** @addtogroup EADC_Driver EADC Driver 23 @{ 24 */ 25 26 /** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants 27 @{ 28 */ 29 30 /*---------------------------------------------------------------------------------------------------------*/ 31 /* EADC_CTL Constant Definitions */ 32 /*---------------------------------------------------------------------------------------------------------*/ 33 #define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode */ 34 #define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode */ 35 36 #define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */ 37 #define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */ 38 39 40 /*---------------------------------------------------------------------------------------------------------*/ 41 /* EADC_SCTL Constant Definitions */ 42 /*---------------------------------------------------------------------------------------------------------*/ 43 #define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */ 44 #define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */ 45 #define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */ 46 47 #define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */ 48 #define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger */ 49 #define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger */ 50 #define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */ 51 #define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger */ 52 #define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger */ 53 #define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */ 54 #define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */ 55 #define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */ 56 #define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */ 57 #define EADC_PWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG0 trigger */ 58 #define EADC_PWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG1 trigger */ 59 #define EADC_PWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG2 trigger */ 60 #define EADC_PWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG3 trigger */ 61 #define EADC_PWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG4 trigger */ 62 #define EADC_PWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM0TG5 trigger */ 63 #define EADC_PWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG0 trigger */ 64 #define EADC_PWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG1 trigger */ 65 #define EADC_PWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG2 trigger */ 66 #define EADC_PWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG3 trigger */ 67 #define EADC_PWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG4 trigger */ 68 #define EADC_PWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< EPWM1TG5 trigger */ 69 #define EADC_BPWM0TG_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM0TG trigger */ 70 #define EADC_BPWM1TG_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM1TG trigger */ 71 72 #define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */ 73 #define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */ 74 #define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */ 75 #define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */ 76 77 78 /*---------------------------------------------------------------------------------------------------------*/ 79 /* EADC_CMP Constant Definitions */ 80 /*---------------------------------------------------------------------------------------------------------*/ 81 #define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */ 82 #define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */ 83 #define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */ 84 #define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */ 85 #define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */ 86 #define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */ 87 88 /*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */ 89 90 /** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions 91 @{ 92 */ 93 /*---------------------------------------------------------------------------------------------------------*/ 94 /* EADC Macro Definitions */ 95 /*---------------------------------------------------------------------------------------------------------*/ 96 97 /** 98 * @brief A/D Converter Control Circuits Reset. 99 * @param[in] eadc The pointer of the specified EADC module. 100 * @return None 101 * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0. 102 */ 103 #define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk) 104 105 /** 106 * @brief Enable PDMA transfer. 107 * @param[in] eadc The pointer of the specified EADC module. 108 * @return None 109 * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, 110 * user can enable this bit to generate a PDMA data transfer request. 111 When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. 112 */ 113 #define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) 114 115 /** 116 * @brief Disable PDMA transfer. 117 * @param[in] eadc The pointer of the specified EADC module. 118 * @return None 119 * @details This macro is used to disable PDMA transfer. 120 */ 121 #define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) 122 123 /** 124 * @brief Enable double buffer mode. 125 * @param[in] eadc The pointer of the specified EADC module. 126 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 127 * @return None 128 * @details The ADC controller supports a double buffer mode in sample module 0~3. 129 * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. 130 */ 131 #define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) 132 133 /** 134 * @brief Disable double buffer mode. 135 * @param[in] eadc The pointer of the specified EADC module. 136 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. 137 * @return None 138 * @details Sample has one sample result register. 139 */ 140 #define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) 141 142 /** 143 * @brief Set ADIFn at A/D end of conversion. 144 * @param[in] eadc The pointer of the specified EADC module. 145 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. 146 * @return None 147 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. 148 */ 149 #define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) 150 151 /** 152 * @brief Set ADIFn at A/D start of conversion. 153 * @param[in] eadc The pointer of the specified EADC module. 154 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. 155 * @return None 156 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. 157 */ 158 #define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) 159 160 /** 161 * @brief Enable the interrupt. 162 * @param[in] eadc The pointer of the specified EADC module. 163 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 164 * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 165 * @return None 166 * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. 167 * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). 168 */ 169 #define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 170 171 /** 172 * @brief Disable the interrupt. 173 * @param[in] eadc The pointer of the specified EADC module. 174 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. 175 * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. 176 * @return None 177 * @details Specific sample module A/D ADINT0 interrupt function Disabled. 178 */ 179 #define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) 180 181 /** 182 * @brief Enable the sample module interrupt. 183 * @param[in] eadc The pointer of the specified EADC module. 184 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 185 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 186 * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. 187 * @return None 188 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 189 */ 190 #define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) 191 192 /** 193 * @brief Disable the sample module interrupt. 194 * @param[in] eadc The pointer of the specified EADC module. 195 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. 196 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. 197 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. 198 * @return None 199 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. 200 */ 201 #define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) 202 203 /** 204 * @brief Set the input mode output format. 205 * @param[in] eadc The pointer of the specified EADC module. 206 * @param[in] u32Format Decides the output format. Valid values are: 207 * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. 208 * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. 209 * @return None 210 * @details The macro is used to set A/D input mode output format. 211 */ 212 #define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) 213 214 /** 215 * @brief Start the A/D conversion. 216 * @param[in] eadc The pointer of the specified EADC module. 217 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 218 * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. 219 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. 220 * @return None 221 * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. 222 */ 223 #define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) 224 225 /** 226 * @brief Cancel the conversion for sample module. 227 * @param[in] eadc The pointer of the specified EADC module. 228 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. 229 * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. 230 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. 231 * @return None 232 * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. 233 */ 234 #define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) 235 236 /** 237 * @brief Get the conversion pending flag. 238 * @param[in] eadc The pointer of the specified EADC module. 239 * @return Return the conversion pending sample module. 240 * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, 241 * the STPFn (n=0~18) bit is automatically cleared to 0. 242 */ 243 #define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) 244 245 /** 246 * @brief Get the conversion data of the user-specified sample module. 247 * @param[in] eadc The pointer of the specified EADC module. 248 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. 249 * @return Return the conversion data of the user-specified sample module. 250 * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. 251 */ 252 #define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) 253 254 /** 255 * @brief Get the data overrun flag of the user-specified sample module. 256 * @param[in] eadc The pointer of the specified EADC module. 257 * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. 258 * @return Return the data overrun flag of the user-specified sample module. 259 * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. 260 */ 261 #define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) 262 263 /** 264 * @brief Get the data valid flag of the user-specified sample module. 265 * @param[in] eadc The pointer of the specified EADC module. 266 * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. 267 * @return Return the data valid flag of the user-specified sample module. 268 * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. 269 */ 270 #define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) 271 272 /** 273 * @brief Get the double data of the user-specified sample module. 274 * @param[in] eadc The pointer of the specified EADC module. 275 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. 276 * @return Return the double data of the user-specified sample module. 277 * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. 278 */ 279 #define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) 280 281 /** 282 * @brief Get the user-specified interrupt flags. 283 * @param[in] eadc The pointer of the specified EADC module. 284 * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. 285 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 286 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 287 * @return Return the user-specified interrupt flags. 288 * @details This macro is used to get the user-specified interrupt flags. 289 */ 290 #define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) 291 292 /** 293 * @brief Get the user-specified sample module overrun flags. 294 * @param[in] eadc The pointer of the specified EADC module. 295 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. 296 * @return Return the user-specified sample module overrun flags. 297 * @details This macro is used to get the user-specified sample module overrun flags. 298 */ 299 #define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) 300 301 /** 302 * @brief Clear the selected interrupt status bits. 303 * @param[in] eadc The pointer of the specified EADC module. 304 * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. 305 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. 306 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. 307 * @return None 308 * @details This macro is used to clear clear the selected interrupt status bits. 309 */ 310 #define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) 311 312 /** 313 * @brief Clear the selected sample module overrun status bits. 314 * @param[in] eadc The pointer of the specified EADC module. 315 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. 316 * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. 317 * @return None 318 * @details This macro is used to clear the selected sample module overrun status bits. 319 */ 320 #define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) 321 322 /** 323 * @brief Check all sample module A/D result data register overrun flags. 324 * @param[in] eadc The pointer of the specified EADC module. 325 * @retval 0 None of sample module data register overrun flag is set to 1. 326 * @retval 1 Any one of sample module data register overrun flag is set to 1. 327 * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. 328 */ 329 #define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) 330 331 /** 332 * @brief Check all sample module A/D result data register valid flags. 333 * @param[in] eadc The pointer of the specified EADC module. 334 * @retval 0 None of sample module data register valid flag is set to 1. 335 * @retval 1 Any one of sample module data register valid flag is set to 1. 336 * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. 337 */ 338 #define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) 339 340 /** 341 * @brief Check all A/D sample module start of conversion overrun flags. 342 * @param[in] eadc The pointer of the specified EADC module. 343 * @retval 0 None of sample module event overrun flag is set to 1. 344 * @retval 1 Any one of sample module event overrun flag is set to 1. 345 * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. 346 */ 347 #define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) 348 349 /** 350 * @brief Check all A/D interrupt flag overrun bits. 351 * @param[in] eadc The pointer of the specified EADC module. 352 * @retval 0 None of ADINT interrupt flag is overwritten to 1. 353 * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. 354 * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. 355 */ 356 #define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) 357 358 /** 359 * @brief Get the busy state of EADC. 360 * @param[in] eadc The pointer of the specified EADC module. 361 * @retval 0 Idle state. 362 * @retval 1 Busy state. 363 * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. 364 */ 365 #define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) 366 367 /** 368 * @brief Configure the comparator 0 and enable it. 369 * @param[in] eadc The pointer of the specified EADC module. 370 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 371 * @param[in] u32Condition specifies the compare condition. Valid values are: 372 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 373 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 374 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 375 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 376 * @return None 377 * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 378 * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or 379 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 380 */ 381 #define EADC_ENABLE_CMP0(eadc,\ 382 u32ModuleNum,\ 383 u32Condition,\ 384 u16CMPData,\ 385 u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 386 (u32Condition) |\ 387 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 388 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 389 EADC_CMP_ADCMPEN_Msk)) 390 391 /** 392 * @brief Configure the comparator 1 and enable it. 393 * @param[in] eadc The pointer of the specified EADC module. 394 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 395 * @param[in] u32Condition specifies the compare condition. Valid values are: 396 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 397 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 398 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 399 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 400 * @return None 401 * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 402 * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or 403 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 404 */ 405 #define EADC_ENABLE_CMP1(eadc,\ 406 u32ModuleNum,\ 407 u32Condition,\ 408 u16CMPData,\ 409 u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 410 (u32Condition) |\ 411 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 412 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 413 EADC_CMP_ADCMPEN_Msk)) 414 415 /** 416 * @brief Configure the comparator 2 and enable it. 417 * @param[in] eadc The pointer of the specified EADC module. 418 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 419 * @param[in] u32Condition specifies the compare condition. Valid values are: 420 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 421 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 422 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 423 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. 424 * @return None 425 * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); 426 * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or 427 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 428 */ 429 #define EADC_ENABLE_CMP2(eadc,\ 430 u32ModuleNum,\ 431 u32Condition,\ 432 u16CMPData,\ 433 u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 434 (u32Condition) |\ 435 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 436 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 437 EADC_CMP_ADCMPEN_Msk)) 438 439 /** 440 * @brief Configure the comparator 3 and enable it. 441 * @param[in] eadc The pointer of the specified EADC module. 442 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. 443 * @param[in] u32Condition specifies the compare condition. Valid values are: 444 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" 445 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value 446 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. 447 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. 448 * @return None 449 * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); 450 * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or 451 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. 452 */ 453 #define EADC_ENABLE_CMP3(eadc,\ 454 u32ModuleNum,\ 455 u32Condition,\ 456 u16CMPData,\ 457 u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ 458 (u32Condition) |\ 459 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ 460 (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ 461 EADC_CMP_ADCMPEN_Msk)) 462 463 /** 464 * @brief Enable the compare window mode. 465 * @param[in] eadc The pointer of the specified EADC module. 466 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 467 * @return None 468 * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. 469 */ 470 #define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) 471 472 /** 473 * @brief Disable the compare window mode. 474 * @param[in] eadc The pointer of the specified EADC module. 475 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. 476 * @return None 477 * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. 478 */ 479 #define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) 480 481 /** 482 * @brief Enable the compare interrupt. 483 * @param[in] eadc The pointer of the specified EADC module. 484 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 485 * @return None 486 * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) 487 * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, 488 * if ADCMPIE is set to 1, a compare interrupt request is generated. 489 */ 490 #define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) 491 492 /** 493 * @brief Disable the compare interrupt. 494 * @param[in] eadc The pointer of the specified EADC module. 495 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. 496 * @return None 497 * @details This macro is used to disable the compare interrupt. 498 */ 499 #define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) 500 501 /** 502 * @brief Disable comparator 0. 503 * @param[in] eadc The pointer of the specified EADC module. 504 * @return None 505 * @details This macro is used to disable comparator 0. 506 */ 507 #define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL) 508 509 /** 510 * @brief Disable comparator 1. 511 * @param[in] eadc The pointer of the specified EADC module. 512 * @return None 513 * @details This macro is used to disable comparator 1. 514 */ 515 #define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL) 516 517 /** 518 * @brief Disable comparator 2. 519 * @param[in] eadc The pointer of the specified EADC module. 520 * @return None 521 * @details This macro is used to disable comparator 2. 522 */ 523 #define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL) 524 525 /** 526 * @brief Disable comparator 3. 527 * @param[in] eadc The pointer of the specified EADC module. 528 * @return None 529 * @details This macro is used to disable comparator 3. 530 */ 531 #define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL) 532 533 /*---------------------------------------------------------------------------------------------------------*/ 534 /* Define EADC functions prototype */ 535 /*---------------------------------------------------------------------------------------------------------*/ 536 void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); 537 void EADC_Close(EADC_T *eadc); 538 void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); 539 void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); 540 void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); 541 542 /*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ 543 544 /*@}*/ /* end of group EADC_Driver */ 545 546 /*@}*/ /* end of group Standard_Driver */ 547 548 #ifdef __cplusplus 549 } 550 #endif 551 552 #endif /* __EADC_H__ */ 553 554
