1 /* 2 * Copyright (c) 2001-2019, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __DX_RNG_H__ 8 #define __DX_RNG_H__ 9 10 // -------------------------------------- 11 // BLOCK: RNG 12 // -------------------------------------- 13 #define DX_RNG_IMR_REG_OFFSET 0x0100UL 14 #define DX_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL 15 #define DX_RNG_IMR_EHR_VALID_INT_MASK_BIT_SIZE 0x1UL 16 #define DX_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL 17 #define DX_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SIZE 0x1UL 18 #define DX_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL 19 #define DX_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SIZE 0x1UL 20 #define DX_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL 21 #define DX_RNG_IMR_VN_ERR_INT_MASK_BIT_SIZE 0x1UL 22 #define DX_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL 23 #define DX_RNG_IMR_WATCHDOG_INT_MASK_BIT_SIZE 0x1UL 24 #define DX_RNG_IMR_RNG_DMA_DONE_INT_BIT_SHIFT 0x5UL 25 #define DX_RNG_IMR_RNG_DMA_DONE_INT_BIT_SIZE 0x1UL 26 #define DX_RNG_ISR_REG_OFFSET 0x0104UL 27 #define DX_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL 28 #define DX_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL 29 #define DX_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL 30 #define DX_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL 31 #define DX_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL 32 #define DX_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL 33 #define DX_RNG_ISR_VN_ERR_BIT_SHIFT 0x3UL 34 #define DX_RNG_ISR_VN_ERR_BIT_SIZE 0x1UL 35 #define DX_RNG_ISR_RNG_DMA_DONE_BIT_SHIFT 0x5UL 36 #define DX_RNG_ISR_RNG_DMA_DONE_BIT_SIZE 0x1UL 37 #define DX_RNG_ISR_RESEEDING_DONE_BIT_SHIFT 0x10UL 38 #define DX_RNG_ISR_RESEEDING_DONE_BIT_SIZE 0x1UL 39 #define DX_RNG_ISR_INSTANTIATION_DONE_BIT_SHIFT 0x11UL 40 #define DX_RNG_ISR_INSTANTIATION_DONE_BIT_SIZE 0x1UL 41 #define DX_RNG_ISR_FINAL_UPDATE_DONE_BIT_SHIFT 0x12UL 42 #define DX_RNG_ISR_FINAL_UPDATE_DONE_BIT_SIZE 0x1UL 43 #define DX_RNG_ISR_OUTPUT_READY_BIT_SHIFT 0x13UL 44 #define DX_RNG_ISR_OUTPUT_READY_BIT_SIZE 0x1UL 45 #define DX_RNG_ISR_RESEED_CNTR_FULL_BIT_SHIFT 0x14UL 46 #define DX_RNG_ISR_RESEED_CNTR_FULL_BIT_SIZE 0x1UL 47 #define DX_RNG_ISR_RESEED_CNTR_TOP_40_BIT_SHIFT 0x15UL 48 #define DX_RNG_ISR_RESEED_CNTR_TOP_40_BIT_SIZE 0x1UL 49 #define DX_RNG_ISR_PRNG_CRNGT_ERR_BIT_SHIFT 0x16UL 50 #define DX_RNG_ISR_PRNG_CRNGT_ERR_BIT_SIZE 0x1UL 51 #define DX_RNG_ISR_REQ_SIZE_BIT_SHIFT 0x17UL 52 #define DX_RNG_ISR_REQ_SIZE_BIT_SIZE 0x1UL 53 #define DX_RNG_ISR_KAT_ERR_BIT_SHIFT 0x18UL 54 #define DX_RNG_ISR_KAT_ERR_BIT_SIZE 0x1UL 55 #define DX_RNG_ISR_WHICH_KAT_ERR_BIT_SHIFT 0x19UL 56 #define DX_RNG_ISR_WHICH_KAT_ERR_BIT_SIZE 0x2UL 57 #define DX_RNG_ICR_REG_OFFSET 0x0108UL 58 #define DX_RNG_ICR_EHR_VALID_BIT_SHIFT 0x0UL 59 #define DX_RNG_ICR_EHR_VALID_BIT_SIZE 0x1UL 60 #define DX_RNG_ICR_AUTOCORR_ERR_BIT_SHIFT 0x1UL 61 #define DX_RNG_ICR_AUTOCORR_ERR_BIT_SIZE 0x1UL 62 #define DX_RNG_ICR_CRNGT_ERR_BIT_SHIFT 0x2UL 63 #define DX_RNG_ICR_CRNGT_ERR_BIT_SIZE 0x1UL 64 #define DX_RNG_ICR_VN_ERR_BIT_SHIFT 0x3UL 65 #define DX_RNG_ICR_VN_ERR_BIT_SIZE 0x1UL 66 #define DX_RNG_ICR_RNG_WATCHDOG_BIT_SHIFT 0x4UL 67 #define DX_RNG_ICR_RNG_WATCHDOG_BIT_SIZE 0x1UL 68 #define DX_RNG_ICR_RNG_DMA_DONE_BIT_SHIFT 0x5UL 69 #define DX_RNG_ICR_RNG_DMA_DONE_BIT_SIZE 0x1UL 70 #define DX_RNG_ICR_RESEEDING_DONE_BIT_SHIFT 0x10UL 71 #define DX_RNG_ICR_RESEEDING_DONE_BIT_SIZE 0x1UL 72 #define DX_RNG_ICR_INSTANTIATION_DONE_BIT_SHIFT 0x11UL 73 #define DX_RNG_ICR_INSTANTIATION_DONE_BIT_SIZE 0x1UL 74 #define DX_RNG_ICR_FINAL_UPDATE_DONE_BIT_SHIFT 0x12UL 75 #define DX_RNG_ICR_FINAL_UPDATE_DONE_BIT_SIZE 0x1UL 76 #define DX_RNG_ICR_OUTPUT_READY_BIT_SHIFT 0x13UL 77 #define DX_RNG_ICR_OUTPUT_READY_BIT_SIZE 0x1UL 78 #define DX_RNG_ICR_RESEED_CNTR_FULL_BIT_SHIFT 0x14UL 79 #define DX_RNG_ICR_RESEED_CNTR_FULL_BIT_SIZE 0x1UL 80 #define DX_RNG_ICR_RESEED_CNTR_TOP_40_BIT_SHIFT 0x15UL 81 #define DX_RNG_ICR_RESEED_CNTR_TOP_40_BIT_SIZE 0x1UL 82 #define DX_RNG_ICR_PRNG_CRNGT_ERR_BIT_SHIFT 0x16UL 83 #define DX_RNG_ICR_PRNG_CRNGT_ERR_BIT_SIZE 0x1UL 84 #define DX_RNG_ICR_REQ_SIZE_BIT_SHIFT 0x17UL 85 #define DX_RNG_ICR_REQ_SIZE_BIT_SIZE 0x1UL 86 #define DX_RNG_ICR_KAT_ERR_BIT_SHIFT 0x18UL 87 #define DX_RNG_ICR_KAT_ERR_BIT_SIZE 0x1UL 88 #define DX_RNG_ICR_WHICH_KAT_ERR_BIT_SHIFT 0x19UL 89 #define DX_RNG_ICR_WHICH_KAT_ERR_BIT_SIZE 0x2UL 90 #define DX_TRNG_CONFIG_REG_OFFSET 0x010CUL 91 #define DX_TRNG_CONFIG_RND_SRC_SEL_BIT_SHIFT 0x0UL 92 #define DX_TRNG_CONFIG_RND_SRC_SEL_BIT_SIZE 0x2UL 93 #define DX_TRNG_CONFIG_SOP_SEL_BIT_SHIFT 0x2UL 94 #define DX_TRNG_CONFIG_SOP_SEL_BIT_SIZE 0x1UL 95 #define DX_TRNG_VALID_REG_OFFSET 0x0110UL 96 #define DX_TRNG_VALID_VALUE_BIT_SHIFT 0x0UL 97 #define DX_TRNG_VALID_VALUE_BIT_SIZE 0x1UL 98 #define DX_EHR_DATA_0_REG_OFFSET 0x0114UL 99 #define DX_EHR_DATA_0_VALUE_BIT_SHIFT 0x0UL 100 #define DX_EHR_DATA_0_VALUE_BIT_SIZE 0x20UL 101 #define DX_EHR_DATA_1_REG_OFFSET 0x0118UL 102 #define DX_EHR_DATA_1_VALUE_BIT_SHIFT 0x0UL 103 #define DX_EHR_DATA_1_VALUE_BIT_SIZE 0x20UL 104 #define DX_EHR_DATA_2_REG_OFFSET 0x011CUL 105 #define DX_EHR_DATA_2_VALUE_BIT_SHIFT 0x0UL 106 #define DX_EHR_DATA_2_VALUE_BIT_SIZE 0x20UL 107 #define DX_EHR_DATA_3_REG_OFFSET 0x0120UL 108 #define DX_EHR_DATA_3_VALUE_BIT_SHIFT 0x0UL 109 #define DX_EHR_DATA_3_VALUE_BIT_SIZE 0x20UL 110 #define DX_EHR_DATA_4_REG_OFFSET 0x0124UL 111 #define DX_EHR_DATA_4_VALUE_BIT_SHIFT 0x0UL 112 #define DX_EHR_DATA_4_VALUE_BIT_SIZE 0x20UL 113 #define DX_EHR_DATA_5_REG_OFFSET 0x0128UL 114 #define DX_EHR_DATA_5_VALUE_BIT_SHIFT 0x0UL 115 #define DX_EHR_DATA_5_VALUE_BIT_SIZE 0x20UL 116 #define DX_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL 117 #define DX_RND_SOURCE_ENABLE_VALUE_BIT_SHIFT 0x0UL 118 #define DX_RND_SOURCE_ENABLE_VALUE_BIT_SIZE 0x1UL 119 #define DX_SAMPLE_CNT1_REG_OFFSET 0x0130UL 120 #define DX_SAMPLE_CNT1_VALUE_BIT_SHIFT 0x0UL 121 #define DX_SAMPLE_CNT1_VALUE_BIT_SIZE 0x20UL 122 #define DX_AUTOCORR_STATISTIC_REG_OFFSET 0x0134UL 123 #define DX_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BIT_SHIFT 0x0UL 124 #define DX_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BIT_SIZE 0xEUL 125 #define DX_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BIT_SHIFT 0xEUL 126 #define DX_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BIT_SIZE 0x8UL 127 #define DX_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL 128 #define DX_TRNG_DEBUG_CONTROL_VNC_BYPASS_BIT_SHIFT 0x1UL 129 #define DX_TRNG_DEBUG_CONTROL_VNC_BYPASS_BIT_SIZE 0x1UL 130 #define DX_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BIT_SHIFT 0x2UL 131 #define DX_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BIT_SIZE 0x1UL 132 #define DX_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BIT_SHIFT 0x3UL 133 #define DX_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BIT_SIZE 0x1UL 134 #define DX_RNG_SW_RESET_REG_OFFSET 0x0140UL 135 #define DX_RNG_SW_RESET_VALUE_BIT_SHIFT 0x0UL 136 #define DX_RNG_SW_RESET_VALUE_BIT_SIZE 0x1UL 137 #define DX_RNG_DEBUG_EN_INPUT_REG_OFFSET 0x01B4UL 138 #define DX_RNG_DEBUG_EN_INPUT_VALUE_BIT_SHIFT 0x0UL 139 #define DX_RNG_DEBUG_EN_INPUT_VALUE_BIT_SIZE 0x1UL 140 #define DX_RNG_BUSY_REG_OFFSET 0x01B8UL 141 #define DX_RNG_BUSY_RNG_BUSY_BIT_SHIFT 0x0UL 142 #define DX_RNG_BUSY_RNG_BUSY_BIT_SIZE 0x1UL 143 #define DX_RNG_BUSY_TRNG_BUSY_BIT_SHIFT 0x1UL 144 #define DX_RNG_BUSY_TRNG_BUSY_BIT_SIZE 0x1UL 145 #define DX_RNG_BUSY_PRNG_BUSY_BIT_SHIFT 0x2UL 146 #define DX_RNG_BUSY_PRNG_BUSY_BIT_SIZE 0x1UL 147 #define DX_RST_BITS_COUNTER_REG_OFFSET 0x01BCUL 148 #define DX_RST_BITS_COUNTER_VALUE_BIT_SHIFT 0x0UL 149 #define DX_RST_BITS_COUNTER_VALUE_BIT_SIZE 0x1UL 150 #define DX_RNG_VERSION_REG_OFFSET 0x01C0UL 151 #define DX_RNG_VERSION_EHR_WIDTH_192_BIT_SHIFT 0x0UL 152 #define DX_RNG_VERSION_EHR_WIDTH_192_BIT_SIZE 0x1UL 153 #define DX_RNG_VERSION_CRNGT_EXISTS_BIT_SHIFT 0x1UL 154 #define DX_RNG_VERSION_CRNGT_EXISTS_BIT_SIZE 0x1UL 155 #define DX_RNG_VERSION_AUTOCORR_EXISTS_BIT_SHIFT 0x2UL 156 #define DX_RNG_VERSION_AUTOCORR_EXISTS_BIT_SIZE 0x1UL 157 #define DX_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BIT_SHIFT 0x3UL 158 #define DX_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BIT_SIZE 0x1UL 159 #define DX_RNG_VERSION_PRNG_EXISTS_BIT_SHIFT 0x4UL 160 #define DX_RNG_VERSION_PRNG_EXISTS_BIT_SIZE 0x1UL 161 #define DX_RNG_VERSION_KAT_EXISTS_BIT_SHIFT 0x5UL 162 #define DX_RNG_VERSION_KAT_EXISTS_BIT_SIZE 0x1UL 163 #define DX_RNG_VERSION_RESEEDING_EXISTS_BIT_SHIFT 0x6UL 164 #define DX_RNG_VERSION_RESEEDING_EXISTS_BIT_SIZE 0x1UL 165 #define DX_RNG_VERSION_RNG_USE_5_SBOXES_BIT_SHIFT 0x7UL 166 #define DX_RNG_VERSION_RNG_USE_5_SBOXES_BIT_SIZE 0x1UL 167 #define DX_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL 168 #define DX_RNG_CLK_ENABLE_VALUE_BIT_SHIFT 0x0UL 169 #define DX_RNG_CLK_ENABLE_VALUE_BIT_SIZE 0x1UL 170 #define DX_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL 171 #define DX_RNG_DMA_ENABLE_VALUE_BIT_SHIFT 0x0UL 172 #define DX_RNG_DMA_ENABLE_VALUE_BIT_SIZE 0x1UL 173 #define DX_RNG_DMA_SRC_MASK_REG_OFFSET 0x01CCUL 174 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL0_BIT_SHIFT 0x0UL 175 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL0_BIT_SIZE 0x1UL 176 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL1_BIT_SHIFT 0x1UL 177 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL1_BIT_SIZE 0x1UL 178 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL2_BIT_SHIFT 0x2UL 179 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL2_BIT_SIZE 0x1UL 180 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL3_BIT_SHIFT 0x3UL 181 #define DX_RNG_DMA_SRC_MASK_EN_SRC_SEL3_BIT_SIZE 0x1UL 182 #define DX_RNG_DMA_SRAM_ADDR_REG_OFFSET 0x01D0UL 183 #define DX_RNG_DMA_SRAM_ADDR_VALUE_BIT_SHIFT 0x0UL 184 #define DX_RNG_DMA_SRAM_ADDR_VALUE_BIT_SIZE 0xBUL 185 #define DX_RNG_DMA_SAMPLES_NUM_REG_OFFSET 0x01D4UL 186 #define DX_RNG_DMA_SAMPLES_NUM_VALUE_BIT_SHIFT 0x0UL 187 #define DX_RNG_DMA_SAMPLES_NUM_VALUE_BIT_SIZE 0x8UL 188 #define DX_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL 189 #define DX_RNG_WATCHDOG_VAL_VALUE_BIT_SHIFT 0x0UL 190 #define DX_RNG_WATCHDOG_VAL_VALUE_BIT_SIZE 0x20UL 191 #define DX_RNG_DMA_STATUS_REG_OFFSET 0x01DCUL 192 #define DX_RNG_DMA_STATUS_RNG_DMA_BUSY_BIT_SHIFT 0x0UL 193 #define DX_RNG_DMA_STATUS_RNG_DMA_BUSY_BIT_SIZE 0x1UL 194 #define DX_RNG_DMA_STATUS_DMA_SRC_SEL_BIT_SHIFT 0x1UL 195 #define DX_RNG_DMA_STATUS_DMA_SRC_SEL_BIT_SIZE 0x2UL 196 #define DX_RNG_DMA_STATUS_NUM_OF_SAMPLES_BIT_SHIFT 0x3UL 197 #define DX_RNG_DMA_STATUS_NUM_OF_SAMPLES_BIT_SIZE 0x8UL 198 #endif //__DX_RNG_H__ 199
