1 /*******************************************************************************
2 * File Name: cycfg_system.c
3 *
4 * Description:
5 * System configuration
6 * This file was automatically generated and should not be modified.
7 * Tools Package 2.2.0.2801
8 * latest-v2.X 2.0.0.6211
9 * personalities 3.0.0.0
10 * udd 3.0.0.562
11 *
12 ********************************************************************************
13 * Copyright 2020 Cypress Semiconductor Corporation
14 * SPDX-License-Identifier: Apache-2.0
15 *
16 * Licensed under the Apache License, Version 2.0 (the "License");
17 * you may not use this file except in compliance with the License.
18 * You may obtain a copy of the License at
19 *
20 * http://www.apache.org/licenses/LICENSE-2.0
21 *
22 * Unless required by applicable law or agreed to in writing, software
23 * distributed under the License is distributed on an "AS IS" BASIS,
24 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25 * See the License for the specific language governing permissions and
26 * limitations under the License.
27 ********************************************************************************/
28
29 #include "cycfg_system.h"
30
31 #define CY_CFG_SYSCLK_ECO_ERROR 1
32 #define CY_CFG_SYSCLK_ALTHF_ERROR 2
33 #define CY_CFG_SYSCLK_PLL_ERROR 3
34 #define CY_CFG_SYSCLK_FLL_ERROR 4
35 #define CY_CFG_SYSCLK_WCO_ERROR 5
36 #define CY_CFG_SYSCLK_CLKBAK_ENABLED 1
37 #define CY_CFG_SYSCLK_CLKBAK_SOURCE CY_SYSCLK_BAK_IN_CLKLF
38 #define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
39 #define CY_CFG_SYSCLK_CLKFAST_DIVIDER 0
40 #define CY_CFG_SYSCLK_FLL_ENABLED 1
41 #define CY_CFG_SYSCLK_FLL_MULT 500U
42 #define CY_CFG_SYSCLK_FLL_REFDIV 20U
43 #define CY_CFG_SYSCLK_FLL_CCO_RANGE CY_SYSCLK_FLL_CCO_RANGE4
44 #define CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV true
45 #define CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE 10U
46 #define CY_CFG_SYSCLK_FLL_IGAIN 9U
47 #define CY_CFG_SYSCLK_FLL_PGAIN 5U
48 #define CY_CFG_SYSCLK_FLL_SETTLING_COUNT 8U
49 #define CY_CFG_SYSCLK_FLL_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT
50 #define CY_CFG_SYSCLK_FLL_CCO_FREQ 355U
51 #define CY_CFG_SYSCLK_FLL_OUT_FREQ 100000000
52 #define CY_CFG_SYSCLK_CLKHF0_ENABLED 1
53 #define CY_CFG_SYSCLK_CLKHF0_DIVIDER CY_SYSCLK_CLKHF_NO_DIVIDE
54 #define CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ 100UL
55 #define CY_CFG_SYSCLK_CLKHF0_CLKPATH CY_SYSCLK_CLKHF_IN_CLKPATH0
56 #define CY_CFG_SYSCLK_ILO_ENABLED 1
57 #define CY_CFG_SYSCLK_ILO_HIBERNATE true
58 #define CY_CFG_SYSCLK_IMO_ENABLED 1
59 #define CY_CFG_SYSCLK_CLKLF_ENABLED 1
60 #define CY_CFG_SYSCLK_CLKPATH0_ENABLED 1
61 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
62 #define CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM 0UL
63 #define CY_CFG_SYSCLK_CLKPATH1_ENABLED 1
64 #define CY_CFG_SYSCLK_CLKPATH1_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
65 #define CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM 0UL
66 #define CY_CFG_SYSCLK_CLKPATH2_ENABLED 1
67 #define CY_CFG_SYSCLK_CLKPATH2_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
68 #define CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM 0UL
69 #define CY_CFG_SYSCLK_CLKPATH3_ENABLED 1
70 #define CY_CFG_SYSCLK_CLKPATH3_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
71 #define CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM 0UL
72 #define CY_CFG_SYSCLK_CLKPATH4_ENABLED 1
73 #define CY_CFG_SYSCLK_CLKPATH4_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
74 #define CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM 0UL
75 #define CY_CFG_SYSCLK_CLKPATH5_ENABLED 1
76 #define CY_CFG_SYSCLK_CLKPATH5_SOURCE CY_SYSCLK_CLKPATH_IN_IMO
77 #define CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM 0UL
78 #define CY_CFG_SYSCLK_CLKPERI_ENABLED 1
79 #define CY_CFG_SYSCLK_CLKPERI_DIVIDER 0
80 #define CY_CFG_SYSCLK_PLL0_ENABLED 1
81 #define CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV 30
82 #define CY_CFG_SYSCLK_PLL0_REFERENCE_DIV 1
83 #define CY_CFG_SYSCLK_PLL0_OUTPUT_DIV 5
84 #define CY_CFG_SYSCLK_PLL0_LF_MODE false
85 #define CY_CFG_SYSCLK_PLL0_OUTPUT_MODE CY_SYSCLK_FLLPLL_OUTPUT_AUTO
86 #define CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ 48000000
87 #define CY_CFG_SYSCLK_CLKSLOW_ENABLED 1
88 #define CY_CFG_SYSCLK_CLKSLOW_DIVIDER 0
89 #define CY_CFG_SYSCLK_CLKTIMER_ENABLED 1
90 #define CY_CFG_SYSCLK_CLKTIMER_SOURCE CY_SYSCLK_CLKTIMER_IN_IMO
91 #define CY_CFG_SYSCLK_CLKTIMER_DIVIDER 0U
92 #define CY_CFG_SYSCLK_WCO_ENABLED 1
93 #define CY_CFG_SYSCLK_WCO_IN_PRT GPIO_PRT0
94 #define CY_CFG_SYSCLK_WCO_IN_PIN 0U
95 #define CY_CFG_SYSCLK_WCO_OUT_PRT GPIO_PRT0
96 #define CY_CFG_SYSCLK_WCO_OUT_PIN 1U
97 #define CY_CFG_SYSCLK_WCO_BYPASS CY_SYSCLK_WCO_NOT_BYPASSED
98 #define CY_CFG_PWR_ENABLED 1
99 #define CY_CFG_PWR_INIT 1
100 #define CY_CFG_PWR_USING_PMIC 0
101 #define CY_CFG_PWR_VBACKUP_USING_VDDD 1
102 #define CY_CFG_PWR_LDO_VOLTAGE CY_SYSPM_LDO_VOLTAGE_LP
103 #define CY_CFG_PWR_USING_ULP 0
104 #define CY_CFG_PWR_REGULATOR_MODE_MIN false
105
106 #if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4)
107 static cy_stc_pra_system_config_t srss_0_clock_0_secureConfig;
108 #endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4)
109 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
110 static const cy_stc_fll_manual_config_t srss_0_clock_0_fll_0_fllConfig =
111 {
112 .fllMult = 500U,
113 .refDiv = 20U,
114 .ccoRange = CY_SYSCLK_FLL_CCO_RANGE4,
115 .enableOutputDiv = true,
116 .lockTolerance = 10U,
117 .igain = 9U,
118 .pgain = 5U,
119 .settlingCount = 8U,
120 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,
121 .cco_Freq = 355U,
122 };
123 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
124 #if defined (CY_USING_HAL)
125 const cyhal_resource_inst_t srss_0_clock_0_pathmux_0_obj =
126 {
127 .type = CYHAL_RSC_CLKPATH,
128 .block_num = 0U,
129 .channel_num = 0U,
130 };
131 #endif //defined (CY_USING_HAL)
132 #if defined (CY_USING_HAL)
133 const cyhal_resource_inst_t srss_0_clock_0_pathmux_1_obj =
134 {
135 .type = CYHAL_RSC_CLKPATH,
136 .block_num = 1U,
137 .channel_num = 0U,
138 };
139 #endif //defined (CY_USING_HAL)
140 #if defined (CY_USING_HAL)
141 const cyhal_resource_inst_t srss_0_clock_0_pathmux_2_obj =
142 {
143 .type = CYHAL_RSC_CLKPATH,
144 .block_num = 2U,
145 .channel_num = 0U,
146 };
147 #endif //defined (CY_USING_HAL)
148 #if defined (CY_USING_HAL)
149 const cyhal_resource_inst_t srss_0_clock_0_pathmux_3_obj =
150 {
151 .type = CYHAL_RSC_CLKPATH,
152 .block_num = 3U,
153 .channel_num = 0U,
154 };
155 #endif //defined (CY_USING_HAL)
156 #if defined (CY_USING_HAL)
157 const cyhal_resource_inst_t srss_0_clock_0_pathmux_4_obj =
158 {
159 .type = CYHAL_RSC_CLKPATH,
160 .block_num = 4U,
161 .channel_num = 0U,
162 };
163 #endif //defined (CY_USING_HAL)
164 #if defined (CY_USING_HAL)
165 const cyhal_resource_inst_t srss_0_clock_0_pathmux_5_obj =
166 {
167 .type = CYHAL_RSC_CLKPATH,
168 .block_num = 5U,
169 .channel_num = 0U,
170 };
171 #endif //defined (CY_USING_HAL)
172 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
173 static const cy_stc_pll_manual_config_t srss_0_clock_0_pll_0_pllConfig =
174 {
175 .feedbackDiv = 30,
176 .referenceDiv = 1,
177 .outputDiv = 5,
178 .lfMode = false,
179 .outputMode = CY_SYSCLK_FLLPLL_OUTPUT_AUTO,
180 };
181 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
182
cycfg_ClockStartupError(uint32_t error)183 __WEAK void cycfg_ClockStartupError(uint32_t error)
184 {
185 (void)error; /* Suppress the compiler warning */
186 while(1);
187 }
188 #if defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4)
init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config)189 __STATIC_INLINE void init_cycfg_secure_struct(cy_stc_pra_system_config_t * secure_config)
190 {
191 #ifdef CY_CFG_PWR_ENABLED
192 secure_config->powerEnable = CY_CFG_PWR_ENABLED;
193 #endif /* CY_CFG_PWR_ENABLED */
194
195 #ifdef CY_CFG_PWR_USING_LDO
196 secure_config->ldoEnable = CY_CFG_PWR_USING_LDO;
197 #endif /* CY_CFG_PWR_USING_LDO */
198
199 #ifdef CY_CFG_PWR_USING_PMIC
200 secure_config->pmicEnable = CY_CFG_PWR_USING_PMIC;
201 #endif /* CY_CFG_PWR_USING_PMIC */
202
203 #ifdef CY_CFG_PWR_VBACKUP_USING_VDDD
204 secure_config->vBackupVDDDEnable = CY_CFG_PWR_VBACKUP_USING_VDDD;
205 #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
206
207 #ifdef CY_CFG_PWR_USING_ULP
208 secure_config->ulpEnable = CY_CFG_PWR_USING_ULP;
209 #endif /* CY_CFG_PWR_USING_ULP */
210
211 #ifdef CY_CFG_SYSCLK_ECO_ENABLED
212 secure_config->ecoEnable = CY_CFG_SYSCLK_ECO_ENABLED;
213 #endif /* CY_CFG_SYSCLK_ECO_ENABLED */
214
215 #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
216 secure_config->extClkEnable = CY_CFG_SYSCLK_EXTCLK_ENABLED;
217 #endif /* CY_CFG_SYSCLK_EXTCLK_ENABLED */
218
219 #ifdef CY_CFG_SYSCLK_ILO_ENABLED
220 secure_config->iloEnable = CY_CFG_SYSCLK_ILO_ENABLED;
221 #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
222
223 #ifdef CY_CFG_SYSCLK_WCO_ENABLED
224 secure_config->wcoEnable = CY_CFG_SYSCLK_WCO_ENABLED;
225 #endif /* CY_CFG_SYSCLK_WCO_ENABLED */
226
227 #ifdef CY_CFG_SYSCLK_FLL_ENABLED
228 secure_config->fllEnable = CY_CFG_SYSCLK_FLL_ENABLED;
229 #endif /* CY_CFG_SYSCLK_FLL_ENABLED */
230
231 #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
232 secure_config->pll0Enable = CY_CFG_SYSCLK_PLL0_ENABLED;
233 #endif /* CY_CFG_SYSCLK_PLL0_ENABLED */
234
235 #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
236 secure_config->pll1Enable = CY_CFG_SYSCLK_PLL1_ENABLED;
237 #endif /* CY_CFG_SYSCLK_PLL1_ENABLED */
238
239 #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
240 secure_config->path0Enable = CY_CFG_SYSCLK_CLKPATH0_ENABLED;
241 #endif /* CY_CFG_SYSCLK_CLKPATH0_ENABLED */
242
243 #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
244 secure_config->path1Enable = CY_CFG_SYSCLK_CLKPATH1_ENABLED;
245 #endif /* CY_CFG_SYSCLK_CLKPATH1_ENABLED */
246
247 #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
248 secure_config->path2Enable = CY_CFG_SYSCLK_CLKPATH2_ENABLED;
249 #endif /* CY_CFG_SYSCLK_CLKPATH2_ENABLED */
250
251 #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
252 secure_config->path3Enable = CY_CFG_SYSCLK_CLKPATH3_ENABLED;
253 #endif /* CY_CFG_SYSCLK_CLKPATH3_ENABLED */
254
255 #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
256 secure_config->path4Enable = CY_CFG_SYSCLK_CLKPATH4_ENABLED;
257 #endif /* CY_CFG_SYSCLK_CLKPATH4_ENABLED */
258
259 #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
260 secure_config->path5Enable = CY_CFG_SYSCLK_CLKPATH5_ENABLED;
261 #endif /* CY_CFG_SYSCLK_CLKPATH5_ENABLED */
262
263 #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
264 secure_config->clkFastEnable = CY_CFG_SYSCLK_CLKFAST_ENABLED;
265 #endif /* CY_CFG_SYSCLK_CLKFAST_ENABLED */
266
267 #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
268 secure_config->clkPeriEnable = CY_CFG_SYSCLK_CLKPERI_ENABLED;
269 #endif /* CY_CFG_SYSCLK_CLKPERI_ENABLED */
270
271 #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
272 secure_config->clkSlowEnable = CY_CFG_SYSCLK_CLKSLOW_ENABLED;
273 #endif /* CY_CFG_SYSCLK_CLKSLOW_ENABLED */
274
275 #ifdef CY_CFG_SYSCLK_CLKHF0_ENABLED
276 secure_config->clkHF0Enable = CY_CFG_SYSCLK_CLKHF0_ENABLED;
277 #endif /* CY_CFG_SYSCLK_CLKHF0_ENABLED */
278
279 #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
280 secure_config->clkHF1Enable = CY_CFG_SYSCLK_CLKHF1_ENABLED;
281 #endif /* CY_CFG_SYSCLK_CLKHF1_ENABLED */
282
283 #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
284 secure_config->clkHF2Enable = CY_CFG_SYSCLK_CLKHF2_ENABLED;
285 #endif /* CY_CFG_SYSCLK_CLKHF2_ENABLED */
286
287 #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
288 secure_config->clkHF3Enable = CY_CFG_SYSCLK_CLKHF3_ENABLED;
289 #endif /* CY_CFG_SYSCLK_CLKHF3_ENABLED */
290
291 #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
292 secure_config->clkHF4Enable = CY_CFG_SYSCLK_CLKHF4_ENABLED;
293 #endif /* CY_CFG_SYSCLK_CLKHF4_ENABLED */
294
295 #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
296 secure_config->clkHF5Enable = CY_CFG_SYSCLK_CLKHF5_ENABLED;
297 #endif /* CY_CFG_SYSCLK_CLKHF5_ENABLED */
298
299 #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
300 secure_config->clkPumpEnable = CY_CFG_SYSCLK_CLKPUMP_ENABLED;
301 #endif /* CY_CFG_SYSCLK_CLKPUMP_ENABLED */
302
303 #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
304 secure_config->clkLFEnable = CY_CFG_SYSCLK_CLKLF_ENABLED;
305 #endif /* CY_CFG_SYSCLK_CLKLF_ENABLED */
306
307 #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
308 secure_config->clkBakEnable = CY_CFG_SYSCLK_CLKBAK_ENABLED;
309 #endif /* CY_CFG_SYSCLK_CLKBAK_ENABLED */
310
311 #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
312 secure_config->clkTimerEnable = CY_CFG_SYSCLK_CLKTIMER_ENABLED;
313 #endif /* CY_CFG_SYSCLK_CLKTIMER_ENABLED */
314
315 #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
316 #error Configuration Error : ALT SYSTICK cannot be enabled for Secure devices.
317 #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED */
318
319 #ifdef CY_CFG_SYSCLK_PILO_ENABLED
320 secure_config->piloEnable = CY_CFG_SYSCLK_PILO_ENABLED;
321 #endif /* CY_CFG_SYSCLK_PILO_ENABLED */
322
323 #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
324 secure_config->clkAltHfEnable = CY_CFG_SYSCLK_ALTHF_ENABLED;
325 #endif /* CY_CFG_SYSCLK_ALTHF_ENABLED */
326
327 #ifdef CY_CFG_PWR_LDO_VOLTAGE
328 secure_config->ldoVoltage = CY_CFG_PWR_LDO_VOLTAGE;
329 #endif /* CY_CFG_PWR_LDO_VOLTAGE */
330
331 #ifdef CY_CFG_PWR_REGULATOR_MODE_MIN
332 secure_config->pwrCurrentModeMin = CY_CFG_PWR_REGULATOR_MODE_MIN;
333 #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
334
335 #ifdef CY_CFG_PWR_BUCK_VOLTAGE
336 secure_config->buckVoltage = CY_CFG_PWR_BUCK_VOLTAGE;
337 #endif /* CY_CFG_PWR_BUCK_VOLTAGE */
338
339 #ifdef CY_CFG_SYSCLK_ECO_FREQ
340 secure_config->ecoFreqHz = CY_CFG_SYSCLK_ECO_FREQ;
341 #endif /* CY_CFG_SYSCLK_ECO_FREQ */
342
343 #ifdef CY_CFG_SYSCLK_ECO_CLOAD
344 secure_config->ecoLoad = CY_CFG_SYSCLK_ECO_CLOAD;
345 #endif /* CY_CFG_SYSCLK_ECO_CLOAD */
346
347 #ifdef CY_CFG_SYSCLK_ECO_ESR
348 secure_config->ecoEsr = CY_CFG_SYSCLK_ECO_ESR;
349 #endif /* CY_CFG_SYSCLK_ECO_ESR */
350
351 #ifdef CY_CFG_SYSCLK_ECO_DRIVE_LEVEL
352 secure_config->ecoDriveLevel = CY_CFG_SYSCLK_ECO_DRIVE_LEVEL;
353 #endif /* CY_CFG_SYSCLK_ECO_DRIVE_LEVEL */
354
355 #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PRT
356 secure_config->ecoInPort = CY_CFG_SYSCLK_ECO_GPIO_IN_PRT;
357 #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PRT */
358
359 #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT
360 secure_config->ecoOutPort = CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT;
361 #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PRT */
362
363 #ifdef CY_CFG_SYSCLK_ECO_GPIO_IN_PIN
364 secure_config->ecoInPinNum = CY_CFG_SYSCLK_ECO_GPIO_IN_PIN;
365 #endif /* CY_CFG_SYSCLK_ECO_GPIO_IN_PIN */
366
367 #ifdef CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN
368 secure_config->ecoOutPinNum = CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN;
369 #endif /* CY_CFG_SYSCLK_ECO_GPIO_OUT_PIN */
370
371 #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
372 secure_config->extClkFreqHz = CY_CFG_SYSCLK_EXTCLK_FREQ;
373 #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
374
375 #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PRT
376 secure_config->extClkPort = CY_CFG_SYSCLK_EXTCLK_GPIO_PRT;
377 #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PRT */
378
379 #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_PIN
380 secure_config->extClkPinNum = CY_CFG_SYSCLK_EXTCLK_GPIO_PIN;
381 #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_PIN */
382
383 #ifdef CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM
384 secure_config->extClkHsiom = CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM;
385 #endif /* CY_CFG_SYSCLK_EXTCLK_GPIO_HSIOM */
386
387 #ifdef CY_CFG_SYSCLK_ILO_HIBERNATE
388 secure_config->iloHibernateON = CY_CFG_SYSCLK_ILO_HIBERNATE;
389 #endif /* CY_CFG_SYSCLK_ILO_HIBERNATE */
390
391 #ifdef CY_CFG_SYSCLK_WCO_BYPASS
392 secure_config->bypassEnable = CY_CFG_SYSCLK_WCO_BYPASS;
393 #endif /* CY_CFG_SYSCLK_WCO_BYPASS */
394
395 #ifdef CY_CFG_SYSCLK_WCO_IN_PRT
396 secure_config->wcoInPort = CY_CFG_SYSCLK_WCO_IN_PRT;
397 #endif /* CY_CFG_SYSCLK_WCO_IN_PRT */
398
399 #ifdef CY_CFG_SYSCLK_WCO_OUT_PRT
400 secure_config->wcoOutPort = CY_CFG_SYSCLK_WCO_OUT_PRT;
401 #endif /* CY_CFG_SYSCLK_WCO_OUT_PRT */
402
403 #ifdef CY_CFG_SYSCLK_WCO_IN_PIN
404 secure_config->wcoInPinNum = CY_CFG_SYSCLK_WCO_IN_PIN;
405 #endif /* CY_CFG_SYSCLK_WCO_IN_PIN */
406
407 #ifdef CY_CFG_SYSCLK_WCO_OUT_PIN
408 secure_config->wcoOutPinNum = CY_CFG_SYSCLK_WCO_OUT_PIN;
409 #endif /* CY_CFG_SYSCLK_WCO_OUT_PIN */
410
411 #ifdef CY_CFG_SYSCLK_FLL_OUT_FREQ
412 secure_config->fllOutFreqHz = CY_CFG_SYSCLK_FLL_OUT_FREQ;
413 #endif /* CY_CFG_SYSCLK_FLL_OUT_FREQ */
414
415 #ifdef CY_CFG_SYSCLK_FLL_MULT
416 secure_config->fllMult = CY_CFG_SYSCLK_FLL_MULT;
417 #endif /* CY_CFG_SYSCLK_FLL_MULT */
418
419 #ifdef CY_CFG_SYSCLK_FLL_REFDIV
420 secure_config->fllRefDiv = CY_CFG_SYSCLK_FLL_REFDIV;
421 #endif /* CY_CFG_SYSCLK_FLL_REFDIV */
422
423 #ifdef CY_CFG_SYSCLK_FLL_CCO_RANGE
424 secure_config->fllCcoRange = CY_CFG_SYSCLK_FLL_CCO_RANGE;
425 #endif /* CY_CFG_SYSCLK_FLL_CCO_RANGE */
426
427 #ifdef CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV
428 secure_config->enableOutputDiv = CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV;
429 #endif /* CY_CFG_SYSCLK_FLL_ENABLE_OUTDIV */
430
431 #ifdef CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE
432 secure_config->lockTolerance = CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE;
433 #endif /* CY_CFG_SYSCLK_FLL_LOCK_TOLERANCE */
434
435 #ifdef CY_CFG_SYSCLK_FLL_IGAIN
436 secure_config->igain = CY_CFG_SYSCLK_FLL_IGAIN;
437 #endif /* CY_CFG_SYSCLK_FLL_IGAIN */
438
439 #ifdef CY_CFG_SYSCLK_FLL_PGAIN
440 secure_config->pgain = CY_CFG_SYSCLK_FLL_PGAIN;
441 #endif /* CY_CFG_SYSCLK_FLL_PGAIN */
442
443 #ifdef CY_CFG_SYSCLK_FLL_SETTLING_COUNT
444 secure_config->settlingCount = CY_CFG_SYSCLK_FLL_SETTLING_COUNT;
445 #endif /* CY_CFG_SYSCLK_FLL_SETTLING_COUNT */
446
447 #ifdef CY_CFG_SYSCLK_FLL_OUTPUT_MODE
448 secure_config->outputMode = CY_CFG_SYSCLK_FLL_OUTPUT_MODE;
449 #endif /* CY_CFG_SYSCLK_FLL_OUTPUT_MODE */
450
451 #ifdef CY_CFG_SYSCLK_FLL_CCO_FREQ
452 secure_config->ccoFreq = CY_CFG_SYSCLK_FLL_CCO_FREQ;
453 #endif /* CY_CFG_SYSCLK_FLL_CCO_FREQ */
454
455 #ifdef CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV
456 secure_config->pll0FeedbackDiv = CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV;
457 #endif /* CY_CFG_SYSCLK_PLL0_FEEDBACK_DIV */
458
459 #ifdef CY_CFG_SYSCLK_PLL0_REFERENCE_DIV
460 secure_config->pll0ReferenceDiv = CY_CFG_SYSCLK_PLL0_REFERENCE_DIV;
461 #endif /* CY_CFG_SYSCLK_PLL0_REFERENCE_DIV */
462
463 #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_DIV
464 secure_config->pll0OutputDiv = CY_CFG_SYSCLK_PLL0_OUTPUT_DIV;
465 #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_DIV */
466
467 #ifdef CY_CFG_SYSCLK_PLL0_LF_MODE
468 secure_config->pll0LfMode = CY_CFG_SYSCLK_PLL0_LF_MODE;
469 #endif /* CY_CFG_SYSCLK_PLL0_LF_MODE */
470
471 #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_MODE
472 secure_config->pll0OutputMode = CY_CFG_SYSCLK_PLL0_OUTPUT_MODE;
473 #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_MODE */
474
475 #ifdef CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ
476 secure_config->pll0OutFreqHz = CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ;
477 #endif /* CY_CFG_SYSCLK_PLL0_OUTPUT_FREQ */
478
479 #ifdef CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV
480 secure_config->pll1FeedbackDiv = CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV;
481 #endif /* CY_CFG_SYSCLK_PLL1_FEEDBACK_DIV */
482
483 #ifdef CY_CFG_SYSCLK_PLL1_REFERENCE_DIV
484 secure_config->pll1ReferenceDiv = CY_CFG_SYSCLK_PLL1_REFERENCE_DIV;
485 #endif /* CY_CFG_SYSCLK_PLL1_REFERENCE_DIV */
486
487 #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_DIV
488 secure_config->pll1OutputDiv = CY_CFG_SYSCLK_PLL1_OUTPUT_DIV;
489 #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_DIV */
490
491 #ifdef CY_CFG_SYSCLK_PLL1_LF_MODE
492 secure_config->pll1LfMode = CY_CFG_SYSCLK_PLL1_LF_MODE;
493 #endif /* CY_CFG_SYSCLK_PLL1_LF_MODE */
494
495 #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_MODE
496 secure_config->pll1OutputMode = CY_CFG_SYSCLK_PLL1_OUTPUT_MODE;
497 #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_MODE */
498
499 #ifdef CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ
500 secure_config->pll1OutFreqHz = CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ;
501 #endif /* CY_CFG_SYSCLK_PLL1_OUTPUT_FREQ */
502
503 #ifdef CY_CFG_SYSCLK_CLKPATH0_SOURCE
504 secure_config->path0Src = CY_CFG_SYSCLK_CLKPATH0_SOURCE;
505 #endif /* CY_CFG_SYSCLK_CLKPATH0_SOURCE */
506
507 #ifdef CY_CFG_SYSCLK_CLKPATH1_SOURCE
508 secure_config->path1Src = CY_CFG_SYSCLK_CLKPATH1_SOURCE;
509 #endif /* CY_CFG_SYSCLK_CLKPATH1_SOURCE */
510
511 #ifdef CY_CFG_SYSCLK_CLKPATH2_SOURCE
512 secure_config->path2Src = CY_CFG_SYSCLK_CLKPATH2_SOURCE;
513 #endif /* CY_CFG_SYSCLK_CLKPATH2_SOURCE */
514
515 #ifdef CY_CFG_SYSCLK_CLKPATH3_SOURCE
516 secure_config->path3Src = CY_CFG_SYSCLK_CLKPATH3_SOURCE;
517 #endif /* CY_CFG_SYSCLK_CLKPATH3_SOURCE */
518
519 #ifdef CY_CFG_SYSCLK_CLKPATH4_SOURCE
520 secure_config->path4Src = CY_CFG_SYSCLK_CLKPATH4_SOURCE;
521 #endif /* CY_CFG_SYSCLK_CLKPATH4_SOURCE */
522
523 #ifdef CY_CFG_SYSCLK_CLKPATH5_SOURCE
524 secure_config->path5Src = CY_CFG_SYSCLK_CLKPATH5_SOURCE;
525 #endif /* CY_CFG_SYSCLK_CLKPATH5_SOURCE */
526
527 #ifdef CY_CFG_SYSCLK_CLKFAST_DIVIDER
528 secure_config->clkFastDiv = CY_CFG_SYSCLK_CLKFAST_DIVIDER;
529 #endif /* CY_CFG_SYSCLK_CLKFAST_DIVIDER */
530
531 #ifdef CY_CFG_SYSCLK_CLKPERI_DIVIDER
532 secure_config->clkPeriDiv = CY_CFG_SYSCLK_CLKPERI_DIVIDER;
533 #endif /* CY_CFG_SYSCLK_CLKPERI_DIVIDER */
534
535 #ifdef CY_CFG_SYSCLK_CLKSLOW_DIVIDER
536 secure_config->clkSlowDiv = CY_CFG_SYSCLK_CLKSLOW_DIVIDER;
537 #endif /* CY_CFG_SYSCLK_CLKSLOW_DIVIDER */
538
539 #ifdef CY_CFG_SYSCLK_CLKHF0_CLKPATH
540 secure_config->hf0Source = CY_CFG_SYSCLK_CLKHF0_CLKPATH;
541 #endif /* CY_CFG_SYSCLK_CLKHF0_CLKPATH */
542
543 #ifdef CY_CFG_SYSCLK_CLKHF0_DIVIDER
544 secure_config->hf0Divider = CY_CFG_SYSCLK_CLKHF0_DIVIDER;
545 #endif /* CY_CFG_SYSCLK_CLKHF0_DIVIDER */
546
547 #ifdef CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ
548 secure_config->hf0OutFreqMHz = CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ;
549 #endif /* CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ */
550
551 #ifdef CY_CFG_SYSCLK_CLKHF1_CLKPATH
552 secure_config->hf1Source = CY_CFG_SYSCLK_CLKHF1_CLKPATH;
553 #endif /* CY_CFG_SYSCLK_CLKHF1_CLKPATH */
554
555 #ifdef CY_CFG_SYSCLK_CLKHF1_DIVIDER
556 secure_config->hf1Divider = CY_CFG_SYSCLK_CLKHF1_DIVIDER;
557 #endif /* CY_CFG_SYSCLK_CLKHF1_DIVIDER */
558
559 #ifdef CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ
560 secure_config->hf1OutFreqMHz = CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ;
561 #endif /* CY_CFG_SYSCLK_CLKHF1_FREQ_MHZ */
562
563 #ifdef CY_CFG_SYSCLK_CLKHF2_CLKPATH
564 secure_config->hf2Source = CY_CFG_SYSCLK_CLKHF2_CLKPATH;
565 #endif /* CY_CFG_SYSCLK_CLKHF2_CLKPATH */
566
567 #ifdef CY_CFG_SYSCLK_CLKHF2_DIVIDER
568 secure_config->hf2Divider = CY_CFG_SYSCLK_CLKHF2_DIVIDER;
569 #endif /* CY_CFG_SYSCLK_CLKHF2_DIVIDER */
570
571 #ifdef CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ
572 secure_config->hf2OutFreqMHz = CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ;
573 #endif /* CY_CFG_SYSCLK_CLKHF2_FREQ_MHZ */
574
575 #ifdef CY_CFG_SYSCLK_CLKHF3_CLKPATH
576 secure_config->hf3Source = CY_CFG_SYSCLK_CLKHF3_CLKPATH;
577 #endif /* CY_CFG_SYSCLK_CLKHF3_CLKPATH */
578
579 #ifdef CY_CFG_SYSCLK_CLKHF3_DIVIDER
580 secure_config->hf3Divider = CY_CFG_SYSCLK_CLKHF3_DIVIDER;
581 #endif /* CY_CFG_SYSCLK_CLKHF3_DIVIDER */
582
583 #ifdef CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ
584 secure_config->hf3OutFreqMHz = CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ;
585 #endif /* CY_CFG_SYSCLK_CLKHF3_FREQ_MHZ */
586
587 #ifdef CY_CFG_SYSCLK_CLKHF4_CLKPATH
588 secure_config->hf4Source = CY_CFG_SYSCLK_CLKHF4_CLKPATH;
589 #endif /* CY_CFG_SYSCLK_CLKHF4_CLKPATH */
590
591 #ifdef CY_CFG_SYSCLK_CLKHF4_DIVIDER
592 secure_config->hf4Divider = CY_CFG_SYSCLK_CLKHF4_DIVIDER;
593 #endif /* CY_CFG_SYSCLK_CLKHF4_DIVIDER */
594
595 #ifdef CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ
596 secure_config->hf4OutFreqMHz = CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ;
597 #endif /* CY_CFG_SYSCLK_CLKHF4_FREQ_MHZ */
598
599 #ifdef CY_CFG_SYSCLK_CLKHF5_CLKPATH
600 secure_config->hf5Source = CY_CFG_SYSCLK_CLKHF5_CLKPATH;
601 #endif /* CY_CFG_SYSCLK_CLKHF5_CLKPATH */
602
603 #ifdef CY_CFG_SYSCLK_CLKHF5_DIVIDER
604 secure_config->hf5Divider = CY_CFG_SYSCLK_CLKHF5_DIVIDER;
605 #endif /* CY_CFG_SYSCLK_CLKHF5_DIVIDER */
606
607 #ifdef CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ
608 secure_config->hf5OutFreqMHz = CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ;
609 #endif /* CY_CFG_SYSCLK_CLKHF5_FREQ_MHZ */
610
611 #ifdef CY_CFG_SYSCLK_CLKPUMP_SOURCE
612 secure_config->pumpSource = CY_CFG_SYSCLK_CLKPUMP_SOURCE;
613 #endif /* CY_CFG_SYSCLK_CLKPUMP_SOURCE */
614
615 #ifdef CY_CFG_SYSCLK_CLKPUMP_DIVIDER
616 secure_config->pumpDivider = CY_CFG_SYSCLK_CLKPUMP_DIVIDER;
617 #endif /* CY_CFG_SYSCLK_CLKPUMP_DIVIDER */
618
619 #ifdef CY_CFG_SYSCLK_CLKLF_SOURCE
620 secure_config->clkLfSource = CY_CFG_SYSCLK_CLKLF_SOURCE;
621 #endif /* CY_CFG_SYSCLK_CLKLF_SOURCE */
622
623 #ifdef CY_CFG_SYSCLK_CLKBAK_SOURCE
624 secure_config->clkBakSource = CY_CFG_SYSCLK_CLKBAK_SOURCE;
625 #endif /* CY_CFG_SYSCLK_CLKBAK_SOURCE */
626
627 #ifdef CY_CFG_SYSCLK_CLKTIMER_SOURCE
628 secure_config->clkTimerSource = CY_CFG_SYSCLK_CLKTIMER_SOURCE;
629 #endif /* CY_CFG_SYSCLK_CLKTIMER_SOURCE */
630
631 #ifdef CY_CFG_SYSCLK_CLKTIMER_DIVIDER
632 secure_config->clkTimerDivider = CY_CFG_SYSCLK_CLKTIMER_DIVIDER;
633 #endif /* CY_CFG_SYSCLK_CLKTIMER_DIVIDER */
634
635 #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE
636 secure_config->clkSrcAltSysTick = CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE;
637 #endif /* CY_CFG_SYSCLK_CLKALTSYSTICK_SOURCE */
638
639 #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD
640 secure_config->altHFcLoad = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD;
641 #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLOAD */
642
643 #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME
644 secure_config->altHFxtalStartUpTime = CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME;
645 #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_TIME */
646
647 #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ
648 secure_config->altHFclkFreq = CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ;
649 #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_FREQ */
650
651 #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV
652 secure_config->altHFsysClkDiv = CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV;
653 #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_CLK_DIV */
654
655 #ifdef CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR
656 secure_config->altHFvoltageReg = CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR;
657 #endif /* CY_CFG_SYSCLK_ALTHF_BLE_ECO_VOL_REGULATOR */
658 }
659 #endif //defined (CY_DEVICE_SECURE) && (CY_CPU_CORTEX_M4)
660 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkBakInit()661 __STATIC_INLINE void Cy_SysClk_ClkBakInit()
662 {
663 Cy_SysClk_ClkBakSetSource(CY_SYSCLK_BAK_IN_CLKLF);
664 }
665 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
666 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkFastInit()667 __STATIC_INLINE void Cy_SysClk_ClkFastInit()
668 {
669 Cy_SysClk_ClkFastSetDivider(0U);
670 }
671 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
672 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_FllInit()673 __STATIC_INLINE void Cy_SysClk_FllInit()
674 {
675 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&srss_0_clock_0_fll_0_fllConfig))
676 {
677 cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
678 }
679 if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(200000UL))
680 {
681 cycfg_ClockStartupError(CY_CFG_SYSCLK_FLL_ERROR);
682 }
683 }
684 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
685 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkHf0Init()686 __STATIC_INLINE void Cy_SysClk_ClkHf0Init()
687 {
688 Cy_SysClk_ClkHfSetSource(0U, CY_CFG_SYSCLK_CLKHF0_CLKPATH);
689 Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
690 }
691 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
692 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_IloInit()693 __STATIC_INLINE void Cy_SysClk_IloInit()
694 {
695 /* The WDT is unlocked in the default startup code */
696 Cy_SysClk_IloEnable();
697 Cy_SysClk_IloHibernateOn(true);
698 }
699 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
700 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkLfInit()701 __STATIC_INLINE void Cy_SysClk_ClkLfInit()
702 {
703 /* The WDT is unlocked in the default startup code */
704 Cy_SysClk_ClkLfSetSource(CY_SYSCLK_CLKLF_IN_WCO);
705 }
706 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
707 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkPath0Init()708 __STATIC_INLINE void Cy_SysClk_ClkPath0Init()
709 {
710 Cy_SysClk_ClkPathSetSource(0U, CY_CFG_SYSCLK_CLKPATH0_SOURCE);
711 }
712 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
713 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkPath1Init()714 __STATIC_INLINE void Cy_SysClk_ClkPath1Init()
715 {
716 Cy_SysClk_ClkPathSetSource(1U, CY_CFG_SYSCLK_CLKPATH1_SOURCE);
717 }
718 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
719 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkPath2Init()720 __STATIC_INLINE void Cy_SysClk_ClkPath2Init()
721 {
722 Cy_SysClk_ClkPathSetSource(2U, CY_CFG_SYSCLK_CLKPATH2_SOURCE);
723 }
724 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
725 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkPath3Init()726 __STATIC_INLINE void Cy_SysClk_ClkPath3Init()
727 {
728 Cy_SysClk_ClkPathSetSource(3U, CY_CFG_SYSCLK_CLKPATH3_SOURCE);
729 }
730 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
731 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkPath4Init()732 __STATIC_INLINE void Cy_SysClk_ClkPath4Init()
733 {
734 Cy_SysClk_ClkPathSetSource(4U, CY_CFG_SYSCLK_CLKPATH4_SOURCE);
735 }
736 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
737 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkPath5Init()738 __STATIC_INLINE void Cy_SysClk_ClkPath5Init()
739 {
740 Cy_SysClk_ClkPathSetSource(5U, CY_CFG_SYSCLK_CLKPATH5_SOURCE);
741 }
742 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
743 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkPeriInit()744 __STATIC_INLINE void Cy_SysClk_ClkPeriInit()
745 {
746 Cy_SysClk_ClkPeriSetDivider(0U);
747 }
748 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
749 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_Pll0Init()750 __STATIC_INLINE void Cy_SysClk_Pll0Init()
751 {
752 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllManualConfigure(1U, &srss_0_clock_0_pll_0_pllConfig))
753 {
754 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
755 }
756 if (CY_SYSCLK_SUCCESS != Cy_SysClk_PllEnable(1U, 10000u))
757 {
758 cycfg_ClockStartupError(CY_CFG_SYSCLK_PLL_ERROR);
759 }
760 }
761 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
762 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkSlowInit()763 __STATIC_INLINE void Cy_SysClk_ClkSlowInit()
764 {
765 Cy_SysClk_ClkSlowSetDivider(0U);
766 }
767 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
768 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_ClkTimerInit()769 __STATIC_INLINE void Cy_SysClk_ClkTimerInit()
770 {
771 Cy_SysClk_ClkTimerDisable();
772 Cy_SysClk_ClkTimerSetSource(CY_SYSCLK_CLKTIMER_IN_IMO);
773 Cy_SysClk_ClkTimerSetDivider(0U);
774 Cy_SysClk_ClkTimerEnable();
775 }
776 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
777 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
Cy_SysClk_WcoInit()778 __STATIC_INLINE void Cy_SysClk_WcoInit()
779 {
780 (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 0U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
781 (void)Cy_GPIO_Pin_FastInit(GPIO_PRT0, 1U, 0x00U, 0x00U, HSIOM_SEL_GPIO);
782 if (CY_SYSCLK_SUCCESS != Cy_SysClk_WcoEnable(1000000UL))
783 {
784 cycfg_ClockStartupError(CY_CFG_SYSCLK_WCO_ERROR);
785 }
786 }
787 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
788 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
init_cycfg_power(void)789 __STATIC_INLINE void init_cycfg_power(void)
790 {
791 /* Reset the Backup domain on POR, XRES, BOD only if Backup domain is supplied by VDDD */
792 #if (CY_CFG_PWR_VBACKUP_USING_VDDD)
793 #ifdef CY_CFG_SYSCLK_ILO_ENABLED
794 if (0u == Cy_SysLib_GetResetReason() /* POR, XRES, or BOD */)
795 {
796 Cy_SysLib_ResetBackupDomain();
797 Cy_SysClk_IloDisable();
798 Cy_SysClk_IloInit();
799 }
800 #endif /* CY_CFG_SYSCLK_ILO_ENABLED */
801 #endif /* CY_CFG_PWR_VBACKUP_USING_VDDD */
802 /* Configure core regulator */
803 #if !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
804 #if CY_CFG_PWR_USING_LDO
805 Cy_SysPm_LdoSetVoltage(CY_SYSPM_LDO_VOLTAGE_LP);
806 #else
807 Cy_SysPm_BuckEnable(CY_SYSPM_BUCK_OUT1_VOLTAGE_LP);
808 #endif /* CY_CFG_PWR_USING_LDO */
809 #if CY_CFG_PWR_REGULATOR_MODE_MIN
810 Cy_SysPm_SystemSetMinRegulatorCurrent();
811 #else
812 Cy_SysPm_SystemSetNormalRegulatorCurrent();
813 #endif /* CY_CFG_PWR_REGULATOR_MODE_MIN */
814 #endif /* !((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */
815 /* Configure PMIC */
816 Cy_SysPm_UnlockPmic();
817 #if CY_CFG_PWR_USING_PMIC
818 Cy_SysPm_PmicEnableOutput();
819 #else
820 Cy_SysPm_PmicDisableOutput();
821 #endif /* CY_CFG_PWR_USING_PMIC */
822 }
823 #endif //((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
824
825
init_cycfg_system(void)826 void init_cycfg_system(void)
827 {
828 #if ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE)))
829 cy_en_pra_status_t configStatus;
830 init_cycfg_secure_struct(&srss_0_clock_0_secureConfig);
831 #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0UL))
832 #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0.
833 #endif
834 #if ((CY_CFG_SYSCLK_CLKPATH1_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 1UL))
835 #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0.
836 #endif
837 #if ((CY_CFG_SYSCLK_CLKPATH2_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 2UL))
838 #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0.
839 #endif
840 #if ((CY_CFG_SYSCLK_CLKPATH3_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 3UL))
841 #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0.
842 #endif
843 #if ((CY_CFG_SYSCLK_CLKPATH4_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 4UL))
844 #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0.
845 #endif
846 #if ((CY_CFG_SYSCLK_CLKPATH5_SOURCE_NUM != 0UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 5UL))
847 #error Configuration Error : ECO, WCO, ALTHF, EXTCLK, ILO, PILO cannot drive HF0.
848 #endif
849
850 configStatus = CY_PRA_FUNCTION_CALL_RETURN_PARAM(CY_PRA_MSG_TYPE_SYS_CFG_FUNC,
851 CY_PRA_FUNC_INIT_CYCFG_DEVICE,
852 &srss_0_clock_0_secureConfig);
853 if ( configStatus != CY_PRA_STATUS_SUCCESS )
854 {
855 cycfg_ClockStartupError(configStatus);
856 }
857
858 #ifdef CY_CFG_SYSCLK_EXTCLK_FREQ
859 Cy_SysClk_ExtClkSetFrequency(CY_CFG_SYSCLK_EXTCLK_FREQ);
860 #endif /* CY_CFG_SYSCLK_EXTCLK_FREQ */
861 #else /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */
862
863 /* Set worst case memory wait states (! ultra low power, 150 MHz), will update at the end */
864 Cy_SysLib_SetWaitStates(false, 150UL);
865 #ifdef CY_CFG_PWR_ENABLED
866 #ifdef CY_CFG_PWR_INIT
867 init_cycfg_power();
868 #else
869 #warning Power system will not be configured. Update power personality to v1.20 or later.
870 #endif /* CY_CFG_PWR_INIT */
871 #endif /* CY_CFG_PWR_ENABLED */
872
873 /* Reset the core clock path to default and disable all the FLLs/PLLs */
874 Cy_SysClk_ClkHfSetDivider(0U, CY_SYSCLK_CLKHF_NO_DIVIDE);
875 Cy_SysClk_ClkFastSetDivider(0U);
876 Cy_SysClk_ClkPeriSetDivider(1U);
877 Cy_SysClk_ClkSlowSetDivider(0U);
878 for (uint32_t pll = CY_SRSS_NUM_PLL; pll > 0UL; --pll) /* PLL 1 is the first PLL. 0 is invalid. */
879 {
880 (void)Cy_SysClk_PllDisable(pll);
881 }
882 Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH1, CY_SYSCLK_CLKPATH_IN_IMO);
883
884 if ((CY_SYSCLK_CLKHF_IN_CLKPATH0 == Cy_SysClk_ClkHfGetSource(0UL)) &&
885 (CY_SYSCLK_CLKPATH_IN_WCO == Cy_SysClk_ClkPathGetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0)))
886 {
887 Cy_SysClk_ClkHfSetSource(0U, CY_SYSCLK_CLKHF_IN_CLKPATH1);
888 }
889
890 Cy_SysClk_FllDisable();
891 Cy_SysClk_ClkPathSetSource(CY_SYSCLK_CLKHF_IN_CLKPATH0, CY_SYSCLK_CLKPATH_IN_IMO);
892 Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);
893 #ifdef CY_IP_MXBLESS
894 (void)Cy_BLE_EcoReset();
895 #endif
896
897
898 /* Enable all source clocks */
899 #ifdef CY_CFG_SYSCLK_PILO_ENABLED
900 Cy_SysClk_PiloInit();
901 #endif
902
903 #ifdef CY_CFG_SYSCLK_WCO_ENABLED
904 Cy_SysClk_WcoInit();
905 #endif
906
907 #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
908 Cy_SysClk_ClkLfInit();
909 #endif
910
911 #ifdef CY_CFG_SYSCLK_ALTHF_ENABLED
912 Cy_SysClk_AltHfInit();
913 #endif
914
915 #ifdef CY_CFG_SYSCLK_ECO_ENABLED
916 Cy_SysClk_EcoInit();
917 #endif
918
919 #ifdef CY_CFG_SYSCLK_EXTCLK_ENABLED
920 Cy_SysClk_ExtClkInit();
921 #endif
922
923 /* Configure CPU clock dividers */
924 #ifdef CY_CFG_SYSCLK_CLKFAST_ENABLED
925 Cy_SysClk_ClkFastInit();
926 #endif
927
928 #ifdef CY_CFG_SYSCLK_CLKPERI_ENABLED
929 Cy_SysClk_ClkPeriInit();
930 #endif
931
932 #ifdef CY_CFG_SYSCLK_CLKSLOW_ENABLED
933 Cy_SysClk_ClkSlowInit();
934 #endif
935
936 #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
937 /* Configure HFCLK0 to temporarily run from IMO to initialize other clocks */
938 Cy_SysClk_ClkPathSetSource(1UL, CY_SYSCLK_CLKPATH_IN_IMO);
939 Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH1);
940 #else
941 #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
942 Cy_SysClk_ClkPath1Init();
943 #endif
944 #endif
945
946 /* Configure Path Clocks */
947 #ifdef CY_CFG_SYSCLK_CLKPATH0_ENABLED
948 Cy_SysClk_ClkPath0Init();
949 #endif
950 #ifdef CY_CFG_SYSCLK_CLKPATH2_ENABLED
951 Cy_SysClk_ClkPath2Init();
952 #endif
953 #ifdef CY_CFG_SYSCLK_CLKPATH3_ENABLED
954 Cy_SysClk_ClkPath3Init();
955 #endif
956 #ifdef CY_CFG_SYSCLK_CLKPATH4_ENABLED
957 Cy_SysClk_ClkPath4Init();
958 #endif
959 #ifdef CY_CFG_SYSCLK_CLKPATH5_ENABLED
960 Cy_SysClk_ClkPath5Init();
961 #endif
962 #ifdef CY_CFG_SYSCLK_CLKPATH6_ENABLED
963 Cy_SysClk_ClkPath6Init();
964 #endif
965 #ifdef CY_CFG_SYSCLK_CLKPATH7_ENABLED
966 Cy_SysClk_ClkPath7Init();
967 #endif
968 #ifdef CY_CFG_SYSCLK_CLKPATH8_ENABLED
969 Cy_SysClk_ClkPath8Init();
970 #endif
971 #ifdef CY_CFG_SYSCLK_CLKPATH9_ENABLED
972 Cy_SysClk_ClkPath9Init();
973 #endif
974 #ifdef CY_CFG_SYSCLK_CLKPATH10_ENABLED
975 Cy_SysClk_ClkPath10Init();
976 #endif
977 #ifdef CY_CFG_SYSCLK_CLKPATH11_ENABLED
978 Cy_SysClk_ClkPath11Init();
979 #endif
980 #ifdef CY_CFG_SYSCLK_CLKPATH12_ENABLED
981 Cy_SysClk_ClkPath12Init();
982 #endif
983 #ifdef CY_CFG_SYSCLK_CLKPATH13_ENABLED
984 Cy_SysClk_ClkPath13Init();
985 #endif
986 #ifdef CY_CFG_SYSCLK_CLKPATH14_ENABLED
987 Cy_SysClk_ClkPath14Init();
988 #endif
989 #ifdef CY_CFG_SYSCLK_CLKPATH15_ENABLED
990 Cy_SysClk_ClkPath15Init();
991 #endif
992
993 /* Configure and enable FLL */
994 #ifdef CY_CFG_SYSCLK_FLL_ENABLED
995 Cy_SysClk_FllInit();
996 #endif
997
998 Cy_SysClk_ClkHf0Init();
999
1000 #if ((CY_CFG_SYSCLK_CLKPATH0_SOURCE_NUM == 0x6UL) && (CY_CFG_SYSCLK_CLKHF0_CLKPATH_NUM == 0U))
1001 #ifdef CY_CFG_SYSCLK_CLKPATH1_ENABLED
1002 /* Apply the ClkPath1 user setting */
1003 Cy_SysClk_ClkPath1Init();
1004 #endif
1005 #endif
1006
1007 /* Configure and enable PLLs */
1008 #ifdef CY_CFG_SYSCLK_PLL0_ENABLED
1009 Cy_SysClk_Pll0Init();
1010 #endif
1011 #ifdef CY_CFG_SYSCLK_PLL1_ENABLED
1012 Cy_SysClk_Pll1Init();
1013 #endif
1014 #ifdef CY_CFG_SYSCLK_PLL2_ENABLED
1015 Cy_SysClk_Pll2Init();
1016 #endif
1017 #ifdef CY_CFG_SYSCLK_PLL3_ENABLED
1018 Cy_SysClk_Pll3Init();
1019 #endif
1020 #ifdef CY_CFG_SYSCLK_PLL4_ENABLED
1021 Cy_SysClk_Pll4Init();
1022 #endif
1023 #ifdef CY_CFG_SYSCLK_PLL5_ENABLED
1024 Cy_SysClk_Pll5Init();
1025 #endif
1026 #ifdef CY_CFG_SYSCLK_PLL6_ENABLED
1027 Cy_SysClk_Pll6Init();
1028 #endif
1029 #ifdef CY_CFG_SYSCLK_PLL7_ENABLED
1030 Cy_SysClk_Pll7Init();
1031 #endif
1032 #ifdef CY_CFG_SYSCLK_PLL8_ENABLED
1033 Cy_SysClk_Pll8Init();
1034 #endif
1035 #ifdef CY_CFG_SYSCLK_PLL9_ENABLED
1036 Cy_SysClk_Pll9Init();
1037 #endif
1038 #ifdef CY_CFG_SYSCLK_PLL10_ENABLED
1039 Cy_SysClk_Pll10Init();
1040 #endif
1041 #ifdef CY_CFG_SYSCLK_PLL11_ENABLED
1042 Cy_SysClk_Pll11Init();
1043 #endif
1044 #ifdef CY_CFG_SYSCLK_PLL12_ENABLED
1045 Cy_SysClk_Pll12Init();
1046 #endif
1047 #ifdef CY_CFG_SYSCLK_PLL13_ENABLED
1048 Cy_SysClk_Pll13Init();
1049 #endif
1050 #ifdef CY_CFG_SYSCLK_PLL14_ENABLED
1051 Cy_SysClk_Pll14Init();
1052 #endif
1053
1054 /* Configure HF clocks */
1055 #ifdef CY_CFG_SYSCLK_CLKHF1_ENABLED
1056 Cy_SysClk_ClkHf1Init();
1057 #endif
1058 #ifdef CY_CFG_SYSCLK_CLKHF2_ENABLED
1059 Cy_SysClk_ClkHf2Init();
1060 #endif
1061 #ifdef CY_CFG_SYSCLK_CLKHF3_ENABLED
1062 Cy_SysClk_ClkHf3Init();
1063 #endif
1064 #ifdef CY_CFG_SYSCLK_CLKHF4_ENABLED
1065 Cy_SysClk_ClkHf4Init();
1066 #endif
1067 #ifdef CY_CFG_SYSCLK_CLKHF5_ENABLED
1068 Cy_SysClk_ClkHf5Init();
1069 #endif
1070 #ifdef CY_CFG_SYSCLK_CLKHF6_ENABLED
1071 Cy_SysClk_ClkHf6Init();
1072 #endif
1073 #ifdef CY_CFG_SYSCLK_CLKHF7_ENABLED
1074 Cy_SysClk_ClkHf7Init();
1075 #endif
1076 #ifdef CY_CFG_SYSCLK_CLKHF8_ENABLED
1077 Cy_SysClk_ClkHf8Init();
1078 #endif
1079 #ifdef CY_CFG_SYSCLK_CLKHF9_ENABLED
1080 Cy_SysClk_ClkHf9Init();
1081 #endif
1082 #ifdef CY_CFG_SYSCLK_CLKHF10_ENABLED
1083 Cy_SysClk_ClkHf10Init();
1084 #endif
1085 #ifdef CY_CFG_SYSCLK_CLKHF11_ENABLED
1086 Cy_SysClk_ClkHf11Init();
1087 #endif
1088 #ifdef CY_CFG_SYSCLK_CLKHF12_ENABLED
1089 Cy_SysClk_ClkHf12Init();
1090 #endif
1091 #ifdef CY_CFG_SYSCLK_CLKHF13_ENABLED
1092 Cy_SysClk_ClkHf13Init();
1093 #endif
1094 #ifdef CY_CFG_SYSCLK_CLKHF14_ENABLED
1095 Cy_SysClk_ClkHf14Init();
1096 #endif
1097 #ifdef CY_CFG_SYSCLK_CLKHF15_ENABLED
1098 Cy_SysClk_ClkHf15Init();
1099 #endif
1100
1101 /* Configure miscellaneous clocks */
1102 #ifdef CY_CFG_SYSCLK_CLKTIMER_ENABLED
1103 Cy_SysClk_ClkTimerInit();
1104 #endif
1105
1106 #ifdef CY_CFG_SYSCLK_CLKALTSYSTICK_ENABLED
1107 Cy_SysClk_ClkAltSysTickInit();
1108 #endif
1109
1110 #ifdef CY_CFG_SYSCLK_CLKPUMP_ENABLED
1111 Cy_SysClk_ClkPumpInit();
1112 #endif
1113
1114 #ifdef CY_CFG_SYSCLK_CLKBAK_ENABLED
1115 Cy_SysClk_ClkBakInit();
1116 #endif
1117
1118 /* Configure default enabled clocks */
1119 #ifdef CY_CFG_SYSCLK_ILO_ENABLED
1120 Cy_SysClk_IloInit();
1121 #endif
1122
1123 #ifndef CY_CFG_SYSCLK_IMO_ENABLED
1124 #error the IMO must be enabled for proper chip operation
1125 #endif
1126
1127 #endif /* ((CY_CPU_CORTEX_M4) && (defined(CY_DEVICE_SECURE))) */
1128
1129 #ifdef CY_CFG_SYSCLK_MFO_ENABLED
1130 Cy_SysClk_MfoInit();
1131 #endif
1132
1133 #ifdef CY_CFG_SYSCLK_CLKMF_ENABLED
1134 Cy_SysClk_ClkMfInit();
1135 #endif
1136
1137 #if ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE)))
1138 /* Set accurate flash wait states */
1139 #if (defined (CY_CFG_PWR_ENABLED) && defined (CY_CFG_SYSCLK_CLKHF0_ENABLED))
1140 Cy_SysLib_SetWaitStates(CY_CFG_PWR_USING_ULP != 0, CY_CFG_SYSCLK_CLKHF0_FREQ_MHZ);
1141 #endif
1142
1143 /* Update System Core Clock values for correct Cy_SysLib_Delay functioning */
1144 SystemCoreClockUpdate();
1145 #ifndef CY_CFG_SYSCLK_ILO_ENABLED
1146 #ifdef CY_CFG_SYSCLK_CLKLF_ENABLED
1147 /* Wait 4 ILO cycles in case of unfinished CLKLF clock source transition */
1148 Cy_SysLib_DelayUs(200U);
1149 #endif
1150 Cy_SysClk_IloDisable();
1151 Cy_SysClk_IloHibernateOn(false);
1152 #endif
1153
1154 #endif /* ((!CY_CPU_CORTEX_M4) || (!defined(CY_DEVICE_SECURE))) */
1155
1156
1157 #if defined (CY_USING_HAL)
1158 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_0_obj);
1159 #endif //defined (CY_USING_HAL)
1160
1161 #if defined (CY_USING_HAL)
1162 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_1_obj);
1163 #endif //defined (CY_USING_HAL)
1164
1165 #if defined (CY_USING_HAL)
1166 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_2_obj);
1167 #endif //defined (CY_USING_HAL)
1168
1169 #if defined (CY_USING_HAL)
1170 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_3_obj);
1171 #endif //defined (CY_USING_HAL)
1172
1173 #if defined (CY_USING_HAL)
1174 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_4_obj);
1175 #endif //defined (CY_USING_HAL)
1176
1177 #if defined (CY_USING_HAL)
1178 cyhal_hwmgr_reserve(&srss_0_clock_0_pathmux_5_obj);
1179 #endif //defined (CY_USING_HAL)
1180 }
1181
