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Searched refs:CPU0_PWRCTRL_BASE_S (Results 1 – 5 of 5) sorted by relevance

/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/partition/
Dplatform_base_address.h79 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/common/partition/
Dplatform_base_address.h115 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an547/partition/
Dplatform_base_address.h112 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an552/partition/
Dplatform_base_address.h117 #define CPU0_PWRCTRL_BASE_S 0x50012000 /* CPU 0 Power Control Block Secure base addres… macro
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/common/device/include/
Dpower_control.h52 (struct cpu0_pwrctrl_t*) CPU0_PWRCTRL_BASE_S;