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Searched refs:CLR_BIT (Results 1 – 18 of 18) sorted by relevance

/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_s1/Native_Driver/
Dtimer_cmsdk_drv.c22 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
89 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_disable_external_input()
104 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_internal()
133 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_disable()
154 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in timer_cmsdk_disable_interrupt()
Dmusca_s1_scc_drv.c24 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1u << (BIT_INDEX))) macro
406 CLR_BIT(scc_regs->scc_mram_ctrl0, SCC_MRAM_CTRL0_FAST_READ_EN); in musca_s1_scc_mram_fast_read_disable()
Dqspi_ip6514e_drv.c28 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
284 CLR_BIT(reg_map->qspi_cfg, QSPI_CFG_ENABLE_POS); in qspi_ip6514e_disable()
500 CLR_BIT(reg_map->qspi_cfg, QSPI_CFG_ENABLE_ADDR_REMAP_POS); in qspi_ip6514e_disable_remap()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_b1/Native_Driver/
Dtimer_cmsdk_drv.c31 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
98 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_disable_external_input()
113 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_internal()
142 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_disable()
163 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in timer_cmsdk_disable_interrupt()
Dqspi_ip6514e_drv.c28 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
284 CLR_BIT(reg_map->qspi_cfg, QSPI_CFG_ENABLE_POS); in qspi_ip6514e_disable()
500 CLR_BIT(reg_map->qspi_cfg, QSPI_CFG_ENABLE_ADDR_REMAP_POS); in qspi_ip6514e_disable_remap()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps2/an519/native_drivers/timer_cmsdk/
Dtimer_cmsdk.c31 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
98 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_disable_external_input()
113 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_internal()
142 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_disable()
163 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in cmsdk_timer_disable_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an524/native_drivers/
Dtimer_cmsdk_drv.c31 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
100 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_disable_external_input()
115 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_internal()
144 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_disable()
165 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in timer_cmsdk_disable_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps2/an521/native_drivers/timer_cmsdk/
Dtimer_cmsdk.c31 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
98 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_disable_external_input()
113 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_internal()
142 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_disable()
163 CLR_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in cmsdk_timer_disable_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/native_drivers/
Dsyscounter_armv8-m_cntrl_drv.c53 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
215 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_EN_OFF); in syscounter_armv8_m_cntrl_disable_counter()
240 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_HDBG_OFF); in syscounter_armv8_m_cntrl_disable_halt_on_debug()
265 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_SCEN_OFF); in syscounter_armv8_m_cntrl_disable_scale()
290 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRMASK_OFF); in syscounter_armv8_m_cntrl_disable_interrupt()
315 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_PSLVERRDIS_OFF); in syscounter_armv8_m_cntrl_disable_pslverr()
332 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRCLR_OFF); in syscounter_armv8_m_cntrl_clear_interrupt()
Dsystimer_armv8-m_drv.c29 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1u << (BIT_INDEX))) macro
231 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_EN_OFF); in systimer_armv8_m_disable_timer()
248 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_IMASK_OFF); in systimer_armv8_m_enable_interrupt()
317 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_EN_OFF); in systimer_armv8_m_disable_autoinc()
334 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_IRQ_CLR_OFF); in systimer_armv8_m_clear_autoinc_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/common/native_drivers/
Dsyscounter_armv8-m_cntrl_drv.c54 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
163 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_EN_OFF); in syscounter_armv8_m_cntrl_disable_counter()
188 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_HDBG_OFF); in syscounter_armv8_m_cntrl_disable_halt_on_debug()
213 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_SCEN_OFF); in syscounter_armv8_m_cntrl_disable_scale()
238 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRMASK_OFF); in syscounter_armv8_m_cntrl_disable_interrupt()
263 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_PSLVERRDIS_OFF); in syscounter_armv8_m_cntrl_disable_pslverr()
280 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRCLR_OFF); in syscounter_armv8_m_cntrl_clear_interrupt()
Dsystimer_armv8-m_drv.c29 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1u << (BIT_INDEX))) macro
173 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_EN_OFF); in systimer_armv8_m_disable_timer()
190 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_IMASK_OFF); in systimer_armv8_m_enable_interrupt()
259 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_EN_OFF); in systimer_armv8_m_disable_autoinc()
276 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_IRQ_CLR_OFF); in systimer_armv8_m_clear_autoinc_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an552/native_drivers/
Dsyscounter_armv8-m_cntrl_drv.c53 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
215 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_EN_OFF); in syscounter_armv8_m_cntrl_disable_counter()
240 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_HDBG_OFF); in syscounter_armv8_m_cntrl_disable_halt_on_debug()
265 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_SCEN_OFF); in syscounter_armv8_m_cntrl_disable_scale()
290 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRMASK_OFF); in syscounter_armv8_m_cntrl_disable_interrupt()
315 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_PSLVERRDIS_OFF); in syscounter_armv8_m_cntrl_disable_pslverr()
332 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRCLR_OFF); in syscounter_armv8_m_cntrl_clear_interrupt()
Dsystimer_armv8-m_drv.c29 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1u << (BIT_INDEX))) macro
231 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_EN_OFF); in systimer_armv8_m_disable_timer()
248 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_IMASK_OFF); in systimer_armv8_m_enable_interrupt()
317 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_EN_OFF); in systimer_armv8_m_disable_autoinc()
334 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_IRQ_CLR_OFF); in systimer_armv8_m_clear_autoinc_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an547/native_drivers/
Dsyscounter_armv8-m_cntrl_drv.c53 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
215 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_EN_OFF); in syscounter_armv8_m_cntrl_disable_counter()
240 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_HDBG_OFF); in syscounter_armv8_m_cntrl_disable_halt_on_debug()
265 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_SCEN_OFF); in syscounter_armv8_m_cntrl_disable_scale()
290 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRMASK_OFF); in syscounter_armv8_m_cntrl_disable_interrupt()
315 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_PSLVERRDIS_OFF); in syscounter_armv8_m_cntrl_disable_pslverr()
332 CLR_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRCLR_OFF); in syscounter_armv8_m_cntrl_clear_interrupt()
Dsystimer_armv8-m_drv.c29 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1u << (BIT_INDEX))) macro
231 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_EN_OFF); in systimer_armv8_m_disable_timer()
248 CLR_BIT(p_cnt->cntp_ctl, SYSCTIMER_ARMV8M_CNTP_CTL_IMASK_OFF); in systimer_armv8_m_enable_interrupt()
317 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_EN_OFF); in systimer_armv8_m_disable_autoinc()
334 CLR_BIT(p_cnt->cntp_aival_ctl, SYSCTIMER_ARMV8M_CNTP_AIVAL_CTL_IRQ_CLR_OFF); in systimer_armv8_m_clear_autoinc_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_s1/Libraries/
Dmt25ql_flash_lib.c27 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
186 CLR_BIT(enhanced_volatile_cfg_reg, ENHANCED_VOLATILE_CFG_REG_DSPI_POS); in set_spi_mode()
194 CLR_BIT(enhanced_volatile_cfg_reg, ENHANCED_VOLATILE_CFG_REG_QSPI_POS); in set_spi_mode()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_b1/Libraries/
Dmt25ql_flash_lib.c27 #define CLR_BIT(WORD, BIT_INDEX) ((WORD) &= ~(1U << (BIT_INDEX))) macro
186 CLR_BIT(enhanced_volatile_cfg_reg, ENHANCED_VOLATILE_CFG_REG_DSPI_POS); in set_spi_mode()
194 CLR_BIT(enhanced_volatile_cfg_reg, ENHANCED_VOLATILE_CFG_REG_QSPI_POS); in set_spi_mode()