CLK_PLLCTL_PLLSRC_HXT (reference) in projects: trusted-firmware-m-3.4.0

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Searched refs:CLK_PLLCTL_PLLSRC_HXT (Results 1 – 4 of 4) sorted by relevance

/trusted-firmware-m-3.4.0/platform/ext/target/nuvoton/m2354/bsp/Library/StdDriver/inc/
D	clk.h	280 #define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 2MHz < FIN/NR < … macro 290 #define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2UL) \| CLK_PLLCTL_NF(16UL) … 293 #define CLK_PLLCTL_64MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(3UL) \| CLK_PLLCTL_NF(16UL) … 296 #define CLK_PLLCTL_84MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2UL) \| CLK_PLLCTL_NF(14UL) … 299 #define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2UL) \| CLK_PLLCTL_NF(16UL) … 302 #define CLK_PLLCTL_128MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(3UL) \| CLK_PLLCTL_NF(16UL) … 305 #define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2UL) \| CLK_PLLCTL_NF(12UL) … 308 #define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2UL) \| CLK_PLLCTL_NF(16UL) …
/trusted-firmware-m-3.4.0/platform/ext/target/nuvoton/m2351/bsp/Library/StdDriver/inc/
D	clk.h	269 #define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 2MHz < FIN/NR < … macro 279 #define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2UL) \| CLK_PLLCTL_NF(16UL) … 282 #define CLK_PLLCTL_64MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(3UL) \| CLK_PLLCTL_NF(16UL) … 285 #define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2UL) \| CLK_PLLCTL_NF(16UL) … 288 #define CLK_PLLCTL_128MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(3UL) \| CLK_PLLCTL_NF(16UL)…
/trusted-firmware-m-3.4.0/platform/ext/target/nuvoton/m2351/bsp/Library/StdDriver/src/
D	clk.c	`345 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); in CLK_SetCoreClock() 775 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) in CLK_EnablePLL()`
/trusted-firmware-m-3.4.0/platform/ext/target/nuvoton/m2354/bsp/Library/StdDriver/src/
D	clk.c	`345 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); in CLK_SetCoreClock() 897 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) in CLK_EnablePLL()`

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