| /trusted-firmware-a-latest/plat/mediatek/mt8183/ |
| D | plat_debug.c | 17 sync_writel(CA15M_DBG_CONTROL, in circular_buffer_setup()
26 sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
29 sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1)); in circular_buffer_unlock()
32 sync_writel(MP1_CPUTOP_PWR_CON + i * 4, in circular_buffer_unlock()
36 sync_writel(DFD_INTERNAL_CTL, 0x1); in circular_buffer_unlock()
42 sync_writel(DFD_INTERNAL_CTL, 0x0); in circular_buffer_lock()
47 sync_writel(MCU_ALL_PWR_ON_CTRL, in clear_all_on_mux()
49 sync_writel(MCU_ALL_PWR_ON_CTRL, in clear_all_on_mux()
56 sync_writel(CA15M_DBG_CONTROL, in l2c_parity_check_setup()
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| /trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/dfd/ |
| D | plat_dfd.c | 22 sync_writel(DFD_INTERNAL_CTL, 0x5); in dfd_setup()
63 sync_writel(DFD_POWER_CTL, 0xF9); in dfd_setup()
77 sync_writel(DFD_CLEAN_STATUS, 0x1); in dfd_setup()
78 sync_writel(DFD_CLEAN_STATUS, 0x0); in dfd_setup()
81 sync_writel(DFD_V30_CTL, 0x1); in dfd_setup()
92 sync_writel(DFD_V35_ENALBE, 0x1); in dfd_setup()
93 sync_writel(DFD_V35_TAP_NUMBER, 0xB); in dfd_setup()
94 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); in dfd_setup()
95 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); in dfd_setup()
98 sync_writel(DFD_HW_TRIGGER_MASK, 0xC); in dfd_setup()
[all …]
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| D | plat_dfd.h | 14 #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \ macro
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| /trusted-firmware-a-latest/plat/mediatek/drivers/dfd/mt8188/ |
| D | plat_dfd.c | 25 sync_writel(DFD_INTERNAL_CTL, 0x5); in dfd_setup()
41 sync_writel(DFD_POWER_CTL, 0xF9); in dfd_setup()
42 sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); in dfd_setup()
43 sync_writel(DFD_V30_CTL, 0xD); in dfd_setup()
56 sync_writel(DFD_V35_ENABLE, 0x1); in dfd_setup()
57 sync_writel(DFD_V35_TAP_NUMBER, 0xB); in dfd_setup()
58 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); in dfd_setup()
59 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); in dfd_setup()
62 sync_writel(DFD_V35_CTL, 0x1); in dfd_setup()
70 sync_writel(DFD_HW_TRIGGER_MASK, 0xC); in dfd_setup()
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| D | plat_dfd.h | 13 #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); dsbsy(); } while (0) macro
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| /trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dfd/ |
| D | plat_dfd.c | 33 sync_writel(DFD_INTERNAL_CTL, 0x5); in dfd_setup()
80 sync_writel(DFD_POWER_CTL, 0xF9); in dfd_setup()
83 sync_writel(DFD_READ_ADDR, DFD_READ_ADDR_VAL); in dfd_setup()
86 sync_writel(DFD_V30_CTL, 0xD); in dfd_setup()
100 sync_writel(DFD_V35_ENABLE, 0x1); in dfd_setup()
101 sync_writel(DFD_V35_TAP_NUMBER, 0xB); in dfd_setup()
102 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); in dfd_setup()
103 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); in dfd_setup()
106 sync_writel(DFD_V35_CTL, 0x1); in dfd_setup()
114 sync_writel(DFD_HW_TRIGGER_MASK, 0xC); in dfd_setup()
[all …]
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| D | plat_dfd.h | 14 #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \ macro
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| /trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/dfd/ |
| D | plat_dfd.c | 24 sync_writel(DFD_INTERNAL_CTL, (BIT(0) | BIT(2))); in dfd_setup()
38 sync_writel(DFD_V30_CTL, 1); in dfd_setup()
50 sync_writel(DFD_V35_ENALBE, 1); in dfd_setup()
51 sync_writel(DFD_V35_TAP_NUMBER, DFD_V35_TAP_NUMBER_VAL); in dfd_setup()
52 sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL); in dfd_setup()
53 sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL); in dfd_setup()
56 sync_writel(DFD_HW_TRIGGER_MASK, DFD_HW_TRIGGER_MASK_VAL); in dfd_setup()
89 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
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| D | plat_dfd.h | 14 #define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \ macro
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| /trusted-firmware-a-latest/plat/mediatek/mt8183/include/ |
| D | plat_debug.h | 10 #define sync_writel(addr, val) \ macro
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| /trusted-firmware-a-latest/plat/mediatek/drivers/dfd/ |
| D | dfd.c | 33 sync_writel(MISC1_CFG_BASE + arg1, arg2); in dfd_smc_dispatcher()
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