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/trusted-firmware-a-latest/plat/imx/imx8m/
Dimx_rdc.c19 mmio_write_32(MDAn(rdc->index), rdc->setting.rdc_mda); in imx_rdc_init()
23 mmio_write_32(PDAPn(rdc->index), rdc->setting.rdc_pdap); in imx_rdc_init()
27 mmio_write_32(MRSAn(rdc->index), rdc->setting.rdc_mem_region[0]); in imx_rdc_init()
28 mmio_write_32(MREAn(rdc->index), rdc->setting.rdc_mem_region[1]); in imx_rdc_init()
29 mmio_write_32(MRCn(rdc->index), rdc->setting.rdc_mem_region[2]); in imx_rdc_init()
/trusted-firmware-a-latest/plat/imx/imx8m/include/
Dimx_rdc.h55 union rdc_setting setting; member
59 {RDC_MDA, (i), .setting.rdc_mda = (mda), }
61 {RDC_PDAP, (i), .setting.rdc_pdap = (pdap), }
65 .setting.rdc_mem_region[0] = (msa), \
66 .setting.rdc_mem_region[1] = (mea), \
67 .setting.rdc_mem_region[2] = (mrc), \
/trusted-firmware-a-latest/docs/_static/css/
Dcustom.css9 * With this setting sequences of whitespace inside
/trusted-firmware-a-latest/docs/security_advisories/
Dsecurity-advisory-tfv-7.rst40 world execution. The mitigation is enabled by setting an implementation defined
63 - Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of
66 - Cortex-A73, by setting bit 3 of ``S3_0_C15_C0_0`` (not documented in the
69 - Cortex-A75, by setting bit 35 (reserved in TRM) of ``CPUACTLR_EL1``
98 - Cortex-A76, by setting and clearing bit 16 (reserved in TRM) of
Dsecurity-advisory-tfv-3.rst67 non-executable by setting the ``SCTLR_ELx.WXN`` bit. This overrides any value
81 mapped into the secure world is non-executable by setting the ``SCR_EL3.SIF``
/trusted-firmware-a-latest/docs/design_documents/
Dcmake_framework.rst68 The related parameters shall be packed into a group (or "setting group"). The
69 setting groups shall be defined and filled with content in config files.
80 extends the built-in functionality, it can use the setting groups described in
125 First, we create a setting group called *mem_conf* and fill it with several
130 Next, we create a target called *fw1* and add the *mem_conf* setting group to
132 the parameters declared in the setting group. Then we set the target type to
Dcontext_mgmt_rework.rst183 registers easily for its own purposes and also have a fixed EL3 sysreg setting
Drss.rst61 core because setting up DMA would require more CPU cycles. The payload is
/trusted-firmware-a-latest/docs/plat/
Dimx8m.rst53 When setting NEED_BL2=1 on imx8mm. We support an alternative way of
67 When setting MEASURED_BOOT=1 on imx8mm we can let TF-A generate event logs
Drpi4.rst66 To accommodate this existing way of configuring and setting up the board,
74 setting them in ``config.txt``. If the GPU firmware finds a magic value in the
Drcar-gen3.rst211 NOTICE: AVS setting succeeded. DVFS_SetVID=0x53
214 NOTICE: BL2: QoS is default setting(rev.0.37)
Dallwinner.rst69 This setting defaults to 1. In some situations that enables too many
Drz-g2.rst184 NOTICE: BL2: QoS is default setting(rev.0.19)
/trusted-firmware-a-latest/plat/allwinner/common/
Darisc_off.S26 # - Using that mask, activate the core output clamps by setting the
/trusted-firmware-a-latest/docs/plat/arm/
Darm-build-options.rst9 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The
/trusted-firmware-a-latest/docs/components/
Dgranule-protection-tables-design.rst53 when setting up the configuration structure.
155 setting the correct register values.
Dromlib-design.rst136 :ref:`Performing an Initial Build` for more information about setting this
Dplatform-interrupt-controller-API.rst252 inserts barrier to make memory updates visible before setting interrupt pending,
Dexception-handling.rst17 The |EHF| is selected by setting the build option ``EL3_EXCEPTION_HANDLING`` to
537 interrupts. This also results in setting the routing bits in ``SCR_EL3``.
Drealm-management-extension.rst300 2. Disable the CPU Idle driver in Linux either by setting the kernel command line
Dxlat-tables-lib-v2-design.rst6 tables based on a description of the memory layout, as well as setting up system
/trusted-firmware-a-latest/drivers/nxp/ddr/nxp-ddr/
Dddrc.c181 #error Invalid setting for DDRC_NUM_CS
/trusted-firmware-a-latest/docs/
Dchange-log.md329 …- add apusys ao devapc setting ([777e3b7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/…
331 …- add devapc setting of apusys rcx ([5986ae5](https://review.trustedfirmware.org/plugins/gitiles/T…
354 …- add more dram pll setting ([8947404](https://review.trustedfirmware.org/plugins/gitiles/TF-A/tru…
837 …- setting default KEY_SIZE ([6f3ca8a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trus…
1081 …- update DDR setting ([138ddcb](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-fi…
1344 …- fix the dfiphymaster setting after dvfs ([ad0cbbf](https://review.trustedfirmware.org/plugins/gi…
1450 …- fix setting power down state ([1f79bdf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/…
1912 …- add more dram pll setting ([4234b90](https://review.trustedfirmware.org/plugins/gitiles/TF-A/tru…
1919 …- add anamix pll override setting for DSM mode ([387a1df](https://review.trustedfirmware.org/plugi…
1925 …- correct the slot ack setting for STOP mode ([724ac3e](https://review.trustedfirmware.org/plugins…
[all …]
/trusted-firmware-a-latest/docs/process/
Dcoding-guidelines.rst407 language extensions and is considered non-standard). In TF-A, setting the
/trusted-firmware-a-latest/docs/design/
Dfirmware-design.rst23 TF-A also implements a library for setting up and managing the translation
330 access to Floating Point and Advanced SIMD registers by setting the
939 supporting library for parameter retrieval, setting return values and context
1609 (other than immediately following PROGBITS sections) by setting
2753 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and

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