| /trusted-firmware-a-latest/drivers/renesas/rcar/pfc/ |
| D | pfc_init.c | 40 #define PRR_PRODUCT_ERR(reg) \ argument
43 reg); \
47 #define PRR_CUT_ERR(reg) \ argument
50 reg); \
56 uint32_t reg; in rcar_pfc_init() local
58 reg = mmio_read_32(RCAR_PRR); in rcar_pfc_init()
60 switch (reg & PRR_PRODUCT_MASK) { in rcar_pfc_init()
62 switch (reg & PRR_CUT_MASK) { in rcar_pfc_init()
84 PRR_PRODUCT_ERR(reg); in rcar_pfc_init()
89 switch (reg & PRR_PRODUCT_MASK) { in rcar_pfc_init()
[all …]
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| /trusted-firmware-a-latest/drivers/renesas/rzg/pfc/ |
| D | pfc_init.c | 31 #define PRR_PRODUCT_ERR(reg) \ argument
34 reg); \
38 #define PRR_CUT_ERR(reg) \ argument
41 reg); \
47 uint32_t reg; in rzg_pfc_init() local
49 reg = mmio_read_32(RCAR_PRR); in rzg_pfc_init()
51 switch (reg & PRR_PRODUCT_MASK) { in rzg_pfc_init()
65 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
70 switch (reg & PRR_PRODUCT_MASK) { in rzg_pfc_init()
73 PRR_PRODUCT_ERR(reg); in rzg_pfc_init()
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| /trusted-firmware-a-latest/drivers/renesas/rcar/qos/ |
| D | qos_init.c | 61 #define PRR_PRODUCT_ERR(reg) \ argument
64 "initialize not supported.\n", reg); \
68 #define PRR_CUT_ERR(reg) \ argument
71 "initialize not supported.\n", reg); \
77 uint32_t reg; in rcar_qos_init() local
90 reg = mmio_read_32(PRR); in rcar_qos_init()
92 switch (reg & PRR_PRODUCT_MASK) { in rcar_qos_init()
95 switch (reg & PRR_CUT_MASK) { in rcar_qos_init()
111 switch (reg & PRR_CUT_MASK) { in rcar_qos_init()
118 PRR_PRODUCT_ERR(reg); in rcar_qos_init()
[all …]
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| /trusted-firmware-a-latest/drivers/renesas/rzg/qos/ |
| D | qos_init.c | 45 #define PRR_PRODUCT_ERR(reg) \ argument
48 "initialize not supported.\n", reg); \
52 #define PRR_CUT_ERR(reg) \ argument
55 "initialize not supported.\n", reg); \
61 uint32_t reg; in rzg_qos_init() local
74 reg = mmio_read_32(PRR); in rzg_qos_init()
76 switch (reg & PRR_PRODUCT_MASK) { in rzg_qos_init()
79 switch (reg & PRR_CUT_MASK) { in rzg_qos_init()
92 PRR_PRODUCT_ERR(reg); in rzg_qos_init()
97 switch (reg & PRR_CUT_MASK) { in rzg_qos_init()
[all …]
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| /trusted-firmware-a-latest/drivers/cadence/nand/ |
| D | cdns_nand.c | 29 uint32_t reg = 0U; in cdns_nand_wait_idle() local
33 reg = mmio_read_32(CNF_CMDREG(CTRL_STATUS)); in cdns_nand_wait_idle()
34 } while (CNF_GET_CTRL_BUSY(reg) != 0U); in cdns_nand_wait_idle()
40 uint32_t reg = 0U; in cdns_nand_wait_thread_ready() local
44 reg = mmio_read_32(CNF_CMDREG(TRD_STATUS)); in cdns_nand_wait_thread_ready()
45 reg &= (1U << (uint32_t)thread_id); in cdns_nand_wait_thread_ready()
46 } while (reg != 0U); in cdns_nand_wait_thread_ready()
53 uint32_t reg = 0U; in cdns_nand_last_opr_status() local
56 reg = mmio_read_32(CNF_CTRLPARAM(FEATURE)); in cdns_nand_last_opr_status()
57 nthreads = CNF_GET_NTHREADS(reg); in cdns_nand_last_opr_status()
[all …]
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| /trusted-firmware-a-latest/lib/extensions/sme/ |
| D | sme.c | 19 u_register_t reg; in sme_enable() local
26 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_enable()
27 reg |= SCR_ENTP2_BIT; in sme_enable()
28 write_ctx_reg(state, CTX_SCR_EL3, reg); in sme_enable()
33 u_register_t reg; in sme_enable_per_world() local
36 reg = per_world_ctx->ctx_cptr_el3; in sme_enable_per_world()
37 reg |= ESM_BIT; in sme_enable_per_world()
38 per_world_ctx->ctx_cptr_el3 = reg; in sme_enable_per_world()
89 u_register_t reg; in sme_disable() local
96 reg = read_ctx_reg(state, CTX_SCR_EL3); in sme_disable()
[all …]
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| /trusted-firmware-a-latest/include/services/ |
| D | drtm_svc.h | 112 #define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \ argument
114 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
120 #define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \ argument
122 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \
128 #define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \ argument
130 reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \
136 #define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \ argument
138 reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \
144 #define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \ argument
146 reg = (((reg) & \
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| /trusted-firmware-a-latest/drivers/marvell/secure_dfx_access/ |
| D | armada_thermal.c | 64 uint32_t reg; in armada_ap806_thermal_read() local
66 reg = mmio_read_32(TSEN_STATUS); in armada_ap806_thermal_read()
68 reg = ((reg & TSEN_STATUS_TEMP_OUT_MASK) >> in armada_ap806_thermal_read()
76 if (reg >= THERMAL_SEN_OUTPUT_MSB) in armada_ap806_thermal_read()
77 reg -= THERMAL_SEN_OUTPUT_COMP; in armada_ap806_thermal_read()
79 *temp = ((COEF_M * ((signed int)reg)) - COEF_B); in armada_ap806_thermal_read()
90 uint32_t reg; in armada_ap806_thermal_overheat_irq_init() local
93 reg = mmio_read_32(DFX_IRQ_CAUSE_REG); in armada_ap806_thermal_overheat_irq_init()
96 reg = mmio_read_32(DFX_IRQ_MASK_REG); in armada_ap806_thermal_overheat_irq_init()
97 reg |= DFX_IRQ_TSEN_OVERHEAT_OFFSET; in armada_ap806_thermal_overheat_irq_init()
[all …]
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| /trusted-firmware-a-latest/plat/imx/common/sci/ |
| D | imx8_mu.c | 13 uint32_t reg, i; in MU_Resume() local
15 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Resume()
17 reg &= ~(MU_CR_GIEn_MASK1 | MU_CR_RIEn_MASK1 | MU_CR_TIEn_MASK1 in MU_Resume()
19 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_Resume()
28 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableRxFullInt() local
30 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); in MU_EnableRxFullInt()
31 reg |= MU_CR_RIE0_MASK1 >> index; in MU_EnableRxFullInt()
32 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableRxFullInt()
37 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableGeneralInt() local
39 reg &= ~(MU_CR_GIRn_MASK1 | MU_CR_NMI_MASK1); in MU_EnableGeneralInt()
[all …]
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| /trusted-firmware-a-latest/plat/marvell/armada/a8k/common/ |
| D | plat_thermal.c | 45 uint32_t reg, timeout = 0; in ext_tsen_probe() local
57 reg = mmio_read_32((uintptr_t)&base->ext_tsen_ctrl_lsb); in ext_tsen_probe()
58 reg &= ~THERMAL_SEN_CTRL_LSB_RST_OFFSET; /* de-assert TSEN_RESET */ in ext_tsen_probe()
59 reg |= THERMAL_SEN_CTRL_LSB_EN_MASK; /* set TSEN_EN to 1 */ in ext_tsen_probe()
60 reg |= THERMAL_SEN_CTRL_LSB_STRT_MASK; /* set TSEN_START to 1 */ in ext_tsen_probe()
61 mmio_write_32((uintptr_t)&base->ext_tsen_ctrl_lsb, reg); in ext_tsen_probe()
63 reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); in ext_tsen_probe()
64 while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && in ext_tsen_probe()
67 reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); in ext_tsen_probe()
71 if ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0) { in ext_tsen_probe()
[all …]
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| /trusted-firmware-a-latest/drivers/allwinner/axp/ |
| D | common.c | 32 int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask) in axp_clrsetbits() argument
37 ret = axp_read(reg); in axp_clrsetbits()
43 return axp_write(reg, val); in axp_clrsetbits()
79 const struct axp_regulator *reg) in setup_regulator() argument
85 if (mvolt < reg->min_volt || mvolt > reg->max_volt) in setup_regulator()
88 val = (mvolt / reg->step) - (reg->min_volt / reg->step); in setup_regulator()
89 if (val > reg->split) in setup_regulator()
90 val = ((val - reg->split) / 2) + reg->split; in setup_regulator()
92 axp_write(reg->volt_reg, val); in setup_regulator()
93 axp_setbits(reg->switch_reg, BIT(reg->switch_bit)); in setup_regulator()
[all …]
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| /trusted-firmware-a-latest/drivers/allwinner/ |
| D | sunxi_rsb.c | 39 uint32_t reg, tries = MAX_TRIES; in rsb_wait_bit() local
42 reg = mmio_read_32(SUNXI_R_RSB_BASE + offset); in rsb_wait_bit()
43 while ((reg & mask) && --tries); /* transaction in progress */ in rsb_wait_bit()
44 if (reg & mask) { in rsb_wait_bit()
54 uint32_t reg; in rsb_wait_stat() local
60 reg = mmio_read_32(SUNXI_R_RSB_BASE + RSB_STAT); in rsb_wait_stat()
61 if (reg == 0x01) in rsb_wait_stat()
64 ERROR("%s: 0x%x\n", desc, reg); in rsb_wait_stat()
65 return -reg; in rsb_wait_stat()
113 uint32_t reg; in rsb_set_bus_speed() local
[all …]
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| /trusted-firmware-a-latest/drivers/renesas/rcar/cpld/ |
| D | ulcb_cpld.c | 36 uint32_t reg; in gpio_set_value() local
38 reg = mmio_read_32(addr); in gpio_set_value()
40 reg |= (1 << gpio); in gpio_set_value()
42 reg &= ~(1 << gpio); in gpio_set_value()
43 mmio_write_32(addr, reg); in gpio_set_value()
48 uint32_t reg; in gpio_direction_output() local
50 reg = mmio_read_32(addr); in gpio_direction_output()
51 reg |= (1 << gpio); in gpio_direction_output()
52 mmio_write_32(addr, reg); in gpio_direction_output()
57 uint32_t reg; in gpio_pfc() local
[all …]
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| /trusted-firmware-a-latest/plat/hisilicon/hikey/ |
| D | hisi_pwrc.c | 42 unsigned int reg = 0; in hisi_pwrc_set_cluster_wfi() local
45 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); in hisi_pwrc_set_cluster_wfi()
46 reg |= PD_DETECT_START0; in hisi_pwrc_set_cluster_wfi()
47 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
49 reg = mmio_read_32(ACPU_SC_SNOOP_PWD); in hisi_pwrc_set_cluster_wfi()
50 reg |= PD_DETECT_START1; in hisi_pwrc_set_cluster_wfi()
51 mmio_write_32(ACPU_SC_SNOOP_PWD, reg); in hisi_pwrc_set_cluster_wfi()
72 unsigned int reg, sec_entrypoint; in hisi_pwrc_setup() local
93 reg = mmio_read_32(AO_SC_SYS_CTRL1); in hisi_pwrc_setup()
95 reg |= AO_SC_SYS_CTRL1_REMAP_SRAM_AARM | in hisi_pwrc_setup()
[all …]
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| /trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/ |
| D | gpc.c | 58 uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4; in gpc_save_imr_lpm() local
62 gpc_saved_imrs[core_id + imr_idx * 4] = mmio_read_32(reg); in gpc_save_imr_lpm()
63 mmio_write_32(reg, ~gpc_wake_irqs[imr_idx]); in gpc_save_imr_lpm()
70 uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4; in gpc_restore_imr_lpm() local
75 mmio_write_32(reg, val); in gpc_restore_imr_lpm()
110 uintptr_t reg; in imx_gpc_hwirq_mask() local
118 reg = gpc_imr_offset[0] + (hwirq / 32) * 4; in imx_gpc_hwirq_mask()
119 val = mmio_read_32(reg); in imx_gpc_hwirq_mask()
121 mmio_write_32(reg, val); in imx_gpc_hwirq_mask()
127 uintptr_t reg; in imx_gpc_hwirq_unmask() local
[all …]
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| /trusted-firmware-a-latest/drivers/renesas/common/rpc/ |
| D | rpc_driver.c | 32 uint32_t product, cut, reg, phy_strtim; in rpc_setup() local
45 reg = mmio_read_32(RPC_PHYCNT); in rpc_setup()
46 reg &= ~RPC_PHYCNT_STRTIM; in rpc_setup()
47 reg |= phy_strtim; in rpc_setup()
48 mmio_write_32(RPC_PHYCNT, reg); in rpc_setup()
49 reg |= RPC_PHYCNT_CAL; in rpc_setup()
50 mmio_write_32(RPC_PHYCNT, reg); in rpc_setup()
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| /trusted-firmware-a-latest/include/drivers/allwinner/ |
| D | axp.h | 42 int axp_read(uint8_t reg);
43 int axp_write(uint8_t reg, uint8_t val);
44 int axp_clrsetbits(uint8_t reg, uint8_t clr_mask, uint8_t set_mask);
45 #define axp_clrbits(reg, clr_mask) axp_clrsetbits(reg, clr_mask, 0) argument
46 #define axp_setbits(reg, set_mask) axp_clrsetbits(reg, 0, set_mask) argument
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| /trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/timer/ |
| D | mt_timer.c | 15 unsigned int reg; in enable_systimer_compensation() local
17 reg = mmio_read_32(CNTCR_REG); in enable_systimer_compensation()
18 reg &= ~COMP_15_EN; in enable_systimer_compensation()
19 reg |= COMP_20_EN; in enable_systimer_compensation()
20 mmio_write_32(CNTCR_REG, reg); in enable_systimer_compensation()
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| /trusted-firmware-a-latest/drivers/arm/css/sds/ |
| D | sds_private.h | 67 uint32_t reg[2]; member
71 ((((struct_header_t *)(_header))->reg[0]) & SDS_HEADER_ID_MASK)
73 (((((struct_header_t *)(_header))->reg[0]) >> SDS_HEADER_MINOR_VERSION_SHIFT)\
76 (((((struct_header_t *)(_header))->reg[1]) >> SDS_HEADER_STRUCT_SIZE_SHIFT)\
79 ((((struct_header_t *)(_header))->reg[1]) & SDS_HEADER_VALID_MASK)
85 uint32_t reg[2]; member
89 (((((region_desc_t *)(region))->reg[0]) & SDS_REGION_SIGNATURE_MASK) == SDS_REGION_SIGNATURE)
91 (((((region_desc_t *)(region))->reg[0]) >> SDS_REGION_STRUCT_COUNT_SHIFT)\
94 (((((region_desc_t *)(region))->reg[0]) >> SDS_REGION_SCH_MINOR_SHIFT)\
96 #define GET_SDS_REGION_SIZE(region) ((((region_desc_t *)(region))->reg[1]))
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| /trusted-firmware-a-latest/drivers/marvell/mochi/ |
| D | apn806_setup.c | 129 uint32_t reg; in setup_smmu() local
132 reg = mmio_read_32(SMMU_sACR); in setup_smmu()
133 reg |= SMMU_sACR_PG_64K; in setup_smmu()
134 mmio_write_32(SMMU_sACR, reg); in setup_smmu()
139 uint32_t reg; in init_aurora2() local
142 reg = mmio_read_32(CCU_GSPMU_CR); in init_aurora2()
143 reg |= GSPMU_CPU_CONTROL; in init_aurora2()
144 mmio_write_32(CCU_GSPMU_CR, reg); in init_aurora2()
154 reg = mmio_read_32(CCU_HTC_CR); in init_aurora2()
155 reg |= (0x1 << CCU_SET_POC_OFFSET); in init_aurora2()
[all …]
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| /trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0_mcbin/board/ |
| D | marvell_plat_config.c | 33 uint32_t reg; in marvell_gpio_config() local
35 reg = mmio_read_32(MPP_CONTROL_REGISTER); in marvell_gpio_config()
36 reg |= MPP_CONTROL_MPP_SEL_52_MASK; in marvell_gpio_config()
37 mmio_write_32(MPP_CONTROL_REGISTER, reg); in marvell_gpio_config()
39 reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER); in marvell_gpio_config()
40 reg |= GPIO52_MASK; in marvell_gpio_config()
41 mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg); in marvell_gpio_config()
43 reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER); in marvell_gpio_config()
44 reg &= ~GPIO52_MASK; in marvell_gpio_config()
45 mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg); in marvell_gpio_config()
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| /trusted-firmware-a-latest/fdts/ |
| D | stm32mp131.dtsi | 21 reg = <0>;
65 reg = <0xa0021000 0x1000>,
83 reg = <0x4000f000 0x400>;
92 reg = <0x40010000 0x400>;
101 reg = <0x40011000 0x400>;
110 reg = <0x40018000 0x400>;
119 reg = <0x40019000 0x400>;
128 reg = <0x44003000 0x400>;
137 reg = <0x49000000 0x40000>;
153 reg = <0x4c000000 0x400>;
[all …]
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| D | stm32mp151.dtsi | 21 reg = <0>;
36 reg = <0xa0021000 0x1000>,
83 reg = <0x40006000 0x400>;
91 reg = <0x4000e000 0x400>;
100 reg = <0x4000f000 0x400>;
109 reg = <0x40010000 0x400>;
119 reg = <0x40011000 0x400>;
128 reg = <0x40013000 0x400>;
143 reg = <0x40018000 0x400>;
152 reg = <0x40019000 0x400>;
[all …]
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| /trusted-firmware-a-latest/plat/marvell/armada/a8k/a80x0_puzzle/board/ |
| D | marvell_plat_config.c | 33 uint32_t reg; in marvell_gpio_config() local
35 reg = mmio_read_32(MPP_CONTROL_REGISTER); in marvell_gpio_config()
36 reg |= MPP_CONTROL_MPP_SEL_52_MASK; in marvell_gpio_config()
37 mmio_write_32(MPP_CONTROL_REGISTER, reg); in marvell_gpio_config()
39 reg = mmio_read_32(GPIO_DATA_OUT1_REGISTER); in marvell_gpio_config()
40 reg |= GPIO52_MASK; in marvell_gpio_config()
41 mmio_write_32(GPIO_DATA_OUT1_REGISTER, reg); in marvell_gpio_config()
43 reg = mmio_read_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER); in marvell_gpio_config()
44 reg &= ~GPIO52_MASK; in marvell_gpio_config()
45 mmio_write_32(GPIO_DATA_OUT_EN_CTRL1_REGISTER, reg); in marvell_gpio_config()
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| /trusted-firmware-a-latest/drivers/renesas/rcar/pfc/H3/ |
| D | pfc_init_h3_v2.c | 579 uint32_t reg; in pfc_init_h3_v2() local
912 reg = mmio_read_32(PFC_DRVCTRL0); in pfc_init_h3_v2()
913 reg = ((reg & DRVCTRL0_MASK) | DRVCTRL0_QSPI0_SPCLK(3) in pfc_init_h3_v2()
921 pfc_reg_write(PFC_DRVCTRL0, reg); in pfc_init_h3_v2()
922 reg = mmio_read_32(PFC_DRVCTRL1); in pfc_init_h3_v2()
923 reg = ((reg & DRVCTRL1_MASK) | DRVCTRL1_QSPI1_MISO_IO1(3) in pfc_init_h3_v2()
931 pfc_reg_write(PFC_DRVCTRL1, reg); in pfc_init_h3_v2()
932 reg = mmio_read_32(PFC_DRVCTRL2); in pfc_init_h3_v2()
933 reg = ((reg & DRVCTRL2_MASK) | DRVCTRL2_AVB_RXC(7) in pfc_init_h3_v2()
941 pfc_reg_write(PFC_DRVCTRL2, reg); in pfc_init_h3_v2()
[all …]
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