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Searched refs:rd_to_wr (Results 1 – 3 of 3) sorted by relevance

/trusted-firmware-a-latest/plat/intel/soc/agilex/soc/
Dagilex_memory_controller.c177 burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio, in configure_ddr_sched_ctrl_regs() local
216 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()
260 / 2) - rd_to_wr + t_rp + t_rcd; in configure_ddr_sched_ctrl_regs()
265 rd_to_wr << DDRTIMING_RDTOWR_OFST | in configure_ddr_sched_ctrl_regs()
/trusted-firmware-a-latest/plat/intel/soc/agilex5/soc/
Dagilex5_memory_controller.c178 burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio, in configure_ddr_sched_ctrl_regs() local
217 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()
261 / 2) - rd_to_wr + t_rp + t_rcd; in configure_ddr_sched_ctrl_regs()
266 rd_to_wr << DDRTIMING_RDTOWR_OFST | in configure_ddr_sched_ctrl_regs()
/trusted-firmware-a-latest/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c206 burst_len_sched_clk, act_to_act, rd_to_wr, wr_to_rd, bw_ratio, in configure_ddr_sched_ctrl_regs() local
245 rd_to_wr = RD_TO_WR(data); in configure_ddr_sched_ctrl_regs()
289 / 2) - rd_to_wr + t_rp + t_rcd; in configure_ddr_sched_ctrl_regs()
294 rd_to_wr << DDRTIMING_RDTOWR_OFST | in configure_ddr_sched_ctrl_regs()