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/trusted-firmware-a-latest/bl31/
Dehf.c54 static unsigned int pri_to_idx(unsigned int priority) in pri_to_idx() argument
58 idx = EHF_PRI_TO_IDX(priority, exception_data.pri_bits); in pri_to_idx()
99 void ehf_activate_priority(unsigned int priority) in ehf_activate_priority() argument
111 if (priority >= run_pri) { in ehf_activate_priority()
113 run_pri, priority); in ehf_activate_priority()
123 idx = pri_to_idx(priority); in ehf_activate_priority()
127 priority, IDX_TO_PRI(cur_pri_idx)); in ehf_activate_priority()
139 old_mask = plat_ic_set_priority_mask(priority); in ehf_activate_priority()
140 if (priority >= old_mask) { in ehf_activate_priority()
142 priority, old_mask); in ehf_activate_priority()
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/trusted-firmware-a-latest/docs/components/
Dexception-handling.rst90 is based on a priority scheme. This priority scheme is closely tied to how the
94 The platform is required to `partition`__ the Secure priority space into
95 priority levels as applicable for the Secure software stack. It then assigns the
96 dispatchers to one or more priority levels. The dispatchers then register
97 handlers for the priority levels at runtime. A dispatcher can register handlers
98 for more than one priority level.
100 .. __: `Partitioning priority levels`_
107 A priority level is *active* when a handler at that priority level is currently
110 priority of the acknowledged interrupt is used to match its registered handler.
111 The priority level is likewise implicitly deactivated when the interrupt
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Dplatform-interrupt-controller-API.rst17 This API should return the priority of the interrupt the PE is currently
22 is read to determine the priority of the interrupt.
108 Function: void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority); [optional]
117 This API should set the priority of the interrupt specified by first parameter
118 ``id`` to the value set by the second parameter ``priority``.
121 writes to GIC *Priority Register* set interrupt priority.
279 This API should set the priority mask (first parameter) in the interrupt
280 controller such that only interrupts of higher priority than the supplied one
281 may be signalled to the PE. The API should return the current priority value
299 performed when priority mask is restored to it's older value. This API returns
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Dsdei.rst84 - Event priority: ``SDEI_MAPF_CRITICAL`` or ``SDEI_MAPF_NORMAL``, as described
136 - ``SDEI_MAPF_NORMAL``: Marks the event as having *Normal* priority. This is
137 the default priority.
139 - ``SDEI_MAPF_CRITICAL``: Marks the event as having *Critical* priority.
181 - Install priority descriptors for Normal and Critical SDEI interrupts.
268 - The priority of the event (either Critical or Normal, as configured by the
269 platform at build-time) shouldn't cause priority inversion. This means:
271 - If it's of Normal priority, neither Normal nor Critical priority dispatch
274 - If it's of a Critical priority, no Critical priority dispatch must be
285 priority so as not to cause priority level inversion within Exception
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Dras.rst327 means that the platform must partition a :ref:`priority level <Partitioning
328 priority levels>` for handling RAS exceptions. The platform must then define
329 the macro ``PLAT_RAS_PRI`` to the priority level used for RAS exceptions.
330 Platforms would typically want to allocate the highest secure priority for
335 documentation. I.e., for interrupts, the priority management is implicit; but
Dsecure-partition-manager.rst664 (i.e. lowest booting priority).
1295 implemented by SPMC to perform priority drop and interrupt deactivation (SPMC
1296 configures EOImode = 0, i.e. priority drop and deactivation are done together).
/trusted-firmware-a-latest/include/bl31/
Dehf.h28 #define EHF_PRI_DESC(plat_bits, priority) \ argument
29 [EHF_PRI_TO_IDX(priority, plat_bits)] = { \
84 void ehf_activate_priority(unsigned int priority);
85 void ehf_deactivate_priority(unsigned int priority);
/trusted-firmware-a-latest/plat/common/
Dplat_gicv2.c191 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) in plat_ic_set_interrupt_priority() argument
193 gicv2_set_interrupt_priority(id, priority); in plat_ic_set_interrupt_priority()
Dplat_gicv3.c233 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority) in plat_ic_set_interrupt_priority() argument
235 gicv3_set_interrupt_priority(id, plat_my_core_pos(), priority); in plat_ic_set_interrupt_priority()
/trusted-firmware-a-latest/services/std_svc/sdei/
Dsdei_private.h30 # error Platform must define SDEI critical priority value
34 # error Platform must define SDEI normal priority value
/trusted-firmware-a-latest/lib/extensions/ras/
Dras_common.c19 # error Platform must define RAS priority value
/trusted-firmware-a-latest/include/drivers/arm/
Dgicv2.h190 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority);
Dgicv3.h581 unsigned int priority);
/trusted-firmware-a-latest/drivers/arm/gic/v2/
Dgicv2_main.c380 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority) in gicv2_set_interrupt_priority() argument
386 gicd_set_ipriorityr(driver_data->gicd_base, id, priority); in gicv2_set_interrupt_priority()
/trusted-firmware-a-latest/docs/security_advisories/
Dsecurity-advisory-tfv-11.rst31 priority SDEI event. The interrupt can be a private peripheral interrupt
/trusted-firmware-a-latest/include/plat/common/
Dplatform.h130 void plat_ic_set_interrupt_priority(unsigned int id, unsigned int priority);
/trusted-firmware-a-latest/drivers/arm/gic/v3/
Dgicv3_main.c1034 unsigned int priority) in gicv3_set_interrupt_priority() argument
1048 gicr_set_ipriorityr(gicr_base, id, priority); in gicv3_set_interrupt_priority()
1052 gicd_set_ipriorityr(gicd_base, id, priority); in gicv3_set_interrupt_priority()
/trusted-firmware-a-latest/fdts/
Dfvp-base-psci-common.dtsi83 * 2. Interrupt priority
/trusted-firmware-a-latest/docs/design/
Dinterrupt-framework-design.rst256 enable the secure interrupts, ensure that their priority is always higher than
731 another higher priority Secure-EL1 interrupt or a EL3 interrupt. The SPD
824 ``yielding`` SMC processing or by a higher priority EL3 interrupt during
943 that means that a higher priority interrupt has preempted it. Invoke
Dfirmware-design.rst1337 (priority, group, configuration). Each element of the array shall be populated
1342 - 8-bit interrupt priority,
/trusted-firmware-a-latest/docs/
Dporting-guide.rst2172 - Configure the priority mask register to allow interrupts of all priorities
2380 This macro must be defined to the EL3 exception priority level associated with
2382 (therefore of lower priority) than ``PLAT_SDEI_CRITICAL_PRI``.
2387 This macro must be defined to the EL3 exception priority level associated with
2389 (therefore of higher priority) than ``PLAT_SDEI_NORMAL_PRI``.
2392 priorities. Among the |SDEI| exceptions, Critical |SDEI| priority must
2393 be higher than Normal |SDEI| priority.
3030 This API returns the type of the highest priority pending interrupt at the
3063 This API returns the id of the highest priority pending interrupt at the
3113 priority pending interrupt from pending to active in the interrupt controller.
Dchange-log.md721 …- add RAS_FFH_SUPPORT check for RAS EHF priority ([1c01284](https://review.trustedfirmware.org/plu…
1271 …- correct ehf priority for SPM_MM ([fb2fd55](https://review.trustedfirmware.org/plugins/gitiles/TF…
3007 …- implement workaround to forward highest priority interrupt ([e1b15b0](https://review.trustedfirm…
7154 - gic: Remove 'lowest priority' constants
7157 should define these if required, or instead determine the correct priority
7219 non-secure world, and may have higher priority than secure world interrupts.
/trusted-firmware-a-latest/docs/getting_started/
Dbuild-options.rst723 ``EL3_PAYLOAD_BASE``. If both are defined, ``EL3_PAYLOAD_BASE`` has priority