| /trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/gpio/ |
| D | mtgpio.c | 36 uint32_t pos, bit; in mt_set_gpio_dir_chip() local
41 pos = pin / MAX_GPIO_REG_BITS; in mt_set_gpio_dir_chip()
45 mmio_write_32(DIR_BASE + 0x10 * pos + CLR, 1U << bit); in mt_set_gpio_dir_chip()
47 mmio_write_32(DIR_BASE + 0x10 * pos + SET, 1U << bit); in mt_set_gpio_dir_chip()
52 uint32_t pos, bit; in mt_get_gpio_dir_chip() local
57 pos = pin / MAX_GPIO_REG_BITS; in mt_get_gpio_dir_chip()
60 reg = mmio_read_32(DIR_BASE + 0x10 * pos); in mt_get_gpio_dir_chip()
66 uint32_t pos, bit; in mt_set_gpio_out_chip() local
71 pos = pin / MAX_GPIO_REG_BITS; in mt_set_gpio_out_chip()
75 mmio_write_32(DOUT_BASE + 0x10 * pos + CLR, 1U << bit); in mt_set_gpio_out_chip()
[all …]
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| /trusted-firmware-a-latest/plat/mediatek/drivers/gpio/ |
| D | mtgpio_common.c | 31 uint32_t pos, bit; in mt_set_gpio_dir_chip() local
36 pos = pin / MAX_GPIO_REG_BITS; in mt_set_gpio_dir_chip()
40 mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit); in mt_set_gpio_dir_chip()
42 mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit); in mt_set_gpio_dir_chip()
48 uint32_t pos, bit; in mt_get_gpio_dir_chip() local
53 pos = pin / MAX_GPIO_REG_BITS; in mt_get_gpio_dir_chip()
56 reg = mmio_read_32(DIR_BASE + 0x10U * pos); in mt_get_gpio_dir_chip()
62 uint32_t pos, bit; in mt_set_gpio_out_chip() local
67 pos = pin / MAX_GPIO_REG_BITS; in mt_set_gpio_out_chip()
71 mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit); in mt_set_gpio_out_chip()
[all …]
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| /trusted-firmware-a-latest/plat/arm/board/arm_fpga/ |
| D | fpga_pm.c | 44 int pos = plat_core_pos_by_mpidr(mpidr); in fpga_pwr_domain_on() local
47 if (pos < 0) { in fpga_pwr_domain_on()
54 hold_base[pos] = PLAT_FPGA_HOLD_STATE_GO; in fpga_pwr_domain_on()
55 flush_dcache_range((uintptr_t)&hold_base[pos], sizeof(uint64_t)); in fpga_pwr_domain_on()
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| /trusted-firmware-a-latest/drivers/io/ |
| D | io_mtd.c | 21 unsigned long long pos; /* Offset in bytes */ member
123 ret = ops->seek(cur->base, cur->pos, extra_offset); in mtd_add_extra_offset()
146 cur->pos = 0U; in mtd_open()
177 cur->pos = offset; in mtd_seek()
180 if (((cur->base + cur->pos + (unsigned long long)offset) >= in mtd_seek()
182 ((cur->base + cur->pos + (unsigned long long)offset) < in mtd_seek()
183 cur->base + cur->pos)) { in mtd_seek()
187 cur->pos += (unsigned long long)offset; in mtd_seek()
218 cur->base + cur->pos, buffer, length); in mtd_read()
219 if ((cur->base + cur->pos + length) > cur->dev_spec->device_size) { in mtd_read()
[all …]
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| /trusted-firmware-a-latest/drivers/rambus/ |
| D | trng_ip_76.c | 216 static uint8_t pos; in eip76_rng_get_random() local
226 if (pos >= EIP76_RNG_OUTPUT_SIZE) { in eip76_rng_get_random()
227 pos = 0; in eip76_rng_get_random()
230 if (pos != 0U) { in eip76_rng_get_random()
237 if (pos || ret > 0) { in eip76_rng_get_random()
238 data[i] = rand[pos++]; in eip76_rng_get_random()
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| /trusted-firmware-a-latest/plat/rpi/common/ |
| D | rpi3_pm.c | 133 unsigned int pos = plat_core_pos_by_mpidr(mpidr); in rpi3_pwr_domain_on() local
136 assert(pos < PLATFORM_CORE_COUNT); in rpi3_pwr_domain_on()
138 hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE; in rpi3_pwr_domain_on()
172 unsigned int pos = plat_my_core_pos(); in rpi3_pwr_down_wfi() local
174 if (pos == 0) { in rpi3_pwr_down_wfi()
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| /trusted-firmware-a-latest/plat/arm/board/a5ds/ |
| D | a5ds_pm.c | 18 unsigned int pos = plat_core_pos_by_mpidr(mpidr); in a5ds_pwr_domain_on() local
21 hold_base[pos] = A5DS_HOLD_STATE_GO; in a5ds_pwr_domain_on()
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| /trusted-firmware-a-latest/include/lib/ |
| D | bakery_lock.h | 26 static inline unsigned int bakery_get_priority(unsigned int t, unsigned int pos) in bakery_get_priority() argument
28 return (t << 8) | pos; in bakery_get_priority()
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| /trusted-firmware-a-latest/plat/nuvoton/npcm845x/ |
| D | npcm845x_psci.c | 140 unsigned int pos = (unsigned int)plat_core_pos_by_mpidr(mpidr); in npcm845x_pwr_domain_on() local
143 assert(pos < PLATFORM_CORE_COUNT); in npcm845x_pwr_domain_on()
145 hold_base += pos * PLAT_NPCM_TM_HOLD_ENTRY_SIZE; in npcm845x_pwr_domain_on()
336 unsigned int pos = plat_my_core_pos(); in npcm845x_pwr_down_wfi() local
338 if (pos == 0) { in npcm845x_pwr_down_wfi()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t186/ |
| D | plat_setup.c | 291 u_register_t cluster_id, cpu_id, pos; in plat_core_pos_by_mpidr() local
308 pos = cpu_id + (cluster_id << 2U); in plat_core_pos_by_mpidr()
311 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) { in plat_core_pos_by_mpidr()
314 ret = (int32_t)pos; in plat_core_pos_by_mpidr()
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| D | plat_psci_handlers.c | 180 uint32_t num_cpus = ncpu, pos = 0; in tegra_last_cpu_in_cluster() local
183 target = states[pos]; in tegra_last_cpu_in_cluster()
188 pos++; in tegra_last_cpu_in_cluster()
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| /trusted-firmware-a-latest/plat/qemu/qemu_sbsa/ |
| D | sbsa_pm.c | 135 int pos = plat_core_pos_by_mpidr(mpidr); in qemu_pwr_domain_on() local
138 if (pos < 0) { in qemu_pwr_domain_on()
142 hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; in qemu_pwr_domain_on()
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| /trusted-firmware-a-latest/drivers/nxp/ddr/nxp-ddr/ |
| D | ddrc.c | 60 uint32_t pos = 0U; in bist() local
78 pos = 37U; in bist()
87 pos = i; in bist()
91 pos, highest); in bist()
92 map_save = ddr_in32(&ddr->dec[pos >> 2]); in bist()
93 shift = (3U - pos % 4U) * 8U + 2U; in bist()
95 pos >> 2U, shift, map_save); in bist()
98 ddr_out32(&ddr->dec[pos >> 2U], temp32); in bist()
133 ddr_out32(&ddr->dec[pos >> 2], map_save); in bist()
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| /trusted-firmware-a-latest/drivers/st/fmc/ |
| D | stm32_fmc2_nand.c | 441 uint16_t pos[8]; in stm32_fmc2_bch_correct() local
471 pos[0] = bchdsr1 & FMC2_BCHDSR1_EBP1_MASK; in stm32_fmc2_bch_correct()
472 pos[1] = (bchdsr1 & FMC2_BCHDSR1_EBP2_MASK) >> FMC2_BCHDSR1_EBP2_SHIFT; in stm32_fmc2_bch_correct()
473 pos[2] = bchdsr2 & FMC2_BCHDSR2_EBP3_MASK; in stm32_fmc2_bch_correct()
474 pos[3] = (bchdsr2 & FMC2_BCHDSR2_EBP4_MASK) >> FMC2_BCHDSR2_EBP4_SHIFT; in stm32_fmc2_bch_correct()
475 pos[4] = bchdsr3 & FMC2_BCHDSR3_EBP5_MASK; in stm32_fmc2_bch_correct()
476 pos[5] = (bchdsr3 & FMC2_BCHDSR3_EBP6_MASK) >> FMC2_BCHDSR3_EBP6_SHIFT; in stm32_fmc2_bch_correct()
477 pos[6] = bchdsr4 & FMC2_BCHDSR4_EBP7_MASK; in stm32_fmc2_bch_correct()
478 pos[7] = (bchdsr4 & FMC2_BCHDSR4_EBP8_MASK) >> FMC2_BCHDSR4_EBP8_SHIFT; in stm32_fmc2_bch_correct()
482 if (pos[i] < (eccsize * 8U)) { in stm32_fmc2_bch_correct()
[all …]
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| /trusted-firmware-a-latest/plat/qemu/common/ |
| D | qemu_pm.c | 143 unsigned pos = plat_core_pos_by_mpidr(mpidr); in qemu_pwr_domain_on() local
146 hold_base[pos] = PLAT_QEMU_HOLD_STATE_GO; in qemu_pwr_domain_on()
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| /trusted-firmware-a-latest/include/plat/common/ |
| D | platform.h | 88 int pos = plat_core_pos_by_mpidr(mpidr); in is_valid_mpidr() local
90 if ((pos < 0) || ((unsigned int)pos >= PLATFORM_CORE_COUNT)) { in is_valid_mpidr()
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| /trusted-firmware-a-latest/plat/nvidia/tegra/soc/t194/ |
| D | plat_psci_handlers.c | 189 uint32_t num_cpus = ncpu, pos = 0; in tegra_last_on_cpu_in_cluster() local
192 target = states[pos]; in tegra_last_on_cpu_in_cluster()
197 pos++; in tegra_last_on_cpu_in_cluster()
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| /trusted-firmware-a-latest/lib/zlib/ |
| D | zlib.h | 1840 z_off64_t pos; member
1846 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
1849 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
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| /trusted-firmware-a-latest/drivers/renesas/common/ddr/ddr_b/ |
| D | boot_init_dram.c | 234 static inline uint32_t vch_nxt(uint32_t pos);
331 static inline uint32_t vch_nxt(uint32_t pos) in vch_nxt() argument
335 for (posn = pos; posn < DRAM_CH_CNT; posn++) { in vch_nxt()
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