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/trusted-firmware-a-latest/plat/xilinx/common/pm_service/
Dpm_api_sys.c114 uint32_t payload[PAYLOAD_ARG_CNT] = {0}; in pm_handle_eemi_call() local
124 PM_PACK_PAYLOAD6(payload, module_id, flag, x0, x1, x2, x3, x4, x5); in pm_handle_eemi_call()
125 return pm_ipi_send_sync(primary_proc, payload, (uint32_t *)result, PAYLOAD_ARG_CNT); in pm_handle_eemi_call()
148 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_self_suspend() local
164 PM_PACK_PAYLOAD6(payload, LIBPM_MODULE_ID, flag, PM_SELF_SUSPEND, in pm_self_suspend()
167 return pm_ipi_send_sync(proc, payload, NULL, 0); in pm_self_suspend()
185 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_abort_suspend() local
194 PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_ABORT_SUSPEND, in pm_abort_suspend()
196 return pm_ipi_send_sync(primary_proc, payload, NULL, 0); in pm_abort_suspend()
216 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_req_suspend() local
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Dpm_ipi.c82 uint32_t payload[PAYLOAD_ARG_CNT], in pm_ipi_send_common()
90 payload[PAYLOAD_CRC_POS] = calculate_crc(payload, IPI_W0_TO_W6_SIZE); in pm_ipi_send_common()
95 mmio_write_32(buffer_base + offset, payload[i]); in pm_ipi_send_common()
118 uint32_t payload[PAYLOAD_ARG_CNT]) in pm_ipi_send_non_blocking()
124 ret = pm_ipi_send_common(proc, payload, IPI_NON_BLOCKING); in pm_ipi_send_non_blocking()
142 uint32_t payload[PAYLOAD_ARG_CNT]) in pm_ipi_send()
148 ret = pm_ipi_send_common(proc, payload, IPI_BLOCKING); in pm_ipi_send()
281 uint32_t payload[PAYLOAD_ARG_CNT], in pm_ipi_send_sync()
288 ret = pm_ipi_send_common(proc, payload, IPI_BLOCKING); in pm_ipi_send_sync()
325 uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t bufsize) in calculate_crc()
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Dpm_svc_main.c54 uint32_t payload[4] = {0}; in ipi_fiq_handler() local
61 ret = pm_get_callbackdata(payload, ARRAY_SIZE(payload), 0, 0); in ipi_fiq_handler()
63 payload[0] = ret; in ipi_fiq_handler()
66 switch (payload[0]) { in ipi_fiq_handler()
/trusted-firmware-a-latest/plat/xilinx/zynqmp/pm_service/
Dzynqmp_pm_api_sys.c271 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_self_suspend() local
281 PM_PACK_PAYLOAD6(payload, PM_SELF_SUSPEND, proc->node_id, latency, in pm_self_suspend()
283 return pm_ipi_send_sync(proc, payload, NULL, 0); in pm_self_suspend()
301 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_req_suspend() local
304 PM_PACK_PAYLOAD5(payload, PM_REQ_SUSPEND, target, ack, latency, state); in pm_req_suspend()
306 return pm_ipi_send_sync(primary_proc, payload, NULL, 0); in pm_req_suspend()
308 return pm_ipi_send(primary_proc, payload); in pm_req_suspend()
334 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_req_wakeup() local
343 PM_PACK_PAYLOAD5(payload, PM_REQ_WAKEUP, target, encoded_address, in pm_req_wakeup()
347 return pm_ipi_send_sync(primary_proc, payload, NULL, 0); in pm_req_wakeup()
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Dzynqmp_pm_svc_main.c45 uint32_t payload[PAYLOAD_ARG_CNT]; member
285 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_smc_handler() local
546 PM_PACK_PAYLOAD5(payload, smc_fid & FUNCID_NUM_MASK, in pm_smc_handler()
548 ret = pm_ipi_send_sync(primary_proc, payload, ret_payload, 3U); in pm_smc_handler()
566 PM_PACK_PAYLOAD6(payload, api_id, pm_arg[0], pm_arg[1], in pm_smc_handler()
568 ret = pm_ipi_send_sync(primary_proc, payload, result, in pm_smc_handler()
Dpm_api_ioctl.c608 uint32_t payload[PAYLOAD_ARG_CNT]; in pm_api_ioctl() local
667 PM_PACK_PAYLOAD5(payload, PM_IOCTL, nid, ioctl_id, arg1, arg2); in pm_api_ioctl()
669 ret = pm_ipi_send_sync(primary_proc, payload, value, 1); in pm_api_ioctl()
/trusted-firmware-a-latest/plat/intel/soc/common/sip/
Dsocfpga_sip_fcs.c137 fcs_rng_payload payload = { in intel_fcs_random_number_gen_ext() local
144 payload_size = sizeof(payload) / MBOX_WORD_BYTE; in intel_fcs_random_number_gen_ext()
147 (uint32_t *) &payload, payload_size, in intel_fcs_random_number_gen_ext()
226 fcs_cntr_set_preauth_payload payload = { in intel_fcs_cntr_set_preauth() local
231 payload_size = sizeof(payload) / MBOX_WORD_BYTE; in intel_fcs_cntr_set_preauth()
233 (uint32_t *) &payload, payload_size, in intel_fcs_cntr_set_preauth()
250 fcs_encrypt_payload payload = { in intel_fcs_encryption() local
256 load_size = sizeof(payload) / MBOX_WORD_BYTE; in intel_fcs_encryption()
268 (uint32_t *) &payload, load_size, in intel_fcs_encryption()
288 fcs_decrypt_payload payload = { in intel_fcs_decryption() local
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/trusted-firmware-a-latest/plat/xilinx/common/include/
Dpm_ipi.h23 uint32_t payload[PAYLOAD_ARG_CNT]);
25 uint32_t payload[PAYLOAD_ARG_CNT]);
27 uint32_t payload[PAYLOAD_ARG_CNT],
34 uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize);
/trusted-firmware-a-latest/plat/intel/soc/common/drivers/ddr/
Dddr.c157 uint32_t payload[IOSSM_CMD_MAX_WORD_SIZE] = {0U}; in ddr_iossm_mailbox_cmd() local
166 OPCODE_GET_MEM_INTF_INFO, payload, i); in ddr_iossm_mailbox_cmd()
171 OPCODE_GET_MEM_TECHNOLOGY, payload, i); in ddr_iossm_mailbox_cmd()
176 OPCODE_GET_MEM_WIDTH_INFO, payload, i); in ddr_iossm_mailbox_cmd()
182 payload, i); in ddr_iossm_mailbox_cmd()
189 payload, i); in ddr_iossm_mailbox_cmd()
209 payload, i); in ddr_iossm_mailbox_cmd()
229 payload, i); in ddr_iossm_mailbox_cmd()
235 payload, i); in ddr_iossm_mailbox_cmd()
241 payload, i); in ddr_iossm_mailbox_cmd()
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/trusted-firmware-a-latest/drivers/arm/css/scmi/
Dscmi_pwr_dmn_proto.c41 SCMI_PAYLOAD_ARG3(mbx_mem->payload, pwr_state_set_msg_flag, in scmi_pwr_state_set()
47 SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret); in scmi_pwr_state_set()
76 SCMI_PAYLOAD_ARG1(mbx_mem->payload, domain_id); in scmi_pwr_state_get()
81 SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *scmi_pwr_state); in scmi_pwr_state_get()
Dscmi_sys_pwr_proto.c34 SCMI_PAYLOAD_ARG2(mbx_mem->payload, flags, system_state); in scmi_sys_pwr_state_set()
39 SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret); in scmi_sys_pwr_state_set()
71 SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *system_state); in scmi_sys_pwr_state_get()
Dscmi_ap_core_proto.c34 SCMI_PAYLOAD_ARG3(mbx_mem->payload, reset_addr & 0xffffffff, in scmi_ap_core_set_reset_addr()
40 SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret); in scmi_ap_core_set_reset_addr()
73 SCMI_PAYLOAD_RET_VAL4(mbx_mem->payload, ret, lo_addr, hi_addr, *attr); in scmi_ap_core_get_reset_addr()
Dscmi_common.c110 SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *version); in scmi_proto_version()
139 SCMI_PAYLOAD_ARG1(mbx_mem->payload, command_id); in scmi_proto_msg_attr()
144 SCMI_PAYLOAD_RET_VAL2(mbx_mem->payload, ret, *attr); in scmi_proto_msg_attr()
/trusted-firmware-a-latest/drivers/scmi-msg/
Dentry.c47 void scmi_write_response(struct scmi_msg *msg, void *payload, size_t size) in scmi_write_response() argument
54 assert(payload && size >= sizeof(int32_t) && size <= msg->out_size && in scmi_write_response()
57 memcpy(msg->out, payload, size); in scmi_write_response()
Dsmt.c40 uint32_t payload[]; member
150 msg.out = (char *)smt_hdr->payload; in scmi_proccess_smt()
156 memcpy(msg.in, smt_hdr->payload, in_payload_size); in scmi_proccess_smt()
Dcommon.h135 void scmi_write_response(struct scmi_msg *msg, void *payload, size_t size);
/trusted-firmware-a-latest/docs/design/
Dalt-boot-flows.rst17 boot flow, where a modified BL2 boots an EL3 payload, instead of loading the
25 When booting an EL3 payload on Arm standard platforms, the configuration of the
28 DRAM to the EL3 payload.
42 Booting an EL3 payload
45 The EL3 payload image is a standalone image and is not part of the FIP. It is
48 - The EL3 payload may reside in non-volatile memory (NVM) and execute in
52 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
57 moment for a debugger to take control of the target and load the payload (for
62 use any other platform-specific mechanism to load the EL3 payload, though.
/trusted-firmware-a-latest/drivers/arm/css/scmi/vendor/
Dscmi_sq.c53 SCMI_PAYLOAD_RET_VAL1(mbx_mem->payload, ret); in scmi_get_draminfo()
55 memcpy(&response, (void *)mbx_mem->payload, sizeof(response)); in scmi_get_draminfo()
/trusted-firmware-a-latest/bl32/optee/
Doptee.mk15 $(info Trusted Firmware-A built for OP-TEE payload support)
/trusted-firmware-a-latest/plat/intel/soc/common/soc/
Dsocfpga_mailbox.c192 mailbox_resp_ctr.payload->header) - in mailbox_read_response_async()
212 mailbox_resp_ctr.payload->data[mailbox_resp_ctr.index] = resp_data; in mailbox_read_response_async()
225 mailbox_resp_ctr.payload->header = resp_data; in mailbox_read_response_async()
238 *header = mailbox_resp_ctr.payload->header; in mailbox_read_response_async()
242 ret_resp_len = MBOX_RESP_LEN(mailbox_resp_ctr.payload->header); in mailbox_read_response_async()
255 (uint8_t *) mailbox_resp_ctr.payload->data, in mailbox_read_response_async()
263 if (MBOX_RESP_ERR(mailbox_resp_ctr.payload->header) > 0U) { in mailbox_read_response_async()
265 mailbox_resp_ctr.payload->header); in mailbox_read_response_async()
266 return -MBOX_RESP_ERR(mailbox_resp_ctr.payload->header); in mailbox_read_response_async()
/trusted-firmware-a-latest/plat/xilinx/versal/
Dbl31_versal_setup.c71 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; in bl31_early_platform_setup2() local
96 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, in bl31_early_platform_setup2()
98 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); in bl31_early_platform_setup2()
/trusted-firmware-a-latest/plat/xilinx/versal_net/
Dbl31_versal_net_setup.c72 uint32_t payload[PAYLOAD_ARG_CNT], max_size = HANDOFF_PARAMS_MAX_SIZE; in bl31_early_platform_setup2() local
117 PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, 1, PM_LOAD_GET_HANDOFF_PARAMS, in bl31_early_platform_setup2()
120 ret_status = pm_ipi_send_sync(primary_proc, payload, NULL, 0); in bl31_early_platform_setup2()
/trusted-firmware-a-latest/docs/plat/arm/arm_fpga/
Dindex.rst11 The FPGA platform requires to pass on a DTB for the non-secure payload
37 - ``PRELOADED_BL33_BASE`` : Physical address of the BL33 non-secure payload.
59 FPGA image (which can be written by the FPGA payload uploader, but is
60 read-only to the CPU). The FPGA payload tool should be given a text file
86 over to the FPGA payload uploader, which will take care of loading the
88 you need at least a BL33 payload (typically a Linux kernel image), optionally
/trusted-firmware-a-latest/docs/design_documents/
Ddrtm_poc.rst5 by measuring and executing a protected payload.
25 doing any needed configuration, loading the target payload image(DLME),
38 prepares the memory region for the target payload, measures the payload,
39 and finally transfers control to the payload.
41 - **DLME**: The protected payload is referred to as the Dynamically Launched
/trusted-firmware-a-latest/docs/plat/
Drpi4.rst44 non-secure payload to not touch the resident TF-A code.
48 see some text from BL31, followed by the output of the EL2 payload.
81 the EL2 payload needs to be a Linux kernel, a bootloader or any other kernel
83 register x0. If the payload has other means of finding the device tree, it

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