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/trusted-firmware-a-latest/plat/nxp/soc-ls1046a/
Dsoc.def17 # set to GIC400 or GIC500
20 # set to CCI400 or CCN504 or CCN508
23 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
26 # TZC IP Details TZC used is TZC380 or TZC400
29 # CONSOLE Details available is NS16550 or PL011
37 # ddr controller - set to MMDC or NXP
40 # ddr phy - set to NXP or SNPS
/trusted-firmware-a-latest/plat/nxp/soc-ls1043a/
Dsoc.def17 # set to GIC400 or GIC500
20 # set to CCI400 or CCN504 or CCN508
23 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
26 # TZC IP Details TZC used is TZC380 or TZC400
29 # CONSOLE Details available is NS16550 or PL011
37 # ddr controller - set to MMDC or NXP
40 # ddr phy - set to NXP or SNPS
/trusted-firmware-a-latest/plat/nxp/soc-ls1088a/
Dsoc.def17 # Set to GIC400 or GIC500
20 # Set to CCI400 or CCN504 or CCN508
28 # Indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
31 # TZC IP Details TZC used is TZC380 or TZC400
34 # CONSOLE Details available is NS16550 or PL011
/trusted-firmware-a-latest/
Ddco.txt17 (a) The contribution was created in whole or in part by me and I
19 indicated in the file; or
24 work with modifications, whether created in whole or in part
27 in the file; or
30 person who certified (a), (b) or (c) and I have not modified
37 this project or the open source license(s) involved.
/trusted-firmware-a-latest/plat/nxp/soc-ls1028a/
Dsoc.def17 # Set to GIC400 or GIC500
20 # Set to CCI400 or CCN504 or CCN508
23 # Layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
26 # TZC used is TZC380 or TZC400
29 # CONSOLE is NS16550 or PL011
/trusted-firmware-a-latest/make_helpers/
Darch_features.mk188 ifneq ($(or $(ENABLE_SPE_FOR_NS),0),0)
200 ifneq ($(or $(ENABLE_SVE_FOR_NS),0),0)
222 ifneq ($(or $(ENABLE_FEAT_MPAM),0),0)
306 ifneq ($(or $(ENABLE_TRBE_FOR_NS),0),0)
/trusted-firmware-a-latest/fdts/
Dstm32mp157c-dhcom-pdk2.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
8 * DHCOM PCB number: 587-200 or newer
9 * PDK2 PCB number: 516-400 or newer
Dstm32mp157a-dhcor-avenger96.dts10 * DHCOR PCB number: 586-100 or newer
11 * Avenger96 PCB number: 588-200 or newer
Dstm32mp25-bl2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
Dstm32mp157c-dhcom-pdk2-fw-config.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
Dstm32mp25xc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
Dstm32mp25xf.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
Dstm32mp255.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/trusted-firmware-a-latest/docs/getting_started/
Dbuild-internals.rst5 :ref:`build-options <build options>` but enabled or disabled indirectly and
6 depends on certain options to be enabled or disabled.
12 interest when Armv8.4-SecEL2 or RME extension is implemented.
14 and ``SPMD_SPM_AT_SEL2`` is set or when ``ENABLE_RME`` is set to 1 (enabled).
/trusted-firmware-a-latest/plat/nxp/soc-lx2160a/
Dsoc.def18 # set to GIC400 or GIC500
21 # set to CCI400 or CCN504 or CCN508
24 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
27 # TZC IP Details TZC used is TZC380 or TZC400
30 # CONSOLE Details available is NS16550 or PL011
/trusted-firmware-a-latest/docs/threat_model/
Dthreat_model_el3_spm.rst26 - Not covering advanced or invasive physical attacks such as decapsulation,
48 | DF1 | SP to SPMC communication. FF-A function invocation or |
60 | | LSP can send direct response SP1 or NWd through SPMC. |
111 NS-EL2 (Hypervisor) or NS-EL1 (VM or OS kernel).
114 such as bus probing or DRAM stress.
131 analysis is evaluated based on the environment being ``Server`` or ``Mobile``.
225 | | driver, or Hypervisor although it remains untrusted|
262 | | PARTITION_INFO_GET or memory sharing primitives. |
277 | Threat | **An endpoint may tamper with its own state or the |
282 | | - its own or another SP state by using an unusual |
[all …]
Dthreat_model_arm_cca.rst13 TF-A with or without Arm CCA support.
38 probe or tamper with off-chip memory.
45 *than GPT, is either held in on-chip memory, or in external memory but with*
53 read-only memory or write-protected memory. This could be on-chip ROM, on-chip
54 OTP, locked on-chip flash, or write-protected on-chip RAM for example.
61 *[R0050] If all or part of initial boot code is instantiated in on-chip*
62 *memory then other trusted subsystems or application PE cannot modify that*
113 | | TF-A through SMC call interface and/or shared |
125 malicious or faulty code running in the realm world, including R-EL2, R-EL1
155 | | | code or access otherwise restricted HW interface. |
/trusted-firmware-a-latest/lib/compiler-rt/
DLICENSE.TXT32 use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
41 documentation and/or other materials provided with the distribution.
45 endorse or promote products derived from this Software without specific
63 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
68 all copies or substantial portions of the Software.
88 other licenses gives permission to use the names of the LLVM Team or the
89 University of Illinois to endorse or promote products derived from this
/trusted-firmware-a-latest/docs/security_advisories/
Dsecurity-advisory-tfv-11.rst32 (PPI) or a shared peripheral interrupt (SPI).
37 or a EL3 panic depending on the GIC version used in the system.
51 register. Which may cause a data abort or an access to a random EL3 memory region.
66 SDEI client is a valid PPI or SPI, otherwise return an error code indicating
77 /* Interrupt must be either PPI or SPI */
/trusted-firmware-a-latest/docs/process/
Dplatform-ports-policy.rst11 documented in the :ref:`Porting Guide`), driver APIs (like the GICv3 drivers) or
23 to upstream their platform code or copy the latest version of the code being
38 If a platform, driver or library interface is no longer maintained, it is best
40 can be a 1-stage or 2-stage process (up to the maintainers).
50 platform ports (or soon to be) to this day.
/trusted-firmware-a-latest/docs/plat/
Drockchip.rst26 - U-Boot - either separately as TPL+SPL or only SPL
32 Rockchip SoCs expect TF-A's BL31 (AARCH64) or BL32 (AARCH32) to get
33 integrated with other boot software like U-Boot or Coreboot, so only
/trusted-firmware-a-latest/docs/components/
Del3-spmc.rst46 - BL32 option is re-purposed to specify the S-EL1 TEE or SP image.
48 - BL33 option can specify the TFTF binary or a normal world loader
49 such as U-Boot or the UEFI framework payload.
90 for managing access control, programming TZ Controller or MPUs.
234 boot (that is prior to NWd is booted) or run-time.
239 The request made by an Hypervisor or OS kernel is forwarded to the SPMC and
253 When invoked from the Hypervisor or OS kernel, the buffers are mapped into the
258 caller, either it being the Hypervisor or OS kernel, as well as a secure
267 - from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD.
269 The format (v1.0 or v1.1) of the populated data structure returned is based upon the
[all …]
Ddebugfs-design.rst12 TFTF test payload or a Linux kernel module.
28 - / is used as root for virtual "files" (e.g. /fip, or /dev/uart)
43 relative or an absolute offset.
68 options. The interface multiplexes drivers or emulated "files":
75 non-secure layers, or for which no support exists in the NS side).
82 shared buffer is used to pass path string parameters, or e.g. to exchange
114 - a test payload, bootloader or hypervisor running at NS-EL2
/trusted-firmware-a-latest/include/export/
DREADME3 or interfaces. They must follow these special rules:
7 - All definitions should be sufficiently namespaced (e.g. with BL_ or TF_) to
20 pre-defined by all common compilers (e.g. __ASSEMBLER__ or __aarch64__).

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