Home
last modified time | relevance | path

Searched refs:mmio_clrsetbits_32 (Results 1 – 25 of 87) sorted by relevance

1234

/trusted-firmware-a-latest/plat/brcm/board/stingray/driver/ext_sram_init/
Dext_sram_init.c24 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2dc), in brcm_stingray_pnor_pinmux_init()
29 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e0), in brcm_stingray_pnor_pinmux_init()
34 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e4), in brcm_stingray_pnor_pinmux_init()
39 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2e8), in brcm_stingray_pnor_pinmux_init()
44 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2ec), in brcm_stingray_pnor_pinmux_init()
49 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f0), in brcm_stingray_pnor_pinmux_init()
54 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f4), in brcm_stingray_pnor_pinmux_init()
59 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2f8), in brcm_stingray_pnor_pinmux_init()
64 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x2fc), in brcm_stingray_pnor_pinmux_init()
69 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x300), in brcm_stingray_pnor_pinmux_init()
[all …]
/trusted-firmware-a-latest/plat/mediatek/drivers/dcm/mt8188/
Dmtk_dcm_utils.c47 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
50 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
53 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
58 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
61 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
64 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
101 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
104 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
107 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
112 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/dcm/
Dmtk_dcm_utils.c63 mmio_clrsetbits_32(MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
66 mmio_clrsetbits_32(MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
69 mmio_clrsetbits_32(MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
74 mmio_clrsetbits_32(MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
77 mmio_clrsetbits_32(MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
80 mmio_clrsetbits_32(MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
117 mmio_clrsetbits_32(MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
120 mmio_clrsetbits_32(MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
123 mmio_clrsetbits_32(MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
128 mmio_clrsetbits_32(MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
[all …]
/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/
Ddfs.c500 mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff, in gen_rk3399_ctl_params_f0()
507 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
516 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
524 mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
529 mmio_clrsetbits_32(CTL_REG(i, 23), (0x7f << 16), in gen_rk3399_ctl_params_f0()
531 mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24), in gen_rk3399_ctl_params_f0()
533 mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al); in gen_rk3399_ctl_params_f0()
534 mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16, in gen_rk3399_ctl_params_f0()
543 mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24, in gen_rk3399_ctl_params_f0()
547 mmio_clrsetbits_32(CTL_REG(i, 34), 0xff, in gen_rk3399_ctl_params_f0()
[all …]
Dsuspend.c152 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, in set_cs_training_index()
173 mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, in override_write_leveling_value()
175 mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), in override_write_leveling_value()
181 mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); in override_write_leveling_value()
225 mmio_clrsetbits_32(PI_REG(ch, 100), 0x3 << 8, 0x2 << 8); in data_training()
228 mmio_clrsetbits_32(PI_REG(ch, 92), in data_training()
266 mmio_clrsetbits_32(PI_REG(ch, 60), 0x3 << 8, 0x2 << 8); in data_training()
268 mmio_clrsetbits_32(PI_REG(ch, 59), in data_training()
312 mmio_clrsetbits_32(PI_REG(ch, 80), 0x3 << 24, in data_training()
318 mmio_clrsetbits_32(PI_REG(ch, 74), in data_training()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/dcm/
Dmtk_dcm_utils.c51 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
54 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
59 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
62 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
99 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
102 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
105 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
110 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
113 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
116 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/dcm/
Dmtk_dcm_utils.c63 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
66 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
69 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
74 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
77 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4, in dcm_mp_cpusys_top_adb_dcm()
80 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_adb_dcm()
117 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
120 mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
123 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
128 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
[all …]
/trusted-firmware-a-latest/plat/brcm/board/stingray/src/
Dsdio.c70 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_CLK, in brcm_stingray_sdio_init()
72 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA0, in brcm_stingray_sdio_init()
74 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA1, in brcm_stingray_sdio_init()
76 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA2, in brcm_stingray_sdio_init()
78 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA3, in brcm_stingray_sdio_init()
80 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA4, in brcm_stingray_sdio_init()
82 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA5, in brcm_stingray_sdio_init()
84 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA6, in brcm_stingray_sdio_init()
86 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_DATA7, in brcm_stingray_sdio_init()
88 mmio_clrsetbits_32(sdio0_cfg->pad_base + PAD_SDIO_CMD, in brcm_stingray_sdio_init()
[all …]
Dbl31_setup.c328 mmio_clrsetbits_32(ICFG_AMAC_RGMII_PHY_CONFIG, AMAC_RPHY_SPEED_MASK, in brcm_stingray_amac_init()
340 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_ARCACHE_MASK, in brcm_stingray_amac_init()
342 mmio_clrsetbits_32(AMAC_IDM0_IO_CONTROL_DIRECT, AMAC_IDM0_AWCACHE_MASK, in brcm_stingray_amac_init()
501 mmio_clrsetbits_32(scr_base + 0x0, clr_mask, set_mask); in brcm_stingray_scr_init()
506 mmio_clrsetbits_32(scr_base + 0x4, clr_mask, set_mask); in brcm_stingray_scr_init()
511 mmio_clrsetbits_32(scr_base + 0x8, clr_mask, set_mask); in brcm_stingray_scr_init()
516 mmio_clrsetbits_32(scr_base + 0xc, clr_mask, set_mask); in brcm_stingray_scr_init()
521 mmio_clrsetbits_32(scr_base + 0x10, clr_mask, set_mask); in brcm_stingray_scr_init()
592 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_ARCACHE_MASK, in brcm_stingray_audio_init()
595 mmio_clrsetbits_32(I2S_IDM_IO_CONTROL, I2S_IDM0_AWCACHE_MASK, in brcm_stingray_audio_init()
/trusted-firmware-a-latest/plat/intel/soc/common/soc/
Dsocfpga_emac.c22 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_0), in socfpga_emac_init()
24 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_1), in socfpga_emac_init()
26 mmio_clrsetbits_32(SOCFPGA_SYSMGR(EMAC_2), in socfpga_emac_init()
/trusted-firmware-a-latest/plat/mediatek/mt8183/
Dbl31_plat_setup.c49 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
51 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->mscib_dcm_en, in platform_setup_cpu()
54 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config, in platform_setup_cpu()
60 mmio_clrsetbits_32( in platform_setup_cpu()
68 mmio_clrsetbits_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config, in platform_setup_cpu()
74 mmio_clrsetbits_32( in platform_setup_cpu()
/trusted-firmware-a-latest/plat/imx/imx8m/
Dimx8m_csu.c23 mmio_clrsetbits_32(CSLx_REG(csu->idx), CSLx_CFG(0xff, csu->idx), in imx_csu_init()
31 mmio_clrsetbits_32(CSU_HP_REG(csu->idx), CSU_HP_CFG(0x1, csu->idx), in imx_csu_init()
39 mmio_clrsetbits_32(CSU_SA_REG(csu->idx), CSU_SA_CFG(0x1, csu->idx), in imx_csu_init()
47 mmio_clrsetbits_32(CSU_HPCONTROL_REG(csu->idx), CSU_HPCONTROL_CFG(0x1, csu->idx), in imx_csu_init()
Dgpc_common.c153 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CLK_ON_LPM, in imx_set_cluster_powerdown()
172 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, 0xf, A53_CLK_ON_LPM); in imx_set_cluster_powerdown()
176 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_AD, (L2PGE | EN_PLAT_PDN), in imx_set_cluster_powerdown()
199 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, A53_CORE_WUP_SRC(last_core), in imx_set_sys_wakeup()
202 mmio_clrsetbits_32(IMX_GPC_BASE + LPCR_A53_BSC, IRQ_SRC_A53_WUP, in imx_set_sys_wakeup()
/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/devapc/
Ddevapc.c46 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain()
60 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
66 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
71 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_infra()
75 mmio_clrsetbits_32(base, 0x1, set_bit); in set_master_domain_remap_infra()
90 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_master_domain_remap_mm()
116 mmio_clrsetbits_32(base, clr_bit, set_bit); in set_module_apc()
/trusted-firmware-a-latest/plat/brcm/board/stingray/driver/
Dusb.c183 mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIWRA, in usb_enable_coherence()
187 mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIRDA, in usb_enable_coherence()
191 mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIWRA, in usb_enable_coherence()
195 mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIRDA, in usb_enable_coherence()
209 mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIWRA, in usb_enable_coherence()
213 mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIRDA, in usb_enable_coherence()
217 mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIWRA, in usb_enable_coherence()
221 mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIRDA, in usb_enable_coherence()
/trusted-firmware-a-latest/drivers/marvell/mochi/
Dapn806_setup.c100 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ in apn_sec_masters_access_en()
106 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
113 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
118 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in apn_sec_masters_access_en()
187 mmio_clrsetbits_32(stream_id_reg[i], mask, in ap806_stream_id_init()
Dap807_setup.c105 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, 0x0U, /* no clear */ in ap_sec_masters_access_en()
111 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
118 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
123 mmio_clrsetbits_32(SEC_MOCHI_IN_ACC_REG, in ap_sec_masters_access_en()
193 mmio_clrsetbits_32(stream_id_reg[i], mask, in ap807_stream_id_init()
/trusted-firmware-a-latest/plat/allwinner/common/
Dsunxi_common.c104 mmio_clrsetbits_32(port_base + (pin / 8) * 4, in sunxi_set_gpio_out()
142 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x00, 0xffU, pin_func); in sunxi_init_platform_r_twi()
145 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x14, 0x0fU, 0xaU); in sunxi_init_platform_r_twi()
148 mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U); in sunxi_init_platform_r_twi()
/trusted-firmware-a-latest/drivers/st/gpio/
Dstm32_gpio.c236 mmio_clrsetbits_32(base + GPIO_MODE_OFFSET, in set_gpio()
240 mmio_clrsetbits_32(base + GPIO_TYPE_OFFSET, in set_gpio()
244 mmio_clrsetbits_32(base + GPIO_SPEED_OFFSET, in set_gpio()
248 mmio_clrsetbits_32(base + GPIO_PUPD_OFFSET, in set_gpio()
253 mmio_clrsetbits_32(base + GPIO_AFRL_OFFSET, in set_gpio()
259 mmio_clrsetbits_32(base + GPIO_AFRH_OFFSET, in set_gpio()
264 mmio_clrsetbits_32(base + GPIO_OD_OFFSET, in set_gpio()
/trusted-firmware-a-latest/include/drivers/nxp/dcfg/
Dscfg.h52 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
59 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
/trusted-firmware-a-latest/drivers/st/crypto/
Dstm32_saes.c140 mmio_clrsetbits_32((cr), _SAES_CR_CHMOD_MASK, _SAES_CR_CHMOD_##mod << _SAES_CR_CHMOD_SHIFT)
295 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK, in saes_prepare_key()
310 mmio_clrsetbits_32(ctx->base + _SAES_CR, _SAES_CR_MODE_MASK, in saes_prepare_key()
438 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK, in stm32_saes_init()
442 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_MODE_MASK, in stm32_saes_init()
475 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_DATATYPE_MASK, in stm32_saes_init()
493 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, in stm32_saes_init()
520 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, in stm32_saes_init()
524 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, in stm32_saes_init()
528 mmio_clrsetbits_32((uintptr_t)&(ctx->cr), _SAES_CR_KEYSEL_MASK, in stm32_saes_init()
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8173/drivers/spm/
Dspm_hotplug.c251 mmio_clrsetbits_32(SPM_PCM_RESERVE, in spm_hotplug_on()
271 mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK, in spm_hotplug_off()
/trusted-firmware-a-latest/plat/intel/soc/stratix10/soc/
Ds10_memory_controller.c226 mmio_clrsetbits_32( in configure_ddr_sched_ctrl_regs()
376 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_DDRIOCTRL, in configure_hmc_adaptor_regs()
385 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
392 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL2, in configure_hmc_adaptor_regs()
399 mmio_clrsetbits_32(S10_MPFE_HMC_ADP_ECCCTRL1, in configure_hmc_adaptor_regs()
/trusted-firmware-a-latest/plat/mediatek/drivers/ptp3/
Dptp3_common.c20 mmio_clrsetbits_32(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK, in ptp3_init()
23 mmio_clrsetbits_32(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK, in ptp3_init()
/trusted-firmware-a-latest/plat/brcm/board/stingray/include/
Dsr_utils.h33 mmio_clrsetbits_32(CDRU_CHIP_STRAP_DATA, in brcm_stingray_set_straps()

1234