Searched refs:memory (Results 1 – 25 of 119) sorted by relevance
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| /trusted-firmware-a-latest/fdts/ |
| D | juno-ethosn.dtsi | 40 compatible = "ethosn-memory";
45 compatible = "ethosn-memory";
56 compatible = "ethosn-memory";
61 compatible = "ethosn-memory";
66 compatible = "ethosn-memory";
71 compatible = "ethosn-memory";
81 compatible = "ethosn-memory";
86 compatible = "ethosn-memory";
91 compatible = "ethosn-memory";
96 compatible = "ethosn-memory";
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| D | stm32mp15-fw-config.dtsi | 17 /* OP-TEE reserved shared memory: located at DDR top or null size */
20 /* OP-TEE secure memory: located right below OP-TEE reserved shared memory */
70 memory-ranges = <
79 memory-ranges = <
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| D | morello-fvp.dts | 17 reserved-memory {
110 /* The first bank of memory, memory map is actually provided by UEFI. */
111 memory@80000000 {
112 device_type = "memory";
117 memory@8080000000 {
118 device_type = "memory";
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| D | stm32mp257f-ev1.dts | 26 memory@80000000 {
27 device_type = "memory";
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| D | n1sdp-single-chip.dts | 23 * In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
26 memory@80000000 {
27 device_type = "memory";
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| D | fvp-ve-Cortex-A7x1.dts | 31 memory@0,80000000 {
32 device_type = "memory";
36 reserved-memory {
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| /trusted-firmware-a-latest/ |
| D | pyproject.toml | 9 { include = "memory", from = "tools/memory"}
13 memory = "memory.memmap:main"
29 [tool.poetry.group.memory.dependencies]
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| D | .gitignore | 25 tools/memory/memory/__pycache__/
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| /trusted-firmware-a-latest/docs/tools/ |
| D | memory-layout-tool.rst | 4 TF-A's memory layout tool is a Python script for analyzing the virtual
5 memory layout of TF-A builds.
26 poetry install --with memory
32 poetry run memory --help
39 main memory regions in an ELF file (i.e. text, bss, rodata) but can be modified
44 $ poetry run memory -s
114 poetry run memory --help
119 The tool enables users to view static memory consumption. When the options
121 the build path to generate a table (per memory type), showing memory allocation
126 $ poetry run memory -f
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| D | index.rst | 8 memory-layout-tool
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| /trusted-firmware-a-latest/plat/nvidia/tegra/scat/ |
| D | bl31.scat | 174 * Bakery locks are stored in normal .bss memory
193 /* padded memory section to store per cpu bakery locks */
204 * Time-stamps are stored in normal .bss memory
206 * The compiler will allocate enough memory for one CPU's time-stamps,
212 /* store timestamps in this carved out memory */
225 /* padded memory section to store per cpu timestamps */
242 * The base address of the coherent memory section must be page-aligned (4K)
245 * memory attributes for the coherent data page tables.
250 * Bakery locks are stored in coherent memory
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-3.rst | 5 | Title | RO memory is always executable at AArch64 Secure EL1 |
27 memory mappings in the form of ``mmap_region`` structures. Each ``mmap_region``
28 has memory attributes represented by the ``mmap_attr_t`` enumeration type. This
32 Read-Only (RO), non-executable memory region.
35 Any memory region mapped as RO will always be executable, regardless of whether
47 permissions separately to data access permissions. All RO normal memory regions
49 would only manifest itself for device memory mapped as RO; use of this mapping
62 permissions but always leaves the memory as executable at Secure EL1.
66 - The xlat\_tables library ensures that all Read-Write (RW) memory regions are
80 - ARM TF EL3 code (for example BL1 and BL31) ensures that all non-secure memory
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| D | security-advisory-tfv-4.rst | 6 | | authentication of unexpected data in secure memory in |
20 | | memory |
72 memory for subsequent authentication. This is implemented by the
88 these unsanitized values and allow the following memory copy operation, that
90 secure memory if the memory is mapped in BL1's address space, or cause a fatal
94 resident in secure memory. This is implemented by the ``bl1_fwu_image_auth()``
112 on the unexpected secure memory accesses. Moreover, the normal world FWU code
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| D | security-advisory-tfv-1.rst | 6 | | unexpectedly large data into secure memory |
18 | Impact | Copy of unexpectedly large data into the free secure memory |
52 implementation is designed to copy an image into secure memory for subsequent
54 unexpectedly large data into secure memory. Note that a separate vulnerability
56 system to change its behaviour based on the unexpected secure memory contents.
98 result in an unexpectedly large copy of data into secure memory.
131 large copy of data into secure memory.
153 This function checks that the passed memory region is within one of the
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| /trusted-firmware-a-latest/plat/arm/board/fvp/fdts/ |
| D | fvp_spmc_manifest.dts | 86 memory@0 {
87 device_type = "memory";
93 memory@1 {
94 device_type = "ns-memory";
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| D | fvp_spmc_optee_sp_manifest.dts | 60 memory@6000000 {
61 device_type = "memory";
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| /trusted-firmware-a-latest/docs/components/ |
| D | granule-protection-tables-design.rst | 7 the systems memory layout, configure the system registers to enable granule
13 spaces have been added to control memory access for each state. The PAS access
48 level 0 table controls access to a relatively large region in memory (block
51 small regions (granules) of memory can be assigned to different PAS with a 2
65 determines how much physical memory is governed by each level 0 entry. A granule
66 is the smallest unit of memory that can be independently assigned to a PAS.
76 creates the tables in memory, and enables granule protection checks. In the
78 memory using the GPT register configuration and saves important data to a
98 #. The desired attributes of this memory region (mapping type, PAS type)
103 structures, then the library will check the desired memory access layout for
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| D | xlat-tables-lib-v2-design.rst | 6 tables based on a description of the memory layout, as well as setting up system
13 upon a description of the memory layout. The memory layout is typically
14 provided by the platform port as a list of memory regions;
20 on. This can be used to temporarily map some memory regions and unmap them
26 #. Support for changing memory attributes of memory regions at run-time.
62 An ``mmap_region`` is an abstract, concise way to represent a memory region to
77 The region attributes specify the type of memory (for example device or cached
78 normal memory) as well as the memory access permissions (read-only or
87 granule size, the library might map a 2MB memory region using either of the two
95 potentially less memory. However, if part of this 2MB region is later remapped
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| D | secure-partition-manager-mm.rst | 167 describe the memory regions that the SPM needs to allocate for a Secure
172 with information about the memory map of the Secure Partition.
204 through a shared memory region. The location of data in the shared memory area
205 is passed as a parameter to the ``MM_COMMUNICATE`` SMC. The shared memory area
210 memory area. The shared memory area is implemented as per the guidelines
214 The format of data structures used to encapsulate data in the shared memory is
293 partition (e.g. management of memory attributes in the translation tables for
408 2. Code memory regions are mapped with RO data and Executable instruction access
411 3. Read Only data memory regions are mapped with RO data and Execute Never
414 4. Read Write data memory regions are mapped with RW data and Execute Never
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| /trusted-firmware-a-latest/plat/arm/board/tc/fdts/ |
| D | tc_spmc_manifest.dts | 120 memory@0 {
121 device_type = "memory";
127 memory@1 {
128 device_type = "ns-memory";
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| D | tc_spmc_optee_sp_manifest.dts | 119 memory@0 {
120 device_type = "memory";
124 memory@1 {
125 device_type = "ns-memory";
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| /trusted-firmware-a-latest/docs/components/measured_boot/ |
| D | event_log.rst | 24 - Event Log base address in secure memory.
26 Note. Currently OP-TEE does not support reading DTBs from Secure memory
31 - Event Log base address in non-secure memory.
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| /trusted-firmware-a-latest/docs/threat_model/ |
| D | threat_model_arm_cca.rst | 36 - All TF-A images run from on-chip memory. Data used by these images also live
37 in on-chip memory. This means TF-A is not vulnerable to an attacker that can
38 probe or tamper with off-chip memory.
42 *[R0147] Monitor code executes entirely from on-chip memory.*
45 *than GPT, is either held in on-chip memory, or in external memory but with*
49 hold data in external memory, even if it is integrity-protected - except for
53 read-only memory or write-protected memory. This could be on-chip ROM, on-chip
62 *memory then other trusted subsystems or application PE cannot modify that*
114 | | memory. |
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| /trusted-firmware-a-latest/docs/plat/ |
| D | rpi4.rst | 12 **IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM,
14 not seem to feature a secure memory controller of any kind, so portions of
42 The BL31 code will patch the provided device tree blob in memory to advertise
43 PSCI support, also will add a reserved-memory node to the DT to tell the
73 memory. The load addresses have a default, but can also be changed by
75 armstub image file, it will put those two load addresses in memory locations
76 near the beginning of memory, where TF-A code picks them up.
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| /trusted-firmware-a-latest/include/drivers/st/ |
| D | stm32_sdmmc2.h | 33 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory);
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