1 /* 2 * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MT_CPU_PM_CPC_H 8 #define MT_CPU_PM_CPC_H 9 10 #include <lib/mmio.h> 11 12 #include <mcucfg.h> 13 #include <platform_def.h> 14 15 #define NEED_CPUSYS_PROT_WORKAROUND (1) 16 17 /* system sram registers */ 18 #define CPUIDLE_SRAM_REG(r) (CPU_IDLE_SRAM_BASE + (r)) 19 20 /* db dump */ 21 #define CPC_TRACE_SIZE (0x20) 22 #define CPC_TRACE_ID_NUM (10) 23 #define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE) 24 25 /* buckup off count */ 26 #define CPC_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1f0) 27 #define CPC_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1f4) 28 29 /* CPC_MCUSYS_CPC_FLOW_CTRL_CFG (0xA814): debug setting */ 30 #define CPC_PWR_ON_SEQ_DIS BIT(1) 31 #define CPC_PWR_ON_PRIORITY BIT(2) 32 #define CPC_AUTO_OFF_EN BIT(5) 33 #define CPC_DORMANT_WAIT_EN BIT(14) 34 #define CPC_CTRL_EN BIT(16) 35 #define CPC_OFF_PRE_EN BIT(29) 36 37 /* CPC_MCUSYS_LAST_CORE_REQ (0xA818) : last core protection */ 38 #define CPUSYS_PROT_SET BIT(0) 39 #define MCUSYS_PROT_SET BIT(8) 40 #define CPUSYS_PROT_CLR BIT(8) 41 #define MCUSYS_PROT_CLR BIT(9) 42 43 #define CPC_PROT_RESP_MASK (0x3) 44 #define CPUSYS_RESP_OFS (16) 45 #define MCUSYS_RESP_OFS (30) 46 47 #define RETRY_CNT_MAX (1000) 48 49 #define PROT_RETRY (0) 50 #define PROT_SUCCESS (1) 51 #define PROT_GIVEUP (2) 52 53 /* CPC_MCUSYS_CPC_DBG_SETTING (0xAB00): debug setting */ 54 #define CPC_PROF_EN BIT(0) 55 #define CPC_DBG_EN BIT(1) 56 #define CPC_FREEZE BIT(2) 57 #define CPC_CALC_EN BIT(3) 58 59 enum mcusys_cpc_lastcore_prot_status { 60 CPC_SUCCESS = 0, 61 CPC_ERR_FAIL, 62 CPC_ERR_TIMEOUT, 63 NF_CPC_ERR, 64 }; 65 66 enum mcusys_cpc_smc_events { 67 CPC_SMC_EVENT_DUMP_TRACE_DATA, 68 CPC_SMC_EVENT_GIC_DPG_SET, 69 CPC_SMC_EVENT_CPC_CONFIG, 70 CPC_SMC_EVENT_READ_CONFIG, 71 NF_CPC_SMC_EVENT, 72 }; 73 74 enum mcusys_cpc_smc_config { 75 CPC_SMC_CONFIG_PROF, 76 CPC_SMC_CONFIG_AUTO_OFF, 77 CPC_SMC_CONFIG_AUTO_OFF_THRES, 78 CPC_SMC_CONFIG_CNT_CLR, 79 CPC_SMC_CONFIG_TIME_SYNC, 80 NF_CPC_SMC_CONFIG, 81 }; 82 83 #define US_TO_TICKS(us) ((us) * 13) 84 #define TICKS_TO_US(tick) ((tick) / 13) 85 86 int mtk_cpu_pm_cluster_prot_aquire(void); 87 void mtk_cpu_pm_cluster_prot_release(void); 88 89 void mtk_cpc_mcusys_off_reflect(void); 90 int mtk_cpc_mcusys_off_prepare(void); 91 92 void mtk_cpc_core_on_hint_set(int cpu); 93 void mtk_cpc_core_on_hint_clr(int cpu); 94 void mtk_cpc_time_sync(void); 95 96 uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2); 97 uint64_t mtk_cpc_trace_dump(uint64_t act, uint64_t arg1, uint64_t arg2); 98 void mtk_cpc_init(void); 99 100 #endif /* MT_CPU_PM_CPC_H */ 101
