| /trusted-firmware-a-latest/drivers/st/regulator/ |
| D | regulator_core.c | 289 int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count) in regulator_list_voltages() argument
295 assert(levels != NULL); in regulator_list_voltages()
306 ret = rdev->desc->ops->list_voltages(rdev->desc, levels, count); in regulator_list_voltages()
320 while ((n > 1U) && ((*levels)[n - 1U] > rdev->max_mv)) { in regulator_list_voltages()
325 if (rdev->max_mv != (*levels)[n - 1]) { in regulator_list_voltages()
331 while ((n > 1U) && ((*levels[0U]) < rdev->min_mv)) { in regulator_list_voltages()
332 (*levels)++; in regulator_list_voltages()
344 if (rdev->min_mv != (*levels)[0U]) { in regulator_list_voltages()
452 const uint16_t *levels; in parse_dt() local
495 ret = regulator_list_voltages(rdev, &levels, &size); in parse_dt()
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| /trusted-firmware-a-latest/include/drivers/st/ |
| D | regulator.h | 56 int regulator_list_voltages(const struct rdev *rdev, const uint16_t **levels, size_t *count);
82 const uint16_t **levels, size_t *count);
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| D | stpmic1.h | 184 int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels,
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| /trusted-firmware-a-latest/docs/components/ |
| D | exception-handling.rst | 95 priority levels as applicable for the Secure software stack. It then assigns the
96 dispatchers to one or more priority levels. The dispatchers then register
97 handlers for the priority levels at runtime. A dispatcher can register handlers
100 .. __: `Partitioning priority levels`_
132 stack—priority levels stack up in strictly increasing fashion, and need to be
135 `Transition of priority levels`_.
166 interrupts into distinct priority levels. A dispatcher that chooses to receive
167 interrupts can then *own* one or more priority levels, and register interrupt
171 Dispatchers are assigned interrupt priority levels in two steps:
173 .. _Partitioning priority levels:
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| D | xlat-tables-lib-v2-design.rst | 361 allows up to 4 lookup levels).
372 memory than expected. The reason is that all levels of translation are
379 on the page size, levels 0 and 1 of translation may only allow table
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| D | ras.rst | 328 priority levels>` for handling RAS exceptions. The platform must then define
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| D | secure-partition-manager-mm.rst | 252 depending on the implemented Exception levels. In S-EL0, the Supervisor Call
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| D | secure-partition-manager.rst | 110 SPMC) residing at different exception levels. To permit the FF-A specification
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| /trusted-firmware-a-latest/drivers/st/pmic/ |
| D | stpmic1.c | 799 int stpmic1_regulator_levels_mv(const char *name, const uint16_t **levels, in stpmic1_regulator_levels_mv() argument
806 *levels = ldo3_special_mode_table; in stpmic1_regulator_levels_mv()
809 *levels = regul->voltage_table; in stpmic1_regulator_levels_mv()
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| D | stm32mp_pmic.c | 413 const uint16_t **levels, size_t *count) in pmic_list_voltages() argument
417 return stpmic1_regulator_levels_mv(desc->node_name, levels, count); in pmic_list_voltages()
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| /trusted-firmware-a-latest/docs/perf/ |
| D | performance-monitoring-unit.rst | 18 The PMU makes 32 counters available at all privilege levels:
50 ``PMCR`` registers. These can be accessed at all privilege levels.
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| D | psci-performance-juno.rst | 26 levels 0, 1 and 2 respectively. It does not support any retention states.
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| /trusted-firmware-a-latest/docs/process/ |
| D | security-hardening.rst | 33 levels must defend from those below when the PMU is treated as an attack
71 exception levels) it instructs counters to increment, obtaining event counts
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| D | coding-guidelines.rst | 509 levels of "weakness". This has resulted in bugs in the past.
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-7.rst | 78 lower exception levels to temporarily disable the mitigation in their execution
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| /trusted-firmware-a-latest/docs/design/ |
| D | psci-pd-tree.rst | 20 levels in the power domain tree to four.
37 domains at higher levels. For example, only a core power domain can be identified
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| D | interrupt-framework-design.rst | 20 exception levels lower than EL3. This could be done with or without the
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| D | firmware-design.rst | 788 levels lower than EL3 will request runtime services using the Secure Monitor
1461 levels for that specific CPU. The PSCI service, upon receiving a power down
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| /trusted-firmware-a-latest/docs/ |
| D | porting-guide.rst | 138 levels in the platform.
153 tree at all the power domain levels used by the platform.
1458 correspond to one of the standard log levels defined in debug.h. The platform
1461 increase the number of log levels.
2537 differently at CPU level versus higher levels. As an example, if the element at
2540 residency statistics. For higher levels (array indices > 0), the residency
2555 differently at CPU level versus higher levels. As an example, if the element at
2558 residency statistics. For higher levels (array indices > 0), the residency
2573 all its parent power domain levels are also woken up. The generic PSCI code
2676 powering off the calling CPU and its higher parent power domain levels as
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| D | change-log.md | 7124 - Warning levels are now selectable with `W=<1,2,3>`
7674 - Added support to manage both privilege levels in translation regimes that
7675 describe translations for 2 Exception levels, specifically the EL1&0
8051 unexpected traps into the higher exception levels and disable secure
8055 in the higher exception levels.
8067 at multiple power levels.
8645 - Adding the concept of debug log levels.
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| /trusted-firmware-a-latest/docs/threat_model/ |
| D | threat_model_arm_cca.rst | 126 and R-EL0 levels.
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| D | threat_model.rst | 144 | | world, including NS-EL0 NS-EL1 and NS-EL2 levels |
147 | | world, including S-EL0 and S-EL1 levels |
241 .. table:: Table 5: Overall risk levels and corresponding aggregate scores
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| /trusted-firmware-a-latest/docs/getting_started/ |
| D | rt-svc-writers-guide.rst | 11 levels lower than EL3 will request runtime services using the Secure Monitor
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| D | build-options.rst | 228 When specifying higher warnings levels (``W=1`` and higher), this option
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