| /trusted-firmware-a-latest/plat/nxp/common/soc_errata/ |
| D | errata_a050426.c | 13 uint32_t i, val3, val4; in erratum_a050426() local
31 for (i = 0U; i < 4U; i++) { in erratum_a050426()
32 mmio_write_32(0x706312000 + (i * 4), 0x55555555); in erratum_a050426()
33 mmio_write_32(0x706312400 + (i * 4), 0x55555555); in erratum_a050426()
34 mmio_write_32(0x706312800 + (i * 4), 0x55555555); in erratum_a050426()
35 mmio_write_32(0x706314000 + (i * 4), 0x55555555); in erratum_a050426()
36 mmio_write_32(0x706314400 + (i * 4), 0x55555555); in erratum_a050426()
37 mmio_write_32(0x706314800 + (i * 4), 0x55555555); in erratum_a050426()
38 mmio_write_32(0x706314c00 + (i * 4), 0x55555555); in erratum_a050426()
40 for (i = 0U; i < 3U; i++) { in erratum_a050426()
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| /trusted-firmware-a-latest/plat/mediatek/drivers/apusys/devapc/ |
| D | apusys_dapc_v1.c | 20 uint32_t i; in set_apusys_dapc_v1() local
26 for (i = 0; i < size; i++) { in set_apusys_dapc_v1()
27 ret += cfg(i, DOMAIN_0, dapc[i].d0_permission); in set_apusys_dapc_v1()
28 ret += cfg(i, DOMAIN_1, dapc[i].d1_permission); in set_apusys_dapc_v1()
29 ret += cfg(i, DOMAIN_2, dapc[i].d2_permission); in set_apusys_dapc_v1()
30 ret += cfg(i, DOMAIN_3, dapc[i].d3_permission); in set_apusys_dapc_v1()
31 ret += cfg(i, DOMAIN_4, dapc[i].d4_permission); in set_apusys_dapc_v1()
32 ret += cfg(i, DOMAIN_5, dapc[i].d5_permission); in set_apusys_dapc_v1()
33 ret += cfg(i, DOMAIN_6, dapc[i].d6_permission); in set_apusys_dapc_v1()
34 ret += cfg(i, DOMAIN_7, dapc[i].d7_permission); in set_apusys_dapc_v1()
[all …]
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| /trusted-firmware-a-latest/drivers/nxp/flexspi/nor/ |
| D | test_fspi.c | 31 uint32_t failed, i; in fspi_test() local
43 for (i = 0; i < size; i++) in fspi_test()
44 if (fspi_swap32(0xffffffff) != buffer[i]) { in fspi_test()
50 NOTICE("[%d]: Success Erase: data in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]); in fspi_test()
52 ERROR("Erase: Failed -->xxx with buffer[%d]=0x%08x\n", i, buffer[i]); in fspi_test()
55 for (i = 0; i < SIZE_BUFFER; i++) in fspi_test()
56 buffer[i] = 0x12345678; in fspi_test()
63 for (i = 0; i < size; i++) in fspi_test()
64 if (fspi_swap32(0x12345678) != buffer[i]) { in fspi_test()
70 NOTICE("[%d]: Success IpWrite with IP READ in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]); in fspi_test()
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| /trusted-firmware-a-latest/plat/intel/soc/stratix10/soc/ |
| D | s10_pinmux.c | 190 unsigned int i; in config_pinmux() local
192 for (i = 0; i < 96; i += 2) { in config_pinmux()
194 hoff_ptr->pinmux_sel_array[i], in config_pinmux()
195 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
198 for (i = 0; i < 96; i += 2) { in config_pinmux()
200 hoff_ptr->pinmux_io_array[i], in config_pinmux()
201 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
204 for (i = 0; i < 42; i += 2) { in config_pinmux()
206 hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
207 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]
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| /trusted-firmware-a-latest/plat/nxp/common/setup/ |
| D | ls_common.c | 63 int i = 0; in mmap_add_ddr_regions_statically() local
66 VERBOSE("DRAM Region %d: %p - %p\n", i, in mmap_add_ddr_regions_statically()
67 (void *) info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
68 (void *) (info_dram_regions->region[i].addr in mmap_add_ddr_regions_statically()
69 + info_dram_regions->region[i].size in mmap_add_ddr_regions_statically()
71 mmap_add_region(info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
72 info_dram_regions->region[i].addr, in mmap_add_ddr_regions_statically()
73 info_dram_regions->region[i].size, in mmap_add_ddr_regions_statically()
77 if (info_dram_regions->region[i].size > in mmap_add_ddr_regions_statically()
79 VERBOSE("Secure DRAM Region %d: %p - %p\n", i, in mmap_add_ddr_regions_statically()
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| /trusted-firmware-a-latest/plat/arm/common/fconf/ |
| D | fconf_sdei_getter.c | 13 #define PRIVATE_EVENT_NUM(i) private_events[3 * (i)] argument
14 #define PRIVATE_EVENT_INTR(i) private_events[3 * (i) + 1] argument
15 #define PRIVATE_EVENT_FLAGS(i) private_events[3 * (i) + 2] argument
17 #define SHARED_EVENT_NUM(i) shared_events[3 * (i)] argument
18 #define SHARED_EVENT_INTR(i) shared_events[3 * (i) + 1] argument
19 #define SHARED_EVENT_FLAGS(i) shared_events[3 * (i) + 2] argument
25 uint32_t i; in fconf_populate_sdei_dyn_config() local
64 for (i = 0; i < sdei_dyn_config.private_ev_cnt; i++) { in fconf_populate_sdei_dyn_config()
65 sdei_dyn_config.private_ev_nums[i] = PRIVATE_EVENT_NUM(i); in fconf_populate_sdei_dyn_config()
66 sdei_dyn_config.private_ev_intrs[i] = PRIVATE_EVENT_INTR(i); in fconf_populate_sdei_dyn_config()
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| D | fconf_sec_intr_config.c | 13 #define G0_INTR_NUM(i) g0_intr_prop[3U * (i)] argument
14 #define G0_INTR_PRIORITY(i) g0_intr_prop[3U * (i) + 1] argument
15 #define G0_INTR_CONFIG(i) g0_intr_prop[3U * (i) + 2] argument
17 #define G1S_INTR_NUM(i) g1s_intr_prop[3U * (i)] argument
18 #define G1S_INTR_PRIORITY(i) g1s_intr_prop[3U * (i) + 1] argument
19 #define G1S_INTR_CONFIG(i) g1s_intr_prop[3U * (i) + 2] argument
103 for (uint32_t i = 0; i < g0_intr_count; i++) { in fconf_populate_sec_intr_config() local
108 sec_intr_property.intr_num = G0_INTR_NUM(i); in fconf_populate_sec_intr_config()
109 sec_intr_property.intr_pri = G0_INTR_PRIORITY(i); in fconf_populate_sec_intr_config()
110 sec_intr_property.intr_cfg = G0_INTR_CONFIG(i); in fconf_populate_sec_intr_config()
[all …]
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| /trusted-firmware-a-latest/plat/rockchip/px30/drivers/soc/ |
| D | soc.c | 48 uint32_t i, j; in clk_gate_con_save() local
50 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_save()
51 clkgt_save[i] = in clk_gate_con_save()
52 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
53 j = i; in clk_gate_con_save()
54 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
56 mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i)); in clk_gate_con_save()
61 uint32_t i, j; in clk_gate_con_restore() local
63 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_restore()
64 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
[all …]
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| /trusted-firmware-a-latest/plat/intel/soc/agilex/soc/ |
| D | agilex_pinmux.c | 217 unsigned int i; in config_pinmux() local
219 for (i = 0; i < 96; i += 2) { in config_pinmux()
221 hoff_ptr->pinmux_sel_array[i], in config_pinmux()
222 hoff_ptr->pinmux_sel_array[i+1]); in config_pinmux()
225 for (i = 0; i < 96; i += 2) { in config_pinmux()
227 hoff_ptr->pinmux_io_array[i], in config_pinmux()
228 hoff_ptr->pinmux_io_array[i+1]); in config_pinmux()
231 for (i = 0; i < 40; i += 2) { in config_pinmux()
233 hoff_ptr->pinmux_fpga_array[i], in config_pinmux()
234 hoff_ptr->pinmux_fpga_array[i+1]); in config_pinmux()
[all …]
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| /trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/ |
| D | dfs.c | 184 uint32_t i, j; in sdram_timing_cfg_init() local
186 for (i = 0; i < sdram_params->num_channels; i++) { in sdram_timing_cfg_init()
187 ptiming_config->dram_info[i].speed_rate = DDR3_DEFAULT; in sdram_timing_cfg_init()
188 ptiming_config->dram_info[i].cs_cnt = sdram_params->ch[i].rank; in sdram_timing_cfg_init()
189 for (j = 0; j < sdram_params->ch[i].rank; j++) { in sdram_timing_cfg_init()
190 ptiming_config->dram_info[i].per_die_capability[j] = in sdram_timing_cfg_init()
191 get_cs_die_capability(sdram_params, i, j); in sdram_timing_cfg_init()
264 uint32_t i; in get_rdlat_adj() local
277 for (i = 0; i < cnt; i++) { in get_rdlat_adj()
278 if (cl == p[i].cl) in get_rdlat_adj()
[all …]
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| D | dram.c | 17 uint32_t os_reg2_val, i; in dram_init() local
25 for (i = 0; i < 2; i++) { in dram_init()
26 struct rk3399_sdram_channel *ch = &sdram_config.ch[i]; in dram_init()
29 if (!(SYS_REG_DEC_CHINFO(os_reg2_val, i))) in dram_init()
32 ch->rank = SYS_REG_DEC_RANK(os_reg2_val, i); in dram_init()
33 ch->col = SYS_REG_DEC_COL(os_reg2_val, i); in dram_init()
34 ch->bk = SYS_REG_DEC_BK(os_reg2_val, i); in dram_init()
35 ch->bw = SYS_REG_DEC_BW(os_reg2_val, i); in dram_init()
36 ch->dbw = SYS_REG_DEC_DBW(os_reg2_val, i); in dram_init()
37 ch->row_3_4 = SYS_REG_DEC_ROW_3_4(os_reg2_val, i); in dram_init()
[all …]
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| /trusted-firmware-a-latest/drivers/arm/rss/ |
| D | rss_comms_protocol_embed.c | 36 uint32_t i; in rss_protocol_embed_serialize_msg() local
46 for (i = 0U; i < in_len; ++i) { in rss_protocol_embed_serialize_msg()
47 msg->io_size[i] = in_vec[i].len; in rss_protocol_embed_serialize_msg()
49 for (i = 0U; i < out_len; ++i) { in rss_protocol_embed_serialize_msg()
50 msg->io_size[in_len + i] = out_vec[i].len; in rss_protocol_embed_serialize_msg()
53 for (i = 0U; i < in_len; ++i) { in rss_protocol_embed_serialize_msg()
54 if (in_vec[i].len > sizeof(msg->trailer) - payload_size) { in rss_protocol_embed_serialize_msg()
58 in_vec[i].base, in rss_protocol_embed_serialize_msg()
59 in_vec[i].len); in rss_protocol_embed_serialize_msg()
60 payload_size += in_vec[i].len; in rss_protocol_embed_serialize_msg()
[all …]
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| D | rss_comms_protocol_pointer_access.c | 32 unsigned int i; in rss_protocol_pointer_access_serialize_msg() local
42 for (i = 0U; i < in_len; ++i) { in rss_protocol_pointer_access_serialize_msg()
43 msg->io_sizes[i] = in_vec[i].len; in rss_protocol_pointer_access_serialize_msg()
44 msg->host_ptrs[i] = (uint64_t)in_vec[i].base; in rss_protocol_pointer_access_serialize_msg()
46 for (i = 0U; i < out_len; ++i) { in rss_protocol_pointer_access_serialize_msg()
47 msg->io_sizes[in_len + i] = out_vec[i].len; in rss_protocol_pointer_access_serialize_msg()
48 msg->host_ptrs[in_len + i] = (uint64_t)out_vec[i].base; in rss_protocol_pointer_access_serialize_msg()
62 unsigned int i; in rss_protocol_pointer_access_deserialize_reply() local
67 for (i = 0U; i < out_len; ++i) { in rss_protocol_pointer_access_deserialize_reply()
68 out_vec[i].len = reply->out_sizes[i]; in rss_protocol_pointer_access_deserialize_reply()
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| /trusted-firmware-a-latest/drivers/arm/gic/v3/ |
| D | gicv3_helpers.c | 153 unsigned int i, num_ints; in gicv3_spis_config_defaults() local
162 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) { in gicv3_spis_config_defaults()
163 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); in gicv3_spis_config_defaults()
171 for (i = MIN_ESPI_ID; i < num_eints; in gicv3_spis_config_defaults()
172 i += (1U << IGROUPR_SHIFT)) { in gicv3_spis_config_defaults()
173 gicd_write_igroupr(gicv3_get_multichip_base(i, gicd_base), i, ~0U); in gicv3_spis_config_defaults()
181 for (i = MIN_SPI_ID; i < num_ints; i += (1U << IPRIORITYR_SHIFT)) { in gicv3_spis_config_defaults()
182 gicd_write_ipriorityr(gicv3_get_multichip_base(i, gicd_base), i, GICD_IPRIORITYR_DEF_VAL); in gicv3_spis_config_defaults()
186 for (i = MIN_ESPI_ID; i < num_eints; in gicv3_spis_config_defaults()
187 i += (1U << IPRIORITYR_SHIFT)) { in gicv3_spis_config_defaults()
[all …]
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| /trusted-firmware-a-latest/tools/cert_create/src/ |
| D | main.c | 101 int rem, i = 0; in print_help() local
132 printf("\t%-32s %s\n", line, cmd_opt_get_help_msg(i)); in print_help()
134 i++; in print_help()
141 int i; in get_key_alg() local
143 for (i = 0 ; i < NUM_ELEM(key_algs_str) ; i++) { in get_key_alg()
144 if (0 == strcmp(key_alg_str, key_algs_str[i])) { in get_key_alg()
145 return i; in get_key_alg()
166 int i; in get_hash_alg() local
168 for (i = 0 ; i < NUM_ELEM(hash_algs_str) ; i++) { in get_hash_alg()
169 if (0 == strcmp(hash_alg_str, hash_algs_str[i])) { in get_hash_alg()
[all …]
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| /trusted-firmware-a-latest/drivers/renesas/rzg/qos/G2N/ |
| D | qos_init_g2n_v10.c | 148 uint32_t i; in qos_init_g2n_v10() local
150 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_g2n_v10()
151 mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]); in qos_init_g2n_v10()
152 mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]); in qos_init_g2n_v10()
154 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_g2n_v10()
155 mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]); in qos_init_g2n_v10()
156 mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]); in qos_init_g2n_v10()
159 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_g2n_v10()
160 mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]); in qos_init_g2n_v10()
161 mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]); in qos_init_g2n_v10()
[all …]
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| /trusted-firmware-a-latest/drivers/renesas/rcar/qos/M3N/ |
| D | qos_init_m3n_v10.c | 150 uint32_t i; in qos_init_m3n_v10() local
152 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3n_v10()
153 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3n_v10()
154 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3n_v10()
156 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3n_v10()
157 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3n_v10()
158 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3n_v10()
161 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3n_v10()
162 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, in qos_init_m3n_v10()
163 qoswt_fix[i]); in qos_init_m3n_v10()
[all …]
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| /trusted-firmware-a-latest/plat/imx/common/ |
| D | imx7_clock.c | 11 unsigned int i; in imx7_clock_uart_init() local
13 for (i = 0; i < MXC_MAX_UART_NUM; i++) in imx7_clock_uart_init()
14 imx_clock_disable_uart(i); in imx7_clock_uart_init()
19 unsigned int i; in imx7_clock_wdog_init() local
21 for (i = 0; i < MXC_MAX_WDOG_NUM; i++) in imx7_clock_wdog_init()
22 imx_clock_disable_wdog(i); in imx7_clock_wdog_init()
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| /trusted-firmware-a-latest/plat/arm/common/aarch64/ |
| D | arm_sdei.c | 29 uint32_t i; in plat_sdei_setup() local
33 for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_cnt); i++) { in plat_sdei_setup()
34 arm_sdei_private[i + 1] = (sdei_ev_map_t)SDEI_PRIVATE_EVENT( in plat_sdei_setup()
35 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_nums[i]), in plat_sdei_setup()
36 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_intrs[i]), in plat_sdei_setup()
37 FCONF_GET_PROPERTY(sdei, dyn_config, private_ev_flags[i])); in plat_sdei_setup()
40 for (i = 0; i < FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_cnt); i++) { in plat_sdei_setup()
41 arm_sdei_shared[i] = (sdei_ev_map_t)SDEI_SHARED_EVENT( in plat_sdei_setup()
42 FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_nums[i]), in plat_sdei_setup()
43 FCONF_GET_PROPERTY(sdei, dyn_config, shared_ev_intrs[i]), in plat_sdei_setup()
[all …]
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| /trusted-firmware-a-latest/plat/qti/common/src/ |
| D | qti_syscall.c | 76 int i = 0; in qti_is_secure_io_access_allowed() local
78 for (i = 0; i < ARRAY_SIZE(qti_secure_io_allowed_regs); i++) { in qti_is_secure_io_access_allowed()
79 if ((uintptr_t) addr == qti_secure_io_allowed_regs[i]) { in qti_is_secure_io_access_allowed()
110 int i; in qti_mem_assign_validate_param() local
125 for (i = 0; i < u_num_mappings; i++) { in qti_mem_assign_validate_param()
126 if ((mem_info[i].mem_addr & (SIZE4K - 1)) in qti_mem_assign_validate_param()
127 || (mem_info[i].mem_size == 0) in qti_mem_assign_validate_param()
128 || (mem_info[i].mem_size & (SIZE4K - 1))) { in qti_mem_assign_validate_param()
130 (unsigned int)mem_info[i].mem_addr, in qti_mem_assign_validate_param()
131 (unsigned int)mem_info[i].mem_size); in qti_mem_assign_validate_param()
[all …]
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| /trusted-firmware-a-latest/drivers/marvell/ |
| D | ap807_clocks_init.c | 47 int i; in pll_set_freq() local
52 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { in pll_set_freq()
54 mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val); in pll_set_freq()
58 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
61 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
65 mmio_write_32(AP807_CPU_PLL_CFG(i), in pll_set_freq()
74 int i; in aro_to_pll() local
76 for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) { in aro_to_pll()
78 reg = mmio_read_32(AP807_CPU_ARO_CTRL(i)); in aro_to_pll()
80 mmio_write_32(AP807_CPU_ARO_CTRL(i), reg); in aro_to_pll()
[all …]
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| /trusted-firmware-a-latest/plat/rockchip/rk3288/drivers/soc/ |
| D | soc.c | 145 uint32_t i = 0; in clk_gate_con_save() local
147 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_save()
148 slp_data.cru_gate_con[i] = in clk_gate_con_save()
149 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
154 uint32_t i; in clk_gate_con_disable() local
156 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_disable()
157 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
162 uint32_t i; in clk_gate_con_restore() local
164 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) in clk_gate_con_restore()
165 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
[all …]
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| /trusted-firmware-a-latest/services/std_svc/drtm/ |
| D | drtm_res_address_map.c | 34 unsigned int i; in drtm_build_address_map() local
41 for (i = 0U; mmap[i].base_pa != 0UL; i++) { in drtm_build_address_map()
43 map->region[i].region_address = mmap[i].base_pa; in drtm_build_address_map()
46 map->region[i].region_size_type = 0; in drtm_build_address_map()
48 map->region[i].region_size_type, in drtm_build_address_map()
49 mmap[i].size / PAGE_SIZE_4KB); in drtm_build_address_map()
52 switch (MT_TYPE(mmap[i].attr)) { in drtm_build_address_map()
55 map->region[i].region_size_type, in drtm_build_address_map()
60 map->region[i].region_size_type, in drtm_build_address_map()
63 map->region[i].region_size_type, in drtm_build_address_map()
[all …]
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| /trusted-firmware-a-latest/plat/arm/board/rdv1mc/ |
| D | rdv1mc_security.c | 44 unsigned int i; in plat_arm_security_setup() local
48 for (i = 0; i < TZC400_COUNT; i++) { in plat_arm_security_setup()
49 arm_tzc400_setup(TZC400_BASE(i), tzc_regions); in plat_arm_security_setup()
55 for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) { in plat_arm_security_setup()
56 INFO("Configuring TrustZone Controller for Chip %u\n", i); in plat_arm_security_setup()
59 arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i) in plat_arm_security_setup()
60 + TZC400_BASE(j), tzc_regions_mc[i-1]); in plat_arm_security_setup()
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| /trusted-firmware-a-latest/drivers/renesas/rcar/qos/M3/ |
| D | qos_init_m3_v11.c | 163 uint32_t i; in qos_init_m3_v11() local
165 for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) { in qos_init_m3_v11()
166 io_write_64(QOSBW_FIX_QOS_BANK0 + i * 8, mstat_fix[i]); in qos_init_m3_v11()
167 io_write_64(QOSBW_FIX_QOS_BANK1 + i * 8, mstat_fix[i]); in qos_init_m3_v11()
169 for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) { in qos_init_m3_v11()
170 io_write_64(QOSBW_BE_QOS_BANK0 + i * 8, mstat_be[i]); in qos_init_m3_v11()
171 io_write_64(QOSBW_BE_QOS_BANK1 + i * 8, mstat_be[i]); in qos_init_m3_v11()
174 for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) { in qos_init_m3_v11()
175 io_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8, qoswt_fix[i]); in qos_init_m3_v11()
176 io_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8, qoswt_fix[i]); in qos_init_m3_v11()
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