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Searched refs:gpc_imr_offset (Results 1 – 2 of 2) sorted by relevance

/trusted-firmware-a-latest/plat/imx/imx8m/imx8mq/
Dgpc.c36 static uint32_t gpc_imr_offset[] = { variable
58 uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4; in gpc_save_imr_lpm()
70 uint32_t reg = gpc_imr_offset[core_id] + imr_idx * 4; in gpc_restore_imr_lpm()
118 reg = gpc_imr_offset[0] + (hwirq / 32) * 4; in imx_gpc_hwirq_mask()
135 reg = gpc_imr_offset[0] + (hwirq / 32) * 4; in imx_gpc_hwirq_unmask()
160 mmio_setbits_32(gpc_imr_offset[core_id], 1); in imx_gpc_mask_irq0()
162 mmio_clrbits_32(gpc_imr_offset[core_id], 1); in imx_gpc_mask_irq0()
197 reg = gpc_imr_offset[cpu_idx] + (hwirq / 32) * 4; in imx_gpc_set_affinity()
207 reg = gpc_imr_offset[i] + (hwirq / 32) * 4; in imx_gpc_set_affinity()
391 for (j = 0U; j < ARRAY_SIZE(gpc_imr_offset); j++) { in imx_gpc_init()
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/trusted-firmware-a-latest/plat/imx/imx8m/
Dgpc_common.c22 static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53… variable
213 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, in imx_set_sys_wakeup()