| /trusted-firmware-a-latest/docs/design/ |
| D | cpu-specific-build-macros.rst | 62 these workarounds are enabled for the wrong CPU revision then the errata
68 for it to specify which errata workarounds should be enabled or not.
76 CPU. This needs to be enabled for all revisions of the CPU.
81 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
84 CPU. This needs to be enabled only for revision >= r3p0 of the CPU.
89 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
92 CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
97 CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35.
102 CPUs. This needs to be enabled only for revision <= r0p1 of Cortex-A53.
105 CPUs. This needs to be enabled only for revision <= r0p2 of Cortex-A53.
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| /trusted-firmware-a-latest/drivers/nxp/tzc/ |
| D | plat_tzc380.c | 86 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_DISABLE; in populate_tzc380_reg_list()
99 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; in populate_tzc380_reg_list()
110 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; in populate_tzc380_reg_list()
121 tzc380_reg_list[list_idx].enabled = TZC_ATTR_REGION_ENABLE; in populate_tzc380_reg_list()
162 tzc380_reg_list[indx].enabled; in mem_access_setup()
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| /trusted-firmware-a-latest/docs/getting_started/ |
| D | build-internals.rst | 5 :ref:`build-options <build options>` but enabled or disabled indirectly and
6 depends on certain options to be enabled or disabled.
13 Default is 0 (disabled). This option will be set to 1 (enabled) when ``SPD=spmd``
14 and ``SPMD_SPM_AT_SEL2`` is set or when ``ENABLE_RME`` is set to 1 (enabled).
18 ELs which gets trapped in EL3. This option will be set to 1 (enabled) if
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| D | build-options.rst | 71 FIP. Automatically enabled if ``SP_LAYOUT_FILE`` is provided.
110 If enabled, it is needed to use a compiler that supports the option
136 Note that Pointer Authentication is enabled for Non-secure world
161 - ``COT``: When Trusted Boot is enabled, selects the desired chain of trust.
167 this is only enabled for a debug build of the firmware.
184 registers in cpu context. This must be enabled, if the platform wants to use
185 this feature in the Secure world and MTE is enabled at ELX. This flag can
200 Note that Pointer Authentication is enabled for Non-secure world irrespective
222 Board Boot authentication at runtime. This option is meant to be enabled only
224 flag has to be enabled. 0 is the default.
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| D | psci-lib-integration-guide.rst | 53 **must not** be enabled).
160 - Instruction cache must be enabled
162 - The page tables must be setup and the MMU enabled
164 - The Data cache must be enabled prior to invoking any of the PSCI library
167 is enabled however, data caches are expected to be enabled.
279 disabled (unless build option ``HW_ASSISTED_COHERENCY`` is enabled) but with MMU
280 initialized and enabled. The major actions performed by this function are:
455 enabled/re-targeted back to the current CPU.
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| /trusted-firmware-a-latest/plat/marvell/armada/a3k/common/ |
| D | dram_win.c | 46 uint32_t enabled; member
191 uint32_t base_reg, ctrl_reg, size_reg, enabled, target; in dram_win_map_build() local
198 enabled = ctrl_reg & CPU_DEC_CR_WIN_ENABLE; in dram_win_map_build()
200 if ((enabled == 0) || (target != DRAM_CPU_DEC_TARGET_NUM)) in dram_win_map_build()
235 if (!win_cfg->enabled) in cpu_win_set()
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| /trusted-firmware-a-latest/plat/arm/common/ |
| D | arm_nor_psci_mem_protect.c | 38 int arm_psci_read_mem_protect(int *enabled) in arm_psci_read_mem_protect() argument
43 *enabled = (tmp == 1) ? 1 : 0; in arm_psci_read_mem_protect()
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| /trusted-firmware-a-latest/plat/st/stm32mp1/ |
| D | stm32mp1_scmi.c | 33 bool enabled; member
77 .enabled = _init_enabled, \
313 return (int32_t)clock->enabled; in plat_scmi_clock_get_state()
330 if (!clock->enabled) { in plat_scmi_clock_set_state()
333 clock->enabled = true; in plat_scmi_clock_set_state()
336 if (clock->enabled) { in plat_scmi_clock_set_state()
339 clock->enabled = false; in plat_scmi_clock_set_state()
468 if (clk->enabled && in stm32mp1_init_scmi_server()
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| /trusted-firmware-a-latest/include/drivers/nxp/tzc/ |
| D | plat_tzc380.h | 31 unsigned int enabled; member
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| /trusted-firmware-a-latest/docs/perf/ |
| D | psci-performance-instr.rst | 10 This page explains how they may be enabled and used to perform all varieties of
37 This feature is enabled with the Boolean flag ``ENABLE_PMF``.
77 PSCI Statistics is enabled with the Boolean build flag
79 collection backend is provided (``ENABLE_PMF`` is implicitly enabled).
88 components in TF-A as well. It is enabled with the Boolean flag
90 be enabled.
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| D | performance-monitoring-unit.rst | 49 the counters are enabled (permitted to increment) via the ``PMCNTENSET`` and
122 security state unless it is enabled here.
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| /trusted-firmware-a-latest/docs/components/ |
| D | mpmm.rst | 11 |MPMM| is enabled on a per-core basis by the EL3 runtime firmware. The presence
28 |AMU| counters that make up the |MPMM| gears must be enabled by the EL3
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| D | realm-management-extension.rst | 45 enabled, TF-A runs in the Root world at EL3. Therefore, the boot flow is
46 modified to run BL2 at EL3 when RME is enabled. In addition to this, a
50 The boot flow when RME is enabled looks like the following:
55 4. BL31 initializes SPM (if SPM is enabled)
88 and the interface between R-EL2 and EL3. When building TF-A with RME enabled,
95 This section describes how you can build and run TF-A with RME enabled.
120 Host is Linux, then the below instructions assume that a suitable RME enabled
281 -C bp.smsc_91c111.enabled=1 \
373 **2. Build RME enabled TF-A with SPM**
375 Build TF-A with RME as well as SPM enabled.
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| /trusted-firmware-a-latest/lib/mpmm/ |
| D | mpmm.mk | 12 $(error MPMM support (`ENABLE_MPMM`) can only be enabled in AArch64 images (`ARCH`))
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| /trusted-firmware-a-latest/docs/components/fconf/ |
| D | amu-bindings.rst | 67 | | | | be enabled prior to EL3 exit. |
140 defined by ``amu1``. This will cause ``counterX`` and ``counterY`` to be enabled
141 for both ``cpu0`` and ``cpu1``, and ``counterZ`` to be enabled for both ``cpu2``
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| /trusted-firmware-a-latest/drivers/arm/ethosn/ |
| D | ethosn_npu.mk | 31 $(error "ETHOSN_NPU_TZMP1 is only available if TRUSTED_BOARD_BOOT is enabled)
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| /trusted-firmware-a-latest/docs/security_advisories/ |
| D | security-advisory-tfv-2.rst | 43 meaning that debug exceptions from Secure EL1 are enabled by the authentication
45 secure privileged invasive debug is enabled by the authentication interface, at
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| D | security-advisory-tfv-7.rst | 40 world execution. The mitigation is enabled by setting an implementation defined
46 The mitigation code is enabled by default, but can be disabled at compile time
88 the default mitigation state for firmware-managed execution contexts is enabled.
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| /trusted-firmware-a-latest/docs/plat/marvell/armada/misc/ |
| D | mvebu-iob.rst | 10 the enabled windows. If there is a hit and it passes the security checks, it is
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1088a/ |
| D | soc.def | 64 # SoC ERRATUM to be enabled
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| /trusted-firmware-a-latest/plat/brcm/board/stingray/driver/ |
| D | usb_phy.c | 495 phy_info->phy_port[index].enabled = (phy_info->ports_enabled in usb_info_fill()
518 if (phy_info->phy_port[index].enabled != 0U) { in usb_phy_init()
547 if (phy_info->phy_port[index].enabled != 0U) { in usb_phy_shutdown()
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| /trusted-firmware-a-latest/docs/design_documents/ |
| D | context_mgmt_rework.rst | 78 both Realm and Secure world will have the same feature set enabled from
148 enabled for the sake of robustness. Another example is, if the MTE feature
149 is enabled for a particular world, this feature will be enabled for Root world
151 be expecting this feature to be enabled and may cause unwanted side-effects
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| /trusted-firmware-a-latest/plat/nxp/soc-ls1028a/ |
| D | soc.def | 72 # SoC ERRATAS to be enabled
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| /trusted-firmware-a-latest/plat/brcm/board/stingray/include/ |
| D | usb_phy.h | 231 uint32_t enabled; member
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| /trusted-firmware-a-latest/docs/threat_model/ |
| D | threat_model_arm_cca.rst | 28 - :ref:`Realm Management Extension (RME)` is enabled on the platform.
65 - Trusted boot and measured boot are enabled. This means an attacker can't boot
75 - No experimental features are enabled. These are typically incomplete features,
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