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Searched refs:dpll_rates_table (Results 1 – 1 of 1) sorted by relevance

/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/
Ddfs.c25 static const struct pll_div dpll_rates_table[] = { variable
1697 pll_cnt = ARRAY_SIZE(dpll_rates_table); in to_get_clk_index()
1701 if (mhz >= dpll_rates_table[i].mhz) in to_get_clk_index()
1859 boot_freq = dpll_rates_table[to_get_clk_index(boot_freq)].mhz; in dram_dfs_init()
2024 mhz = dpll_rates_table[index].mhz; in ddr_set_rate()
2036 m0_configure_ddr(dpll_rates_table[index], ddr_index); in ddr_set_rate()
2059 return dpll_rates_table[index].mhz * 1000 * 1000; in ddr_round_rate()