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/trusted-firmware-a-latest/docs/resources/diagrams/plantuml/
Dfip-secure-partitions.puml163 signed_spkg_1 -down-> fiptool
164 signed_spkg_2 -down-> fiptool
165 fiptool -down-> fip
/trusted-firmware-a-latest/docs/perf/
Dpsci-performance-juno.rst25 Juno supports CPU, cluster and system power down states, corresponding to power
350 last CPUs in their respective clusters to power down, therefore both the L1 and
381 effectively serializes the SCP power down commands from all CPUs.
383 On platforms with a more efficient CPU power down mechanism, it should be
412 are large because all other CPUs in the cluster are powered down during the
413 test. The ``CPU_SUSPEND`` call powers down to the cluster level, requiring a
421 CPU 4 continues to run while CPU 5 is suspended. Hence CPU 5 only powers down to
482 CPUs in that cluster are powerered down during the test. The ``CPU_OFF`` call
483 powers down to the cluster level, requiring a flush of both L1 and L2 caches.
486 lead CPU 4 is running and CPU 5 only powers down to level 0, which only requires
/trusted-firmware-a-latest/drivers/renesas/common/ddr/ddr_b/
Dboot_init_dram_config.c1890 uint32_t dataL, down, up; in opencheck_SSI_WS6() local
1914 down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1; in opencheck_SSI_WS6()
1932 if (down == up) { in opencheck_SSI_WS6()
/trusted-firmware-a-latest/docs/getting_started/
Dpsci-lib-integration-guide.rst68 whether the PSCI API resulted in power down of the CPU.
79 be preserved across CPU power down/power up cycles are maintained in
95 ``cpu_context_t`` is stripped down for just PSCI CPU context management.
264 caller if PSCI API causes power down of the CPU. In this case, when the CPU
276 `PSCI`_. For AArch32, on wakeup from power down the CPU resets to secure SVC
452 appropriately during CPU power down/power up. Any secure interrupt targeted
454 to power down of the current CPU. During power up, these interrupt can be
482 The ``svc_suspend`` callback is called during power down bu either
486 (first parameter) denotes the highest power domain level being powered down
516 The CPU operations (cpu_ops) framework implement power down sequence specific
Dbuild-options.rst1143 and restore during SYSTEM_SUSPEND without powering down GIC. Default is 0.
/trusted-firmware-a-latest/docs/design_documents/
Dpsci_osi_mode.rst27 uses the shared cache, the core power domains must be powered down before the
28 shared cache power domain can be powered down.
278 cores in a topology node call CPU_OFF, the last core will power down the node.
558 idle-state-name = "little-power-down";
568 idle-state-name = "little-rail-power-down";
578 idle-state-name = "big-power-down";
588 idle-state-name = "big-rail-power-down";
600 idle-state-name = "cluster-power-down";
Dcontext_mgmt_rework.rst30 The below section lays down the design principles for re-factoring the context
/trusted-firmware-a-latest/plat/allwinner/common/
Darisc_off.S76 reset: l.sw 0x1c00(r13),r0 # pull down our own reset line
/trusted-firmware-a-latest/docs/process/
Dcode-review-guidelines.rst35 down-vote.
38 down-vote.
/trusted-firmware-a-latest/docs/components/
Dromlib-design.rst122 This will have for effect to shift down all the BL images by 1 page.
Drmm-el3-comms-spec.rst66 down into RMM certain platform specific information dynamically. This allows
Dxlat-tables-lib-v2-design.rst85 The granularity controls the translation table level to go down to when mapping
/trusted-firmware-a-latest/docs/about/
Dfeatures.rst17 - Library support for CPU specific reset and power down sequences. This
/trusted-firmware-a-latest/docs/design/
Dfirmware-design.rst502 buffer, CPU reset and power down operations, PSCI data, platform data and so on.
1364 #. Processor specific power down sequences.
1376 #. allows each processor to implement the power down sequence mandated in
1389 different CPUs during power down and reset handling. The platform can specify
1398 ``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1453 CPU specific power down sequence
1458 retrieved during power down sequences.
1460 Various CPU drivers register handlers to perform power down at certain power
1461 levels for that specific CPU. The PSCI service, upon receiving a power down
1462 request, determines the highest power level at which to execute power down
[all …]
Dcpu-specific-build-macros.rst980 Cortex-A57 cluster power down sequence by not flushing the Level 1 data
983 is a known safe deviation from the Cortex-A57 TRM defined power down
/trusted-firmware-a-latest/docs/
Dporting-guide.rst169 Defines the local power state corresponding to the deepest power down
181 PSCI implementation to distinguish between retention and power down local
189 power domain level (power-down and retention). If the platform needs to
1331 present) during a cluster power down sequence. The default weak implementation
1332 doesn't do anything. Since this API is called during the power down sequence,
2538 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2556 index 0 (CPU power level) in the ``pwr_domain_state`` array indicates a power down
2683 power down state where as it could be either power down, retention or run state
2701 power down state where as it could be either power down, retention or run state
2722 calls this function when suspending to a power down state, and it guarantees
[all …]
Dchange-log.md1445 …- clear power down bit during wakeup ([5f0f7e4](https://review.trustedfirmware.org/plugins/gitiles…
1446 …- clear power down interrupt status before enable ([2d056db](https://review.trustedfirmware.org/pl…
1450 …- fix setting power down state ([1f79bdf](https://review.trustedfirmware.org/plugins/gitiles/TF-A/…
2234 …- add per-cpu power down support for warm reset ([158ed58](https://review.trustedfirmware.org/plug…
6079 - Support for powering down CPUs during CPU suspend has been removed
6393 - xilinx: versal: Implement power down/restart related EEMI, SMC handler for
6524 - ti: k3: common: Enable ARM cluster power down and rename device IDs to be
7606 power-down state and with data caches enabled.
7839 - Skip performing cache maintenance during power-up and power-down.
7846 (DSU). The power-down and power-up sequences are therefore mostly managed in
[all …]
/trusted-firmware-a-latest/docs/plat/arm/
Darm-build-options.rst137 require all the CPUs to execute the CPU specific power down sequence to