| /trusted-firmware-a-latest/plat/nuvoton/npcm845x/ |
| D | npcm845x_serial_port.c | 53 volatile int delay; in npcm845x_wait_for_empty() local
55 for (delay = 0; delay < 10000; delay++) { in npcm845x_wait_for_empty()
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| /trusted-firmware-a-latest/plat/intel/soc/common/soc/ |
| D | socfpga_reset_manager.c | 419 uint32_t delay = 0; in socfpga_bridges_enable() local
452 for (delay = 0; delay < 1000; delay++) { in socfpga_bridges_enable()
489 for (delay = 0; delay < 1000; delay++) { in socfpga_bridges_enable()
590 for (delay = 0; delay < 1000; delay++) { in socfpga_bridges_enable()
673 for (delay = 0; delay < 1000; delay++) { in socfpga_bridges_enable()
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| /trusted-firmware-a-latest/plat/rpi/rpi4/ |
| D | rpi4_bl31_setup.c | 102 static void ldelay(register_t delay) in ldelay() argument
109 : "=&r" (delay) : "0" (delay) in ldelay()
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| /trusted-firmware-a-latest/plat/rockchip/rk3328/drivers/pmu/ |
| D | pmu.c | 272 uint32_t delay = PLL_LOCKED_TIMEOUT; in pm_pll_wait_lock() local
274 while (delay > 0) { in pm_pll_wait_lock()
278 delay--; in pm_pll_wait_lock()
280 if (delay == 0) in pm_pll_wait_lock()
315 uint32_t delay = PLL_LOCKED_TIMEOUT; in dpll_resume() local
326 while (delay > 0) { in dpll_resume()
330 delay--; in dpll_resume()
332 if (delay == 0) in dpll_resume()
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| /trusted-firmware-a-latest/fdts/ |
| D | morello-soc.dts | 333 polling-delay-passive = <200>; /* ms */
334 polling-delay = <1000>; /* ms */
359 polling-delay-passive = <200>; /* ms */
360 polling-delay = <1000>; /* ms */
384 polling-delay-passive = <200>; /* ms */
385 polling-delay = <1000>; /* ms */
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| D | stm32mp15xx-dhcor-som.dtsi | 131 regulator-enable-ramp-delay = <300000>;
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| /trusted-firmware-a-latest/plat/brcm/board/stingray/driver/ |
| D | ihost_pll_config.c | 202 static void insert_delay(unsigned int delay) in insert_delay() argument
206 for (index = 0; index < delay; index++) in insert_delay()
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| /trusted-firmware-a-latest/tools/marvell/doimage/secure/ |
| D | sec_img_7K.cfg | 21 jtag = { enable = true; delay = 20; };
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| D | sec_img_8K.cfg | 21 jtag = { enable = true; delay = 20; };
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| /trusted-firmware-a-latest/plat/renesas/common/ |
| D | common.mk | 113 drivers/renesas/common/delay/micro_delay.c \
135 drivers/renesas/common/delay/micro_delay.c \
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| /trusted-firmware-a-latest/plat/allwinner/common/ |
| D | arisc_off.S | 59 l.movhi r13, 0x1f0 # address of R_CPUCFG (delay)
79 l.nop 0x0 # (delay slot)
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| /trusted-firmware-a-latest/docs/process/ |
| D | faq.rst | 20 set and the impact of any delay. Feel free to add a comment to your patch set
49 the delay will be less than 1 day. If the TF maintainers are trying to merge
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| D | code-review-guidelines.rst | 100 Patch author(s) may be busy with other priorities, causing a delay in
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| /trusted-firmware-a-latest/drivers/mtd/nand/ |
| D | raw_nand.c | 60 static int nand_send_wait(unsigned int delay, unsigned int tim) in nand_send_wait() argument
68 req.delay_ms = delay; in nand_send_wait()
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| /trusted-firmware-a-latest/plat/rockchip/px30/drivers/pmu/ |
| D | pmu.c | 857 uint32_t delay = PLL_LOCKED_TIMEOUT; in pm_pll_wait_lock() local
859 while (delay > 0) { in pm_pll_wait_lock()
863 delay--; in pm_pll_wait_lock()
866 if (delay == 0) in pm_pll_wait_lock()
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| /trusted-firmware-a-latest/drivers/nxp/flexspi/nor/ |
| D | fspi.c | 803 for (uint8_t delay = 100U; delay > 0U; delay--) { in fspi_init() local
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| /trusted-firmware-a-latest/plat/renesas/rzg/ |
| D | platform.mk | 234 -Idrivers/renesas/common/delay \
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| /trusted-firmware-a-latest/plat/renesas/rcar/ |
| D | platform.mk | 319 -Idrivers/renesas/common/delay \
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| /trusted-firmware-a-latest/docs/getting_started/ |
| D | build-options.rst | 920 - ``TWED_DELAY``: Numeric value to be set in order to delay the trapping of
922 this delay. It can take values in the range (0-15). Default value is ``0``
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| /trusted-firmware-a-latest/docs/ |
| D | change-log.md | 1677 …- use CDDWW for write to read delay ([fa01056](https://review.trustedfirmware.org/plugins/gitiles/…
2366 …- add 100us delay after USB OTG SRC bit 0 clear ([66345b8](https://review.trustedfirmware.org/plug…
4789 …- delay after enabling CPU power ([86a7429](https://review.trustedfirmware.org/plugins/gitiles/TF-…
5501 - Move ddr and delay driver to common directory
5609 - Update delay code to be compatible with 1200 MHz CPU
5686 - Disable ITAPDLYENA bit for zero ITAP delay
6197 - Fixed incorrect delay timer reads
6446 - smmu: SMMUv3: Changed retry loop to delay timer
6677 - delay: Timeout detection support
6771 - mmc: Increase delay between ACMD41 retries
[all …]
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